LC7441N, 7441NE Picture-in-picture Controller VCRs Prelimina

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LC7441N, 7441NE Picture-in-picture Controller VCRs Prelimina

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Ordering number:ENN*3941B
LC7441N, 7441NE
Picture-in-picture Controller VCRs
Preliminary Overview
LC7441N, 7441NE picture-in picture (PIP) system controller NTSC, multi-system (both NTSC PAL) VCRs. LC7441 system configuration requires discrete LC7480 converter memory ICs. LC7441 system controller provides nested-picture main-screen/sub-screen video signal control. Single multiple sub-screens occupying 11.11% (one-third height, one-third width) main-screen constructed controlled. Features include still/active display, white/color frame, fixed/variable (screen) positioning, wipe function gradual sub-screen display erasure. Sub-screen horizontal resolution achieved 6-bit, 64-level samples. LC7441 construction includes interface, vertical(VERT) filter, memory controller, odd-field decision circuits, read/write PLLs converters. LC7441 operates from supply available 64-pin DIPs 64-pin QIPs.
Package Dimensions
unit:mm 3071-DIP64S
[LC7441N]
19.05
16.8
57.2
0.95
0.48
1.78
1.01
SANYO DIP64S
unit:mm 3159-QIP64E
[LC7441NE]
17.2
Features
NTSC, multi-system compatibility. signals. Forms component-based controller system. (nested) sub-screens occupying 11.11% main-screen. Still active video display control. White colored screen frames. Fixed variable screen positioning. Gradual sub-screen display erasure (wipe) function. interface, vertical (VERT) filter, memory controller. Three converters. supply. 64-pin 64-pin QIP.
14.0 0.35
0.15
17.2
14.0
3.0max
15.6
SANYO QIP64E
SANYO products described contained herein have specifications that handle applications that require extremely high levels reliability, such life-support systems, aircraft's control systems, other applications whose failure reasonably expected result serious physical and/or material damage. Consult with your SANYO representative nearest before using SANYO products described contained herein such applications. SANYO assumes responsibility equipment failures that result from using products values that exceed, even momentarily, rated values (such maximum ratings, operating condition ranges,or other parameters) listed products specifications SANYO products described contained herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
O3101TN (KT)/51595TH(ID)/4212JN No.3941-1/20
0.51min
5.0max
0.25
LC7441N, 7441NE
Assignments
view
No.3941-2/20
LC7441N, 7441NE
Block Diagram
No.3941-3/20
LC7441N, 7441NE
System Diagram
Functions
Number Name Equivalent circuit Function
TV/VCR
TV/VCR select, CMOS input
NTSC/PAL
NTSC/PAL select, CMOS input
Dual-port memory control outputs
Continued next page.
No.3941-4/20
LC7441N, 7441NE
Continued from preceding page.
Number Name SODI3 SODI2 SODI1 SODI0 WDO3 WDO2 WDO1 WDO0 DVSS ADCLK CLAMPAD interface Y-select output interface select output interface select output Sampling-clock output conversion clamp pulse output Sub-screen horizontal sync input 6-bit, sampled digital data inputs AD5, lsb, digital supply Digital ground 8-bit, dual-port memory address output lines lsb, 4-bit, dual-port memory input data output lines 4-bit, dual-port memory serial output data, inputs Equivalent circuit Function
Sub-screen vertical sync, Schmitt-trigger input
Main-screen horizontal sync input
Main-screen vertical sync, Schmitt-trigger input
PLLOH
Read-PLL horizontal sync signal select, CMOS input
Active-LOW standby mode set, CMOS input
Sub-screen frame ON/OFF select, CMOS input
KDIS
Sub-screen display ON/OFF select, CMOS input
Continued next page.
No.3941-5/20
LC7441N, 7441NE
Continued from preceding page.
Number Name Equivalent circuit Function Serial data enable still picture select, CMOS input Serial data data select, CMOS input Serial data sub-screen horizontal position select, CMOS input Serial data clock sub-screen vertical position select, CMOS input Frame output Main-screen/sub-screen switch, blanking signal output
SDE/STL SER/PIN SD/FHP
SCK/FVP
WAKU
KOUT
Active-LOW reset, CMOS input
CLAMPDA
converter clamp-pulse output
AVDD AVSS BAOUT YAOUT RAOUT
analog supply Analog ground converter output converter output converter output connection
VREF
converters reference voltage input
BIAS
converters bias capacitor connection
KLPFO
Sub-screen horizontal sync charge-pump, tristate output
KLPFI
Sub-screen horizontal sync clock input
OLPFI
Sub-screen horizontal sync clock input
OLPFO
Main-screen horizontal sync charge-pump, tristate output
No.3941-6/20
LC7441N, 7441NE Specifications
Absolute Maximum Ratings DVDD AVDD, DVSS AVSS
Parameter Supply voltage Input voltage Output voltage Allowable power dissipation Operating temperature Storage temperature Symbol Topr Tstg Conditions Ratings to+7.0 VDD+0.3 VDD+0.3 +125 Unit
Allowable Operating Ranges 25°C, DVDD AVDD
Parameter Supply voltage Supply voltage range Symbol Conditions Ratings Unit
Electrical Characteristics 27°C, DVDD AVDD ±10%,
Parameter Digital supply current Analog supply current Standby supply current Input leakage current input low-level voltage CMOS input low-level voltage input high-level voltage CMOS input high-level voltage Reference voltage KLPFI OLPFI input voltage KLPFO OLPFO output leakage current Output low-level voltage outputs except KLPFO OLPFO KLPFO OLPFO output low-level voltage Output high-level voltage outputs except KLPFO OLPFO KLPFO OLPFO output high-level voltage KLPFI OLPFI pull-up current YAOUT, RAOUT BAOUT output impedance Phase compensating capacitance Symbol IDDD IDDA IDDO IOFF VIL1 VIL2 VIH1 VIH2 VREF VOL1 VOL2 VOH1 VOH2 sine wave, capacitive coupling VI=VDD IOL=4 IOL=1 IOH=- IOH=- VRES=VSBY=VSS VDD-
0.7VDD
Conditions VRES=VSBY=VDD, fOV=fKV=60Hz, fOH=fKH=15kHz, fKLPFI=fOLPFI=20MHz VRES=VSBY=VDD, fOV=fKV=60Hz, fOH=fKH=15kHz, fKLPFI=fOLPFI=20MHz VRES=VSBY=VSS
Ratings
Unit
0.3VDD
AVDD- +0.01
AVDD
+0.1
Vp-p
No.3941-7/20
LC7441N, 7441NE
Timing Characteristics 27°C, DVDD AVDD ±10%,
Parameter pulsewidth rise time fall time pulsewidth rise time fall time pulsewidth rise time fall time period setup time hold time pulsewidth rise time fall time setup time hold time Symbol tSCW tSCR tSCF tSCI tDSU tCSU
Conditions
Ratings
Unit
Sync Pulse
Televison Sync Pulse
Serial Intreface
No.3941-8/20
LC7441N, 7441NE Function Description
NTSC/PAL NTSC/PAL should tied HIGH NTSC, PAL.
Parameter Horizontal vertical sync polarity
TV/VCR TV/VCR should tied HIGH television mode, mode. differences between modes shown following table figure.
(TV/VCR LOW)
Television (TV/VCR HIGH)
Y-signal converter output polarity
WAKU output vertical frame
KOUT, WAKU converter output timing
Output simultaneously
KOUT WAKU delayed
Note shaded converter outputs indicate frame data. t1=132ns, t2=396ns, t3=528ns, t4=176ns, t5=308ns, t6=352ns, t7=220ns, t8=616ns, t9=484ns Converter Interface controller interfaces with LC7480 multiplexing converter using VREF inputs CLAMPAD, YSW, RSW, ADCLK outputs. LC7480 converts video signals into 6-bit digital data which input AD5. YSW, control LC7480 input multiplexer. conversion sequence
shown following figure. conversion frequencies shown following table. LC7441 LC7480 should mounted closely possible care taken with layout because high signal frequencies.
No.3941-9/20
LC7441N, 7441NE
System NTSC 15,734 15,625
Conversion frequency (MHz) Total 320fH) 5.035 5.000 (fTY 160fH) 2.517 2.500 (fTR 80fH) 1.258 1.250 (fTB 80fH) 1.258 1.250
CLAMPAD output pulse follows input pulse. CLAMPAD should HIGH during horizontal blanking period shown following figure.
Note that when HIGH during reset standby, CLAMPAD HIGH.
Note t1=5.6µs, t2=2.4µs, t3>0µs t4>0.5µs
No.3941-10/20
LC7441N, 7441NE
On-chip Converter normal converter clock frequencies clock frequencies when RAR(Revise Aspect Ratio) Table converter clock frequency
System NTSC 15,734 15,625 (fCY 480fH) 7.552 7.500
register HIGH shown tables respectively.
Clock frequency (MHz) (fCR 240fH) 3.776 3.750 (fCB 240fH) 3.776 3.750
Table Changing clock frequency with
register HIGH HIGH NTSC/PAL Input HIGH 480fH 416fH 565fH 240fH 208fH 283fH 240fH 208fH 283fH
Note don't care CLAMPDA HIGH during main-screen horizontal sync pulses, shown following figure.
converter data when sub-screen displayed shown, first, following table. Note that when TV/VCR HIGH, signal output when LOW,
Output YAOUT RAOUT BAOUT converter data TV/VCR HIGH 111111 100000 100000 TV/VCR 000000 100000 100000
SCK/FVP SD/FHP SDE/STL KDIS
SER/PIN Sub-screen vertical position select Sub-screen horizontal position select Still/active display select HIGH Serial data clock Serial data Serial data enable
Initial sub-screen ON/OFF Sub-screen ON/OFF select selection when controller reset Initial sub-screen frame Sub-screen frame ON/OFF ON/OFF selection when select controller reset
Dual-function Inputs Input logic levels select sub-screen display parameters when SER/PIN LOW, serial data input logic levels, when SER/PIN HIGH, shown following table.
No.3941-11/20
LC7441N, 7441NE
Serial Data Interface When SER/PIN HIGH, SD/FHP, SCK/FVP SDE/ function serial-interface data, clock dataenable inputs, respectively, shown following figure. After SDE/STL goes LOW, data bits internal register address, D17,
register data. After data been received, address automatically incremented, data next register. After SDE/STL goes from HIGH LOW, address selection reoccurs.
Internal Registers internal control registers shown following table. Note that lower four bits address byte
Address VWIPE WKVAR2 VDFS1 WKVAR HWIPE WKVAR1 VDFS0 FILD KOUT2 YWK5 RWK5 BWK5
determine register address, upper four bits ignored.
position POSVAR STL2 YWK3 RWK3 BWK3 STL1 YWK2 RWK2 BWK2 FVPR FVPR YWK1 RWK1 BWK1 FHPR FHPR YWK0 RWK0 BWK0 KOUT
KOUT1 YWK4 RWK4 BWK4
No.3941-12/20
LC7441N, 7441NE
Reset Standby Modes controller reset holding standby mode either holding setting register HIGH. PLLs stopped internal registers shown following table. Note that input levels used determine some initial register values. example, KDIS when brought LOW, then KOUT, KOUT1 KOUT2 registers LOW.
Register WKVAR, WKVAR1, WKVAR2 FILD KOUT, KOUT1, KOUT2 POSVAR STL, STL1, STL2 FVPR FHPR Reset KDIS SDE/STL SCK/FVP SD/FHP HIGH Standby SDE/STL SCK/FVP SD/FHP
Register VWIPE HWIPE WK1, VDFS1 VDFS0 YWK0 YWK5 RWK0 RWK5 BWK0 BWK5 MUL,
Reset HIGH
Standby
Note Register unchanged power-up, hold several microseconds after power supply stabilizes shown following figure. Note that represent start controller operation, respectively.
Register data written when controller standby mode, memory data lost because PLLs stopped memory refreshed. Dual-port Interface dual-port interface comprises SODI0 SODI3 inputs WDO0 WDO3, RAS, outputs.
LC7441 dual-port should mounted closely possible care taken with layuout because high speed memory accesses. data read, memory refresh data transfer waveforms shown figures respectively. Note that when HIGH, 1/1696fH NTSC/PAL also HIGH, 1248fH NTSC/PAL LOW.
No.3941-13/20
LC7441N, 7441NE
Figure Data read
Figure before memory refresh
Figure Data transfer
No.3941-14/20
LC7441N, 7441NE
Memory Write Range horizontal memory-write range dots comprising 126, dots data, respectively. NTSC vertical memory-write
ranges horizontal lines, respectively, shown figures respectively.
Figure NTSC memory write range
Figure memory write range
No.3941-15/20
LC7441N, 7441NE
Memory Readout Range horizontal memory-readout range dots comprising 122, dots data, respectively. NTSC vertical memory readout ranges horizontal lines, respectively, shown figures respectively.
Figure memory readout range
Figure NTSC memory readout range Sync Signals layout should allow noise induced signals from sync-separator because this cause screen distortion. subscreen display should turned when sync signals
become unstable because display become distorted. input signals should video horizontal sync signals shown following figure.
Note PLLOH read-PLL locks main-screen horizontal sync frequency when PLLOH HIGH, sub-screen horizontal sync frequency, when PLLOH LOW. Using clock generate horizontal sync signal determine sub-screen display position results error-free display. PLLOH normally held HIGH. However, when unstable, PLLOH should held LOW, otherwise clock becomes unstable sub-screen flickers.
Odd-field Decision Circuits OH/OV KH/KV odd-field decision circuits measure phase difference between horizontal vertical sync pulses shown following figure. When field odd, single output horizontal sync pulse blanked during vertical sync pulse period, when even, blanked. phase difference measured between falling edges sync pulses when TV/VCR HIGH, between rising edges, when TV/VCR LOW.
No.3941-16/20
LC7441N, 7441NE
Operating Information LC7441 operates under input control when SER/ LOW, under serial control, when SER/PIN HIGH. display sub-screen when under input control, either sub-screens, when under serial control. Single- Dual-screen Operation Under Serial Control Writing register data address selects single-screen mode, writing data address dual-screen mode. registers selecting single-screen parameters VWIPE, HWIPE address registers. register selecting dual-screen parameters WKVAR1, WKVAR2 address registers. Sub-screen ON/OFF control sub-screen when KDIS input HIGH, OFF, when LOW. Serial control, single screen sub-screen when KOUT HIGH, OFF, when LOW. Serial control, dual screen Sub-screen when KOUT1 HIGH, OFF, when LOW. Sub-screen when KOUT2 HIGH, OFF, when LOW. Sub-screen Position sub-screen position fixed variable. four fixed positions shown figure variable position which determined registers follows, figure ((VP0 VP5) ((HP0 HP5) 60fH
Note that variable positions outside main-screen area ignored.
Figure Sub-screen positions
Note Figures brackets apply displays.
register HIGH HIGH NTSC/PAL Input HIGH HIGH Read-VCO frequency 1,440fH 1,440fH 1,248fH 1,696fH frequency 60fH 60fH 52fH 70.7fH
Note Normal write-VCO frequency 1280fH.
Figure Variable screen positions
No.3941-17/20
LC7441N, 7441NE
control sub-screen position determined SCK/FVP SD/FHP input levels shown following figure.(SCK/FVP, SD/FHP)
YWK0 YWK5, RWK0 RWK5 BWK0 BWK5 used frame color. white frame corresponds YWK, data values 110000, 100000 100000, respectively. control frame, which always white, when input HIGH, OFF, when LOW. Serial control, single screen frame when input HIGH, OFF, LOW. frame color using frame-color registers when WKVAR HIGH, white, when LOW. When register FILD HIGH, field screen displayed; when LOW, frame screen displayed. Serial control, dual-screen screen frame when HIGH, OFF, when LOW. screen frame when HIGH, OFF, when LOW. screen frame color using frame-color registers when WKVAR1 HIGH, white, when LOW. screen frame color using framecolor registers when WKVAR2 HIGH, white, when LOW. Wipe Function wipe function allows gradual display erasure sub-screen when serial control, single-screen mode. Wipe direction using VWIPE HWIPE registers shown following table. When wiping OFF, sub-screen turns instantaneously, otherwise screen display erasure occurs stages over approximately second. Note that screen erasure reverse sequence display.
Operation
Serial control, single screen sub-screen position variable when POSVAR HIGH, fixed, when LOW. fixed screen position determined FVPR FHPR address shown following figure.
Serial control, dual screen screen position fixed, determined FVPR FHPR address screen position variable, determined HP5. Sub-screen Frame sub-screen, screens, have frame, white frame colored frame. converter registers
VWIPE HWIPE
HIGH
HIGH
HIGH
HIGH
No.3941-18/20
LC7441N, 7441NE
Dual-screen Priority When dual screens overlap vertically, priority screen display determined register. higher screen priority when HIGH, lower screen, when shown following figure. When higher screen priority, lower screen OFF, when lower screen priority, higher
screen display ends first overlapped screen line. Note that prioritized display occurs even screens superimpose that side-by-side sub-screens cannot displayed.
Note dotted areas display. Multi-system Display Multi-system mode selected when register HIGH, single-system mode, when LOW. multisystem mode, fixed vertical positions correspond main-screen system, single-system mode, sub-screen system, shown following table.
register HIGH HIGH
NTSC/PAL Input HIGH HIGH
198H 158H 158H 198H
No.3941-19/20
LC7441N, 7441NE
sub-screen expands vertically multi-system display NTSC sub-screen contracts because systems different number scan lines. These changes sub-screen aspect ratios corrected using RAR(Revise Aspect Ratio) register, shown following figure. When HIGH, horizontal clock frequency adjusted correct aspect ratio.
Specifications SANYO products described contained herein stipulate performance, characteristics, functions described products independent state, guarantees performance, characteristics, functions described products mounted customer's products equipment. verify symptoms states that cannot evaluated independent device, customer should always evaluate test devices mounted customer's products equipment. SANYO Electric Co., Ltd. strives supply high-quality high-reliability products. However, semiconductor products fail with some probability. possible that these probabilistic failures could give rise accidents events that could endanger human lives, that could give rise smoke fire, that could cause damage other property. When designing equipment, adopt safety measures that these kinds accidents events cannot occur. Such measures include limited protective circuits error prevention circuits safe design, redundant design, structural design. event that SANYO products(including technical data,services) described contained herein controlled under applicable local export control laws regulations, such products must expor without obtaining expor license from authorities concerned accordance with above law. part this publication reproduced transmitted form means, electronic mechanical, including photocopying recording, information storage retrieval system, otherwise, without prior written permission SANYO Electric Co., Ltd. information described contained herein subject change without notice product/technology improvement, etc. When designing equipment, refer "Delivery Specification" SANYO product that intend use. Information (including circuit diagrams circuit parameters) herein example only guaranteed volume production. SANYO believes information herein accurate reliable, guarantees made implied regarding infringements intellectual property rights other rights third parties.
This catalog provides information October, 2001. Specifications information herein subject change without notice.
No.3941-20/20

LC7441N, 7441NE Picture-in-picture Controller VCRs Prelimina

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