LE25LB642CT Serial EEPROM (SPI Bus)(64Kbit) LE25LB642CT 64Kb
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Ordering number ENA1471
LE25LB642CT
Serial EEPROM (SPI Bus)(64Kbit)
LE25LB642CT 64Kbit EEPROM that supports serial peripheral interface (SPI). realizes high speed operation high level reliability incorporating SANYO's high performance CMOS EEPROM technology. interface compatible with protocol, therefore, best suited applications that require small-scale rewritable nonvolatile parameter memory. Moreover, LE25LB642CT bytes page rewrite function that provides rapid data rewriting.
Features
Capacity Single supply voltage Serial interface Operating clock frequency current dissipation Page write function Rewrite time Number rewrite times Data retention period High reliability 64Kbits 1.8V 3.6V Mode0, Mode3 supported 5MHz (2.5V 3.6V), 3MHz (1.8V 3.6V) Standby (max.) Active (Read) (max.) Active (Rewrite) (max.) 32bytes 10ms times/Page(Page=32Byte) 20years Adopts SANYO's proprietary symmetric memory array configuration (USP6947325) Incorporates feature prohibit write operations under voltage conditions.
This product licensed from Silicon Storage Technology, Inc. (USA), manufactured sold SANYO Semiconductor Co., Ltd.
SANYO Semiconductor Co.,Ltd. products described contained herein are, with regard "standard application", intended general electronics equipment (home appliances, equipment, communication device, office equipment, industrial equipment etc.). products mentioned herein shall intended "special application" (medical equipment whose purpose sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level reliability directly threaten human lives case failure malfunction product cause harm human bodies, shall they grant guarantee thereof. should intend products applications outside standard applications customer considering such and/or outside scope intended standard applications, please consult with prior intended use. there consultation inquiry before intended use, customer shall solely responsible use. Specifications SANYO Semiconductor Co.,Ltd. products described contained herein stipulate performance, characteristics, functions described products independent state, guarantees performance, characteristics, functions described products mounted customer' products equipment. verify symptoms states that cannot evaluated independent device, customer should always evaluate test devices mounted customer' products equipment.
51309 /20090401-S00009 No.NA1471-1/14
LE25LB642CT
Assignment
Bottom view
Descriptions
PIN.1 PIN.2 HOLD Power supply Hold Serial clock Serial data input Ground Write protect Serial data output Chip select
PIN.3 PIN.4 PIN.5
PIN.6 PIN.7 PIN.8
1.52 1.02 0.35(max)
Block Diagram
ADDRESS BUFFERS LATCHES
XDECODER
EEPROM Cell Array
Y-DECODER
CONTROL LOGIC
BUFFERS DATA LATCHES
SERIAL INTERFACE
HOLD
Specifications
Absolute Maximum Rating/If electrical stress exceeding maximum rating applied, device damaged.
Parameter Storage temperature Supply voltage input voltage Overshoot voltage (below 20ns) Symbol Conditions Ratings +150 -0.5 -0.5 VDD+0.5 -1.0 VDD+0.5 Unit
Operating Conditions
Parameter Operating temperature Operating supply voltage Symbol Conditions Ratings Unit
Electrical Characteristics
Parameter Supply current when reading Symbol ICCR Conditions 0.1VDD, HOLD 0.9VDD 0.1VDD/0.9VDD, Open Operating frequency 5MHz, 3.6V 0.1VDD, HOLD 0.9VDD 0.1VDD/0.9VDD, Open Operating frequency 5MHz, 2.5V 0.1VDD, HOLD 0.9VDD 0.1VDD/0.9VDD, Open Operating frequency 3MHz, 1.8V Supply current when writing ICCW 3.6V., 0.1VDD/0.9VDD, tWC=10ms Unit
No.NA1471-2/14
LE25LB642CT
CMOS standby current VDD, 3.6V VDD, 2.5V Input leakage current Output leakage current Input voltage Input high voltage Output voltage VOL1 VOL2 VOL3 Output high voltage VOH1 VOH2 VOH3 VDD, max. VDD, max. max. min. 2.0mA, 3.6V 1.5mA, 2.5V 0.15mA, 1.8V -2.0mA, 3.6V -0.4mA, 2.5V -0.1mA, 1.8V 0.8VDD 0.8VDD 0.8VDD -0.3 0.7VDD 0.3VDD VDD+0.3
Capacitance 25°C, 1.0MHz
Parameter Output capacitance Input capacitance Symbol Conditions Unit
Note These parameters sampled 100% tested.
Electrical Characteristics
Input pulse level Input pulse rise/fall time Output detection voltage Output load 10ns 30pF
Characteristics FCLK 5MHz)/VDD 2.5V 3.6V
Parameter Clock frequency logic high level pulse width logic level pulse width Input signal rise/fall time setup time setup time Data setup time Data hold time hold time hold time standby pulse width output high impedance time output data time Output data hold time setup time hold time HOLD setup time HOLD hold time HOLD output impedance time HOLD output high impedance time Write cycle time output impedance time Symbol FCLK tCLHI tCLLO tCSS tCLS tCSH tCLH tCPH tCHZ tWPS tWPH tHLz tHHz tCLZ Conditions Unit
No.NA1471-3/14
LE25LB642CT
Characteristics FCLK 3MHz)/VDD 1.8V 3.6V
Parameter Clock frequency logic high level pulse width logic level pulse width Input signal rise/fall time setup time setup time Data setup time Data hold time hold time hold time standby pulse width output high impedance time output data time Output data hold time setup time hold time HOLD setup time HOLD hold time HOLD output impedance time HOLD output high impedance time Write cycle time output impedance time Symbol FCLK tCLHI tCLLO tCSS tCLS tCSH tCLH tCPH tCHZ tWPS tWPH tHLz tHHz tCLZ Conditions Unit
Table Command Settings
Command Write enable (WREN) Write disable (WRDI) Status register read (RDSR) Status register write (WRSR) Read (READ) Write (WRITE) Explanatory notes Table following each code indicates that number given hexadecimal notation. Addresses commands "don't care." "PD" stands page program data. amount data from bytes input. cycle DATA A15-A8 A15-A8 A7-A0 A7-A0 cycle cycle cycle cycle cycle cycle
No.NA1471-4/14
LE25LB642CT
Figure Serial Input Timing
(SPI Mode
tCPH
tCLS tCSS tCLHI tCLLO tCSH tCLH
DATA VALID
(SPI Mode
High Impedance
High Impedance
tCPH
tCLS tCSS tCLLO tCLHI tCSH tCLH
DATA VALID
High Impedance
High Impedance
No.NA1471-5/14
LE25LB642CT
Figure Serial Output Timing
(SPI Mode
tCLZ DATA VALID tCHZ
(SPI Mode
tCLZ DATA VALID tCHZ
No.NA1471-6/14
LE25LB642CT
Description Commands Their Operations
"Table Command Settings" provides list overview commands. detailed description functions operations corresponding each command presented below.
Read (READ)
Consisting first through third cycles, read command inputs 16-bit addresses following (03h), data designated addresses output synchronized SCK. data output from falling edge third cycle bit0 reference. "Figure READ" shows timing waveforms. When input continuously after read command been input data designated addresses been output, address automatically incremented inside device while being input, corresponding data output sequence. input continued after internal address arrives highest address, internal address returns lowest address (0000h), data output continued. setting logic level high, device deselected, read cycle ends. While device deselected, output high-impedance state.
Figure READ
Mode3
Mode0 8CLK
(00000011)
Add.
(A15-A8)
Add.
(A7-A0)
High Impedance
Data Out(N) Data Out(N+1)
Addresses "don't care." synchronization with rising edges clock signals, command identified addresses taken through synchronization with falling edges clock signal later, data output
No.NA1471-7/14
LE25LB642CT
Status Registers
status registers read operating setting statuses inside device from outside (status register read) protect information (status register write). There bits total, "Table Status Registers" gives significance each bit.
Table Status Registers
Bit0 Name Logic Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 SRWP Reserved Reserved Reserved Status register write enabled Status register write disabled Block protect information status register description Function Ready Busy write operation) Write disabled Write enabled Nonvolatile information Nonvolatile information Nonvolatile information Power-on time Information
2-1. Status Register Read (RDSR)
contents status registers read using status register read command. This command executed even during write operation. "Figure Status Register READ" shows timing waveforms status register read. Consisting only first cycle, status register command outputs contents status registers synchronized falling edge clock (SCK) with which eighth (05h) been input. terms output sequence, SRWP (bit7) first output, each time clock input, other bits (bit0) output sequence, synchronized falling clock edge. clock input continued after (bit0) been output, data output returning (SRWP) that first output, after which output repeated long clock input continued. data read status register read command time.
Figure Status Register Read
Mode3
Mode0 8CLK
(00000101)
Hight Impedance
Status Register
No.NA1471-8/14
LE25LB642CT
2-2. Status Register Write (WRSR)
information status registers BP0, BP1, SRWP rewritten using status register write command. RDY, WEN, bit4, bit5, bit6 read-only bits cannot rewritten. information bits BP0, BP1, SRWP stored non-volatile memory, when written these bits, contents retained even power-down. "Figure Status Register Write" shows timing waveforms status register write, Figure shows status register write flowchart. Consisting first second cycles, status register write command initiates internal write operation rising edge after data been input following (01h). operation this command, information bits BP0, BP1, SRWP rewritten. Since bits (bit0), (bit1), bit4, bit5, bit6 status register cannot written, problem will arise attempt made them value when rewriting status register. Status register write ends detected status register read. Information status register rewritten 1,000 times (min.). initiate status register write, logic level must high status register must "1".
Figure Status Register Write
Self-timed Write Cycle tSRW
tWPS tWPH
Mode3
Mode0 8CLK
(00000001)
DATA
Hight Impedance
2-3. Contents Each Status Register
(bit0) Ready/Busy detection register detecting write end. When "1", device busy state, when "0", means that write operation completed. (bit1) Write enable register detecting whether device perform write operations. "0", device will perform write operation even write command input. "1", device perform write operation area that block-protected. controlled using write enable write disable commands. inputting write enable command (06h), "1", inputting write disable command (04h), "0". following states, automatically order protect against unintentional writing. power-on Upon completion write Upon completion status register write write operation been performed inside device because, instance, command input write operations failed write operation been performed protected address, will retain status established prior issue command concerned. Furthermore, state will changed read operation.
No.NA1471-9/14
LE25LB642CT
BP0, (bits2, Block Protect Settings Block protect status register bits that rewritten, memory space protected depending these bits. setting conditions, refer "Table Protect Level Setting Conditions."
Table Protect Level Setting Conditions
Status Register Bits Protection Block (Level) (Whole area unprotected) (Upper area protected) (Upper area protected) (Whole area protected) Protected Area None 1800h 1FFFh 1000h 1FFFh 0000h 1FFFh
SRWP (bit7) Status Register Write Protect Settings Status register write protect SRWP protecting status registers, information rewritten. When SRWP logic level low, status register write command ignored, status registers BP0, BP1, BP2, SRWP protected. When logic level high, status registers protected regardless SRWP state. SRWP setting conditions shown "Table SRWP Setting Conditions."
Table SRWP Setting Conditions
SRWP Hardware protected (HPM) Protected Protected Unprotected Software protected (SPM) Unprotected Protected Unprotected Mode Status Register Protected Area Unprotected Area
Bit4, bit5, bit6 reserved bits, have significance.
Write Enable (WREN)
Before performing operations listed below, device must placed write enable state. Operation same setting status register "1", state enabled inputting write enable command. "Figure Write Enable" shows timing waveforms when write enable operation performed. write enable command consists only first cycle, initiated inputting (06h). Write (WRITE) Status register write (WRSR)
Write Disable (WRDI)
write disable command sets status register prohibit unintentional writing. "Figure Write Disable" shows timing waveforms. write disable command consists only first cycle, initiated inputting (04h). write disable state (WEN "0") exited setting using write enable command (06h).
Figure Write Enable
Mode3
Figure Write Disable
Mode3
Mode0 8CLK
(00000110)
Mode0 8CLK
(00000100)
High Impedance
High Impedance
No.NA1471-10/14
LE25LB642CT
Write (WRITE)
LE25LB642CT enables pages with 32bytes written. number bytes from 32bytes written within same sector page (page addresses A5). "Figure Write" shows write timing waveforms, Figure shows write flowchart. After falling edge, command (02H) input followed 16-bit addresses (Add). write data then loaded until rising edge, internal addresses incremented (Add+1) every time data loaded 1-byte increments. data loading continues until rising edge. data loaded exceeded 32bytes, 32bytes loaded last written. write data must loaded 1-byte increments, write operation performed rising edge occurring other timing. write time 10ms (max.) when 32bytes (1page) written time.
Figure Write
Self-timed Write Cycle
Mode3
Mode0 8CLK
(00000010)
Add.
(A15-A8)
Add.
(A7-A0)
(N+1)
(N+2)
(N+31)
High Impedance
Addresses "don't care."
Hold Function
Using HOLD pin, hold function suspends serial communication places hold status). "Figure HOLD" shows timing waveforms. device placed hold status falling HOLD edge while logic level low, exits from hold status rising HOLD edge. When logic level high, HOLD must rise fall. hold function takes effect when logic low, hold status exited serial communication reset rising edge. hold status, output high-impedance state, "don't care."
Figure HOLD
Active HOLD Active
HOLD
tHHZ tHLZ High Impedance
No.NA1471-11/14
LE25LB642CT
Hardware Data Protection
order protect against unintentional writing power-on, LE25LB642CT incorporates power-on reset function.
Software Data Protection
This product eliminates possibility unintentional operations recognizing commands under following conditions. When write command input rising edge timing cycle (8CLK units SCK). When write data 1-byte increments. When status register write command input 2bus cycles more.
Power-on
order protect against unintentional writing, must kept power-on. After power-on, supply voltage stabilized 1.8V higher, wait (tPU_READ) before inputting command start read operation. Similarly, wait 10ms (tPU_WRITE) after supply voltage stabilized 1.8V higher before inputting command start write operation.
Decoupling Capacitor
A0.1F ceramic capacitor must provided each device connected between order ensure that device will operate stably.
No.NA1471-12/14
LE25LB642CT
Figure Status Register Write Flowchart Figure Write Flowchart
Status register write Start write enable command Write Start write enable command
Data
status register write command Address Address write command
Program start rising edge
Data status register read command Data Data
status register write Write start rising edge
status register read command
*Automatically placed write disabled state status register write.
write *Automatically placed write disabled state write.
No.NA1471-13/14
LE25LB642CT
Application Note
Precautions Power-on order protect against unintentional writing, LE25LB642CT incorporates power-on rest circuit. following conditions must order ensure that power-on reset circuit will operate stably. guarantees given data event instantaneous power failure occurring during write operation.
Symbol tRISE tOFF Vbot Power rise time Power time Power bottom voltage Item 3.6V Unit
tRISE
tOFF Vbot
Note: must high.
SANYO Semiconductor Co.,Ltd. assumes responsibility equipment failures that result from using products values that exceed, even momentarily, rated values (such maximum ratings, operating condition ranges, other parameters) listed products specifications SANYO Semiconductor Co.,Ltd. products described contained herein. SANYO Semiconductor Co.,Ltd. strives supply high-quality high-reliability products, however, semiconductor products fail malfunction with some probability. possible that these probabilistic failures malfunction could give rise accidents events that could endanger human lives, trouble that could give rise smoke fire, accidents that could cause damage other property. When designing equipment, adopt safety measures that these kinds accidents events cannot occur. Such measures include limited protective circuits error prevention circuits safe design, redundant design, structural design. event that SANYO Semiconductor Co.,Ltd. products described contained herein controlled under applicable local export control laws regulations, such products require export license from authorities concerned accordance with above law. part this publication reproduced transmitted form means, electronic mechanical, including photocopying recording, information storage retrieval system, otherwise, without prior written consent SANYO Semiconductor Co.,Ltd. information described contained herein subject change without notice product/technology improvement, etc. When designing equipment, refer "Delivery Specification" SANYO Semiconductor Co.,Ltd. product that intend use. Information (including circuit diagrams circuit parameters) herein example only; guaranteed volume production. Upon using technical information products described herein, neither warranty license shall granted with regard intellectual property rights other rights SANYO Semiconductor Co.,Ltd. third party. SANYO Semiconductor Co.,Ltd. shall liable claim suits with regard third party's intellctual property rights which resulted from technical information products mentioned above.
This catalog provides information May, 2009. Specifications information herein subject change without notice.
No.NA1471-14/14
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