LE24LB642CS Wire Serial Interface EEPROM (64k EEPROM) LE24LB

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LE24LB642CS Wire Serial Interface EEPROM (64k EEPROM) LE24LB

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Ordering number ENA1464A
LE24LB642CS
Wire Serial Interface EEPROM (64k EEPROM)
LE24LB642CS 2-wire serial interface EEPROM. realizes high speed high level reliability incorporating SANYO's high performance CMOS EEPROM technology. This device compatible with memory protocol, therefore best suited application that requires small-scale re-writable nonvolatile parameter memory.
Functions
Capacity: bits bits) Single supply voltage: 1.7V 3.6V Interface: wire serial interface (I2C Bus*) slave addresses: S2=0, S1=0, S0=0 Operating clock frequency: 400kHz power consumption Standby: (max) Active (Read): 0.5mA (max) Automatic page write mode: Bytes Read mode: Sequential read random read Erase/Write cycles: cycles Data Retention: years High reliability: Adopts SANYO's proprietary symmetric memory array configuration (USP6947325) Noise filters connected pins Incorporates feature prohibit write operations under voltage conditions. Package LE24LB642CS-TL WLP6
trademark Philips Corporation. This product licensed from Silicon Storage Technology, Inc. (USA), manufactured sold SANYO Semiconductor Co., Ltd.
SANYO Semiconductor Co.,Ltd. products described contained herein are, with regard "standard application", intended general electronics equipment (home appliances, equipment, communication device, office equipment, industrial equipment etc.). products mentioned herein shall intended "special application" (medical equipment whose purpose sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level reliability directly threaten human lives case failure malfunction product cause harm human bodies, shall they grant guarantee thereof. should intend products applications outside standard applications customer considering such and/or outside scope intended standard applications, please consult with prior intended use. there consultation inquiry before intended use, customer shall solely responsible use. Specifications SANYO Semiconductor Co.,Ltd. products described contained herein stipulate performance, characteristics, functions described products independent state, guarantees performance, characteristics, functions described products mounted customer' products equipment. verify symptoms states that cannot evaluated independent device, customer should always evaluate test devices mounted customer' products equipment.
61009 51309 20090401-S00007 No.A1464-1/11
LE24LB642CS
Assignment
Bottom view
PIN.1 Nonconnected Ground Power supply Write protect Serial clock input Serial data input/output
Descriptions
PIN.2 PIN.3 PIN.4
PIN.5 PIN.6
1.50 1.06 0.50(max)
Block Diagram
Input buffer Condition detector Serial controller
Write controller
High voltage generator
Address generator
decoder
EEPROM Array
buffer
decoder Sense
Serial-parallel converter
Specifications
Absolute Maximum Ratings
Parameter Supply voltage input voltage Over-shoot voltage Storage temperature Tstg Below 20ns Symbol Conditions Ratings -0.5 +4.6 -0.5 VDD+0.5 -1.0 VDD+1.0 +150 unit
Note: electrical stress exceeding maximum rating applied, device damaged.
Operating Conditions
Parameter Operating supply voltage Operating temperature Symbol Conditions Ratings unit
No.A1464-2/11
LE24LB642CS
Electrical Characteristics
Parameter Supply current reading Supply current writing Standby current Input leakage current Output leakage current (SDA) Input voltage Input voltage (CMOS) Input high voltage Input high voltage (CMOS) Output voltage Symbol ICC1 ICC2 VILC VIHC IOL=0.7mA, VDD=1.7V IOL=2.0mA, VDD=2.5V VDD*0.8 VDD-0.2 f=400kHz f=400kHz VIN=VDD VIN=GND VOUT=GND -2.0 -2.0 Conditions VDD=1.7V 3.6V +2.0 +2.0 VDD*0.2 unit
Capacitance/Ta=25°C, f=1MHz
Parameter In/Output capacitance Input capacitance Symbol CI/O VI/O=0V (SDA) VIN=0V (other than SDA) Conditions unit
Note: This parameter sampled 100% tested.
Electric Characteristics
Input pulse level Input pulse rise fall time Output detection voltage Output load 20ns 50pF+Pull resistor 3.0k
R=3.0k
C=50pF
Output Load Circuit
Parameter Slave mode clock frequency clock time clock high time output delay time data output hold time Start condition setup time Start condition hold time Data setup time Data hold time Stop condition setup time rise time fall time release time Noise suppression time Write cycle time
Symbol fSCLS tLOW tHIGH tSU.STA tHD.STA tSU.DAT tHD.DAT tSU.STO tBUF 1200 1200
VDD=1.7V 3.6V
unit
No.A1464-3/11
LE24LB642CS
Timing
tHIGH tLOW tHD.STA tHD.DAT tSU.DAT tSU.STO SDA/OUT tBUF
tSU.STA SDA/IN
Write Timing
Write Data
Acknowledge
Stop condition
Start condition
Functions
(serial clock input) serial clock input that processes signals rising falling edges clock signals. (serial data input/output) used transfer serial data input/output, consists signal input n-channel transistor open drain output pin. Like pin, must pulled resistor level wired-ORed with open drain open collector) output device use. (write protect) When high, write protection enabled, writing into memory areas prohibited. When low, writing possible memory areas. Read operations performed regardless status.
No.A1464-4/11
LE24LB642CS
Functional Description
Start condition When line high level, start condition established changing line from high low. operation EEPROM slave starts start condition. Stop condition When line high level, stop condition established changing line from high. When device read sequence, read operation suspended when stop condition received, device standby mode. When write sequence, capture write data ended when stop condition received, EEPROM internal write operation started.
tSU.STA tHD.STA tSU.STO
Start condition
Stop condition
Data transfer Data transferred changing line while line low. When line changed while line high, resulting condition will recognized start stop condition.
tSU.DAT tHD.DAT
Acknowledge During data transfer, 8-bits transferred succession, then ninth clock cycle period device system receiving data sets line low, sends acknowledge signal indicating that data been received. acknowledge signal sent during EEPROM internal write operation.
(EEPROM input)
(Master output) Acknowledge output Start condition
(EEPROM output)
No.A1464-5/11
LE24LB642CS
Device addressing purposes communication, master device system generates start condition slave device. Communication with particular slave device enabled sending along device address, which 7-bits long, read/write command code, which long, immediately following start condition. upper four bits device address called device code which, this product, fixed "1010." This device upper 3-bit Slave Device address Slave address (S0, S2), which fixed inside. value Slave address S0=0, S1=0, S2=0. When device code input from slave addresses compared with product's device code slave addresses that were mounting stage found match, product sends acknowledge signal during ninth clock cycle period, initiates read write operation accordance with read write command code. they match, EEPROM returns standby mode. When read operation performed immediately after slave device been switched, random read command must used.
Slave Address
Device Code LE24LB642CS
Device address word
EEPROM write operation 6-1. Byte writing When EEPROM receives 7-bit device address write command code after start condition, generates acknowledge signal. After this, receives 3-bit don't-care bits 13-bit word address, generates acknowledge signal, receives 8-bit writing data, generates acknowledge signal when receives stop condition, rewrite operation EEPROM designated memory address will start. Rewriting completed period after stop condition. During EEPROM rewrite operation, input accepted acknowledge signals generated.
Word Address Start Data Stop don't care
6-2. Page writing This product enables pages with bytes written. basic data transfer procedure same byte writing: Following start condition, 9-bit device address write command code "0," word address (n), data input this order while confirming acknowledge every bits. page write mode established after data input, write data (n+1) input without inputting stop condition. After this, write data equivalent largest page size received continuous process repeating receiving 8-bit write data generating acknowledge signals. point when write data (n+1) been input, lower bits (A0-A4) word addresses automatically incremented form (n+1) address. this way, write data successively input, word address page incremented each time write data input. write data exceeds bytes last address page exceeded, word address page rolled over. Write data will input into same address more times, such cases write data that input last will take effect. Finally, EEPROM internal write operation corresponding page size which write data received starts from designated memory address when stop condition received.
No.A1464-6/11
LE24LB642CS
Word Address(n) Start Data(n)
Data(n+x)
Data(n+1)
don't care
6-3. Acknowledge polling Acknowledge polling used find when EEPROM internal write operation completed. When stop condition received EEPROM starts rewriting, operations prohibited, response given signals sent master device. Therefore, order find when EEPROM internal write operation completed, start condition, device address write command code sent from master device EEPROM (slave device), response slave device detected. other words, slave device does send acknowledge signal, means that internal write operation progress; conversely, does send acknowledge signal, means that internal write operation been completed. When codes sent master device during acknowledge polling, write random read performed next, write command executed. current read sequential read performed next, read command executed. After write command executed ACK="L" confirmed, start condition/stop condition entered cancel command change standby mode.
During Write Start Start During Write Start Write
EEPROM read operations 7-1. Current address reading address equivalent memory address accessed last held internal address EEPROM both write* read operations. Therefore, provided that master device recognized position EEPROM address pointer, data read from memory address with current address pointer without specifying word address. with writing, current address reading involves receiving 7-bit device address read command code following start condition, which time EEPROM generates acknowledge signal. After this, 8-bit data (n+1) address output serially starting with highest bits. After bits have been output, sending acknowledge signal inputting stop condition, EEPROM completes read operation standby mode. previous read address last address, address current address reading rolled over become address write data more bytes less than bytes, current address after page writing address equivalent number bytes written specified word address write data more bytes, designated word address. last address (A4-A0=11111b) page been designated byte write word address, first address (A4-A0=00000b) page serves internal address after writing.
Device Address Start Data(n+1) Stop
No.A1464-7/11
Stop
LE24LB642CS
7-2. Random read Random read mode which selected memory address specified data read. address specified dummy write input. First, when EEPROM receives 7-bit device address write command code following start condition, generates acknowledge signal. then receives 3-bit don't-care bits 13-bit word address generates acknowledge signal. These operations used load word address address counter EEPROM. Next, start condition input again, current read performed. This generates word address data that input using dummy write input. After data generated, stop condition input without input acknowledge signal, reading completed, standby mode established.
Device Address Start Word Address(n)
Dummy Write
Device Address Start
Data(n) Stop don't care Stop
Current Read
7-3. Sequential read this mode, data read continuously, sequential read operations performed with both current address read random read. after 8-bit data been output, acknowledge input reading continued without issuing stop condition, address incremented, data next address output. acknowledge continues input after data been output this way, data successively output while address incremented. When last address reached, rolled over address data continues read. with current address read random read, operation completed inputting stop condition without sending acknowledge signal.
Device Address Start Data(n) Data(n+1) Data(n+2) Data(n+x)
No.A1464-8/11
LE24LB642CS
Application Notes Software reset function Software reset (start condition dummy clock cycles start condition), shown figure below, executed order avoid erroneous operation after power-on reset while command input sequence. During dummy clock input period, must opened (set high pull-up resistor). Since possible output read data output from EEPROM during dummy clock period, forcibly entering will result overcurrent flow. Note that this software reset function does work during internal write cycle.
Dummy clock cycle
Start condition Start condition
Pull-up resistor demands protocol function, must connected pull-up resistor (with resistance from several several tens without fail. appropriate value must selected this resistance (RPU) basis microcontroller other devices controlling this product well VOL-IOL characteristics product. Generally, when resistance high, operating frequency will restricted; conversely, when low, operating current consumption will increase. maximum resistance maximum resistance must such that potential, which determined total (IL) input leaks devices connected RPU, completely satisfy input high level (VIH min) microcontroller EEPROM. However, resistance value that satisfies rise time fall time must set. maximum value (VDD VIH)/IL Example: When VDD=2.5V maximum value (2.5V 2.5V 0.8)/2A 250k minimum value resistance corresponding low-level output voltage (VOL max) SANYO's EEPROM must set. minimum value (VDD VOL)/IOL Example: When VDD=2.5V, 0.4V minimum value (2.5V 0.4)/1mA 2.1k Recommended setting strike good balance between operating frequency requirements power consumption. assumed that load capacitance 50pF output data strobe time 500ns, will about 500ns/50pF 10k.
EEPROM Master device CBUS
No.A1464-9/11
LE24LB642CS
Notes write protect operation This product prohibits writing when high. ensure full write protection, high periods from start condition stop condition, conditions below must satisfied.
Item Setup time Hold time Symbol tSU.WP tHD.WP VDD=1.7 3.6V unit
tSU.WP
tHD.WP
Start condition
Stop condition
Precautions when turning power This product contains power-on reset circuit preventing inadvertent writing data when power turned following conditions must order ensure stable operation this circuit. data guarantees given event instantaneous power failure during internal write operation.
Item Power rise time Power time Power bottom voltage Symbol tRISE tOFF Vbot VDD=1.7 3.6V unit
tRISE
tOFF Vbot
Notes: must high high. Steps must taken ensure that pins placed high-impedance state. possible satisfy instruction Note above, during power rise After power stabilized, pins must controlled shown below, with both pins high.
tLOW
tSU.DAT
tSU.DAT
No.A1464-10/11
LE24LB642CS
possible satisfy instruction Note above After power stabilized, software reset must executed. possible satisfy instructions both Note above After power stabilized, steps must executed, then software reset must executed. Noise filter pins This product contains filter circuit eliminating noise pins. Pulses 100ns less recognized because this function. Function inhibit writing when supply voltage This product contains supply voltage monitoring circuit that inhibits inadvertent writing below guaranteed operating supply voltage range. data protected ensuring that write operations started voltages (typ.) 1.3V below. Slave address settings This product does come with slave address pins, information slave addresses held internally. were slave addresses before shipment. During device addressing, these slave address codes must executed following device code.
SANYO Semiconductor Co.,Ltd. assumes responsibility equipment failures that result from using products values that exceed, even momentarily, rated values (such maximum ratings, operating condition ranges, other parameters) listed products specifications SANYO Semiconductor Co.,Ltd. products described contained herein. SANYO Semiconductor Co.,Ltd. strives supply high-quality high-reliability products, however, semiconductor products fail malfunction with some probability. possible that these probabilistic failures malfunction could give rise accidents events that could endanger human lives, trouble that could give rise smoke fire, accidents that could cause damage other property. When designing equipment, adopt safety measures that these kinds accidents events cannot occur. Such measures include limited protective circuits error prevention circuits safe design, redundant design, structural design. event that SANYO Semiconductor Co.,Ltd. products described contained herein controlled under applicable local export control laws regulations, such products require export license from authorities concerned accordance with above law. part this publication reproduced transmitted form means, electronic mechanical, including photocopying recording, information storage retrieval system, otherwise, without prior written consent SANYO Semiconductor Co.,Ltd. information described contained herein subject change without notice product/technology improvement, etc. When designing equipment, refer "Delivery Specification" SANYO Semiconductor Co.,Ltd. product that intend use. Information (including circuit diagrams circuit parameters) herein example only; guaranteed volume production. Upon using technical information products described herein, neither warranty license shall granted with regard intellectual property rights other rights SANYO Semiconductor Co.,Ltd. third party. SANYO Semiconductor Co.,Ltd. shall liable claim suits with regard third party's intellctual property rights which resulted from technical information products mentioned above.
This catalog provides information June, 2009. Specifications information herein subject change without notice.
No.A1464-11/11

LE24LB642CS Wire Serial Interface EEPROM (64k EEPROM) LE24LB

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