LC87F1JJ8A CMOS FROM 192K byte, 24576 byte on-chip 8-bit 1-c

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LC87F1JJ8A CMOS FROM 192K byte, 24576 byte on-chip 8-bit 1-c

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Ordering number ENA1455
LC87F1JJ8A
CMOS FROM 192K byte, 24576 byte on-chip
8-bit 1-chip Microcontroller with USB-host controller
LC87F1JJ8A 8-bit microcomputer that, centered around running minimum cycle time 83.3ns, integrates single chip number hardware features such 192K-byte flash (onboard programmable), 24576-byte RAM, on-chip debugger, sophisticated 16-bit timer/counter (may divided into 8-bit timers), 16-bit timer (may divided into 8-bit timers PWMs), four 8-bit timers with prescaler, base timer serving realtime clock, channels synchronous interface with automatic data transfer capabilities, asynchronous/synchronous interface, UART interface (full duplex), full-speed interface (host control function), 8-bit 12-channel converter, channels 12-bit PWM, system clock frequency divider, infrared remote control receiver circuit, 41-source 10-vector interrupt feature.
Features
Flash Capable on-board programming with wide range supply voltages: 5.5V Block-erasable byte units Writes data 2-byte units 196608 bits 24576 bits Cycle Time 83.3ns (When CF=12MHz) Note: cycle time here refers read speed.
This product licensed from Silicon Storage Technology, Inc. (USA), manufactured sold SANYO Semiconductor Co., Ltd.
SANYO Semiconductor Co.,Ltd. products described contained herein are, with regard "standard application", intended general electronics equipment (home appliances, equipment, communication device, office equipment, industrial equipment etc.). products mentioned herein shall intended "special application" (medical equipment whose purpose sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level reliability directly threaten human lives case failure malfunction product cause harm human bodies, shall they grant guarantee thereof. should intend products applications outside standard applications customer considering such and/or outside scope intended standard applications, please consult with prior intended use. there consultation inquiry before intended use, customer shall solely responsible use. Specifications SANYO Semiconductor Co.,Ltd. products described contained herein stipulate performance, characteristics, functions described products independent state, guarantees performance, characteristics, functions described products mounted customer' products equipment. verify symptoms states that cannot evaluated independent device, customer should always evaluate test devices mounted customer' products equipment.
Ver.1.02
52009HKIM 20090407-S00004 No.A1455-1/28
LC87F1JJ8A
Minimum Instruction Cycle Time (tCYC) 250ns (When CF=12MHz) Ports ports Ports whose direction designated 1-bit units (P10 P17, P27, P34, P73, PWM0, PWM1, XT2) Ports whose direction designated 4-bit units (P00 P07) ports (UHD+, UHD-) Dedicated oscillator ports (CF1, CF2) Input-only port (also used oscillation) (XT1) Reset (RES) Power supply pins (VSS1 VSS3, VDD1 VDD3) Timers Timer 16-bit timer/counter with capture registers. Mode 8-bit timer with 8-bit programmable prescaler (with 8-bit capture registers) channels Mode 8-bit timer with 8-bit programmable prescaler (with 8-bit capture registers) 8-bit counter (with 8-bit capture registers) Mode 16-bit timer with 8-bit programmable prescaler (with 16-bit capture registers) Mode 16-bit counter (with 16-bit capture registers) Timer 16-bit timer/counter that supports PWM/toggle outputs Mode 8-bit timer with 8-bit prescaler (with toggle outputs) 8-bit timer/ counter with 8-bit prescaler (with toggle outputs) Mode 8-bit with 8-bit prescaler channels Mode 16-bit timer/counter with 8-bit prescaler (with toggle outputs) (toggle outputs also possible from lower-order bits) Mode 16-bit timer with 8-bit prescaler (with toggle outputs) (lower-order bits used outputs) Timer 8-bit timer with 6-bit prescaler Timer 8-bit timer with 6-bit prescaler Timer 8-bit timer with 6-bit prescaler (with toggle outputs) Timer 8-bit timer with 6-bit prescaler (with toggle outputs) Base timer clock selectable from subclock (32.768kHz crystal oscillation), system clock, timer prescaler output. Interrupts programmable different time schemes SIO0: Synchronous serial interface first/MSB first mode selectable Transfer clock cycle: 512/3 tCYC Automatic continuous data transmission bits, specifiable 1-bit units) (Suspension resumption data transmission possible byte units) SIO1: 8-bit asynchronous/synchronous serial interface Mode Synchronous 8-bit serial 3-wire configuration, tCYC transfer clocks) Mode Asynchronous serial (half-duplex, data bits, stop bit, 2048 tCYC baudrates) Mode mode (start bit, data bits, tCYC transfer clocks) Mode mode (start detect, data bits, stop detect) SIO4: Synchronous serial interface first/MSB first mode selectable Transfer clock cycle: 1020/3 tCYC Automatic continuous data transmission 8192 bytes, specifiable byte units) (Suspension resumption data transmission possible byte units word units) Auto-start-on-falling-edge function Clock polarity selectable CRC16 calculator circuit built
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No.A1455-2/28
LC87F1JJ8A
Continued from preceding page.
SIO9: Synchronous serial interface first/MSB first mode selectable Transfer clock cycle: 1020/3 tCYC Automatic continuous data transmission 8192 bytes, specifiable byte units) (Suspension resumption data transmission possible byte units word units) Auto-start-on-falling-edge function Clock polarity selectable CRC16 calculator circuit built Full Duplex UART Data length: 7/8/9 bits selectable Stop bits: bits continuous transmission mode) Baud rate: 16/3 8192/3 tCYC Converter: bits channels PWM: Multifrequency 12-bit channels Infrared Remote Control Receiver Circuit Noise rejection function (noise filter time constant: Approx. 120s when 32.768kHz crystal oscillator selected base clock) Supports data encoding systems such (Pulse Position Modulation) Manchester encoding. X'tal HOLD mode release function Interface (host control function) Compliant with full-speed (12M bps) specifications Supports transfer types (control transfer, bulk transfer, interrupt transfer, isochronous transfer). Audio Interface Sampling frequency (fs): Master clock frequency: 256fs/384fs clock selectable: 48fs/64fs Data length: 16/18/20/24 bits first/MSB first mode selectable format selectable Watchdog Timer Watchdog timer using external circuitry Interrupt reset signals selectable Clock Output Function output clock with clock rate 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 source oscillator clock selected system clock. output source oscillation clock subclock.
No.A1455-3/28
LC87F1JJ8A
Interrupts sources, vector addresses Provides three levels (low (L), high (H), highest (X)) multiplex interrupt control. interrupt requests level equal lower than current interrupt accepted. When interrupt requests more vector addresses occur same time, interrupt highest level takes precedence over other interrupts. interrupts same level, interrupt into smallest vector address takes precedence.
Vector Address 00003H 0000BH 00013H 0001BH 00023H 0002BH 00033H 0003BH 00043H 0004BH Level INT0 INT1 INT2/T0L/INT4/UHC active/remote control signal receive INT3/INT5/base timer T0H/INT6/UHC device attach/UHC device detach/UHC resume T1L/T1H/INT7/SIO9/AIF start SIO0/UART1 receive SIO1/SIO4/UART1 transmit/AIF ADC/T6/T7/UHC-ACK/UHC-NAK/UHC error/UHC-STALL Port error Interrupt Source
Priority levels interrupts same level, with smallest vector address takes precedence. Subroutine Stack Levels: 12288 levels maximum (The stack allocated RAM.) High-speed Multiplication/Division Instructions bits bits tCYC execution time) bits bits tCYC execution time) bits bits tCYC execution time) bits bits tCYC execution time) Oscillation Circuits oscillation circuit (internal): oscillation circuit: Crystal oscillation circuit: circuit (internal):
system clock system clock system clock, realtime clock interface (see Fig.5) audio interface (see Fig.
No.A1455-4/28
LC87F1JJ8A
Standby Function HALT mode: Halts instruction execution while allowing peripheral circuits continue operation. Oscillation halted automatically. There three ways releasing HALT mode. Setting reset lower level. System resetting watchdog timer Generating interrupt HOLD mode: Suspends instruction execution operation peripheral circuits. base clock generator, crystal oscillators automatically stop operation. There five ways releasing HOLD mode. Setting reset lower level System resetting watchdog timer Having interrupt source established INT0, INT1, INT2, INT4, INT5 pins INT0 INT1 pins must configured only level detection. Having interrupt source established port Having active interrupt source established host control circuit X'tal HOLD mode: Suspends instruction execution operation peripheral circuits except base timer. base clock generator, oscillator automatically stop operation. state crystal oscillation established when X'tal HOLD mode entered retained. There seven ways releasing X'tal HOLD mode. Setting reset level System resetting watchdog timer Having interrupt source established INT0, INT1, INT2, INT4, INT5 pins INT0 INT1 pins must configured only level detection. Having interrupt source established port Having interrupt source established base timer circuit Having active interrupt source established host control circuit Having interrupt source established infrared remote controller receiver circuit Package Form Lead-/Halogen-free type Development Tools On-chip debugger: TCB87- type LC87F1JJ8A Flash Programming Boards
Package Programming board W87F55256SQ
Flash Programmer
Maker Flash Support Group, Inc. (FSG) Flash Support Group, Inc. (FSG) SANYO(Note Single/ganged SANYO Onboard single/ganged Onboard single/ganged Single Model AF9708/ AF9709/AF9709B/AF9709C (including Ando Electric Co., Ltd. models) AF9101/AF9103(main unit) (FSG) SIB87(interface driver) (SANYO) SKK/SKK Type (SANYO FWS) SKK-DBG Type (SANYO FWS) Application version: 1.04 later Chip data version: 2.17 later LC87F1JJ8 (Note LC87F1JJ2A Rev. 03.12 later LC87F1JJ2A Supported Version Device
Note PC-less standalone onboard programming possible using onboard programmer (AF9101/AF9103) serial interface driver (SIB87) provided SANYO pair. Note Dedicated programming device program required depending programming conditions. Contact SANYO have questions difficulties regarding this matter.
No.A1455-5/28
LC87F1JJ8A
Package Dimensions
unit (typ) 3163B
(0.75) 0.18
0.15
1.7max
(1.5)
SANYO SQFP48(7X7)
Assignment
P27/INT5/SCK9 P26/INT5/SI9/WR9 P25/INT5/SO9/RD9 P24/INT5/INT7/SCK4 P23/INT4/SI4/WR P22/INT4/SO4/RD P21/INT4 P20/INT4/INT6 P07/AN7/T7O/LRCK P06/AN6/T6O/BCLK P05/AN5/CKO/SDAT P04/AN4/DBGP2 UHDUHD+ VDD3 VSS3 P34/UFILT P33/AFILT P31/URX1 P30/UTX1 P70/INT0/T0LCP/AN8 P71/INT1/T0HCP/AN9 P72/INT2/T0IN
LC87F1JJ8A
P03/AN3/DBGP1 P02/AN2/DBGP0 P01/AN1 P00/AN0 VSS2 VDD2 PWM0/MCLKO PWM1/MCLKI P17/T1PWMH/BUZ P16/T1PWML P15/SCK1 P14/SI1/SB1
P73/INT3/T0IN/RMIN XT1/AN10 XT2/AN11 VSS1 VDD1 P10/SO0 P11/SI0/SB0 P12/SCK0 P13/SO1
view
SANYO: "Lead-/Halogen-free type"
No.A1455-6/28
LC87F1JJ8A
SQFP48 NAME P73/INT3/T0IN/RMIN XT1/AN10 XT2/AN11 VSS1 VDD1 P10/SO0 P11/SI0/SB0 P12/SCK0 P13/SO1 P14/SI1/SB1 P15/SCK1 P16/T1PWML P17/T1PWMH/BUZ PWM1/MCLKI PWM0/MCLKO VDD2 VSS2 P00/AN0 P01/AN1 P02/AN2/DBGP0 P03/AN3/DBGP1 SQFP48 NAME P04/AN4/DBGP2 P05/AN5/CKO/SDAT P06/AN6/T6O/BCLK P07/AN7/T7O/LRCK P20/INT4/INT6 P21/INT4 P22/INT4/SO4/RD P23/INT4/SI4/WR P24/INT5/INT7/SCK4 P25/INT5/SO9/RD9 P26/INT5/SI9/WR9 P27/INT5/SCK9 UHDUHD+ VDD3 VSS3 P34/UFILT P33/AFILT P31/URX1 P30/UTX1 P70/INT0/T0LCP/AN8 P71/INT1/T0HCP/AN9 P72/INT2/T0IN
No.A1455-7/28
LC87F1JJ8A
System Block Diagram
Interrupt control
Standby control
FROM
X'tal
Clock generator
SIO0
interface
SIO1
Port
register
SIO4
Port
register
SIO9
Port
Timer
Port
Timer
Port INT0 INT7 noise filter UART1
Timer
Timer
Timer
Audio interface
Stack pointer
Timer
Infrared remote control receiver circuit
Watchdog timer
Base timer
On-chip debugger
PWM0
PWM1
host
No.A1455-8/28
LC87F1JJ8A
Description
Name VSS1,VSS2, VSS3 VDD1, VDD2 VDD3 Port power supply power supply reference voltage 8-bit ports specifiable 4-bit units Pull-up resistors turned 4-bit units. HOLD release input Port interrupt input functions converter input ports: AN7(P00 P07) On-chip debugger pins: DBGP0 DBGP2(P02 P04) P05: System clock output/audio interface SDAT input/output P06: Timer toggle output/audio interface BCLK input/output P07: Timer toggle output/audio interface LRCK input/output Port 8-bit ports specifiable 1-bit units Pull-up resistors turned 1-bit units. functions P10: SIO0 data output P11: SIO0 data input/bus input/output P12: SIO0 clock input/output P13: SIO1 data output Port 8-bit ports specifiable 1-bit units Pull-up resistors turned 1-bit units. functions P23: INT4 input/HOLD release input/timer event input/timer capture input/ timer capture input P27: INT5 input/HOLD release input/timer event input/timer capture input/ timer capture input P20: INT6 input/timer capture input P22: SIO4 data input/output/parallel interface output P23: SIO4 data input/output/parallel interface output P24: SIO4 clock input/output/INT7 input/timer capture input P25: SIO9 data input/output/parallel interface output P26: SIO9 data input/output/parallel interface output P27: SIO9 clock input/output Interrupt acknowledge types Rising INT4 INT5 INT6 INT7 5-bit ports specifiable 1-bit units Pull-up resistors turned 1-bit units. functions P30: UART1 transmit P31: UART1 receive P33: Audio interface filter circuit connection (See Fig. P34: interface filter circuit connection (See Fig. enable enable enable enable Falling enable enable enable enable Rising Falling enable enable enable enable level disable disable disable disable level disable disable disable disable P14: SIO1 data input/bus input/output P15: SIO1 clock input/output P16: Timer PWML output P17: Timer PWMH output/beeper output Description Option
Port
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No.A1455-9/28
LC87F1JJ8A
Continued from preceding page.
Name Port 4-bit ports specifiable 1-bit units Pull-up resistors turned 1-bit units. functions P70: INT0 input/HOLD release input/timer capture input/watchdog timer output P71: INT1 input/HOLD release input/timer capture input P72: INT2 input/HOLD release input/timer event input/timer capture input/ high speed clock counter input P73: INT3 input (input with noise filter)/timer event input/timer capture input/ infrared remote control receiver input converter input ports: AN8(P70), AN9(P71) Interrupt acknowledge types Rising INT0 INT1 INT2 INT3 enable enable enable enable Falling enable enable enable enable Rising Falling disable disable enable enable level enable enable disable disable level enable enable disable disable Description Option
PWM0 PWM1
PWM0, PWM1 output ports General-purpose input port functions PWM0: Audio interface master clock output PWM1: Audio interface master clock input
UHDUHD+
data UHD-/general-purpose port data UHD+/general-purpose port Reset 32.768kHz crystal oscillator input functions General-purpose input port converter input port: AN10 Must connected VDD1 when used. 32.768kHz crystal oscillator output functions General-purpose input port converter input port: AN11 Must configured oscillation kept open used.
Ceramic/crystal resonator input Ceramic/crystal resonator output
Port Output Types
table below lists types port outputs presence/absence pull-up resistor. Data read into input port even output mode.
Port Name Option Selected Units Option Type PWM0, PWM1 UHD+, UHDXT1 Nch-open drain CMOS CMOS CMOS Input only 32.768kHz crystal resonator output (Nch-open drain when general-purpose output mode) Programmable Programmable CMOS Nch-open drain CMOS Nch-open drain Output Type Pull-up Resistor Programmable (Note Programmable Programmable
Note Programmable pull-up resistors port controlled units (P00 07).
No.A1455-10/28
LC87F1JJ8A
User Options
Option Name Port output type Type Flash Version Option Selected Units CMOS Nch-open drain CMOS Nch-open drain CMOS Nch-open drain CMOS Program start address Regulator Regulator Regulator HOLD mode) Regulator HALT mode) Nch-open drain 00000h 1FE00h Nonuse Nonuse Nonuse Setting
Power Treatment
Connect shown below minimize noise input VDD1 extend backup period. sure electrically short VSS1, VSS2, VSS3 pins. Example When microcontroller backup state HOLD mode, power sustain high level output ports supplied their backup capacitors.
backup Power supply VDD1
VDD2 VDD3
VSS1 VSS2 VSS3
Example high level output ports sustained unstable HOLD backup mode.
backup Power supply VDD1
VDD2 VDD3
VSS1 VSS2 VSS3
No.A1455-11/28
LC87F1JJ8A
Reference Power Option
When voltage 5.5V supplied VDD1 internal reference voltage circuit activated, reference voltage port output generated. active/inactive state reference voltage circuit switched optional settings. procedure marking optional settings described below.
Option settings regulator regulator HOLD mode regulator HALT mode Reference voltage circuit state Normal mode HOLD mode HALT mode Active Active Active Nonuse Nonuse Active Inactive Inactive Nonuse Active Inactive Active Nonuse Nonuse Nonuse Inactive Inactive Inactive
When reference voltage circuit made inactive, level reference voltage port output equal VDD1. Selection used reference voltage circuit inactive HOLD HALT mode. When reference voltage circuit activated, current drain increases approximately 100A compared with when reference voltage circuit inactive. Circuit example When VDD1=VDD2=3.3V Inactivating reference voltage circuit (selection (4)). Connecting VDD3 VDD1 VDD2.
Power supply 3.3V VDD1 UHD+ UHDVDD2 2.2F
connector
VDD3
UFILT
VSS1 VSS2 VSS3 2.2F
Needs adjustment target board. Circuit example When VDD1=VDD2=5.0V Activating reference voltage circuit (selection (1)). Isolating VDD3 from VDD1 VDD2, connecting capacitor between VDD3 VSS.
Power supply VDD1 UHD+ UHDVDD2 VDD3 2.2F 0.1F VSS1 VSS2 VSS3 2.2F UFILT connector
No.A1455-12/28
LC87F1JJ8A
Absolute Maximum Ratings 25°C, VSS1 VSS2 VSS3
Parameter Maximum supply voltage Input voltage Input/output voltage Peak output current IOPH(2) IOPH(3) PWM0, PWM1 Port Average High level output current output current (Note 1-1) IOMH(2) IOMH(3) PWM0, PWM1 Port Total output current IOAH(2) IOAH(3) IOAH(4) IOAH(5) Peak output current IOPL(2) IOPL(3) Average level output current output current (Note 1-1) IOML(2) IOML(3) Total output current IOAL(2) IOAL(3) IOAL(4) IOAL(5) Allowable power dissipation Operating ambient temperature Storage ambient temperature Tstg Topr Port PWM0, PWM1 Ports PWM0, PWM1 Ports UHD+, IOAL(1) IOML(1) IOPL(1) Port PWM0, PWM1 Ports PWM0, PWM1 Port UHD+, UHDP02 Ports PWM0, PWM1 P00, Ports Ports PWM0, PWM1 P00, Ports Ports Total current applicable pins Total current applicable pins Total current applicable pins Total current applicable pins Total current applicable pins Ta=-40 +85°C applicable applicable +125 applicable applicable applicable IOAH(1) Ports IOMH(1) Ports IOPH(1) VI(1) VIO(1) XT1, Ports PWM0, PWM1 Ports When CMOS output type selected applicable applicable When CMOS output type selected applicable When CMOS output type selected applicable applicable When CMOS output type selected applicable Total current applicable pins Total current applicable pins Total current applicable pins Total current applicable pins Total current applicable pins applicable -7.5 -0.3 VDD+0.3 Symbol Pin/Remarks VDD1, VDD2, VDD3 Conditions VDD[V] VDD1= VDD2= VDD3 -0.3 -0.3 Specification +6.5 VDD+0.3 unit
Note 1-1: average output current average current values measured over 100ms intervals.
No.A1455-13/28
LC87F1JJ8A
Allowable Operating Conditions -40°C +85°C, VSS1 VSS2 VSS3
Parameter Operating supply voltage (Note 2-1) Memory sustaining supply voltage High level input voltage VIH(1) Ports port input/ interrupt side PWM0, PWM1 VIH(2) VIH(3) level input voltage VIL(2) VIL(3) VIL(4) VIL(5) VIL(6) Instruction cycle time (Note 2-2) External system clock frequency FEXCF(1) tCYC Except onboard programming mode open System clock frequency division ratio=1/1 External system clock duty =50±5% open System clock frequency division ratio=1/1 External system clock duty =50±5% Oscillation frequency range (Note 2-3) FmRC FsX'tal XT1, FmCF(2) CF1, FmCF(1) CF1, When 12MHz ceramic oscillation Fig. When 6MHz ceramic oscillation Fig. Internal oscillation 32.768kHz crystal oscillation Fig. 32.768 Port watchdog timer side XT1, XT2, CF1, VIL(1) Port watchdog timer side XT1, XT2, CF1, Ports port input/ interrupt side Port PWM0, PWM1 0.9VDD 0.75VDD 0.245 0.490 0.1VDD +0.4 0.2VDD 0.15VDD +0.4 0.2VDD 0.8VDD -1.0 0.25VDD 0.3VDD +0.7 VDD1=VDD2=VDD3 Symbol VDD(1) Pin/Remarks VDD1=VDD2=VDD3 Conditions 0.245s tCYC 200s 0.490s tCYC 200s Except onboard programming mode register contents sustained HOLD mode. Specification VDD[V] unit
Note 2-1: must held greater than equal 3.0V flash onboard programming mode. Note 2-2: Relationship between tCYC oscillation frequency 3/FmCF division ratio 6/FmCF division ratio 1/2. Note 2-3: oscillation characteristics examples.
No.A1455-14/28
LC87F1JJ8A
Electrical Characteristics -40°C +85°C, VSS1 VSS2 VSS3
Parameter High level input current Symbol IIH(1) Pin/Remarks Ports Port PWM0, PWM1 UHD+, UHDIIH(2) IIH(3) level input current IIL(1) XT1, Ports Port PWM0, PWM1 UHD+, UHDIIL(2) IIL(3) High level output voltage VOH(1) VOH(2) VOH(3) VOH(4) VOH(5) VOH(6) level output voltage VOL(1) VOL(2) VOL(3) VOL(4) VOL(5) VOL(6) VOL(7) VOL(8) Pull-up resistance Rpu(1) Rpu(2) Hysteresis voltage capacitance VHYS Ports Port Port pins pins other than that under test: VIN=VSS f=1MHz Ta=25°C Ports PWM0, PWM1 Ports PWM0, PWM1 (Note 3-1) P00, XT1, Ports Conditions VDD[V] Output disabled Pull-up resistor VIN=VDD (Including output Tr's leakage current) Input port configuration VIN=VDD VIN=VDD Output disabled Pull-up resistor VIN=VSS (Including output Tr's leakage current) Input port configuration VIN=VSS VIN=VSS IOH=-1mA IOH=-0.4mA IOH=-0.2mA IOH=-10mA IOH=-1.6mA IOH=-1mA IOL=30mA IOL=5mA IOL=2.5mA IOL=10mA IOL=1.6mA IOL=1mA IOL=1.6mA IOL=1mA VOH=0.9VDD 0.1VDD VDD-1 VDD-0.4 VDD-0.4 VDD-1.5 VDD-0.4 VDD-0.4 Specification unit
Note 3-1: When system clock output function (P05) audio interface output function (P05 P07) used.
No.A1455-15/28
LC87F1JJ8A
Serial Characteristics -40°C +85°C, VSS1 VSS2 VSS3
SIO0 Serial Characteristics (Note 4-1-1)
Parameter Frequency level pulse width High level pulse width tSCKHA(1a) Continuous data transfer mode USB, AIF, SIO4, SIO9, DMCOPY used same time. Input clock Fig. (Note 4-1-2) tSCKHA(1b) Continuous data transfer mode used same time. AIF, SIO4, SIO9, DMCOPY used same time. Fig. (Note 4-1-2) tSCKHA(1c) Continuous data transfer mode USB, AIF, SIO4, SIO9, DMCOPY used same time. Fig. Serial clock (Note 4-1-2) Frequency level pulse width High level pulse width tSCKHA(2a) Continuous data transfer mode USB, AIF, SIO4, SIO9, DMCOPY used same time. When CMOS output type Output clock selected Fig. tSCKHA(2b) Continuous data transfer mode used same time. AIF, SIO4, SIO9, DMCOPY used same time. When CMOS output type selected. Fig.9. tSCKHA(2c) Continuous data transfer mode USB, AIF, SIO4, SIO9, DMCOPY used same time When CMOS output type selected Fig.9. tSCKH(2) +2tCYC tSCKH(2) (25/3)tCYC tSCKH(2) +2tCYC tSCKH(2) (19/3)tCYC tCYC tSCKH(2) +2tCYC tSCKH(2) (10/3)tCYC tSCKH(2) tSCK(2) tSCKL(2) SCK0(P12) When CMOS output type selected Fig. tSCK tCYC tSCKH(1) Symbol tSCK(1) tSCKL(1) Pin/ Remarks SCK0(P12) Fig. Conditions VDD[V] Specification unit
Note 4-1-1: These specifications theoretical values. Margins must allowed according actual operating conditions. Note 4-1-2: application where serial clock input used continuous data transfer mode, time from SI0RUN being when serial clock high falling edge first serial clock must longer than tSCKHA.
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No.A1455-16/28
LC87F1JJ8A
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Parameter Data setup time Serial input Symbol tsDI(1) Pin/ Remarks SB0(P11), SI0(P11) Data hold time thDI(1) Conditions VDD[V] Must specified with respect rising edge SIOCLK. Fig. 0.03 Output delay Input clock time tdDO(2) tdDO(1) SO0(P10), SB0(P11) Continuous data transfer mode (Note 4-1-3) Synchronous 8-bit mode (Note 4-1-3) tdDO(3) Output clock (Note 4-1-3) (1/3)tCYC +0.05 0.03 Specification unit
(1/3)tCYC +0.05 1tCYC +0.05
Note 4-1-3: Must specified with respect falling edge SIOCLK. Must specified time beginning output state change open drain output mode. Fig. SIO1 Serial Characteristics (Note 4-2-1)
Parameter Frequency Input clock level pulse width High level pulse width Frequency Output clock level pulse width High level pulse width Data setup time Serial input tsDI(2) SB1(P14), SI1(P14) Data hold time thDI(2) Must specified with respect rising edge SIOCLK. Fig. 0.03 Output delay time Serial output tdDO(4) SO1(P13), SB1(P14) Must specified with respect falling edge SIOCLK. Must specified time beginning output state change open drain output mode. Fig. (1/3)tCYC +0.05 0.03 tSCKH(4) tSCK(4) tSCKL(4) SCK1(P15) When CMOS output type selected Fig. tSCKH(3) Symbol tSCK(3) tSCKL(3) Pin/ Remarks SCK1(P15) Fig. Conditions VDD[V] tCYC tSCK Specification unit
Note 4-2-1: These specifications theoretical values. Margins must allowed according actual operating conditions.
Serial clock
Serial output
No.A1455-17/28
LC87F1JJ8A
SIO4 Serial Characteristics (Note 4-3-1)
Parameter Frequency level pulse width High level pulse width tSCKHA(5a) USB, SIO0 continuous transfer mode, AIF, SIO9, DMCOPY used same time. Input clock Fig. (Note 4-3-2) tSCKHA(5b) used same time SIO0 continuous transfer mode, AIF, SIO9, DMCOPY used same time. Fig. (Note 4-3-2) tSCKHA(5c) USB, SIO0 continuous transfer mode, SIO9, DMCOPY used same time. used same time. Fig. Serial clock (Note 4-3-2) Frequency level pulse width High level pulse width (Note 4-3-3) tSCKHA(6a) USB, SIO0 continuous transfer mode, AIF, SIO9, DMCOPY used same time. When CMOS output type selected. Output clock Fig. tSCKHA(6b) used same time. SIO0 continuous transfer mode, AIF, SIO9, DMCOPY used same time. When CMOS output type selected. Fig. tSCKHA(6c) USB, SIO0 continuous transfer mode, SIO9, DMCOPY used same time. used same time. When CMOS output type selected. Fig. tSCKH(6) (5/3)tCYC tSCKH(6) (34/3)tCYC tSCKH(6) (5/3)tCYC tSCKH(6) (19/3)tCYC tCYC tSCKH(6) (5/3)tCYC tSCKH(6) (10/3)tCYC tSCKH(6) tSCK(6) tSCKL(6) SCK4(P24) When CMOS output type selected. Fig. tSCK tCYC tSCKH(5) Symbol tSCK(5) tSCKL(5) Pin/ Remarks SCK4(P24) Fig. Conditions VDD[V] Specification unit
Note 4-3-1: These specifications theoretical values. Margins must allowed according actual operating conditions. Note 4-3-2: application where serial clock input used continuous data transfer mode, period from time SI4RUN with serial clock high falling edge first serial clock must longer than tSCKHA. Note 4-3-3: When using serial clock output, make sure that load SCK4 (P24) meets following conditions: Clock rise time tSCKR 0.037s (see Figure 12.) Ta=+25°C, VDD=3.3V
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Continued from preceding page.
Parameter Data setup time Serial input Symbol tsDI(3) Pin/ Remarks SO4(P22), SI4(P23) Data hold time thDI(3) Conditions VDD[V] Must specified with respect rising edge SIOCLK. Fig. 0.03 Output delay time Serial output tdDO(5) SO4(P22), SI4(P23) Must specified with respect falling edge SIOCLK. Must specified time beginning output state change open drain output mode. Fig. (1/3)tCYC +0.05 0.03 Specification unit
SIO9 Serial Characteristics (Note 4-4-1)
Parameter Frequency level pulse width High level pulse width tSCKHA(7a) USB, SIO0 continuous transfer mode, AIF, SIO4, DMCOPY used same time. Serial clock Input clock Fig. (Note 4-4-2) tSCKHA(7b) used same time. SIO0 continuous transfer mode, AIF, SIO4, DMCOPY used same time. Fig. (Note 4-4-2) tSCKHA(7c) USB, SIO0 continuous transfer mode, SIO4, DMCOPY used same time. used same time. Fig. (Note 4-4-2) tCYC tSCKH(7) Symbol tSCK(7) tSCKL(7) Pin/ Remarks SCK9(P27) Fig. Conditions VDD[V] Specification unit
Note 4-4-1: These specifications theoretical values. Margins must allowed according actual operating conditions. Note 4-4-2: application where serial clock input used continuous data transfer mode, period from time SI9RUN with serial clock high falling edge first serial clock must longer than tSCKHA.
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Continued from preceding page.
Parameter Frequency level pulse width High level pulse width (Note 4-4-3) tSCKHA(8a) USB, SIO0 continuous transfer mode, AIF, SIO4, DMCOPY used same time. When CMOS output type selected. Output clock Serial clock Fig. tSCKHA(8b) used same time. SIO0 continuous transfer mode, AIF, SIO4, DMCOPY used same time. When CMOS output type selected Fig. tSCKHA(8c) USB, SIO0 continuous transfer mode SIO4, DMCOPY used same time. used same time. When CMOS output type selected. Fig. Data setup time Serial input tsDI(4) SO9(P25), SI9(P26) Must specified with respect rising edge SIOCLK. Fig. Data hold time thDI(4) 0.03 Must specified with respect falling edge SIOCLK. Must specified time beginning output state change open drain output mode Fig. (1/3)tCYC +0.05 0.03 tSCKH(8) (5/3)tCYC tSCKH(8) (43/3)tCYC tSCKH(8) (5/3)tCYC tSCKH(8) (19/3)tCYC tCYC tSCKH(8) (5/3)tCYC tSCKH(8) (10/3)tCYC tSCKH(8) Symbol tSCK(8) tSCKL(8) Pin/ Remarks SCK9(P27) Conditions VDD[V] When CMOS output type selected. Fig. tSCK Specification unit tCYC
Output delay time Serial output
tdDO(6)
SO9(P25), SI9(P26)
Note 4-4-3: When using serial clock output, make sure that load SCK9 (P27) meets following conditions: Clock rise time tSCKR 0.037s (see Figure 12.) Ta=+25°C, VDD=3.3V
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Pulse Input Conditions -40°C +85°C, VSS1 VSS2 VSS3
Parameter High/low level pulse width Symbol tPIH(1) tPIL(1) Pin/Remarks INT0(P70), INT1(P71), INT2(P72), INT4(P20 P23), INT5(P24 P27), INT6(P20), INT7(P24) tPIH(2) tPIL(2) tPIH(3) tPIL(3) tPIH(4) tPIL(4) tPIL(5) tPIL(6) INT3(P73) when noise filter time constant INT3(P73) when noise filter time constant 1/32 INT3(P73) when noise filter time constant 1/128 RMIN(P73) Interrupt source flag set. Event inputs timer enabled. Interrupt source flag set. Event inputs timer enabled. Interrupt source flag set. Event inputs timer enabled. Recognized infrared remote control receiver circuit signal Resetting enabled. RMCK (Note 5-1) tCYC Conditions VDD[V] Interrupt source flag set. Event inputs timer enabled. Specification unit
Note 5-1: Represents period reference clock tCYC tCYC source frequency subclock) infrared remote control receiver circuit.
Converter Characteristics -40°C +85°C, VSS1 VSS2 VSS3
Parameter Resolution Absolute accuracy Conversion time TCAD Symbol Pin/Remarks AN0(P00) AN7(P07), AN8(P70), AN9(P71), AN10(XT1), AN11(XT2) conversion (when ADCR2=0) (Note 6-2) (Note 6-1) Conditions VDD[V] 15.68 (tCYC= 0.490µs) 23.52 conversion (when ADCR2=1) (Note 6-2) (tCYC= 0.735µs) 18.82 (tCYC= 0.294µs) 47.04 Analog input voltage range Analog port input current IAINH IAINL VAIN=VDD VAIN=VSS VAIN (tCYC= 0.735µs) Specification unit
±1.5
97.92 (tCYC= 3.06µs) 97.92 (tCYC= 3.06µs) 97.92 (tCYC= 1.53µs) 97.92 (tCYC= 1.53µs)
Note 6-1: quantization error (±1/2LSB) excluded from absolute accuracy. Note 6-2: conversion time refers period from time when instruction starting conversion process issued time conversion results register(s) loaded with complete digital conversion value corresponding analog input value.
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Consumption Current Characteristics -40°C +85°C, VSS1 VSS2 VSS3
Parameter Normal mode consumption current (Note 7-1) IDDOP(2) Symbol IDDOP(1) Pin/ Remarks VDD1 =VDD2 =VDD3 Conditions VDD[V] FmCF=12MHz ceramic oscillation mode FsX'tal=32.768kHz crystal oscillation mode System clock 12MHz side Internal oscillation stopped Internal oscillation stopped circuit stopped frequency division ratio IDDOP(3) FmCF=12MHz ceramic oscillation mode FsX'tal=32.768kHz crystal oscillation mode System clock 12MHz side IDDOP(4) Internal oscillation mode active Internal oscillation stopped circuit active frequency division ratio IDDOP(5) IDDOP(6) IDDOP(7) IDDOP(8) IDDOP(9) IDDOP(10) IDDOP(11) IDDOP(12) IDDOP(13) HALT mode consumption current (Note7-1) IDDHALT(2) IDDHALT(1) FmCF=12MHz ceramic oscillation mode FsX'tal=32.768kHz crystal oscillation mode System clock 6MHz side Internal oscillation stopped frequency division ratio FmCF=0Hz (oscillation stopped) FsX'tal=32.768kHz crystal oscillation mode System clock internal oscillation frequency division ratio FmCF=0Hz (oscillation stopped) FsX'tal=32.768kHz crystal oscillation mode System clock crystal oscillation side (32.768kHz) Internal oscillation stopped frequency division ratio HALT mode FmCF=12MHz ceramic oscillation mode FsX'tal=32.768kHz crystal oscillation mode System clock 12MHz side Internal oscillation stopped Internal oscillation stopped circuit stopped frequency division ratio IDDHALT(3) HALT mode FmCF=12MHz ceramic oscillation mode FsX'tal=32.768kHz crystal oscillation mode System clock 12MHz side IDDHALT(4) Internal oscillation mode active Internal oscillation stopped circuit active frequency division ratio IDDHALT(5) IDDHALT(6) IDDHALT(7) IDDHALT(8) IDDHALT(9) IDDHALT(10) HALT mode FmCF=12MHz ceramic oscillation mode FsX'tal=32.768kHz crystal oscillation mode System clock 6MHz side Internal oscillation stopped frequency division ratio HALT mode FmCF=0Hz (oscillation stopped) FsX'tal=32.768kHz crystal oscillation mode System clock internal oscillation frequency division ratio 0.17 0.70 0.41 0.20 0.95 0.77 0.43 0.36 Specification unit
Note 7-1: consumption current value includes none currents that flow into output internal pull-up resistors.
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Parameter HALT mode consumption current (Note 7-1) IDDHALT(13) IDDHALT(12) Symbol IDDHALT(11) Pin/ Remarks VDD1 =VDD2 =VDD3 HALT mode FmCF=0Hz (oscillation stopped) FsX'tal=32.768kHz crystal oscillation mode System clock crystal oscillation side (32.768kHz) Internal oscillation stopped frequency division ratio HOLD mode consumption current Timer HOLD mode consumption current IDDHOLD(1) IDDHOLD(2) IDDHOLD(3) IDDHOLD(4) IDDHOLD(5) IDDHOLD(6) Timer HOLD mode CF1=VDD open (External clock mode) FsX'tal=32.768kHz crystal oscillation mode VDD1 HOLD mode CF1=VDD open (External clock mode) 0.24 0.12 0.11 Conditions VDD[V] Specification unit
Note 7-1: consumption current value includes none currents that flow into output internal pull-up resistors.
Characteristics Timing -40°C +85°C, VSS1 VSS2 VSS3
Parameter High level output level output Output signal crossover voltage Differential input sensitivity Differential input common mode range High level input level input data rise time data fall time Symbol VOH(USB) VOL(USB) VCRS VIH(USB) VIL(USB) RS=33, CL=50pF RS=33, CL=50pF (UHD+)-(UHD-) Conditions 15k±5% 1.5k±5% 3.6V Specification unit
F-ROM Programming Characteristics +10°C +55°C, VSS1 VSS2 VSS3
Parameter Onboard programming current Programming time tFW(1) tFW(2) Symbol IDDFW(1) Pin/ Remarks VDD1 Conditions VDD[V] Excluding power dissipation microcontroller block Erase operation Write operation Specification unit
Main System Clock Oscillation
constant values oscillator oscillation circuit main system clocks must determined after exercising extensive oscillation evaluation tests. application which host function used, oscillator having accuracy precision that satisfy specifications. oscillation stabilization time refers time interval that required oscillation stabilized following cases (see Figure Till oscillation gets stabilized after goes above operating voltage lower limit. Till oscillation gets stabilized after instruction starting main clock oscillation circuit executed. Till oscillation gets stabilized after HOLD mode released. Till oscillation gets stabilized after X'tal HOLD mode released with CFSTOP (OCR register,
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Subsystem Clock Oscillation
Table shows characteristics sample subsystem clock oscillation circuit that measured using SANYOdesignated oscillation characteristics evaluation board external components with circuit constant values with which oscillator vendor confirmed normal stable oscillation. Table Characteristics Sample subsystem Clock Oscillator Circuit with Crystal Oscillator
Nominal Frequency Vendor Name Oscillator Name [pF] 32.768kHz EPSON TOYOCOM MC-306 Circuit Constant [pF] OPEN 560k Operating Voltage Range Oscillation Stabilization Time Applicable value=12.5pF type Remarks
oscillation stabilization time refers time interval that required oscillation stabilized following cases (see Figure Till oscillation gets stabilized after instruction starting subclock oscillation circuit executed. Till oscillation gets stabilized after HOLD mode released with EXTOSC (OCR register, Note: components that involved oscillation should placed close another possible because they vulnerable influences circuit pattern.
X'tal
Figure Oscillator Circuit
Figure Crystal Oscillator Circuit
0.5VDD
Figure Timing Measurement Point
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Operating lower limit Power supply Reset time
Internal oscillation tmsCF
CF1, tmsX'tal
XT1, Execute oscillation enable instruction. Operating mode Unpredictable Reset Instruction execution
Reset Time Oscillation Stabilization Time
HOLD release signal
HOLD release signal valid
Internal oscillation
tmsCF
CF1, tmsX'tal When oscillation enabled before entry into HOLD mode XT1,
Operating mode
HOLD
HALT
HOLD Release Signal Oscillation Stabilization Time Figure Oscillation Stabilization Time
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P34/UFILT
2.2F
When using internal circuit generate 48MHz clock USB, necessary connect filter circuit P34/UFILT such that shown left figure.
Figure External Filter Circuit Internal USB-dedicated Circuit
P33/AFILT
4.7F
generate master clock audio interface using internal circuit, necessary connect filter circuit P33/AFILT that shown left figure.
Figure External Filter Circuit Audio Interface (Used with Internal Circuit)
UHD+
necessary adjust Circuit Constant Port Peripheral Circuit each mounting board.
UHD5pF
Figure Port Peripheral Circuit
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RRES
CRES
Note: Determine value CRES RRES that reset signal present period 200µs after supply voltage goes beyond lower limit IC's operating voltage.
Figure Reset Circuit
SIOCLK:
DATAIN:
DATAOUT:
Data transfer period (SIO0, only)
tSCK tSCKL SIOCLK: tsDI DATAIN: tdDO DATAOUT: Data transfer period (SIO0, only) tSCKL SIOCLK: tsDI DATAIN: tdDO DATAOUT: thDI tSCKHA thDI tSCKH
Figure Serial Waveform
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tPIL
tPIH
Figure Pulse Input Timing Signal Waveform
Vcrs
Figure Data Signal Timing Voltage Level
VIH(1) min=0.3VDD+0.7V
tSCKR
tSCKR: Defined time period from time state output starts changing till time reaches value VIH(1).
Figure Serial Clock Output Timing Signal Waveform
SANYO Semiconductor Co.,Ltd. assumes responsibility equipment failures that result from using products values that exceed, even momentarily, rated values (such maximum ratings, operating condition ranges, other parameters) listed products specifications SANYO Semiconductor Co.,Ltd. products described contained herein. SANYO Semiconductor Co.,Ltd. strives supply high-quality high-reliability products, however, semiconductor products fail malfunction with some probability. possible that these probabilistic failures malfunction could give rise accidents events that could endanger human lives, trouble that could give rise smoke fire, accidents that could cause damage other property. When designing equipment, adopt safety measures that these kinds accidents events cannot occur. Such measures include limited protective circuits error prevention circuits safe design, redundant design, structural design. event that SANYO Semiconductor Co.,Ltd. products described contained herein controlled under applicable local export control laws regulations, such products require export license from authorities concerned accordance with above law. part this publication reproduced transmitted form means, electronic mechanical, including photocopying recording, information storage retrieval system, otherwise, without prior written consent SANYO Semiconductor Co.,Ltd. information described contained herein subject change without notice product/technology improvement, etc. When designing equipment, refer "Delivery Specification" SANYO Semiconductor Co.,Ltd. product that intend use. Information (including circuit diagrams circuit parameters) herein example only; guaranteed volume production. Upon using technical information products described herein, neither warranty license shall granted with regard intellectual property rights other rights SANYO Semiconductor Co.,Ltd. third party. SANYO Semiconductor Co.,Ltd. shall liable claim suits with regard third party's intellectual property rights which resulted from technical information products mentioned above.
This catalog provides information April, 2009. Specifications information herein subject change without notice.
No.A1455-28/28

LC87F1JJ8A CMOS FROM 192K byte, 24576 byte on-chip 8-bit 1-c

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