LE25FW418A 4M-bit Serial Flash Memory with High-Density Read Mode
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Ordering number ENA1432
LE25FW418A
4M-bit Serial Flash Memory with High-Density Read Mode
LE25FW418A Serial flash memory 3.0V single power supply operation, support serial peripheral interface (S.P.I.). There three kinds erase functions, Small Sector bytes) erase, Sector (64K bytes) erase Chip erase. Page program program arbitrary data from byte byte. Program time high speed, 1.5ms (Typ.). Moreover, LE25FW418A makes best feature serial flash memory, stored 8pin very small package. LE25FW418A best suited applications that require re-programmable nonvolatile storage program memory. LE25FW418A also High-Density read mode (hereafter, HD_READ mode) that most high-speed data transfer world flash memory with serial interface. About eight times data-transfer velocity achieved without changing clock frequency used usual serial flash memory using this mode. instance, possible read with 400Mbit/s maximum using HD_READ mode 50MHz though standard serial flash memory read with 50Mbit/s less.
Features
Read/write operations enabled single 3.0V power supply: 3.6V supply voltage range Operating frequency 50MHz Temperature range +70°C,-40 85°C(Planning)
Continued next page.
This product licensed from Silicon Storage Technology, Inc. (USA), manufactured sold SANYO Semiconductor Co., Ltd.
SANYO Semiconductor Co.,Ltd. products described contained herein are, with regard "standard application", intended general electronics equipment (home appliances, equipment, communication device, office equipment, industrial equipment etc.). products mentioned herein shall intended "special application" (medical equipment whose purpose sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level reliability directly threaten human lives case failure malfunction product cause harm human bodies, shall they grant guarantee thereof. should intend products applications outside standard applications customer considering such and/or outside scope intended standard applications, please consult with prior intended use. there consultation inquiry before intended use, customer shall solely responsible use. Specifications SANYO Semiconductor Co.,Ltd. products described contained herein stipulate performance, characteristics, functions described products independent state, guarantees performance, characteristics, functions described products mounted customer' products equipment. verify symptoms states that cannot evaluated independent device, customer should always evaluate test devices mounted customer' products equipment.
61709 20090428-S00004 No.A1432-1/27
LE25FW418A
Continued from preceding page.
Serial interface mode mode supported Sector size bytes/small sector, bytes/sector Small sector erase, sector erase, chip erase functions Page program function (256 bytes/page) High-Density read mode (HD_READ) Block protect function Highly reliable read/write Number rewrite times 100,000 times Small sector erase time 25ms (typ.), 0.1s (max.) Sector erase time 25ms (typ.), 0.5s (max.) Chip erase time 250ms (typ.), (max.) Page program time 1.5ms/256 bytes (typ.), 2.5ms/256 bytes (max.) Status functions Ready/busy information, protect information Data retention period years Package LE25FW418ATT MSOP8 (225mil)
Package Dimensions
unit:mm (typ) 3276
(0.7) 1.27
0.35
0.85max
0.125
SANYO MSOP8(225mil)
Figure Assignments
(SIO3) (SIO2)
0.08
(0.65)
HOLD (SIO1) (SIO0)
view
No.A1432-2/27
LE25FW418A
Figure Block Diagram
XDECODER ADDRESS BUFFERS LATCHES
Flash EEPROM Cell Array
Y-DECODER
CONTROL LOGIC
BUFFERS DATA LATCHES
SERIAL INTERFACE
(SIO0) (SIO3) (SIO2)
HOLD (SIO1)
Table Description
Symbol (SIO0) (SIO3) (SIO2) HOLD (SIO1) Name Serial clock Serial data input (Serial data I/O0) Serial data output (Serial data I/O3) Chip select This controls data input/output timing. input data addresses serially from (Least Significant Bit). input data addresses output data serially HD_READ mode) output data serially from LSB. input data addresses output data serially HD_READ mode) Description
HD_READ mode
device becomes active when logic level this low; deselected placed standby status when logic level high. write-protect block protect bits (BP0, BP1, BP2) status register write protect (SRWP) status register co-operation with status register write protect (SRWP). input data addresses output data serially HD_READ mode) pause serial communications with device without deselecting device. input data addresses output data serially HD_READ mode) This supplies 3.6V supply voltage. This supplies supply voltage.
Write-protect (Serial data I/O2) Hold (Serial data I/O1) Power supply Ground
No.A1432-3/27
LE25FW418A
Table Command Settings
Command Read cycle HD_READ mode Small sector erase Sector erase Chip erase Page program Write enable Write disable Power down Status register read Status register write Read silicon Read silicon Exit power down mode A7-A0 DATA A23-A16 A15-A8 A7-A0 cycle A23-A16 A23-A16 A23-A16 A23-A16 A15-A8 A15-A8 A7-A0 A7-A0 cycle A15-A8 A15-A8 cycle A7-A0 A7-A0 cycle cycle cycle
Explanatory notes Table signifies "don't care" (that say, value input). following each code indicates that number given hexadecimal notation. Addresses commands "Don't care". order commands other than read command recognized, must rise after cycle input. mode register data. Various operation methods HD_READ mode such operation frequencies clock latency. Please refer Table details. "PD" stands page program data. amount data from bytes 1-byte unit input. silicon commands, command with setting that manufacturer code first output. long clock input continued, device code output continuously, followed repeated output 10h. Read (ABh) don't care. read cycle from address A0=`0' outputs manufacture code (SANYO: 62h). read cycle address A0=`1' outputs device code (10h).
No.A1432-4/27
LE25FW418A
Device Operation
LE25FW418A features electrical on-chip erase functions using single 3.0V power supply, that have been added EPROM functions industry standard that support serial interfaces. Interfacing control facilitated incorporating command registers inside chip. read, erase, program other required functions device executed through command registers. command addresses data input accordance with "Table Command Settings" latched inside device order execute required operations. "Figure Serial Input Timing" shows timing waveforms serial data input. First, falling edge device selected, serial input enabled commands, addresses, etc. These inputs introduced internally sequence starting with synchronization with rising edge. this time, output high-impedance state. output placed low-impedance state when data output sequence starting with synchronized falling clock edge during read, status register read silicon Refer "Figure Serial Output Timing" serial output timing. LE25FW418A supports both serial interface mode mode falling edge, mode automatically selected logic level low, mode automatically selected logic level high. Figure Serial Input Timing
tCPH tCLS tCSS tCLHI tCLLO tCSH tCLH
DATA VALID
High Impedance
High Impedance
Figure Serial Output Timing
tCLZ DATA VALID tCHZ
No.A1432-5/27
LE25FW418A
Outline High-Density read mode (HD_READ mode) operation
LE25FW418A HD_READ mode addition kinds normal read read read). HD_READ mode greatly different from normal mode three points. first difference role pins. Four pins (SO, HOLD, become pins (SIO3 SIO0) HD_READ mode while input (SI) output (SO) only normal mode respectively shown Figure Because HOLD operate HD_READ mode, setting read address outputting read data become done from four pins. second difference relation between clock data output. rising edge made trigger address input falling edge made trigger data output normal mode. However, both edges rising falling will done address taking data outputting HD_READ mode. third difference data composition time reading. read HD_READ mode though read normal read. Therefore, please least significant (LSB) address input HD_READ mode.
Assignments
Entry Normal mode HOLD view Slipping SIO3 SIO2 HD_READ mode SIO1 SIO0 view
Figure Serial input output timing diagram HD_READ mode (CL=1.0)
tCSS tCLHI tCLLO tCLZ
SIO3
data
data
SIO2
data
data
SIO1
data
data
SIO0
data
data
No.A1432-6/27
LE25FW418A
Command Definition
"Table Command Settings" provides list overview commands. detailed description functions operations corresponding each command presented below. Conventional Read There read commands, cycle read command cycle read command. Consisting first through fourth cycles, cycle read command inputs 24-bit addresses following (03h), data designated addresses output synchronized SCK. data output from falling clock edge fourth cycle reference. "Figure Read" shows timing waveforms. Consisting first through fifth cycles, cycle read command inputs 24-bit addresses dummy bits following (0Bh). data output from using falling clock edge fifth cycle reference. "Figure Read" shows timing waveforms. only difference between these commands whether dummy bits fifth cycle input. When input continuously after read command been input data designated addresses been output, address automatically incremented inside device while being input, corresponding data output sequence. input continued after internal address arrives highest address (7FFFFh), internal address returns lowest address (00000h), data output continued. setting logic level high, device deselected, read cycle ends. While device deselected, output high-impedance state. Figure Read
Mode3 Mode0 8CLK High Impedance DATA DATA DATA
Figure Read
Mode3 Mode0 8CLK High Impedance DATA DATA DATA
No.A1432-7/27
LE25FW418A
High-Density Read LE25FW418A HD_READ mode addition kinds normal read read read). HD_READ mode greatly different from normal mode three points. first difference role pins. Four pins (SO, HOLD, become pins (SIO3 SIO0) HD_READ mode while input (SI) output (SO) only normal mode respectively shown Figure Because HOLD operate HD_READ mode, setting read address outputting read data become done from four pins. second difference relation between clock data output. rising edge made trigger address input falling edge made trigger data output normal mode. However, both edges rising falling will done address taking data outputting HD_READ mode. third difference data composition time reading. read HD_READ mode though read normal read. Therefore, please least significant (LSB): address input HD_READ mode. When HD_READ mode used with LE25FW418A, necessary input HD_READ mode command first according usual serial input specification. Please refer Table command input HD_READ mode. command composed cycles, various operation methods HD_READ mode second cycle. Please refer Table content. Please refer Figure input waveform when HD_READ mode set. HD_READ mode becomes effective making after command input. keeps maintaining HD_READ mode until power supply above-mentioned release command input after entering HD_READ mode once. Figure HD_READ mode setting waveform (CL=1.0)
CL=0.5 CL=0 Mode0 A23-A0 SIO3(SO) High Impedance SIO2(WP) CL=1.0
SIO1(HOLD) 16CLK SIO0(SI)
Register Setting
Normal mode
HD_READ mode
Because HD_READ mode entry input normal mode, either input mode possible. However, there concept mode period when HD_READ mode set. Please control according timing that provides with this specifications.
No.A1432-8/27
LE25FW418A
composition input output changes into composition four pins enters HD_READ mode. Therefore, start address reading HD_READ mode from four pins (SIO0 SIO3). this time, address from latched internally rising edge rising falling edge SCK. Please refer Figure However, necessary note following points. Even fixed four pins become input waiting states HD_READ mode. Therefore, please state four pins this period much possible. input level changes becomes middle potential, penetration current will flow input buffer inside flash. address that input only even number address because output data read each HD_READ mode. Please input most significant (A23) address. input address from don't care. Those serial flash memory that exceeds 8Mbit (planning). Please rise arbitrary timing when want stop reading HD_READ mode temporarily. level this time doesn't output state Hi-Z after tCHZ rising four pins (SIO0 SIO3) become input waiting states. Therefore, please state four pins this period level level. Afterwards, please execute from address input again when restart reading. Address A23-A0 xx55AAh release from HD_READ mode normal mode, then operation that makes immediately when becomes after address input done. Please refer Figure Figure HD_READ mode release waveform
tCPH tCSH tCPH
Data output SIO3(SO) A23-0=xx55AAh
SIO2(WP)
SIO1(HOLD)
SIO0(SI)
HD_READ mode
Normal mode
No.A1432-9/27
LE25FW418A
HD_READ Mode Register Setting Various operation methods HD_READ mode internal register HD_READ mode command input second cycle. register eight bits all, shows meaning each table HD_READ mode register table. This register setting effective until release from HD_READ mode normal mode. necessary again each temporary stop reading HD_READ mode. Table HD_READ Mode Register Table
REGBL2 REGBL1 REGBL0 REGFCLK1 REGFCLK0 REGCL2 REGCL1 REGCL0
Name REGBL2 REGBL1 REGBL0 REGFCLK1 REGFCLK0 REGCL2 REGCL1 REGCL0
Function continuous Burst length [REGBL2, REGBL1, REGBL0]
value content 4words wrap around words wrap around words wrap around words wrap around 16MHz less power save mode
Clock frequency [REGFCLK1, REGFCLK0]
25MHz less 50MHz less 51MHz more Clock latency Clock latency
Clock latency [REGCL2, REGCL1, REGCL0]
Clock latency Clock latency Clock latency Clock latency
specification that exceeds fCLK=50MHz planning. When fCLK exceeds 30MHz, necessary adjust more. length setting this model, kinds reading methods "Continuous reading" "Wrap around reading" HD_READ mode alternately. And, delimitation address four kinds (every words, words, words, words (one word bits)) "Wrap around reading". Continuous reading When burst length set, Continuous reading specifying register bit. Continuous reading method automatically continues read long input. Reading begun from input address, internal address automatically count addresses (every bits). internal address reaches final address (7FFFEh), returns first address (00000h) reading continued. wants shift arbitrary address way, operation that makes once makes again done.
No.A1432-10/27
LE25FW418A
Wrap around reading When burst length set, wrap around reading method specifying register bit. wrap around reading method automatically continues read long input. Reading begun from input address, internal address automatically count addresses (every bits). internal address reaches delimitation address beforehand, returns head delimitation address reading repeated. delimitation address four kinds (every words, words, words words (one word bits)) subordinate position bits register bit. instance, words becomes unit address delimitation reading word wrap around. After reaches final word address delimitation words, returns first word reading done even reading started from which address. order reading words when address third word from head read start address follows.
order reading address 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000 0001 0010
order reading address
0011
0100
0101
0110
Mark address
Clock frequency setting this model, necessary register clock frequency according operation frequency used .The clock 50MHz less input present. Especially, power saving mode that decreases power consumption HD_READ selected specifying register bit. However, this power saving mode with operation frequency 16MHz less. Moreover, spec (tV2) output data time from changes this case. Clock latency setting this model, clock latency: number clocks from setting address output first data) setting clock latency register bit. Please refer Figure method counting falling edge first after address input assumed CL=0, added every half clock SCK. within range from 3.0. However, when clock frequency exceeds 30MHz, necessary more.
No.A1432-11/27
LE25FW418A
Status Register Status Register's contents shown Table Status Register perform detection state device setup protection. Table Status Registers
Bit0 Name Logic Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 SRWP Reserved bits Reserved bits Status register write enabled Status register write disabled Nonvolatile information Block protect information status register descriptions BP0, BP1, BP2. Nonvolatile information Function Ready Erase/Program Write disabled Write enabled Nonvolatile information Power-on Time Information
Nonvolatile information
4-1. Status Register Read contents status registers read using status register read command. This command executed even during following operations. Small sector erase, sector erase, chip erase Page program Status register write "Figure Status Register Read" shows timing waveforms status register read. Consisting only first cycle, status register command outputs contents status registers synchronized falling edge clock (SCK) with which eighth (05h) been input. terms output sequence, SRWP (bit first output, each time clock input, other bits (bit output sequence, synchronized falling clock edge. clock input continued after (bit been output, data output returning (SRWP) that first output, after which output repeated long clock input continued. data read status register read command time (even during program erase cycle). Figure Status Register Read
Mode Mode 8CLK
High Impedance
DATA
DATA
DATA
No.A1432-12/27
LE25FW418A
4-2. Status Register Write Status Register Write, BP0, BP1, SRWP rewritten. RDY, WEN, Bit5, Bit6 read-only, BP0, BP1, SRWP non-volatile. timing waveform shown Figure flow chart shown Figure Status Register Write command consists cycle cycle, internal Write operation starts with rising edge after inputting data after OP-code (01h). Erase program automatically performed inside device Status Register Write rewrites BP0, BP1, SRWP non-volatilized data. write-in data read-only bits (RDY, WEN, don't care. Status Register Write detectable with Status Register Read. number times rewriting Status Register Write 1,000 times (min). order perform Status Register Write, necessary change Status Register into state pin. Figure Status Register Write
Self-timed Write Cycle tSRW tWPS tWPH
Mode3 Mode0
8CLK DATA
High Impedance
4-3. Contents Each Status Register (bit register detecting write (program, erase status register write) end. When "1", device busy state, when "0", means that write completed.
No.A1432-13/27
LE25FW418A
(bit register detecting whether device perform write operations. "0", device will perform write operation even write command input. "1", device perform write operations area that block-protected. controlled using write enable write disable commands. inputting write enable command (06h), "1"; inputting write disable command (04h), "0." following states, automatically order protect against unintentional writing. power-on Upon completion small sector erase, sector erase chip erase Upon completion page program Upon completion status register write write operation been performed inside LE25FW418A because, instance, command input write operations (small sector erase, sector erase, chip erase, page program, status register write) failed write operation been performed protected address, will retain status established prior issue command concerned. Furthermore, state will changed read operation. BP0, BP1, (bits Block protect BP0, BP1, status register bits that rewritten, memory space protected depending these bits. setting conditions, refer "Table Protect level setting conditions". Table Protect Level Setting Conditions
Protect Level (Whole area unprotected) (1/8 protected) (1/4 protected) (1/2 protected) (Whole area protected) (Whole area protected) (Whole area protected) (Whole area protected) Status Register Bits None 70000h 7FFFFh 60000h 7FFFFh 40000h 7FFFFh 00000h 7FFFFh 00000h 7FFFFh 00000h 7FFFFh 00000h 7FFFFh Protected Area
Chip erase enabled only when protect level SRWP (bit Status register write protect SRWP protecting status registers, information rewritten. When SRWP logic level low, status register write command ignored, status registers BP0, BP1, BP2, SRWP protected. When logic level high, status registers protected regardless SRWP state. SRWP setting conditions shown "Table SRWP setting conditions". Table SRWP Setting Conditions
SRWP Status Register Protect State Unprotected Protected Unprotected Unprotected
Bits reserved bits, have significance.
No.A1432-14/27
LE25FW418A
Write Enable Before performing operations listed below, device must placed write enable state. Operation same setting status register "1", state enabled inputting write enable command. "Figure Write Enable" shows timing waveforms when write enable operation performed. write enable command consists only first cycle, initiated inputting (06h). Small sector erase, sector erase, chip erase Page program Status register write Write Disable write disable command sets status register prohibit unintentional writing. "Figure Write Disable" shows timing waveforms. write disable command consists only first cycle, initiated inputting (04h). write disable state (WEN "0") exited setting using write enable command (06h). Figure Write Enable
Mode3 Mode0 8CLK
Figure Write Disable
Mode3 Mode0
8CLK
High Impedance
High Impedance
Power-down power-down command sets commands, with exception silicon read command command exit from power-down, acceptance prohibited state (power-down). "Figure Power-down" shows timing waveforms. power-down command consists only first cycle, initiated inputting (B9h). However, power-down command issued during internal write operation will ignored. power-down state exited using power-down exit command (power-down exited also when cycle more silicon read command (ABh) been input). "Figure Exiting from Power-down" shows timing waveforms power-down exit command. Figure Power-down
tPRB Mode3 Mode0 8CLK Mode3 Mode0 8CLK
Figure Exiting from Power-down
High Impedance
High Impedance
No.A1432-15/27
LE25FW418A
Small Sector Erase Small sector erase operation that sets memory cell data small sector "1". small sector consists 4Kbytes. "Figure Small Sector Erase" shows timing waveforms, Figure shows small sector erase flowchart. small sector erase command consists first through fourth cycles, initiated inputting 24-bit addresses following (D7h). Addresses valid, Addresses "don't care". After command been input, internal erase operation starts from rising edge, ends automatically control exercised internal timer. Erase also detected using status register RDY. Figure Small Sector Erase
Self-timed Erase Cycle tSSE Mode3 Mode0 8CLK
High Impedance
Sector Erase Sector erase operation that sets memory cell data sector "1". sector consists 64Kbytes. "Figure Sector Erase" shows timing waveforms, Figure shows sector erase flowchart. sector erase command consists first through fourth cycles, initiated inputting 24-bit addresses following (D8h). Addresses valid, Addresses "don't care". After command been input, internal erase operation starts from rising edge, ends automatically control exercised internal timer. Erase also detected using status register RDY. Figure Sector Erase
Self-timed Erase Cycle Mode3 Mode0 8CLK
High Impedance
No.A1432-16/27
LE25FW418A
Chip Erase Chip erase operation that sets memory cell data sectors "1". "Figure Chip Erase" shows timing waveforms, Figure shows chip erase flowchart. chip erase command consists only first cycle, initiated inputting (C7h). After command been input, internal erase operation starts from rising edge, ends automatically control exercised internal timer. Erase also detected using status register RDY. Figure Chip Erase
Self-timed Erase Cycle tCHE
Mode3 Mode0 8CLK
High Impedance
Page Program Page Program program arbitrary numbers bytes bytes into sector erased advance. Figure shows timing waveform flow chart shown Figure 24-bit address inputted after OP-code (02H). address A18-A0 effective. Then, loading possible program data during low. When data loaded exceeds bytes, bytes loaded programmed. necessary load program data byte, when programs loading data below byte unit, normal Page Program performed. Figure Page Program
Self-timed Program Cycle Mode3 Mode0 8CLK
2079
High Impedance
No.A1432-17/27
LE25FW418A
Silicon Read Silicon read operation that reads manufacturer code device code information. "Table Silicon codes table" lists silicon codes. silicon read command accepted during writing. methods used silicon reading. first method involves inputting command: setting completed with only first cycle input, subsequent cycles manufacturer code device code repeatedly output succession long clock input continued. Refer "Figure 19-a Silicon read waveforms. second method involves inputting command. This command consists first through fourth cycles, silicon read when dummy bits 8-bit address input after (ABh). When address "0", manufacturer code read fifth cycle, device code read sixth cycle. "Figure 19-b Silicon read shows timing waveforms. after manufacturer code device code been read, input continued, manufacturer code device code output alternately with each cycle. When address "1", reading starts with device code fifth cycle. Table Silicon Codes
Address Manufacturer code Device code Output Code
data output starting with falling clock edge fourth cycle silicon reading ends rising edge. Figure 19-a Silicon Read
Mode3 Mode0 8CLK SiID SiID SiID
High Impedance
Figure 19-b Silicon Read
Mode3 Mode0
8CLK High Impedance SiID SiID SiID
No.A1432-18/27
LE25FW418A
Hold Function Using HOLD pin, hold function suspends serial communication places hold status). "Figure HOLD" shows timing waveforms. device placed hold status falling HOLD edge while logic level low, exits from hold status rising HOLD edge. When logic level high, HOLD must rise fall. hold function takes effect when logic level low, hold status exited serial communication reset rising edge. hold status, output high-impedance state, "don't care". Figure HOLD
Active
HOLD
Active
HOLD tHHZ
tHLZ High Impedance
Power-on Please make high prevent careless writing when turn power supply. Please begin command input read operation after 100s (tPU_READ) from state which powersupply voltage 2.7V more steady. Please begin command input program erase operation after 10ms (tPU_WRITE) from state which power-supply voltage 2.7V more steady. Figure Power-on Timing
Program, Erase Write Command Allowed VDD(max) Full Access Allowed Chip selection Allowed Read Access Allowed
VDD(min) tPU_READ tPU_WRITE
No.A1432-19/27
LE25FW418A
Hardware Data Protection order protect against unintentional writing power-on, LE25FW418A incorporates power-on reset function. following conditions must order ensure that power reset circuit will operate stably. guarantees given data event instantaneous power failure occurring during writing period. Figure Power-down Timing
Program, Erase Write Command Allowed VDD(max) Device Access Allowed
VDD(min)
tPU_READ tPU_WRITE
vBOT
Software Data Protection LE25FW418A eliminates possibility unintentional operations recognizing commands under following conditions. When write command input rising edge timing cycle units SCK) When page program data 1-byte increments When status register write command input cycles more Decoupling Capacitor 0.1F ceramic capacitor must provided each device connected between order ensure that device will operate stably.
No.A1432-20/27
LE25FW418A
Specifications
Absolute Maximum Ratings
Parameter Maximum supply voltage voltage (all pins) Storage temperature Tstg Symbol With respect With respect Conditions Ratings -0.5 +4.6 -0.5 VDD+0.5 +150 unit
Operating Conditions
Parameter Operating supply voltage Operating ambient temperature Symbol Conditions Ratings +85(Planning) unit
Allowable Operating Conditions
Parameter Power Supply Current (Normal Mode) Symbol ICCR Conditions 0.1VDD, HOLD 0.9VDD 0.1VDD 0.9VDD, =open clock frequency 50MHz, Power Supply Current (HD_Read) ICCR 0.1VDD, HOLD open max. Clock frequency 16MHz (Power saving mode) 0.1VDD, HOLD open max. Clock frequency 25MHz (frequency setting=0:1) 0.1VDD, HOLD open max. Clock frequency 50MHz (frequency setting=1:0) Power Supply Current (Write) CMOS standby current Input Leakage Current Output Leakage Current Input Voltage Input High Voltage Output Voltage ICCW tSSE=80ms, tSE=100ms, tCHE=250ms, tPP=0.5ms HOLD VDD-0.3V, open VIL, VDD, VDD, 100A, 1.6mA, Output High Voltage -100A, VDD-0.2 -0.3 0.7VDD Ratings unit
VDD+0.3
Power-on Timing
Parameter Time from power-on read operation Time from power-on write operation Power-down time Power-down voltage tPU_READ tPU_WRITE vBOT Symbol Ratings unit
Capacitance Ta=25°C, f=1MHz
Parameter Output capacitance Input Capacitance Symbol VDQ=0V VIN=0V Conditions Ratings unit
Note: These parameter values represent results measurements undertaken devices rather values some sampled devices.
No.A1432-21/27
LE25FW418A
Characteristics
Parameter Clock frequency High pulse width pulse width Input rising, falling time Setup time Setup time Data Setup time Data Hold time Address Setup time (HD_READ Mode) Address Hold time (HD_READ Mode) output valid output valid (HD_READ) output valid (HD_READ, power saving mode) Hold time Hold time Standby pulse width High-Z output Output data hold time HOLD Setup time HOLD Hold time HOLD High Low-Z Output HOLD High-Z Output Setup time Hold time Status Register Write cycle time Page Program cycle time Small Sector Erase cycle time Sector Erase cycle time Chip Erase cycle time Power Down recovery time Low-Z output 2.7V 3.0V=3ns 3.0V 3.6V=2.5ns tCSH tCLH tCPH tCHZ tHLZ tHHZ tWPS tWPH tSRW tSSE tCHE tPRB tCLZ 0.025 0.025 0.25 Symbol fCLK tCLHI tCLLO tCSS tCLS Ratings unit
Test Conditions
Input pulse 3.0V Input rising/falling Input timing 0.3VDD, 0.7VDD Output timing level Output load 30pF Note: test conditions "typ", measurements conducted using 3.0V room temperature.
No.A1432-22/27
LE25FW418A
Figure Status Register Write Flowchart
Status register write
Start
Write enable
status register write command
Data
Program start rising edge
status register read command
status register write Automatically placed write disabled state status register write
No.A1432-23/27
LE25FW418A
Figure Erase Flowcharts
Sector erase
Small sector erase
Start
Start
Write enable
Write enable
sector erase command
Address
small sector erase command
Address
Address
Address
Address
Address
Start erase rising edge
Start erase rising edge
status register read command
status register read command
erase
erase
Automatically placed write disabled state erase
Automatically placed write disabled state erase
No.A1432-24/27
LE25FW418A
Chip erase Start
Write enable
chip erase command
Start erase rising edge
status register read command
erase
Automatically placed write disabled state erase
No.A1432-25/27
LE25FW418A
Figure Page Program Flowchart
Page program Start
Write enable
page program command
Address
Address
Address
Data
Data
Start program rising edge
status register read command
programming Automatically placed write disabled state programming operation.
No.A1432-26/27
LE25FW418A
SANYO Semiconductor Co.,Ltd. assumes responsibility equipment failures that result from using products values that exceed, even momentarily, rated values (such maximum ratings, operating condition ranges, other parameters) listed products specifications SANYO Semiconductor Co.,Ltd. products described contained herein. SANYO Semiconductor Co.,Ltd. strives supply high-quality high-reliability products, however, semiconductor products fail malfunction with some probability. possible that these probabilistic failures malfunction could give rise accidents events that could endanger human lives, trouble that could give rise smoke fire, accidents that could cause damage other property. When designing equipment, adopt safety measures that these kinds accidents events cannot occur. Such measures include limited protective circuits error prevention circuits safe design, redundant design, structural design. event that SANYO Semiconductor Co.,Ltd. products described contained herein controlled under applicable local export control laws regulations, such products require export license from authorities concerned accordance with above law. part this publication reproduced transmitted form means, electronic mechanical, including photocopying recording, information storage retrieval system, otherwise, without prior written consent SANYO Semiconductor Co.,Ltd. information described contained herein subject change without notice product/technology improvement, etc. When designing equipment, refer "Delivery Specification" SANYO Semiconductor Co.,Ltd. product that intend use. Information (including circuit diagrams circuit parameters) herein example only; guaranteed volume production. Upon using technical information products described herein, neither warranty license shall granted with regard intellectual property rights other rights SANYO Semiconductor Co.,Ltd. third party. SANYO Semiconductor Co.,Ltd. shall liable claim suits with regard third party's intellectual property rights which resulted from technical information products mentioned above.
This catalog provides information June, 2009. Specifications information herein subject change without notice.
No.A1432-27/27
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