LC872G08A LC872G06A LC872G04A CMOS 8K/6K/4K-byte 256-byte integra

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LC872G08A LC872G06A LC872G04A CMOS 8K/6K/4K-byte 256-byte integra

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Ordering number ENA1400
LC872G08A LC872G06A LC872G04A
CMOS 8K/6K/4K-byte 256-byte integrated
8-bit 1-chip Microcontroller
SANYO LC872G08A/06A/04A 8-bit microcomputer that, centered around running minimum cycle time 83.3ns, integrates single chip number hardware features such 8K/6K/4K-byte ROM, 256-byte RAM, sophisticated 16-bit timers/counters (may divided into 8-bit timers), 16-bit timer/counter (may divided into 8-bit timers/counters 8-bit PWMs), 8-bit timers with prescaler, base timer serving time-of-day clock, high-speed clock counter, synchronous interface, asynchronous/synchronous interface, UART interface (full duplex), 12-bit/8-bit 8-channel converter, system clock frequency divider, internal reset 18-source 10-vector interrupt feature.
Features
8192 bits (LC872G08A) 6144 bits (LC872G06A) 4096 bits (LC872G04A) bits (LC872G08A/06A/04A)
SANYO Semiconductor Co.,Ltd. products described contained herein are, with regard "standard application", intended general electronics equipment (home appliances, equipment, communication device, office equipment, industrial equipment etc.). products mentioned herein shall intended "special application" (medical equipment whose purpose sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level reliability directly threaten human lives case failure malfunction product cause harm human bodies, shall they grant guarantee thereof. should intend products applications outside standard applications customer considering such and/or outside scope intended standard applications, please consult with prior intended use. there consultation inquiry before intended use, customer shall solely responsible use. Specifications SANYO Semiconductor Co.,Ltd. products described contained herein stipulate performance, characteristics, functions described products independent state, guarantees performance, characteristics, functions described products mounted customer' products equipment. verify symptoms states that cannot evaluated independent device, customer should always evaluate test devices mounted customer' products equipment.
Ver. 0.40
12109HKIM 20081216-S00009 No.A1400-1/27
LC872G08A/06A/04A
Minimum Cycle 83.3ns (12MHz VDD=2.7V 5.5V) 100ns (10MHz VDD=2.2V 5.5V) 250ns (4MHz VDD=1.8V 5.5V) Note: cycle time here refers read speed. Minimum Instruction Cycle Time 250ns (12MHz VDD=2.7V 5.5V) 300ns (10MHz VDD=2.2V 5.5V) 750ns (4MHz VDD=1.8V 5.5V) Ports Normal withstand voltage ports Ports direction designated 1-bit units Ports direction designated 4-bit units Dedicated oscillator ports/input ports Reset Power pins
(P1n, P20, P21, P70) (P0n) (CF1/XT1, CF2/XT2) (RES) (VSS1, VDD1)
Timers Timer 16-bit timer/counter with capture register. Mode 8-bit timer with 8-bit programmable prescaler (with 8-bit capture register) channels Mode 8-bit timer with 8-bit programmable prescaler (with 8-bit capture register) 8-bit counter (with 8-bit capture register) Mode 16-bit timer with 8-bit programmable prescaler (with 16-bit capture register) Mode 16-bit counter (with 16-bit capture register) Timer 16-bit timer/counter that supports PWM/toggle outputs Mode 8-bit timer with 8-bit prescaler (with toggle outputs) 8-bit timer/ counter with 8-bit prescaler (with toggle outputs) Mode 8-bit with 8-bit prescaler channels Mode 16-bit timer/counter with 8-bit prescaler (with toggle outputs) (toggle outputs also possible from lower-order bits) Mode 16-bit timer with 8-bit prescaler (with toggle outputs) (The lower-order bits used PWM) Timer 8-bit timer with 6-bit prescaler (with toggle outputs) Timer 8-bit timer with 6-bit prescaler (with toggle outputs) Base timer clock selectable from subclock (32.768kHz crystal oscillation), system clock, timer prescaler output. Interrupts programmable different time schemes High-Speed Clock Counter count clocks with maximum clock rate 20MHz main clock 10MHz). generate output real time. SIO0: 8-bit Synchronous serial interface first/MSB first mode selectable Built-in 8-bit baudrate generator (maximum transfer clock cycle=4/3tCYC) SIO1: 8-bit asynchronous/synchronous serial interface Mode Synchronous 8-bit serial 3-wire configuration, tCYC transfer clocks) Mode Asynchronous serial (half-duplex, data bits, stop bit, 2048 tCYC baudrates) Mode mode (start bit, data bits, tCYC transfer clocks) Mode mode (start detect, data bits, stop detect)
No.A1400-2/27
LC872G08A/06A/04A
UART Full duplex 7/8/9 data bits selectable stop bits continuous data transmission) Built-in baudrate generator Converter: bits/8 bits channels bits/8 bits converter resolution selectable Remote Control Receiver Circuit (sharing pins with P15, SCK1, INT3, T0IN) Noise rejection function (noise filter time constant selectable from tCYC, tCYC, tCYC) Clock Output Function generate clock outputs with frequency 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 source clock selected system clock. generate source clock subclock Watchdog Timer External watchdog timer Interrupt reset signals selectable Interrupts sources, vector addresses Provides three levels (low (L), high (H), highest (X)) multiplex interrupt control. interrupt requests level equal lower than current interrupt accepted. When interrupt requests more vector addresses occur same time, interrupt highest level takes precedence over other interrupts. interrupts same level, interrupt into smallest vector address takes precedence.
Vector Address 00003H 0000BH 00013H 0001BH 00023H 0002BH 00033H 0003BH 00043H 0004BH Level INT0 INT1 INT2/T0L/INT4 INT3/base timer T1L/T1H SIO0/UART1 receive SIO1/UART1 transmit ADC/T6/T7 Port Interrupt Source
Priority levels interrupts same level, with smallest vector address takes precedence. Subroutine Stack Levels: 128levels (The stack allocated RAM.) High-speed Multiplication/Division Instructions bits bits tCYC execution time) bits bits tCYC execution time) bits bits tCYC execution time) bits bits tCYC execution time)
No.A1400-3/27
LC872G08A/06A/04A
Oscillation Circuits Internal oscillation circuits Low-speed oscillation circuit system clock (100kHz) Medium-speed oscillation circuit system clock (1MHz) Multifrequency oscillation circuit system clock (8MHz) External oscillation circuits Hi-speed oscillation circuit: system clock, with internal speed crystal oscillation circuit: low-speed system clock, with internal crystal oscillation circuits share same pins. active circuit selected under program control. Both crystal oscillator circuits stop operation system reset. When reset released, only oscillation circuit resumes operation. System Clock Divider Function current. minimum instruction cycle selectable from 300ns, 600ns, 1.2s, 2.4s, 4.8s, 9.6s, 19.2s, 38.4s, 76.8s main clock rate 10MHz). Internal Reset Function Power-on reset (POR) function reset generated only power-on time. release level selected from levels (1.67V, 1.97V, 2.07V, 2.37V, 2.57V, 2.87V, 3.86V, 4.35V) through option configuration. Low-voltage detection reset (LVD) function functions combined generate resets when power turned when power voltage falls below certain level. use/disuse function voltage threshold level levels: 1.91V, 2.01V, 2.31V, 2.51V, 2.81V, 3.79V, 4.28V). Standby Function HALT mode: Halts instruction execution while allowing peripheral circuits continue operation. Oscillation halted automatically. HOLD mode: Suspends instruction execution operation peripheral circuits. crystal oscillators automatically stop operation. There four ways resetting HOLD mode. Setting reset lower level. System resetting watchdog timer low-voltage detection Having interrupt source established either INT0, INT1, INT2 INT4 INT0 INT1 HOLD mode reset available only when level detection set. Having interrupt source established port X'tal HOLD mode: Suspends instruction execution operation peripheral circuits except base timer. oscillator automatically stop operation. state crystal oscillations established when X'tal HOLD mode entered retained. There five ways resetting X'tal HOLD mode. Setting reset level. System resetting watchdog timer low-voltage detection. Having interrupt source established either INT0, INT1, INT2 INT4 INT0 INT1 HOLD mode reset available only when level detection set. Having interrupt source established port Having interrupt source established base timer circuit. Note: Available only when X'tal oscillation selected.
No.A1400-4/27
LC872G08A/06A/04A
Package Form MFP24S (300mil): Lead-free type SSOP24 (225mil): Lead-free type (Development) Development Tools On-chip debugger: TCB87 TypeB LC87D2G08A TCB87 TypeB LC87F2G08A Note: LC87F2G08A On-chip debugger function limited. Flash Version LC87F2G08A
Package Dimensions
unit (typ) 3112B
12.5
Package Dimensions
unit (typ) 3287
0.63
(0.75) 0.35
0.15
(0.5)
1.7max
0.22 0.15
SANYO MFP24S(300mil)
SANYO SSOP24(225mil)
(1.3)
1.5max
(1.5)
No.A1400-5/27
LC872G08A/06A/04A
Assignment
P70/INT0/T0LCP/AN8 VSS1 CF1/XT1 CF2/XT2 VDD1 P10/SO0 P11/SI0/SB0 P12/SCK0 P13/SO1 P14/SI1/SB1 P15/SCK1/INT3/T0IN
P07/T7O P06/AN6/T6O P05/AN5/CKO P04/AN4 P03/AN3 P02/AN2 P01/AN1 P00/AN0 P21/URX/INT4/T1IN P20/UTX/INT4/T1IN P17/T1PWMH/BUZ/INT1/T0HCP P16/T1PWML/INT2/T0IN
LC872G08A LC872G06A LC872G04A
view
SANYO: MFP24S (300mil) "Lead-free Type" SANYO: SSOP24 (225mil) "Lead-free Type" (Development)
MFP24S SSOP24
NAME P70/INT0/T0LCP/AN8 VSS1 CF1/XT1 CF2/XT2 VDD1 P10/SO0 P11/SI0/SB0 P12/SCK0 P13/SO1 P14/SI1/SB1 P15/SCK1/INT3/T0IN
MFP24S SSOP24
NAME P16/T1PWML/INT2/T0IN P17/T1PWMH/BUZ/INT1/T0HCP P20/UTX/INT4/T1IN P21/URX/INT4/T1IN P00/AN0 P01/AN1 P02/AN2 P03/AN3 P04/AN4 P05/AN5/CKO P06/AN6/T6O P07/T7O
No.A1400-6/27
LC872G08A/06A/04A
System Block Diagram
Interrupt control
Standby control
Flash
X'tal Reset control Clock generator
Reset circuit (LVD/POR)
register
register
SIO0
interface
SIO1
Port
Timer
Port
Timer
Port
Timer
Port
Timer
Stack pointer
Base timer
INT0 INT3 (Noise filter)
UART1
Port INT4
No.A1400-7/27
LC872G08A/06A/04A
Description
Name VSS1 VDD1 Port Power supply Power supply 8-bit port specifiable 4-bit units Pull-up resistors turned 4-bit units. HOLD reset input Port interrupt input functions P05: System clock output P06: Timer toggle output P07: Timer toggle output P00(AN0) P06(AN6): converter input Port 8-bit port specifiable 1-bit units Pull-up resistors turned 1-bit units. functions P10: SIO0 data output P11: SIO0 data input/bus P12: SIO0 clock P13: SIO1 data output P14: SIO1 data input P15: SIO1 clock INT3 input (with noise filter) timer event input timer capture input P16: Timer 1PWML output INT2 input/HOLD reset input/timer event input timer capture input P17: Timer 1PWMH output beeper output INT1 input HOLD reset input timer capture input Interrupt acknowledge type Rising INT1 INT2 INT3 enable enable enable Falling enable enable enable Rising Falling disable enable enable level enable disable disable level enable disable disable Description Option
Port
2-bit port specifiable 1-bit units Pull-up resistors turned 1-bit units. functions P20: UART transmit P21: UART receive P21: INT4 input HOLD reset input timer event input timer capture input timer capture input Interrupt acknowledge types Rising INT4 enable Falling enable Rising Falling enable level disable level disable
Continued next page.
No.A1400-8/27
LC872G08A/06A/04A
Continued from preceding page.
Name Port 1-bit port specifiable 1-bit units Pull-up resistors turned 1-bit units. functions P70: INT0 input HOLD reset input timer capture input watchdog timer output P70(AN8): converter input Interrupt acknowledge types Rising INT0 CF1/XT1 enable Falling enable Rising Falling disable level enable level enable Description Option
External reset input internal reset output Ceramic resonator 32.768kHz crystal oscillator input function General-purpose input port
CF2/XT2
Ceramic resonator 32.768kHz crystal oscillator output function General-purpose input port
Port Output Types
table below lists types port outputs presence/absence pull-up resistor. Data read into input port even output mode.
Port Name Option selected units Option type CMOS Nch-open drain CMOS Nch-open drain CMOS Nch-open drain Nch-open drain Output type Pull-up resistor Programmable (Note Programmable Programmable Programmable Programmable Programmable
Note control presence absence programmable pull-up resistors port switching between low-and high-impedance pull-up connection exercised nibble (4-bit) units (P00 07).
User Option Table
Option Name Port output form Option Type Mask Version Flash Version Option Selected Units Option Selection CMOS Nch-open drain CMOS Nch-open drain CMOS Nch-open drain Program start address Low-voltage detection reset function Power-on reset function Detect level Power-On reset level Detect function 00000h 01E00h Enable:Use Disable:Not Used 7-level 8-level
Mask option selection change possible after mask completed. Program start address mask version 00000h.
No.A1400-9/27
LC872G08A/06A/04A
Recommended Unused Connections
Recommended Unused Connections Port Name Board CF1/XT1 CF2/XT2 Open Open Open Open Pulled with 100k resistor less Pulled with 100k resistor less Software Output Output Output Output General-purpose input port General-purpose input port
Notes CF1/XT1 CF2/XT2 pins When using general-purpose input ports Since CF1/XT1 CF2/XT2 pins configured oscillator pins system reset time, necessary current limiting resistor greater CF2/XT2 series when using them general-purpose input pins. Differences between flash mask version
System Reset Time State Flash version LC87F2G08A Mask version LC872G08A/06A/04A CF1/XT1 CF2/XT2 CF1/XT1 CF2/XT2 high internal resistor high internal resistor After System Reset Released oscillation state oscillation state oscillation state oscillation state
Power Treatment Recommendations (VDD1, VSS1)
Connect bypass capacitors that meet following conditions between VDD1 VSS1 pins: Connect among VDD1 VSS1 pins bypass capacitors with shortest possible heavy lead wires, making sure that impedances between both pins bypass capacitors equal possible (L1=L1', L2=L2'). Connect large-capacity capacitor small-capacity capacitor parallel. capacitance should approximately 0.1F.
VSS1
VDD1
No.A1400-10/27
LC872G08A/06A/04A
Absolute Maximum Ratings 25°C, VSS1
Parameter Maximum supply voltage Input voltage Input/output voltage Peak output High level output current current Mean output current (Note 1-1) Total output current IOAH(1) IOAH(2) IOAH(3) Peak output current IOPL(2) level output current IOPL(3) Mean output current (Note 1-1) IOML(2) IOML(3) Total output current IOAL(1) IOAL(2) IOAL(3) IOAL(4) Power Dissipation max(2) max(1) IOML(1) IOPL(1) Ports Ports Ports P00, Ports P00, Port Ports MFP24S(300mil) Total applicable pins Total applicable pins Ta=-40 +85°C Package only Ta=-40 +85°C Package with thermal resistance board (Note 1-2) max(3) max(4) SSOP24(225mil) Ta=-40 +85°C Package only Ta=-40 +85°C Package with thermal resistance board (Note 1-2) Operating ambient temperature Storage ambient temperature Tstg Topr +125 applicable applicable Total applicable pins Total applicable pins applicable applicable applicable Total applicable pins applicable Total applicable pins Total applicable pins IOMH Ports IOPH CF1, Ports Ports CMOS output select applicable CMOS output select applicable -7.5 Symbol Pin/Remarks VDD1 Conditions VDD[V] -0.3 -0.3 -0.3 Specification +6.5 VDD+0.3 VDD+0.3 unit
Note 1-1: mean output current mean value measured over 100ms. Note 1-2: SEMI standards thermal resistance board (size: glass epoxy) used.
No.A1400-11/27
LC872G08A/06A/04A
Allowable Operating Conditions -40°C +85°C, VSS1
Parameter Operating supply voltage Symbol VDD(1) VDD(2) VDD(3) Memory sustaining supply voltage High level input voltage VIH(2) VIH(3) VIH(4) level input voltage VIL(2) VIL(1) VIH(1) Ports port input/ interrupt side Ports Port watchdog timer side CF1, Ports port input/ interrupt side Ports VIL(3) VIL(4) Instruction cycle time tCYC (Note 2-1) Port watchdog timer side CF1, External system clock frequency FEXCF open System clock frequency division ratio=1/1 External system clock duty=50±5% open System clock frequency division ratio=1/2 External system clock duty=50±5% Oscillation frequency range (Note 2-2) FmCF(3) CF1, FmCF(2) CF1, FmCF(1) CF1, 12MHz ceramic oscillation. Fig. 10MHz ceramic oscillation. Fig. 4MHz ceramic oscillation. oscillation normal amplifier size selected. (CFLAMP=0) Fig. 4MHz ceramic oscillation. oscillation amplifier size selected. (CFLAMP=1) Fig. FmMRC Frequency variable oscillation. frequency division ratio. (RCCTD=0) (Note 2-3) FmRC FmSRC FsX'tal XT1, Internal medium-speed oscillation Internal low-speed oscillation 32.768kHz crystal oscillation Fig. 32.768 7.44 8.56 24.4 0.245 0.294 0.735 0.2VDD 0.15VDD+0.4 0.2VDD 0.8VDD-1.0 0.25VDD 0.3VDD+0.7 0.9VDD 0.75VDD 0.1VDD+0.4 0.3VDD+0.7 VDD1 Pin/Remarks VDD1 Conditions VDD[V] 0.245s tCYC 200s 0.294s tCYC 200s 0.735s tCYC 200s register contents sustained HOLD mode. Specification unit
Note 2-1: Relationship between tCYC oscillation frequency 3/FmCF division ratio 6/FmCF division ratio 1/2. Note 2-2: Tables oscillation constants. Note 2-3: When switching system clock, allow oscillation stabilization time 100s longer after multifrequency oscillator circuit transmits from "oscillation stopped" "oscillation enabled" state.
No.A1400-12/27
LC872G08A/06A/04A
Electrical Characteristics -40°C +85°C, VSS1
Parameter High level input current Symbol IIH(1) Pin/Remarks Ports P70, Conditions VDD[V] Output disabled Pull-up resistor VIN=VDD (Including output Tr's leakage current) IIH(2) level input current IIL(1) Ports P70, VIN=VDD Output disabled Pull-up resistor VIN=VSS (Including output Tr's leakage current) IIL(2) High level output voltage VOH(1) VOH(2) VOH(3) level output voltage VOL(1) VOL(2) VOL(3) VOL(4) VOL(5) VOL(6) VOL(7) VOL(8) Pull-up resistance Rpu(1) Rpu(2) Rpu(3) Ports Port P00, Ports Ports VIN=VSS IOH=-1mA IOH=-0.35mA IOH=-0.15mA IOL=10mA IOL=1.4mA IOL=0.8mA IOL=1.4mA IOL=0.8mA IOL=25mA IOL=4mA IOL=2mA VOH=0.9VDD When Port selected low-impedance pull-up. VOH=0.9VDD When Port selected high-impedance pull-up. Hysteresis voltage VHYS(1) VHYS(2) capacitance Ports P70, pins pins other than that under test: VIN=VSS f=1MHz Ta=25°C 0.1VDD 0.07VDD VDD-1 VDD-0.4 VDD-0.4 Specification unit
No.A1400-13/27
LC872G08A/06A/04A
Serial Characteristics -40°C +85°C, VSS1
SIO0 Serial Characteristics (Note 4-1-1)
Parameter Frequency Input clock level pulse width High level pulse width Output clock Frequency level pulse width High level pulse width Serial input Data setup time Data hold time Output delay Input clock time tdD0(2) tdD0(3) tsDI(1) thDI(1) tdD0(1) SO0(P10), SB0(P11) SB0(P11), SI0(P11) Must specified with respect rising edge SIOCLK. Fig. Continuous data transmission/reception mode (Note 4-1-2) Synchronous 8-bit mode (Note 4-1-2) Output clock (Note 4-1-2) 0.05 (1/3)tCYC +0.08 1tCYC +0.08 0.05 tSCKH(2) tSCK(2) tSCKL(2) SCK0(P12) CMOS output selected Fig. tSCK tSCKH(1) Symbol tSCK(1) tSCKL(1) Pin/ Remarks SCK0(P12) Conditions VDD[V] Fig. tCYC Specification unit
Serial output
Serial clock
(1/3)tCYC +0.08
Note 4-1-1: These specifications theoretical values. margin depending use. Note 4-1-2: Must specified with respect falling edge SIOCLK. Must specified time beginning output state change open drain output mode. Fig. SIO1 Serial Characteristics (Note 4-2-1)
Parameter Frequency Input clock level pulse width High level pulse width Frequency Output clock level pulse width High level pulse width Data setup time Serial input tsDI(2) SB1(P14), SI1(P14) Data hold time thDI(2) Must specified with respect rising edge SIOCLK. Fig. 0.05 Output delay time Serial output tdD0(4) SO1(P13), SB1(P14) Must specified with respect falling edge SIOCLK. Must specified time beginning output state change open drain output mode. Fig. (1/3)tCYC +0.08 0.05 tSCKH(4) tSCK(4) tSCKL(4) SCK1(P15) CMOS output selected Fig. tSCKH(3) Symbol tSCK(3) tSCKL(3) Pin/ Remarks SCK1(P15) Fig. Conditions VDD[V] tCYC tSCK Specification unit
Note 4-2-1: These specifications theoretical values. margin depending use.
Serial clock
No.A1400-14/27
LC872G08A/06A/04A
Pulse Input Conditions -40°C +85°C, VSS1
Parameter High/low level pulse width Symbol tPIH(1) tPIL(1) Pin/Remarks INT0(P70), INT1(P17), INT2(P16), INT4(P20 P21) tPIH(2) tPIL(2) tPIH(3) tPIL(3) tPIH(4) tPIL(4) tPIL(5) INT3(P15) when noise filter time constant INT3(P15) when noise filter time constant 1/32 INT3(P15) when noise filter time constant 1/128 Interrupt source flag set. Event inputs timer enabled. Interrupt source flag set. Event inputs timer nabled. Interrupt source flag set. Event inputs timer enabled. Resetting enabled. tCYC Conditions VDD[V] Interrupt source flag set. Event inputs timer enabled. Specification unit
No.A1400-15/27
LC872G08A/06A/04A
Converter Characteristics VSS1 <12bits Converter Mode/Ta -40°C +85°C
Parameter Resolution Absolute accuracy Conversion time TCAD Symbol Pin/Remarks AN0(P00) AN6(P06), AN8(P70) (Note 6-1) (Note 6-1) Conversion time calculation formulas. (Note 6-2) Conversion time calculation formulas. (Note 6-2) Analog input voltage range Analog port input current IAINH IAINL VAIN=VDD VAIN=VSS VAIN Conditions VDD[V] Specification unit
<8bits Converter Mode/Ta -40°C +85°C
Parameter Resolution Absolute accuracy Conversion time TCAD Symbol Pin/Remarks AN0(P00) AN6(P06) AN8(P70) Conversion time calculation formulas. (Note 6-2) Conversion time calculation formulas. (Note 6-2) Analog input voltage range Analog port input current IAINH IAINL VAIN=VDD VAIN=VSS VAIN (Note 6-1) Conditions VDD[V] Specification ±1.5 unit
Conversion time calculation formulas: 12bits Converter Mode: TCAD(Conversion time) ((52/(AD division 8bits Converter Mode: TCAD(Conversion time) ((32/(AD division
External oscillation (FmCF) CF-12MHz Operating supply voltage range (VDD) 4.0V 5.5V 3.0V 5.5V CF-10MHz 4.0V 5.5V 3.0V 5.5V CF-4MHz 3.0V 5.5V 2.4V 3.6V System division ratio (SYSDIV) Cycle time (tCYC) 250ns 250ns 300ns 300ns 750ns 750ns division ratio (ADDIV) 1/16 1/16 1/32 12bit 34.8s 69.5s 41.8s 83.4s 104.5s 416.5s conversion time (TCAD) 8bit 21.5s 42.8s 25.8s 51.4s 64.5s 256.5s
Note 6-1: quantization error (±1/2LSB) must excluded from absolute accuracy. absolute accuracy must measured microcontroller's state which operations occur pins adjacent analog input channel. Note 6-2: conversion time refers period from time instruction starting conversion process till time conversion results register(s) loaded with complete digital conversion value corresponding analog input value. conversion time times normal-time conversion time when: first conversion performed 12-bit conversion mode after system reset. first conversion performed after conversion mode switched from 8-bit 12-bit conversion mode.
No.A1400-16/27
LC872G08A/06A/04A
Power-on Reset (POR) Characteristics -40°C +85°C, VSS1
Specification Parameter release voltage Symbol PORRL Pin/Remarks Conditions Select from option. (Note 7-1) Option selected voltage 1.67V 1.97V 2.07V 2.37V 2.57V 2.87V 3.86V 4.35V Detection voltage unknown state Power supply rise time PORIS Power supply rise time from 1.6V. POUKS Fig. (Note 7-2) 0.95 1.55 1.85 1.95 2.25 2.45 2.75 3.73 4.21 1.67 1.97 2.07 2.37 2.57 2.87 3.86 4.35 1.79 2.09 2.19 2.49 2.69 2.99 3.99 4.49 unit
Note7-1: release level selected levels only when reset function disabled. Note7-2: unknown state before transistors start operation.
Voltage Detection Reset (LVD) Characteristics -40°C +85°C, VSS1=0V
Specification Parameter reset voltage (Note 8-2) Symbol LVDET Pin/Remarks Conditions Select from option. (Note 8-1) (Note 8-3) Fig. Option selected voltage 1.91V 2.01V 2.31V 2.51V 2.81V 3.79V 4.28V hysteresys width LVHYS 1.91V 2.01V 2.31V 2.51V 2.81V 3.79V 4.28V Detection voltage unknown state voltage detection minimum width (Reply sensitivity) TLVDW LVUKS Fig. (Note 8-4) LVDET-0.5V Fig. 0.95 1.81 1.91 2.21 2.41 2.71 3.69 4.18 1.91 2.01 2.31 2.51 2.81 3.79 4.28 2.01 2.11 2.41 2.61 2.91 3.89 4.38 unit
Note8-1: reset level selected levels only when reset function enabled. Note8-2: reset voltage specification values include hysteresis voltage. Note8-3: reset voltage exceed specification values when port output state changes and/or when large current flows through port. Note8-4: unknown state before transistors start operation.
No.A1400-17/27
LC872G08A/06A/04A
Consumption Current Characteristics -40°C +85°C, VSS1
Parameter Normal mode consumption current (Note 9-1) (Note 9-2) IDDOP(2) Symbol IDDOP(1) Pin/ Remarks VDD1 Conditions VDD[V] FmCF=12MHz ceramic oscillation mode System clock 12MHz side Internal speed medium speed oscillation stopped. Frequency variable oscillation stopped. frequency division ratio CF1=24MHz external clock System clock side Internal speed medium speed oscillation stopped. Frequency variable oscillation stopped. frequency division ratio IDDOP(3) FmCF=10MHz ceramic oscillation mode System clock 10MHz side Internal speed medium speed oscillation stopped. Frequency variable oscillation stopped. frequency division ratio IDDOP(4) FmCF=4MHz ceramic oscillation mode System clock 4MHz side Internal speed medium speed oscillation stopped. Frequency variable oscillation stopped. frequency division ratio IDDOP(5) oscillation amplifier size selected. (CFLAMP=1) FmCF=4MHz ceramic oscillation mode System clock 4MHz side Internal speed medium speed oscillation stopped. Frequency variable oscillation stopped. frequency division ratio IDDOP(6) FsX'tal=32.768kHz crystal oscillation mode Internal speed oscillation stopped. System clock internal medium speed oscillation. Frequency variable oscillation stopped. frequency division ratio IDDOP(7) FsX'tal=32.768kHz crystal oscillation mode Internal speed medium speed oscillation stopped. System clock 8MHz with frequency variable oscillation frequency division ratio IDDOP(8) External FsX'tal FmCF oscillation stopped. System clock internal speed oscillation. Internal medium speed oscillation sopped. Frequency variable oscillation stopped. frequency division ratio IDDOP(9) External FsX'tal FmCF oscillation stopped. System clock internal speed oscillation. Internal medium speed oscillation stopped. Frequency variable oscillation stopped. frequency division ratio Ta=-10 +50°C 11.2 10.5 Specification unit
Note9-1: Values consumption current include current that flows into output transistors internal pull-up resistors. Note9-2: consumption current values include operational current function specified.
Continued next page.
No.A1400-18/27
LC872G08A/06A/04A
Continued from preceding page.
Parameter Normal mode consumption current (Note 9-1) (Note 9-2) IDDOP(11) Symbol IDDOP(10) Pin/ Remarks VDD1 Conditions VDD[V] FsX'tal=32.768kHz crystal oscillation mode System clock 32.768kHz side Internal speed medium speed oscillation stopped. Frequency variable oscillation stopped. frequency division ratio FsX'tal=32.768kHz crystal oscillation mode System clock 32.768kHz side Internal speed medium speed oscillation stopped. Frequency variable oscillation stopped. frequency division ratio Ta=-10 +50°C HALT mode consumption current (Note 9-1) (Note 9-2) IDDHALT(1) HALT mode FmCF=12MHz ceramic oscillation mode System clock 12MHz side Internal speed medium speed oscillation stopped. Frequency variable oscillation stopped. frequency division ratio IDDHALT(2) HALT mode CF1=24MHz external clock System clock side Internal speed medium speed oscillation stopped. Frequency variable oscillation stopped. frequency division ratio IDDHALT(3) HALT mode FmCF=10MHz ceramic oscillation mode System clock 10MHz side Internal speed medium speed oscillation stopped. Frequency variable oscillation stopped. frequency division ratio IDDHALT(4) HALT mode FmCF=4MHz ceramic oscillation mode System clock 4MHz side Internal speed medium speed oscillation stopped. Frequency variable oscillation stopped. frequency division ratio IDDHALT(5) HALT mode oscillation amplifier size selected. (CFLAMP=1) FmCF=4MHz ceramic oscillation mode System clock 4MHz side Internal speed medium speed oscillation stopped. Frequency variable oscillation stopped. frequency division ratio IDDHALT(6) HALT mode FsX'tal=32.768kHz crystal oscillation mode Internal speed oscillation stopped. System clock internal medium speed oscillation Frequency variable oscillation stopped. frequency division ratio Specification unit
Note9-1: Values consumption current include current that flows into output transistors internal pull-up resistors. Note9-2: consumption current values include operational current function specified.
Continued next page.
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Continued from preceding page.
Parameter HALT mode consumption current (Note 9-1) (Note 9-2) Symbol IDDHALT(7) Pin/ remarks VDD1 HALT mode FsX'tal=32.768kHz crystal oscillation mode Internal speed medium speed oscillation stopped. System clock 8MHz with frequency variable oscillation frequency division ratio IDDHALT(8) HALT mode External FsX'tal FmCF oscillation stopped. System clock internal speed oscillation. Internal medium speed oscillation stopped. Frequency variable oscillation stopped. frequency division ratio IDDHALT(9) HALT mode External FsX'tal FmCF oscillation stopped. System clock internal speed oscillation. Internal medium speed oscillation stopped. Frequency variable oscillation stopped. frequency division ratio Ta=-10 +50°C IDDHALT(10) HALT mode FsX'tal=32.768kHz crystal oscillation mode System clock 32.768kHz side Internal speed medium speed oscillation stopped. Frequency variable oscillation stopped. frequency division ratio IDDHALT(11) HALT mode FsX'tal=32.768kHz crystal oscillation mode System clock 32.768kHz side Internal speed medium speed oscillation stopped. Frequency variable oscillation stopped. frequency division ratio Ta=-10 +50°C HOLD mode consumption current (Note 9-1) (Note 9-2) IDDHOLD(3) IDDHOLD(2) IDDHOLD(1) HOLD mode CF1=VDD open (External clock mode) HOLD mode CF1=VDD open (External clock mode) Ta=-10 +50°C HOLD mode CF1=VDD open (External clock mode) option selected IDDHOLD(4) HOLD mode CF1=VDD open (External clock mode) Ta=-10 +50°C option selected Timer HOLD mode consumption current (Note 9-1) (Note 9-2) IDDHOLD(6) IDDHOLD(5) Timer HOLD mode FsX'tal=32.768 crystal oscillation mode Timer HOLD mode FsX'tal=32.768kHz crystal oscillation mode Ta=-10 +50°C 0.02 0.01 0.02 0.01 0.009 Conditions VDD[V] Specification unit
Note9-1: Values consumption current include current that flows into output transistors internal pull-up resistors. Note9-2: consumption current values include operational current function specified.
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UART (Full Duplex) Operating Conditions -40°C +85°C, VSS1
Parameter Transfer rate Symbol Pin/Remarks UTX(P20) URX(P21) Conditions VDD[V] 16/3 Specification 8192/3 unit tCYC
Data length: Stop bits Parity bits:
7/8/9 bits (LSB first) (2-bit continuous data transmission) None Example Continuous 8-bit Data Transmission Mode Processing (First Transmit Data=55H)
Start Stop Transmit data (LSB first) transmission
Start transmission
Example Continuous 8-bit Data Reception Mode Processing (First Receive Data=55H)
Start Start reception Receive data (LSB first)
Stop reception
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Characteristics Sample Main System Clock Oscillation Circuit
Given below characteristics sample main system clock oscillation circuit that measured using SANYO-designated oscillation characteristics evaluation board external components with circuit constant values with which oscillator vendor confirmed normal stable oscillation. Table Characteristics Sample Main System Clock Oscillator Circuit with Ceramic Oscillator oscillation normal amplifier size selected (CFLAMP=0) MURATA
Nominal Frequency Circuit Constant Type Oscillator Name [pF] 12MHz CSTCE12M0G52-R0 (10) [pF] (10) Open Open 10MHz LEAD CSTLS10M0G53-B0 (15) (15) CSTCE10M0G52-R0 (10) (10) Open Open Open Open 8MHz LEAD CSTLS8M00G53-B0 (15) (15) CSTCE8M00G52-R0 (10) (10) Open Open Open Open 6MHz LEAD CSTLS6M00G53-B0 (15) (15) CSTCR6M00G53-R0 (15) (15) Open Open Open Open 4MHz LEAD CSTLS4M00G53-B0 (15) (15) CSTCR4M00G53-R0 (15) (15) Open Open Open Open 1.0k 1.0k 1.0k 1.0k 1.5k 1.0k 1.5k 1.5k 2.2k 1.5k 2.2k 1.5k 3.3k 1.5k 3.3k Operating Voltage Range Oscillation Stabilization Time [ms] [ms] Internal C1,C2 Remarks
oscillation amplifier size selected (CFLAMP=1) MURATA
Nominal Frequency Circuit Constant Type Oscillator Name [pF] CSTCR4M00G53-R0 CSTCR4M00G53095-R0 4MHz CSTLS4M00G53-B0 LEAD CSTLS4M00G53095-B0 (15) (15) (15) (15) (15) (15) (15) [pF] (15) Open Open Open Open Open Open Open Open 1.0k 2.2k 1.0k 2.2k 1.0k 2.2k 1.0k 2.2k Operating Voltage Range Oscillation Stabilization Time [ms] [ms] Internal C1,C2 Remarks
oscillation stabilizing time period until oscillation becomes stable after becomes higher than minimum operating voltage. (See Fig. Time till oscillation gets stabilized after reset state released Till oscillation gets stabilized after instruction starting main clock oscillation circuit executed Till oscillation gets stabilized after HOLD mode reset. Till oscillation gets stabilized after X'tal HOLD mode reset with CFSTOP (OCR register,
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Characteristics Sample Subsystem Clock Oscillator Circuit
Given below characteristics sample subsystem clock oscillation circuit that measured using SANYOdesignated oscillation characteristics evaluation board external components with circuit constant values with which oscillator vendor confirmed normal stable oscillation. Table Characteristics Sample Subsystem Clock Oscillator Circuit with Crystal Oscillator EPSON TOYOCOM
Nominal Frequency Type Oscillator Name [pF] 32.768kHz MC-306 Circuit Constant [pF] Operating Voltage Range Oscillation Stabilization Time Applicable value 7.0pF Remarks
oscillation stabilizing time period until oscillation becomes stable after becomes higher than minimum operating voltage. (See Fig. Till oscillation gets stabilized after instruction starting subclock oscillation circuit executed Till oscillation starts gets stabilized after HOLD mode reset when EXTOSC (OCR register, CFSTOP (OCR register, (Notes implementation oscillator circuit) Oscillation influenced circuit pattern layout printed circuit board. Place oscillation-related components close chip each other possible with shortest possible pattern length. Keep signal lines whose state changes suddenly which large current flows away from oscillator circuit possible make sure that they cross another. sure insert current limiting resistor (Rd) that oscillation amplitude never exceeds input voltage level that specified absolute maximum rating. oscillator circuit constants shown above sample characteristic values that measured using SANYOdesignated oscillation evaluation board. Since accuracy oscillation frequency other characteristics vary according board which installed, recommended that user consult resonator vendor oscillation evaluation user's production board when using applications that require high oscillation accuracy. further information, contact your resonator vendor SANYO Semiconductor sales representative serving your locality. must noted, when replacing flash version microcontroller with mask version, that their operating voltage ranges differ even when oscillation constant external oscillator same.
CF1/XT1
CF2/XT2
CF/X'tal
Figure Oscillator Circuit
0.5VDD
Figure Timing Measurement Point
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Power supply Operating lower limit Reset time
Internal Medium speed oscillation
tmsCF/tmsXtal CF1,
Instruction execution (Note2) Operating mode Unpredictable Reset Instruction execution
Reset Time Oscillation Stabilization Time
HOLD reset signal
HOLD reset signal absent
HOLD reset signal valid
Internal Medium speed oscillation speed oscillation tmsCF CF1, (Note1) tmsX'tal CF1, (Note2)
State
HOLD
HALT
HOLD Reset Signal Oscillation Stabilization Time Note1: Mainclock oscillation circuit selected. Note2: Subclock oscillation circuit selected. Figure Oscillation Stabilization Times
No.A1400-24/27
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RRES
CRES
Note: External circuits reset vary depending usage LVD. Please refer user's manual more information.
Figure Reset Circuit
SIOCLK:
DATAIN:
DATAOUT:
tSCK tSCKL SIOCLK: tsDI DATAIN: tdDO DATAOUT: thDI tSCKH
Figure Serial Output Waveforms
tPIL
tPIH
Figure Pulse Input Timing Signal Waveform
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release voltage (PORRL)
Reset period Unknown-state (POUKS)
100s longer
Reset period
Figure Waveform observed when only used (LVD used) (RESET pin: Pull-up resistor RRES only) function generates reset only when power turned starting level. stable reset will generated power turned again when power level does down level shown (a). such case anticipated, function together with function implement external reset circuit. reset generated only when power level goes down level shown power turned again after this condition continues 100s longer.
hysteresis width (LVHYS) release voltage (LVDET+LVHYS)
reset voltage (LVDET) Reset period Unknown-state (LVUKS) Reset period Reset period
Figure Waveform observed when both functions used (RESET pin: Pull-up resistor RRES only) Resets generated both when power turned when power level lowers. hysteresis width (LVHYS) provided prevent repetitions reset release entry cycles near detection level.
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release voltage
reset voltage
TLVDW
LVDET-0.5V
Figure voltage detection minimum width (Example momentary power loss/Voltage variation waveform)
SANYO Semiconductor Co.,Ltd. assumes responsibility equipment failures that result from using products values that exceed, even momentarily, rated values (such maximum ratings, operating condition ranges, other parameters) listed products specifications SANYO Semiconductor Co.,Ltd. products described contained herein. SANYO Semiconductor Co.,Ltd. strives supply high-quality high-reliability products, however, semiconductor products fail malfunction with some probability. possible that these probabilistic failures malfunction could give rise accidents events that could endanger human lives, trouble that could give rise smoke fire, accidents that could cause damage other property. When designing equipment, adopt safety measures that these kinds accidents events cannot occur. Such measures include limited protective circuits error prevention circuits safe design, redundant design, structural design. event that SANYO Semiconductor Co.,Ltd. products described contained herein controlled under applicable local export control laws regulations, such products require export license from authorities concerned accordance with above law. part this publication reproduced transmitted form means, electronic mechanical, including photocopying recording, information storage retrieval system, otherwise, without prior written consent SANYO Semiconductor Co.,Ltd. information described contained herein subject change without notice product/technology improvement, etc. When designing equipment, refer "Delivery Specification" SANYO Semiconductor Co.,Ltd. product that intend use. Information (including circuit diagrams circuit parameters) herein example only; guaranteed volume production. Upon using technical information products described herein, neither warranty license shall granted with regard intellectual property rights other rights SANYO Semiconductor Co.,Ltd. third party. SANYO Semiconductor Co.,Ltd. shall liable claim suits with regard third party's intellectual property rights which resulted from technical information products mentioned above.
This catalog provides information December, 2008. Specifications information herein subject change without notice.
No.A1400-27/27

LC872G08A LC872G06A LC872G04A CMOS 8K/6K/4K-byte 256-byte integra

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