LC87F5ND0C CMOS FROM 128K byte, 6144 byte on-chip 8-bit 1-ch

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LC87F5ND0C CMOS FROM 128K byte, 6144 byte on-chip 8-bit 1-ch

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Ordering number ENA1380
LC87F5ND0C
CMOS FROM 128K byte, 6144 byte on-chip
8-bit 1-chip Microcontroller
SANYO LC87F5ND0C 8-bit microcomputer that, centered around running minimum cycle time 83.3ns, integrate single chip number hardware features such 128K-byte flash (onboard rewritable), 6144-byte RAM, Onchip debugging function, sophisticated 16-bit timers/counters (may divided into 8-bit timers), 16-bit timer/counter (may divided into 8-bit timers/counters 8-bit PWMs), four 8-bit timers with prescaler, base timer serving time-of-day clock, high-speed clock counter, synchronous ports (with automatic block transmission/reception capabilities), asynchronous/synchronous port, UART ports (full duplex), four 12-bit channels, 8-bit 15-channel converter, system clock frequency divider, 29source 10-vector interrupt feature.
Features
Flash Capable on-board-programing with wide range, 5.5V, voltage source Block-erase byte units 131072 bits 6144 bits Minimum Cycle Time 83.3ns (12MHz) VDD=2.8 5.5V 125ns (8MHz) VDD=2.5 5.5V 500ns (2MHz) VDD=2.2 5.5V Note: cycle time indicates speed read ROM.
This product licensed from Silicon Storage Technology, Inc. (USA), manufactured sold SANYO Semiconductor Co., Ltd.
SANYO Semiconductor Co.,Ltd. products described contained herein are, with regard "standard application", intended general electronics equipment (home appliances, equipment, communication device, office equipment, industrial equipment etc.). products mentioned herein shall intended "special application" (medical equipment whose purpose sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level reliability directly threaten human lives case failure malfunction product cause harm human bodies, shall they grant guarantee thereof. should intend products applications outside standard applications customer considering such and/or outside scope intended standard applications, please consult with prior intended use. there consultation inquiry before intended use, customer shall solely responsible use. Specifications SANYO Semiconductor Co.,Ltd. products described contained herein stipulate performance, characteristics, functions described products independent state, guarantees performance, characteristics, functions described products mounted customer' products equipment. verify symptoms states that cannot evaluated independent device, customer should always evaluate test devices mounted customer' products equipment.
Ver.1.00
10709HKIM 20081126-S00001 A1380-1/25
LC87F5ND0C
Minimum Instruction Cycle Time (tCYC) 250ns (12MHz) VDD=2.8 5.5V 375ns (8MHz) VDD=2.5 5.5V 1.5s (2MHz) VDD=2.2 5.5V Ports Normal withstand voltage ports Ports whose direction designated 1-bit units Ports whose direction designated 2-bit units Ports whose direction designated 4-bit units Normal withstand voltage input port Dedicated oscillator ports Reset pins Power pins
(P1n, P2n, P3n, P73, P8n, PAn, PBn, PCn, S2Pn, PWM0, PWM1, XT2) (PEn, PFn) (P0n) (XT1) (CF1, CF2) (RES) (VSS1 VSS4, VDD1 VDD4)
Timers Timer 16-bit timer/counter with capture register Mode 8-bit timer with 8-bit programmable prescaler (with 8-bit capture registers) channels Mode 8-bit timer with 8-bit programmable prescaler (with 8-bit capture registers) 8-bit counter (with 8-bit capture registers) Mode 16-bit timer with 8-bit programmable prescaler (with 16-bit capture registers) Mode 16-bit counter (with 16-bit capture registers) Timer 16-bit timer/counter that supports PWM/toggle output Mode 8-bit timer with 8-bit prescaler (with toggle outputs) 8-bit timer/counter(with toggle outputs) Mode 8-bit with 8-bit prescaler channels Mode 16-bit timer/counter with 8-bit prescaler (with toggle outputs) (toggle outputs also from lower-order 8-bits) Mode 16-bit timer with 8-bit prescaler (with toggle outputs) (The lower-order bits used PWM.) Timer 8-bit timer with 6-bit prescaler Timer 8-bit timer with 6-bit prescaler Timer 8-bit timer with 6-bit prescaler (with toggle outputs) Timer 8-bit timer with 6-bit prescaler (with toggle outputs) Base timer clock selectable from subclock (32.768kHz crystal oscillation), system clock, timer prescaler output. Interrupts programmable different time schemes. High-speed Clock Counter count clocks with maximum clock rate 24MHz main clock 12MHz). generate output real-time. SIO0: 8-bit synchronous serial interface first/MSB first mode selectable Built-in 8-bit baudrate generator (maximum transfer clock cycle tCYC) Automatic continuous data transmission bits, specifiable units, suspension resumption data transmission possible byte units) SIO1: 8-bit asynchronous/synchronous serial interface Mode Synchronous 8-bit serial 3-wire configuration, tCYC transfer clocks) Mode Asynchronous serial (half-duplex, data bits, stop bit, 2048 tCYC baudrates) Mode mode (start bit, data bits, tCYC transfer clocks) Mode mode (start detect, data bits, stop detect) SIO2: synchronous serial interface first mode Built-in 8-bit baudrate generator (maximum transfer clock cycle tCYC) Automatic continuous data transmission bytes)
No.A1380-2/25
LC87F5ND0C
UART: channels Full duplex 7/8/9 data bits selectable stop bits continuous transmission mode) Built-in baudrate generator (with baudrates 16/3 8192/3 tCYC) Converter: bits channels PWM: Multifrequency 12-bit channels Remote Control Receiver Circuit (sharing pins with P73, INT3, T0IN) Noise filtering function (noise filter time constant selectable from tCYC, tCYC, tCYC) noise filtering function available INT3, T0IN, T0HCP signal P73. When read with instruction, signal level that read regardless availability noise filtering function. Watchdog Timer External watchdog timer Interrupt reset signals selectable Clock Output Function Able output selected oscillation clock 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 system clock. Able output oscillation clock clock. Interrupts sources, vector addresses Provides three levels (low (L), high (H), highest (X)) multiplex interrupt control. interrupt requests level equal lower than current interrupt accepted. When interrupt requests more vector addresses occur same time, interrupt highest level takes precedence over other interrupts. interrupts same level, interrupt into smallest vector address takes precedence.
Vector Address 00003H 0000BH 00013H 0001BH 00023H 0002BH 00033H 0003BH 00043H 0004BH Level INT0 INT1 INT2/T0L/INT4 INT3/INT5/base timer0/base timer1 T0H/INT6 T1L/T1H/INT7 SIO0/UART1 receive/UART2 receive SIO/UART1 transmit/UART2 transmit ADC/T6/T7/PWM4, PWM5 Port 0/T4/T5/PWM0, PWM1 Interrupt Source
Priority levels interrupts same level, with smallest vector address takes precedence. Subroutine Stack Levels: 3072 levels maximum (the stack allocated RAM) High-speed Multiplication/Division Instructions 16-bits 8-bits tCYC execution time) 24-bits 16-bits tCYC execution time) 16-bits 8-bits tCYC execution time) 24-bits 16-bits tCYC execution time) Oscillation Circuits oscillation circuit (internal) oscillation circuit Crystal oscillation circuit Multifrequency oscillation circuit (internal)
system clock system clock, with internal low-speed system clock system clock
No.A1380-3/25
LC87F5ND0C
System Clock Divider Function current. minimum instruction cycle selectable from 250ns, 500ns, 1.0s, 2.0s, 4.0s, 8.0s, 16.0s, 32.0s, 64.0s main clock rate 12MHz). Standby Function HALT mode: Halts instruction execution while allowing peripheral circuits continue operation. Oscillation halted automatically. Canceled system reset occurrence interrupt. HOLD mode: Suspends instruction execution operation peripheral circuits. crystal oscillators automatically stop operation. There three ways resetting HOLD mode. Setting reset level. Setting least INT0, INT1, INT2, INT4, INT5 pins specified level Having interrupt source established port X'tal HOLD mode: Suspends instruction execution operation peripheral circuits except base timer. oscillators automatically stop operation. state crystal oscillation established when HOLD mode entered retained. There four ways resetting X'tal HOLD mode. Setting reset level Setting least INT0, INT1, INT2, INT4, INT5 pins specified level Having interrupt source established port Having interrupt source established base timer circuit On-chip Debugger Function Permits software debugging with test device installed target board. Package Form QIP100E "Lead-free type" Development Tools Evaluation (EVA) chip Emulator On-chip-debugger Programming Boards
Package QIP100E Programming boards W87F52256Q
LC87EV690 EVA62S ECB876600D SUB875C00 POD100QFP ICE-B877300 SUB875C00 POD100QFP TCB87-TypeB LC87F5ND0C
Flash Programmer
Maker Flash Support Group, Inc. (Single) Flash Support Group, Inc. (Gang) Model AF9708/09/09B (including product Ando Electric Co.,Ltd) AF9723(Main body) (including product Ando Electric Co.,Ltd) AF9833(Unit) (including product Ando Electric Co.,Ltd) SKK/SKK Type-B/SKK Type-B (SANYO FWS) Support version(Note) Revision After Rev.02.82 Revision After Rev.02.29 LC87F5NC8A Revision After Rev.01.88 Application Version: SANYO After 1.04 Chip Data Version: After2.10 LC87F5NC8A Device LC87F5NC8A
No.A1380-4/25
LC87F5ND0C
Package Dimensions
unit (typ) 3151A
23.2
14.0
20.0
0.65 (0.58)
(2.7)
0.15
3.0max
SANYO QIP100E(14X20)
17.2
No.A1380-5/25
Assignment
VSS3 VDD3 PC7/DBGP2 PC6/DBGP1 PC5/DBGP0
LC87F5ND0C
LC87F5ND0C
PA3/AN12 PA4/AN13 PA5/AN14 P70/INT0/T0LCP/AN8 P71/INT1/T0HCP/AN9 P72/INT2/T0IN/T0LCP P73/INT3/T0IN/T0HCP XT1/AN10 XT2/AN11 VSS1 VDD1 P80/AN0 P81/AN1 P82/AN2 P83/AN3 P84/AN4 P85/AN5 P86/AN6 P87/AN7 P10/SO0 P11/SI0/SB0 P12/SCK0 P13/SO1 P14/SI1/SB1 P15/SCK1 P16/T1PWML P17/T1PWMH/BUZ
P35/URX2 P34/UTX2 P33/URX1 P32/UTX1 P31/PWM5 P30/PWM4 P27/INT5/T1IN/T0LCP/T0HCP P26/INT5/T1IN/T0LCP/T0HCP P25/INT5/T1IN/T0LCP/T0HCP P23/INT4/T1IN/T0LCP/T0HCP P22/INT4/T1IN/T0LCP/T0HCP P21/INT4/T1IN/T0LCP/T0HCP P07/T7O P06/T6O P05/CKO VSS2 VDD2 PWM0 PWM1 SI2P3/SCK20 SI2P2/SCK2
view
SANYO: "Lead-free Type"
No.A1380-6/25
SI2P1/SI2/SB2 SI2P0/SO2 VDD4 VSS4
LC87F5ND0C
System Block Diagram
Interrupt control
Flash Standby control X'tal SIO0 Interface register Clock generator
SIO1 SIO2
Port
Port
register
Timer
Port
Timer
Port
Timer
Port
Timer
INT0 Noise rejection filter Port
PWM0/1
PWM4/5
Stack Pointer Base timer Port Watchdog Timer Timer Port On-chip debugger Timer Port
UART1
Port
UART2
Port
No.A1380-7/25
LC87F5ND0C
Description
Name VSS1, VSS2 VSS3, VSS4 VDD1, VDD2 VDD3, VDD4 Port Power supply Power supply 8-bit port specifiable 4-bit units Pull-up resistor turned 4-bit units HOLD release input Port interrupt input functions P05: System clock output (system clock/subclock selectable) P06: Timer toggle output P07: Timer toggle output Port 8-bit port specifiable 1-bit units Pull-up resistor turned 1-bit units functions P10: SIO0 data output P11: SIO0 data input, P12: SIO0 clock P13: SIO1 data output P14: SIO1 data input, P15: SIO1 clock P16: Timer PWML output P17: Timer PWMH output, Beeper output Port 8-bit port specifiable 1-bit units Pull-up resistor turned 1-bit units Other functions P20: INT4 input/HOLD reset input/timer event input/timer capture input/ timer capture input/INT6 input/timer capture input P23: INT4 input/HOLD reset input/timer event input/timer capture input/ timer capture input P24: INT5 input/HOLD reset input/timer event input/timer capture input/ timer capture input/INT7 input/timer capture input P27: INT5 input/HOLD reset input/timer event input/timer capture input/ timer capture input Interrupt acknowledge type Rising INT4 INT5 INT6 INT7 enable enable enable enable Falling enable enable enable enable Rising/ Falling enable enable enable enable level disable disable disable disable level disable disable disable disable Description Option
Port
7-bit port specifiable 1-bit units Pull-up resistor turned 1-bit units functions P30: PWM4 output P31: PWM5 output P32: UART1 transmit P33: UART1 receive P34: UART2 transmit P35: UART2 receive
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No.A1380-8/25
LC87F5ND0C
Continued from preceding page.
Name Port 4-bit port specifiable 1-bit units Pull-up resistor turned 1-bit units Other functions P70: INT0 input/HOLD release input/Timer capture input/Output watchdog timer P71: INT1 input/HOLD release input/Timer capture input P72: INT2 input/HOLD release input/Timer event input/Timer capture input P73: INT3 input with noise filter/Timer event input/Timer capture input Interrupt acknowledge type Rising INT0 INT1 INT2 INT3 enable enable enable enable Falling enable enable enable enable Rising/ Falling disable disable enable enable level enable enable disable disable level enable enable disable disable Description Option
converter input port: (P70), (P71) Port 8-bit port specifiable 1-bit units Other functions P87: converter input port Port 6-bit port specifiable 1-bit units Pull-up resistor turned 1-bit units Shared pins converter input ports: PA3(AN12) PA5(AN15) Port Port 8-bit port specifiable 1-bit units Pull-up resistor turned 1-bit units 8-bit port specifiable 1-bit units Pull-up resistor turned 1-bit units functions DBGP0 DBGP2 (PC5 PC7): On-chip Debugger Port Port SIO2 Port SI2P0 SI2P3 8-bit port specifiable 2-bit units Pull-up resistor turned 1-bit units 8-bit port specifiable 2-bit units Pull-up resistor turned 1-bit units 4-bit port specifiable 1-bit units Shared functions: SI2P0: SIO2 data output SI2P1: SIO2 data input, input/output SI2P2: SIO2 clock input/output SI2P3: SIO2 clock output PWM0, PWM1 PWM0, PWM1 output port General-purpose available Reset Input terminal 32.768kHz X'tal oscillation Shared functions: AN10: converter input port General-purpose input port Must connected VDD1 used. Output terminal 32.768kHz X'tal oscillation Shared functions: AN11: converter input port General-purpose port Must oscillation kept open used. Ceramic resonator input Ceramic resonator output
No.A1380-9/25
LC87F5ND0C
Port Output Types
table below lists types port outputs presence/absence pull-up resistor. Data read into input port even output mode.
Port Options Selected Units Option Type SI2P0, SI2P2 SI2P3 SI2P1 PWM0, PWM1 CMOS (when selected ordinary port) N-channel open drain (When SIO2 data selected) CMOS Input only Output 32.768kHz quartz oscillator N-channel open drain (when general-purpose output mode) CMOS N-channel open drain CMOS N-channel open drain CMOS N-channel open drain CMOS N-channel open drain N-channel open drain CMOS N-channel open drain CMOS N-channel open drain CMOS N-channel open drain CMOS N-channel open drain CMOS CMOS CMOS Output Type Pull-up Resistor Programmable (Note Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable
Note Programmable pull-up resistors port controlled 4-bit units (P00 07). Make following connection minimize noise input VDD1 prolong backup time. sure electrically short VSS1, VSS2, VSS3 VSS4 pins. (Example When backup active HOLD mode, high level port outputs supplied backup capacitors.
Back-up capacitor Power Supply VDD1
VDD2
VDD3
VDD4 VSS1 VSS2 VSS3 VSS4
No.A1380-10/25
LC87F5ND0C
(Example high-level output ports unstable when HOLD mode backup effect.
Back-up capacitor Power Supply VDD1
VDD2
VDD3
VDD4 VSS1 VSS2 VSS3 VSS4
Absolute Maximum Ratings 25°C, VSS1 VSS2 VSS3 VSS4
Parameter Maximum Supply voltage Input voltage Input/Output Voltage VI(1) VIO(1) Symbol Pins/Remarks VDD1, VDD2, VDD3, VDD4 XT1, Ports Ports Ports SI2P0 SI2P3 PWM0, PWM1,XT2 Peak output current IOPH(2) IOPH(3) Average output current (Note1-1) High level output current IOM(2) IOM(3) Total output current IOAH(1) IOAH(2) IOAH(3) IOAH(4) IOM(1) IOPH(1) Ports Ports SI2P0 SI2P3 PWM0, PWM1 Ports Ports SI2P0 SI2P3 PWM0, PWM1 PWM0, PWM1 SI2P0 SI2P3 Port Port PWM0, PWM1 SI2P0 SI2P3 IOAH(5) IOAH(6) IOAH(7) IOAH(8) IOAH(9) IOAH(10) Ports Ports Ports Port Ports Ports Total applicable pins Total applicable pins Total applicable pins Total applicable pins Total applicable pins Total applicable pins Total applicable pins Total applicable pins application pin. application pin. Total applicable pins Total applicable pins application pin. application pin. CMOS output select application -7.5 CMOS output select application -0.3 VDD+0.3 Conditions VDD[V] VDD1=VDD2=VDD3=VDD4 -0.3 -0.3 Specification +6.5 VDD+0.3 unit
Note 1-1: Average output current average current 100ms interval.
Continued next page.
No.A1380-11/25
LC87F5ND0C
Continued from preceding page.
Parameter Peak output current Symbol IOPL(1) Pins/Remarks Ports Ports SI2P0 SI2P3 PWM0, PWM1 IOPL(2) IOPL(3) Average output current (Note1-1) IOML(1) P00, Ports Ports Ports SI2P0 SI2P3 PWM0, PWM1 level output current IOML(2) IOML(3) Total output current IOAL(1) IOAL(2) IOAL(3) IOAL(4) IOAL(5) IOAL(6) P00, Ports Port Port Ports PWM0, PWM1 SI2P0 SI2P3 Port Port PWM0, PWM1 SI2P0 SI2P3 IOAL(7) IOAL(8) IOAL(9) IOAL(10) IOAL(11) IOAL(12) Maximum power dissipation Operating ambient temperature Storage ambient temperature Tstg Topr Ports Ports Ports Port Ports Ports Total applicable pins Total applicable pins Total applicable pins Total applicable pins Total applicable pins Total applicable pins Ta=-40 +85°C +125 Total applicable pins Total applicable pins application pin. application pin. Total applicable pins Total applicable pins Total applicable pins Total applicable pins application pin. application pin. application pin. Conditions VDD[V] application pin. Specification unit
Note 1-1: Average output current average current 100ms interval.
No.A1380-12/25
LC87F5ND0C
Recommended Operating Conditions -40°C +85°C, VSS1 VSS2 VSS3 VSS4
Parameter Operating supply voltage (Note2-1) Memory sustaining supply voltage High level input voltage VIH(1) Ports SI2P0 SI2P3 port input/ interrupt side VIH(2) Ports Ports PWM0, PWM1 VIH(3) VIH(4) level input voltage VIL(1) Watchdog timer side XT1, XT2, CF1, Ports SI2P0 SI2P3 port input/ interrupt VIL(2) Ports Ports PWM0, PWM1 VIL(5) VIL(6) Instruction cycle time (Note2-2) External system clock frequency FEXCF(1) open System clock frequency division rate=1/1 External system clock duty=50±5% open System clock frequency division rate=1/2 Oscillation frequency Range (Note2-3) FmCF(3) CF1, FmCF(2) CF1, FmCF(1) CF1, 12MHz ceramic oscillation Fig. 8MHz ceramic oscillation Fig. 4MHz ceramic oscillation Fig. FmRC FmMRC FsX'tal XT1, Internal oscillation Frequency variable oscillation source oscillation 32.768kHz crystal oscillation. Fig. 32.768 24.4 tCYC Port Watchdog Timer XT1, XT2, CF1, 0.245 0.367 1.470 0.2VDD 0.15VDD +0.4 0.2VDD 0.8VDD -1.0 0.25VDD 0.3VDD +0.7 0.9VDD 0.75VDD 0.1VDD +0.4 0.3VDD +0.7 VDD1=VDD2 =VDD3=VDD4 Symbol VDD(1) Pins/Remarks VDD1=VDD2 =VDD3=VDD4 Conditions VDD[V] 0.245s tCYC200s 0.367s tCYC200s 1.470s tCYC200s register contents HOLD mode. Specification unit
Note 2-1: must held greater than equal 2.7V flash onboard programming mode. Note 2-2: Relationship between tCYC oscillation frequency 3/FmCF division ratio 6/FmCF division ratio 1/2. Note 2-3: Tables oscillation constants.
No.A1380-13/25
LC87F5ND0C
Electrical Characteristics -40°C +85°C, VSS1 VSS2 VSS3 VSS4
Parameter High level input current Symbol IIH(1) Pins/Remarks Ports Ports Ports SI2P0 SI2P3 PWM0, PWM1 IIH(2) IIH(3) level input current IIL(1) XT1, Using input port VIN=VDD Ports Ports Ports SI2P0 SI2P3 PWM0, PWM1 IIL(2) IIL(3) High level output voltage VOH(1) VOH(2) VOH(3) VOH(4) VOH(5) VOH(6) VOH(7) VOH(8) level output voltage VOL(1) VOL(2) VOL(3) VOL(4) VOL(5) VOL(6) VOL(7) VOL(8) Pull-up resistation Rpu(1) Rpu(2) Hysteresis voltage VHYS Ports Port Ports Ports SI2P0 SI2P3 capacitance pins pins other than that under test: VIN=VSS f=1MHz Ta=25°C 2.2to 0.1VDD Ports Ports Ports SI2P0 SI2P3 PWM0, PWM1, P00, PWM0, PWM1 P30, P31(PWM4, output mode) IOH=-1.6mA IOH=-1.0mA IOL=10mA IOL=1.6mA IOL=1.0mA IOL=30mA IOL=5.0mA IOL=2.5mA IOL=1.6mA IOL=1.0mA VOH=0.9VDD Ports XT1, Using input port VIN=VSS Ports Ports SI2P0 SI2P IOH=-0.2mA IOH=-0.4mA IOH=-0.2mA IOH=-10mA VIN=VSS IOH=-1.0mA IOH=-0.4mA VDD-1 -0.4 -0.4 -0.4 -0.4 -1.5 -0.4 -0.4 VIN=VDD Output disable Pull-up resistor VIN=VSS (including off-leak current output Tr.) Conditions VDD[V] Output disable Pull-up resistor VIN=VDD (including off-leak current output Tr.) Specification unit
No.A1380-14/25
LC87F5ND0C
Serial Characteristics -40°C +85°C, VSS1 VSS2 VSS3 VSS4
SIO0 Serial Characteristics (Note 4-1-1)
Parameter Frequency level pulse width High level pulse width Input clock tSCKHA(1a) Continuous data transmission/reception mode SIO2 simultaneous. Fig. (Note 4-1-2) tSCKHA(1b) Continuous data transmission/reception mode SIO2 simultaneous. Serial clock Fig. (Note 4-1-2) Frequency level pulse width High level pulse width Output clock tSCKHA(2a) Continuous data transmission/reception mode SIO2 simultaneous. CMOS output selected. Fig. tSCKHA(2b) Continuous data transmission/reception mode SIO2 simultaneous. CMOS output selected. Fig. Data setup time Serial input tsDI(1) SI0(P11), SB0(P11) Data hold time thDI(1) Must specified with respect rising edge SIOCLK fig. 0.03 Output Input clock delay time tdD0(2) tdD0(1) SO0(P10), SB0(P11), Continuous data transmission/reception mode (Note 4-1-3) Synchronous 8-bit mode. (Note 4-1-3) tdD0(3) Output clock (Note 4-1-3) 0.03 tSCKH(2) +2tCYC tSCKH(2) +(16/3) tCYC tSCKH(2) +2tCYC tSCKH(2) +(10/3) tCYC tCYC tSCKH(2) tSCK(2) tSCKL(2) SCK0(P12) CMOS output selected. Fig. tSCK tSCKH(1) Symbol tSCK(1) tSCKL(1) Pins /Remarks SCK0(P12) Fig. Conditions VDD[V] Specification unit
tCYC
(1/3)tCYC +0.05 1tCYC +0.05
Serial output
(1/3)tCYC +0.05
Note 4-1-1: These specifications theoretical values. margin depending use. Note 4-1-2: serial-clock-input continuous trans/rec mode, time from SI0RUN being when serial clock first negative edge serial clock must longer than tSCKHA. Note 4-1-3: Must specified with respect falling edge SIOCLK. Must specified time beginning output state change open drain output mode. Fig.
No.A1380-15/25
LC87F5ND0C
SIO1 Serial Characteristics (Note 4-2-1)
Parameter Frequency Input clock level pulse width High level pulse width Frequency Output clock level pulse width High level pulse width Data setup time Serial input tsDI(2) SI1(P14), SB1(P14) Data hold time thDI(2) Must specified with respect rising edge SIOCLK fig. 0.03 Output delay Serial output time tdD0(4) SO1(P13), SB1(P14) Must specified with respect falling edge SIOCLK Must specified time beginning output state change open drain output mode. Fig. (1/3)tCYC +0.05 0.03 tSCKH(4) tSCK(4) tSCKL(4) SCK1(P15) CMOS output selected. Fig. tSCKH(3) Symbol Tsck(3) tSCKL(3) Pins/ Remarks SCK1(P15) Fig. Conditions VDD[V] tCYC tSCK Specification unit
Note 4-2-1: These specifications theoretical values. margin depending use.
Serial clock
No.A1380-16/25
LC87F5ND0C
SIO2 Serial Characteristics (Note 4-3-1)
Parameter Frequency level pulse width High level pulse width Input clock tSCKHA(5a) Continuous data transmission/ reception mode SIO0 simultaneous. Fig. (Note 4-3-2) tSCKHA(5b) Continuous data transmission/ reception mode SIO0 simultaneous. Serial clock Fig. (Note 4-3-2) Frequency level pulse width High level pulse width Output clock tSCKHA(6a) Continuous data transmission/ reception mode SIO0 simultaneous. CMOS output selected. Fig. tSCKHA(6b) Continuous data transmission/ reception mode SIO0 simultaneous. CMOS output selected. Fig. Data setup time Serial input tsDI(3) SI2(SI2P1), SB2(SI2P1) Data hold Time thDI(3) Must specified with respect rising edge SIOCLK fig. 0.03 Output delay Serial output time tdD0(5) (SI2P0), SB2(SI2P1) Must specified with respect falling edge SIOCLK Must specified time beginning output state change open drain output mode. Fig. (1/3)tCYC +0.05 0.03 tSCKH(6) +(5/3)tCYC tSCKH(6) +(19/3)tCYC tSCKH(6) +(5/3)tCYC tSCKH(6) +(10/3)tCYC tCYC tSCKH(6) tSCK(6) tSCKL(6) SCK2 (SI2P2), SCK2O (SI2P3) CMOS output selected. Fig. tSCK tSCKH(5) Symbol tSCK(5) tSCKL(5) Pins/ Remarks SCK2 (SI2P2) Fig. Conditions VDD[V] min. Specification max. unit
tCYC
Note 4-3-1: These specifications theoretical values. margin depending use. Note 4-3-2: serial-clock-input time from SI2RUN being when serial clock first negative edge serial clock must longer than tSCKHA.
No.A1380-17/25
LC87F5ND0C
Pulse Input Conditions -40°C +85°C, VSS1 VSS2 VSS3 VSS4
Parameter High/low level pulse width Symbol tPIH(1) tPIL(1) Pins/Remarks INT0(P70), INT1(P71), INT2(P72) INT4(P20 P23), INT5(P24 P27), INT6(P20) INT7(P24) tPIH(2) tPIL(2) tPIH(3) tPIL(3) tPIH(4) tPIL(4) tPIL(5) INT3(P73) when noise filter time constant 1/1. INT3(P73)(The noise rejection clock selected 1/32.) INT3(P73)(The noise rejection clock selected 1/128.) Interrupt source flag set. Event inputs timer enabled. Interrupt source flag set. Event inputs timer enabled. Interrupt source flag set. Event inputs timer enabled. Reset acceptable. tCYC Conditions VDD[V] Interrupt source flag set. Event inputs timer enabled. Specification unit
Converter Characteristics -40°C +85°C, VSS1 VSS2 VSS3 VSS4
Parameter Resolution Absolute accuracy Conversion time TCAD Symbol Pins/Remarks AN0(P80) AN7(P87), AN8(P70), AN9(P71), AN10(XT1), AN11(XT2), AN12(PA3), AN13(PA4), AN14(PA5) conversion (when ADCR2=1) (Note 6-2) conversion (when ADCR2=0) (Note 6-2) (Note 6-1) Conditions VDD[V] 11.74 (tCYC= 0.367s) 23.53 (tCYC= 0.735s) 15.68 (tCYC= 0.245s) 23.49 Analog input voltage range Analog port input current IAINH IAINL VAIN=VDD VAIN=VSS VAIN (tCYC= 0.367s) Specification ±1.5 97.92 (tCYC= 3.06s) 97.92 (tCYC= 3.06s) 97.92 (tCYC= 1.53s) 97.92 (tCYC= 1.53s) unit
Note 6-1: quantization error (±1/2 LSB) excluded from absolute accuracy value. Note 6-2: conversion time refers interval from time instruction starting converter issued till complete digital value corresponding analog input value loaded required register.
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Consumption Current Characteristics -40°C +85°C, VSS1 VSS2 VSS3 VSS4
Parameter Normal mode consumption current (Note 7-1) Symbol IDDOP(1) Pins/Remarks VDD1 =VDD2 =VDD3 =VDD4 Conditions VDD[V] FmCF=12MHz ceramic oscillation mode FmX'tal=32.768kHz crystal oscillation mode System clock 12MHz side Internal oscillation stopped frequency variable oscillation stopped frequency division ratio. IDDOP(2) FmCF=8MHz ceramic oscillation mode FmX'tal=32.768kHz crystal oscillation mode System clock 8MHz side IDDOP(3) Internal oscillation stopped frequency variable oscillation stopped frequency division ratio. IDDOP(4) FmCF=4MHz ceramic oscillation mode FmX'tal=32.768kHz crystal oscillation mode IDDOP(5) System clock 4MHz side Internal oscillation stopped frequency variable oscillation stopped frequency division ratio. IDDOP(6) FmCF=0Hz (oscillation stopped) FmX'tal=32.768kHz crystal oscillation mode IDDOP(7) System clock internal oscillation frequency variable oscillation stopped frequency division ratio. IDDOP(8) FmCF=0Hz (oscillation stopped) FmX'tal=32.768kHz crystal oscillation mode. System clock 1MHz with frequency IDDOP(9) variable oscillation Internal oscillation stopped frequency division ratio. IDDOP(10) FmCF=0Hz (oscillation stopped) FmX'tal=32.768kHz crystal oscillation mode. IDDOP(11) System clock 32.768kHz side. Internal oscillation stopped frequency variable oscillation stopped frequency division ratio. HALT mode consumption current (Note 7-1) IDDHALT(1) VDD1 =VDD2 =VDD3 =VDD4 HALT mode FmCF=12MHz ceramic oscillation mode FmX'tal=32.768kHz crystal oscillation mode System clock 12MHz side Internal oscillation stopped frequency variable oscillation stopped frequency division ratio. IDDHALT(2) HALT mode FmCF=8MHz ceramic oscillation mode FmX'tal=32.768kHz crystal oscillation mode IDDHALT(3) System clock 8MHz side Internal oscillation stopped frequency variable oscillation stopped frequency division ratio. 0.78 1.45 0.65 11.5 16.5 15.8 10.9 21.5 Specification unit
Note 7-1: consumption current value includes none currents that flow into output internal pull-up resistors
Continued next page.
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Continued from preceding page.
Parameter HALT mode consumption current (Note 7-1) IDDHALT(5) Symbol IDDHALT(4) Pins/Remarks VDD1 =VDD2 =VDD3 =VDD4 HALT mode FmCF=4MHz ceramic oscillation mode FmX'tal=32.768kHz crystal oscillation mode System clock 4MHz side Internal oscillation stopped frequency variable oscillation stopped frequency division ratio. IDDHALT(6) HALT mode FmCF=0Hz (oscillation stopped) FmX'tal=32.768kHz crystal oscillation mode IDDHALT(7) System clock internal oscillation frequency variable oscillation stopped frequency division ratio. IDDHALT(8) HALT mode FmCF=0Hz (oscillation stopped) FmX'tal=32.768kHz crystal oscillation mode. IDDHALT(9) System clock 1MHz with frequency variable oscillation Internal oscillation stopped frequency division ratio. IDDHALT(10) HALT mode FmCF=0Hz (oscillation stopped) FmX'tal=32.768kHz crystal oscillation mode. IDDHALT(11) System clock 32.768kHz side. Internal oscillation stopped frequency variable oscillation stopped frequency division ratio. HOLD mode consumption current Timer HOLD mode consumption current IDDHOLD(4) IDDHOLD(1) IDDHOLD(2) IDDHOLD(3) VDD1 HOLD mode CF1=VDD open (External clock mode) Timer HOLD mode CF1=VDD open (External clock mode) FmX'tal=32.768kHz crystal oscillation mode 0.02 0.05 0.57 1.15 0.19 0.38 0.57 Conditions VDD[V] Specification unit
Note 7-1: consumption current value includes none currents that flow into output internal pull-up resistors
F-ROM Programming Characteristics +10°C +55°C, VSS1 VSS2 VSS3 VSS4
Parameter Onboard programming current Programming time tFW(1) tFW(2) Erasing programming Symbol IDDFW(1) Pins/Remarks VDD1 Conditions VDD[V] Without current Specification unit
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LC87F5ND0C
UART (Full Duplex) Operating Conditions -40°C +85°C, VSS1 VSS2 VSS3 VSS4
Parameter Transfer rate Symbol UBR, UBR2 Pins/Remarks UTX1(P32), RTX1(P33), UTX2(P33), RTX2(P34) 16/3 8192/3 tCYC Conditions VDD[V] Specification unit
Data length 7/8/9 bits (LSB first) Stop bits 1-bit (2-bit continuous data transmission) Parity bits None Example Continuous 8-bit Data Transmission Mode Processing (First Transmit Data 55H)
Start Start transmission Transmit data (LSB first) Stop transmission
UBR2
Example Continuous 8-bit Data Reception Mode Processing (First Receive Data 55H)
Start Start reception Receive data (LSB first) Stop reception
UBR2
VDD1, VSS1 Terminal Condition
necessary place capacitors between VDD1 VSS1 describe below. Place capacitors close VDD1 VSS1 possible. Place capacitors that length each terminal each capacitor equal L1', L2'). Place high capacitance capacitor capacitance capacitor parallel. Capacitance must more than 0.1F. thicker pattern VDD1 VSS1.
VSS1
VDD1
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Characteristics Sample Main System Clock Oscillation Circuit
Given below characteristics sample main system clock oscillation circuit that measured using SANYO-designated oscillation characteristics evaluation board external components with circuit constant values with which oscillator vendor confirmed normal stable oscillation. Table Characteristics Sample Main System Clock Oscillator Circuit with Ceramic Oscillator
Nominal Frequency 12MHz 10MHz MURATA 8MHz Vendor Name Circuit Constant Oscillator Name [pF] CSTCE12M0G52-R0 CSTCE10M0G52-R0 CSTLS10M0G53-B0 CSTCE8M00G52-R0 CSTLS8M00G53-B0 4MHz CSTCR4M00G53-R0 CSTLS4M00G53-B0 (10) (10) (15) (10) (15) (15) (15) [pF] (10) (10) (15) (10) (15) (15) (15) Open Open Open Open Open Open Open 1.5k 1.5k Operating Voltage Range Oscillation Stabilization Time [ms] 0.03 0.03 0.03 0.03 0.03 0.03 0.03 [ms] Internal C1,C2 Internal C1,C2 Internal C1,C2 Internal C1,C2 Internal C1,C2 Internal C1,C2 Internal C1,C2 Remarks
oscillation stabilization time refers time interval that required oscillation stabilized after goes above operating voltage lower limit (see Fig.
Characteristics Sample Subsystem Clock Oscillator Circuit
Given below characteristics sample subsystem clock oscillation circuit that measured using SANYOdesignated oscillation characteristics evaluation board external components with circuit constant values with which oscillator vendor confirmed normal stable oscillation. Table Characteristics Sample Subsystem Clock Oscillator Circuit with Crystal Oscillator
Nominal Frequency Vendor Name EPSON TOYOCOM Circuit Constant Oscillator Name [pF] 32.768kHz MC-306 [pF] Open 560k Operating Voltage Range Oscillation Stabilization Time Applicable value=12.5pF Remarks
oscillation stabilization time refers time interval that required oscillation stabilized after instruction starting subclock oscillation circuit executed time interval that required oscillation stabilized after HOLD mode reset (see Figure. Note: components that involved oscillation should placed close another possible because they vulnerable influences circuit pattern.
X'tal
Figure Ceramic Oscillator Circuit
Figure Crystal Oscillator Circuit
0.5VDD
Figure Timing Measurement Point
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Power supply limit Reset time
Internal oscillation tmsCF CF1,
tmsX'tal XT1,
Operating mode
Unfixed
Reset
Instruction execution
Reset Time Oscillation Stabilization Time
HOLD reset signal
HOLD reset Signal absent
HOLD reset signal VALID
Internal oscillation tmsCF CF1,
tmsX'tal XT1,
State
HOLD
HALT
HOLD Release Signal Oscillation Stabilization Time Figure Oscillation Stabilization Times
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RRES
CRES
Note: Select CRES RRES value assure that least 200s reset time generated after becomes higher than minimum operating voltage.
Figure Reset Circuit
SIOCLK:
DATAIN:
DATAOUT:
Data transfer period (SIO0,2 only)
tSCK tSCKL SIOCLK: tsDI DATAIN: tdDO DATAOUT: Data transfer period (SIO0,2 only) tSCKLA SIOCLK: tsDI DATAIN: tdDO DATAOUT: thDI tSCKHA thDI tSCKH
Figure Serial Waveforms
tPIL
tPIH
Figure Pulse Input Timing Signal Waveform
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SANYO Semiconductor Co.,Ltd. assumes responsibility equipment failures that result from using products values that exceed, even momentarily, rated values (such maximum ratings, operating condition ranges, other parameters) listed products specifications SANYO Semiconductor Co.,Ltd. products described contained herein. SANYO Semiconductor Co.,Ltd. strives supply high-quality high-reliability products, however, semiconductor products fail malfunction with some probability. possible that these probabilistic failures malfunction could give rise accidents events that could endanger human lives, trouble that could give rise smoke fire, accidents that could cause damage other property. When designing equipment, adopt safety measures that these kinds accidents events cannot occur. Such measures include limited protective circuits error prevention circuits safe design, redundant design, structural design. event that SANYO Semiconductor Co.,Ltd. products described contained herein controlled under applicable local export control laws regulations, such products require export license from authorities concerned accordance with above law. part this publication reproduced transmitted form means, electronic mechanical, including photocopying recording, information storage retrieval system, otherwise, without prior written consent SANYO Semiconductor Co.,Ltd. information described contained herein subject change without notice product/technology improvement, etc. When designing equipment, refer "Delivery Specification" SANYO Semiconductor Co.,Ltd. product that intend use. Information (including circuit diagrams circuit parameters) herein example only; guaranteed volume production. Upon using technical information products described herein, neither warranty license shall granted with regard intellectual property rights other rights SANYO Semiconductor Co.,Ltd. third party. SANYO Semiconductor Co.,Ltd. shall liable claim suits with regard third party's intellectual property rights which resulted from technical information products mentioned above.
This catalog provides information November, 2008. Specifications information herein subject change without notice.
No.A1380-25/25

LC87F5ND0C CMOS FROM 128K byte, 6144 byte on-chip 8-bit 1-ch

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