LC89058W-E Overview Digital Audio Interface Receiver LC

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LC89058W-E Overview Digital Audio Interface Receiver LC

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Ordering number ENA1056A
LC89058W-E
Overview
Digital Audio Interface Receiver
LC89058W-E digital audio interface receiver that demodulates signals according data transfer format between digital audio devices IEC60958/61937 JEITA CPR-1205. supports demodulation sampling frequencies 192kHz. LC89058W-E easily replace existing LC89057W-VF4A-E. LC89058W-E incorporates number features cost optimal receiving digital data amplifiers receivers.
Features
Clock Built-in false lock prevention circuit provide accurate lock. Includes built-in oscillation amplifier frequency divider quartz resonator. Output clock: 512fs, 256fs, 128fs, 64fs, 32fs, 16fs, 2fs, 1/2fs, 1/4fs. Possible oscillation amplifier (external input) clock output regardless status. Generates transition period signal switching between clock oscillation amplifier (external input) clock. Allows user clock output frequency each sampling frequency band input data. Data receive S/PDIF serial data sampling frequencies 32kHz 192kHz. Equipped with total digital data input pins: input with amplifier input pins with tolerable level signal. generate data demodulated through output data separately from maximum kinds S/PDIFs. Equipped S/PDIF input data detection function. Possible monitor data input status 32kHz 192kHz with microcontroller.
Continued next page.
SANYO Semiconductor Co.,Ltd. products described contained herein are, with regard "standard application", intended general electronics equipment (home appliances, equipment, communication device, office equipment, industrial equipment etc.). products mentioned herein shall intended "special application" (medical equipment whose purpose sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level reliability directly threaten human lives case failure malfunction product cause harm human bodies, shall they grant guarantee thereof. should intend products applications outside standard applications customer considering such and/or outside scope intended standard applications, please consult with prior intended use. there consultation inquiry before intended use, customer shall solely responsible use. Specifications SANYO Semiconductor Co.,Ltd. products described contained herein stipulate performance, characteristics, functions described products independent state, guarantees performance, characteristics, functions described products mounted customer' products equipment. verify symptoms states that cannot evaluated independent device, customer should always evaluate test devices mounted customer' products equipment.
41509HKIM VL-2643/N0508HKIM VL-2625 No.A1056-1/64
LC89058W-E
Continued from preceding page.
Equipped with serial data input pin. Possible switch with demodulation output automatically according state circuit. reception range S/PDIF interface limited. LC89058W-E no-signal input state reception range exceeded. Supports data output that facilitates interfacing with DSP. Other Supports Multi-channel transfer reception, using master/slave function. Equipped with 4bits general-purpose pins. They used interface with peripheral ICs. general-purpose pins also serve selector inputs. Possible switch with HDMI XM-radio signals. Generates DTS-CD/LD detection flag detection synchronization signal. Outputs interrupt signal microcontroller (interrupt source selected). Calculates sampling frequency input signal outputs from terminal microcontroller interface. Outputs IEC61937 burst preamble from microcontroller interface. Outputs IEC60958 channel status (non-PCM data delimiter bit). Outputs emphasis information channel status. four LC89058W-Es same time setting 2-bit chip address. Runs single 3.3V power supply (S/PDIF input microcontroller interface support interface.) SQFP48 package
Package Dimensions
unit (typ) 3163B
(0.75) 0.18
0.15
1.7max
(1.5)
SANYO SQFP48(7X7)
No.A1056-2/64
LC89058W-E
Assignment
AUDIO
MOUT
DGND
DVDD
DVDD DVDD
RERR
CKST
DGND
SDIN SLRCK SBCK RDATA RLRCK DVDD DGND RBCK RMCK AGND AVDD
XMODE DGND DVDD
LC89058W-E
GPIO0 GPIO1 GPIO2 GPIO3 RXOUT2
XOUT
RXOUT1
DGND
DVDD
XMCK
DGND Pull-down resistor internal selection
Function
view
Functions
Table Functions
Name RXOUT1 DGND DVDD DVDD DGND AVDD AGND RMCK RBCK DGND DVDD RLRCK RDATA SBCK SLRCK SDIN I5(pd) I5(pd) I5(pd) I5(pd) I(pd) I5(pd) I5(pd) RX0-6 input S/PDIF through output withstand voltage input level compatible S/PDIF input (connected when set) Co-axial compatible S/PDIF input (supported demodulation sampling frequency 96kHz) withstand voltage input level compatible S/PDIF input (connected when set) withstand voltage input level compatible S/PDIF input Digital Digital power supply (3.3V) tolerable input level compatible S/PDIF input tolerable input level compatible S/PDIF input tolerable input level compatible S/PDIF input Digital power supply (3.3V) Digital loop filter connection Analog power supply (3.3V) Analog system clock output (VCO, 512fs, XIN) system clock (64fs) Digital Digital power supply (3.3V) system clock (fs) Serial audio data output system clock output (16fs, 32fs, 64fs, 128fs) system clock output (fs/4, fs/2, 2fs) External serial audio data input
Continued next page.
No.A1056-3/64
LC89058W-E
Continued from preceding page.
Name DGND DVDD XMCK XOUT DVDD DGND MOUT AUDIO CKST RERR XMODE DGND DVDD GPIO0 GPIO1 GPIO2 GPIO3 RXOUT2 Digital Digital power supply (3.3V) Oscillation amplifier clock output Output connected resonator External clock input pin, connected resonator (12.288MHz/24.576MHz) Digital power supply Digital Emphasis information Input monitor output Chip address setting input Channel status output Chip address setting input Clock switching transition period signal output Master/slave setting input Microcontroller interrupt signal output Pins44-48 setting input lock error, data error flag output microcontroller I/F, read data output (3-state) microcontroller I/F, write data input microcontroller I/F, chip enable input microcontroller I/F, clock input System reset input Digital Digital power supply (3.3V) General-purpose Selector input (output referred RDATA pin) General-purpose Selector input (output referred RLRCK pin) General-purpose Selector input (output referred RBCK pin) General-purpose Selector input (output referred RMCK pin) RX0-6 input S/PDIF through output Function
Input voltage: -0.3 3.6V, -0.3 5.5V Output voltage: -0.3 3.6V Pins have internal pull-down resistor (pd). Their level fixed when they unselected. Pins input pins chip address setting when held level. serves input designating master slave when held level. serves input configuring pins when held level. DVDD AVDD pins must held same level turned same timing preclude Latch-up conditions.
No.A1056-4/64
LC89058W-E
Block Diagram
MOUT AUDIO calculator GPIO0 GPIO1 GPIO2 GPIO3 RXOUT2 RXOUT1 Cbit, Clock Divider RMCK RBCK RLRCK SBCK SLRCK Input Selector Demodulation Lock detect Data Selector RERR SDIN RDATA Microcontroller XMODE
XOUT XMCK
Oscillation Amplifier
Clock Selector
CKST
Figure LC89058W-E Block Diagram
No.A1056-5/64
LC89058W-E
Common Different Points between LC89057W-VF4A-E LC89058W-E
Common Features Table 7.1: Common LC89057W-VF4A-E LC89058W-E functions (Hardware/Software Compatibility)
Item Package Supply voltage reception range Oscillation amplifier input frequency 2-system-clock output S/PDIF inputs Serial data input Non-PCM flag output Emphasis information output DTS-CD/LD detection function General-purpose Chip address setting Mode setting external resistor Microcontroller interface Register configuration SQFP48(9x9) 3.3V single source 32kHz 192kHz 12.288MHz/24.576MHz RMCK, RBCK, RLRCK, SBCK, SLRCK maximum coaxial, optical) SDIN AUDIO EMPHA (consumer professional) 14-bit format detection supported bits addresses maximum (master/salve supported) resistors used (SANYO-proprietary command address bits, data bits LC89057W-VF4A-E SBCK: 16fs, SLRCK: output added MOUT (consumer only) input regulations has. LC89058W-E
Removed Functions Table 7.2: Differences between LC89057W-VF4A-E LC89058W-E (Removed Functions)
Item Function S/PDIF unlock path switching External clock synchronization mode system clock synchronization Data output format output Input computed output Microcontroller interrupt signal LC89057W-VF4A-E Modulation demodulation Asynchronous system MSB, 16kHz 192kHz (Low pulse, level output)
LC89058W-E Modulation removed (demodulation only) Removed Removed Synchronization clock (SELMTD, RCKSEL removed) Right-justified removed (left-justified MSB, only) Removed 32kHz 192kHz 32kHz, removed) Pulse output mode removed (level output only)
Added Modified Functions Table 7.3: Differences between LC89057W-VF4A-E LC89058W-E (Added Modified Functions)
Item Oscillation amplifier initial setting clock output Master clock output Clock output when source Clock switching RMCK CKST polarity S/PDIF reception limitation S/PDIF input detection range Input value monitor output General-purpose input General-purpose input/output LC89057W-VF4A-E Suspended while locked 256fs 512fs Multiple input output limitation Clock count preserved maintain continuity) Polarity cannot switched Reflected only error flag. 32kHz 96kHz (XIN=24.57M/12.28MHz) Microcontroller interface output only timing control Parallel function only LC89058W-E Permanent operation 512fs Multiple input each band output RBCK SBCK must less RMCK Switched during CKST pulse output Polarity switched Reflected both error flag clock output 32kHz 192kHz (XIN=24.576MHz only) Microcontroller interface outputs Polling supported (with interrupt) Internal selector input also supported. Page 20-26
No.A1056-6/64
LC89058W-E
Differences Microcontroller Registers 7.4.1 Differences write commands Table 7.4: LC89057W-VF4A-E Write Register
Addr Setting Item system Demodulator system Master clock system output clock system output clock Source switching Data input/output Output format source selection RERR conditions Modulation system Modulation data Test Test Test Test DI15 TESPBSEL1 AMPOPR1 XRLRCK1 XSLRCK1 RXOFF SLRCKP EMPF ERWT1 TCKSEL DI14 PBSEL0 AMPOPR0 XRLRCK0 XSLRCK0 RDTMUT ROSEL2 SBCKP SLIPO ERWT0 DI13 TXOPR FSLIM1 EXSYNC XRBCK1 XSBCK1 RDTSTA ROSEL1 RLRCKP PCRNW FSERR TXMOD1 DI12 RXOPR FSLIM0 PLLOPR XRBCK0 XSBCK0 RDTSEL ROSEL0 RBCKP UNPCM RESTA TXMOD0 DI11 INTOPF RXMON XMSEL1 XRSEL1 PSLRCK1 ULSEL CSRNW XTWT1 TXMUT DI10 AOSEL XMSEL0 XRSEL0 PSLRCK0 RCKSEL RISEL2 OFSEL2 FSCHG XTWT0 VMODE TDTSEL DOEN VOSEL XINSEL PRSEL1 PSBCK1 OCKSEL RISEL1 OFSEL1 INDET REDER VISEL TXLRP SYSRST UOSEL PLLSEL PRSEL0 PSBCK0 SELMTD RISEL0 OFSEL0 ERROR RESEL UISEL TXDFS
Table 7.5: LC89058W-E Write Register
Addr Setting Item System setting System setting Master clock system output clock system output clock Source switching Data input/output Output format source selection RERR condition setting General-purpose Test System setting Data input/output Other output settings Test DI15 TES"0" AMPOPR1 XRLRCK1 XSLRCK1 SLRCKP EMPF ERWT1 FSSEL1 DI14 AMPOPR0 XRLRCK0 XSLRCK0 RDTMUT ROSEL2 SBCKP GPIO ERWT0 RXSEL2 FSSEL0 DI13 FSLIM1 XRBCK1 XSBCK1 RDTSTA ROSEL1 RLRCKP PCRNW FSERR CKSTP RXSEL1 DI12 FSLIM0 PLLOPR XRBCK0 XSBCK0 RDTSEL ROSEL0 RBCKP UNPCM RESTA RMCKP RXSEL0 DI11 RXMON XMSEL1 XRSEL1 PSLRCK1 CSRNW EDTMUT PTOXW1 DI10 AOSEL XMSEL0 XRSEL0 PSLRCK0 RISEL2 FSCHG PLLDV1 EMCKP PTOXW0 DOEN XINSEL PRSEL1 PSBCK1 OCKSEL RISEL1 INDET REDER PLLDV0 EXTSEL SYSRST MOSEL PRSEL0 PSBCK0 RISEL0 OFDSEL ERROR RESEL PLLACC GPIOS
Except MOSEL, PRSEL [1:0], OFDSEL, GPIO, SELMTD RCKSEL, command address inadvertently specified commands that removed from LC89057W-VF4A-E assumed ignored. commands added LC89058W-E allocated command addresses
No.A1056-7/64
LC89058W-E
7.4.2 Differences read commands Table 7.6: Changes Register Function between LC89057W-VF4A-E LC89058W-E
Address 0xE9 LC89057W-VF4A-E channel status write register LC89058W-E Removed
Table 7.7: Differences Read Registers between LC89057W-VF4A-E LC89058W-E
LC89057W-VF4A-E Register DO10 DO11 DO12 DO13 DO14 DO15 DO16 DO17 DO18 DO19 DO20 DO21 DO22 DO23 0xEA RXDET0 RXDET1 RXDET2 RXDET3 RXDET4 RXDET5 RXDET6 RXDET7 OERROR OINDET OFSCHG OCSRNW OUNPCM OPCRNW OSLIPO OEMPF CSBIT1 IEC1937 DTS51 DTSES F0512 F1024 F2048 F4096 0xEB FSC0 FSC1 FSC2 FSC3 FSDAT0 FSDAT1 FSDAT2 FSDAT3 FSDAT4 FSDAT5 FSDAT6 FSDAT7 0xEA RXDET0 RXDET1 RXDET2 RXDET3 RXDET4 RXDET5 RXDET6 OERROR OINDET OFSCHG OCSRNW OUNPCM OPCRNW OGPIO OEMPF CSBIT1 IEC1937 DTS51 DTSES LC89058W-E 0xEB FSC0 FSC1 FSC2 FSC3
addresses 0xEC 0xED remain same both LC89057W-VF4A-E LC89058W-E.
No.A1056-8/64
LC89058W-E
Points Notice about Replacing When replacing LC89057W-VF4A-E with LC89058W-E, necessary review circuit pattern design printed circuit board advance depending device used. Particular attention should directed pins whose functionality according setting. This section contains notes cautions observed when replacing LC89057W-VF4A-E with LC89058W-E. details pin, Chapter Initial System Settings Chapter Description Demodulation Function. Refer specifications LC89057W-VF4A-E when replacing LC89058W-E with LC89057W-VF4A-E. Table 7.8: Differences between LC89057W-VF4A-E LC89058W-E (Pins
LC89057W-VF4A-E Modulation function Pull-down Pin.44 TMCK Input Pin.45 TBCK Input Pin.46 TLRCK Input Pin.47 TDATA Input Pin.48 Output Pin.44 GPIO0 Input LC89058W-E General-purpose function Pin.45 GPIO1 Input Pin.46 GPIO2 Input Pin.47 GPIO3 Input S/PDIF Pin.48 RXOUT2 Output S/PDIF Pin.47 GPIO3 Output Pin.48 RXOUT2 Output
General-purpose function Pull-up Pin.44 PIO0 In/Output Pin.45 PIO1 In/Output Pin.46 PIO2 In/Output Pin.47 PIO3 In/Output Pin.48 PIOEN Input Pin.44 GPIO0 Output
General-purpose function Pin.45 GPIO1 Output Pin.46 GPIO2 Output
7.5.1 Change from LC89057W-VF4A-E LC89058W 7.5.1 When pull-down
Print Board LC89057W-VF4A-E Pin. LC89058W-E Pin.
TMCK TBCK TLRCK TDATA
Pin. Pin. Pin. Pin. Pin.
GPIO0 GPIO1 GPIO2 GPIO3 RXOUT2
Pin. Pin. Pin. Pin. Pin.
Figure Change from LC89057W-VF4A-E LC89058W-E (when pull-down) this case, system that doesn't modulation function general-purpose function replaced with LC89058W-E. After replacement, LC89058W-E used condition that pins connect with open.
No.A1056-9/64
LC89058W-E
7.5.1.2 When pull-up 7.5.1.2.1 case "Pin GND"
Print Board LC89057W-VF4A-E LC89058W-E
Pin.
Pin.
PIO0 PIO1 PIO2 PIO3 PIOEN
Pin. Pin. Pin. Pin. Pin.
GPIO0 GPIO1 GPIO2 GPIO3 RXOUT2
Pin. Pin. Pin. Pin. Pin.
Open when LC89058W-E
Figure Change from LC89057W-VF4A-E LC89058W-E (when pull-up) After replacement, pins used general purpose output function. (pin open) necessary review circuit pattern printed circuit board because setting differs from each other. 7.5.1.2.2 case "Pin VDD"
Print Board LC89057W-VF4A-E PIO0 PIO1 PIO2 PIO3 LC89058W-E Pin.
Pin. Pin. Pin. Pin. Pin. GPIO0 GPIO1 GPIO2 GPIO3 RXOUT2
Pin. Pin. Pin. Pin. Pin.
PIOEN Pin. Open when LC89058W-E
Figure Change from LC89057W-VF4A-E LC89058W-E (when pull-up) necessary review circuit pattern printed circuit board change pull-up resistor pull-down resistor because pins used general purpose input function. necessary review circuit pattern printed circuit board because setting differs from each other.
No.A1056-10/64
LC89058W-E
7.5.2 Change from LC89058W-E LC89057W-VF4A-E 7.5.2.1 When pull-down
Print Board LC89058W-E GPIO0 GPIO1 GPIO2 GPIO3 RXOUT2 LC89057W-VF4A-E Pin.
Pin. Pin. Pin. Pin. Pin. Pin.
PIO0 PIO1 PIO2 PIO3 PIOEN
Pin. Pin. Pin. Pin. Pin.
Short when LC89057W-VF4A-E
Figure Change from LC89058W-E LC89057W-VF4A-E (when pull-down) necessary review circuit pattern printed circuit board change pull-up resistor pull-down resistor because pins used general purpose input function. necessary review circuit pattern printed circuit board because setting differs from each other. After replacement, RXOUT2 output LC89057W-VF4A-E cannot used. 7.5.2.2 When pull-up
Print Board LC89058W-E LC89057W-VF4A-E
Pin.
Pin.
GPIO0 GPIO1 GPIO2 GPIO3 RXOUT2
Pin. Pin. Pin. Pin. Pin.
PIO0 PIO1 PIO2 PIO3 PIOEN
Pin. Pin. Pin. Pin. Pin.
Short when LC89057W-VF4A-E
Figure Change from LC89058W-E LC89057W-VF4A-E (when pull-up) After replacement, pins used general purpose output function. However, necessary review circuit pattern printed circuit board because GND. After replacement, RXOUT2 output LC89057W-VF4A-E cannot used.
No.A1056-11/64
LC89058W-E
Electrical Characteristics
Absolute Maximum Ratings Table 8.1: Absolute Maximum Ratings AGND DGND
Parameter Maximum supply voltage Maximum supply voltage Input voltage Input voltage Output voltage Storage ambient temperature Operating ambient temperature Maximum input/output current Symbol AVDD DVDD VIN1 VIN2 VOUT Tstg Topr IIN, IOUT 8-1-6 8-1-1 8-1-2 8-1-3 8-1-4 8-1-5 Conditions Ratings -0.3 +4.6 -0.3 +4.6 -0.3 VDD+0.3 (max.3.9V) -0.3 +5.8 -0.3 VDD+0.3 (max.3.9V) +125 Unit
8-1-1: AVDD 8-1-2: DVDD 8-1-3: RX1, RBCK, RLRCK, XIN, GPIO0, GPIO1, GPIO2, GPIO3 pins 8-1-4: RX0, RX2, RX3, RX4, RX5, RX6, SDIN, XMODE pins 8-1-5: RXOUT1, RMCK, RBCK, RLRCK, RDATA, SBCK, SLRCK, XMCK, XOUT, MOUT, AUDIO pins, CKST, INT, RERR, GPIO0, GPIO1, GPIO2, GPIO3, RXOUT2 pins 8-1-6: input/output Allowable Operating Ranges Table 8.2: Recommended Operating Conditions AGND DGND
Parameter Supply voltage Input voltage range Input voltage range Operating temperature Symbol AVDD, DVDD VIN1 VIN2 Topr 8-2-1 8-2-2 Conditions Ratings AVDD, DVDD Unit
8-2-1: RX1, RBCK, RLRCK, XIN, GPIO0, GPIO1, GPIO2, GPIO3 pins 8-2-2: RX0, RX2, RX3, RX4, RX5, RX6, SDIN, XMODE pins
No.A1056-12/64
LC89058W-E
Characteristics Table 8.3: Characteristics 70°C, AVDD DVDD 3.6V, AGND DGND
Parameter Input, High Input, Input, High Input, Output, High Output, Output, High Output, Output, High Output, Output, High Output, Input amplitude Consumption current Pull-down resistance Symbol 8-3-7 8-3-8 8-3-9 8-3-6 VDD-0.8 8-3-5 VDD-0.8 8-3-4 VDD-0.8 8-3-3 8-3-2 -0.3 VDD-0.8 8-3-1 Conditions 0.7VDD 0.2VDD Ratings Unit
8-3-1: CMOS compatible: RBCK, RLRCK input pins during slave settings 8-3-2: compatible: Input pins other than those listed above 8-3-3: -12mA, 8mA: RMCK output 8-3-4: -8mA, 8mA: XOUT, XMCK output pins 8-3-5: -4mA, 4mA: RXOUT1, RBCK, RLRCK, RDATA, SBCK, SLRCK, RERR, MOUT, GPIO0, GPIO1, GPIO2, GPIO3, RXOUT2 output pins 8-3-6: -2mA, 2mA: Output pins other than those listed above 8-3-7: Before capacitance input pin, reception frequency possible 96kHz. 8-3-8: Ta=25°C, fs=96kHz 8-3-9: RX0, RX2, RX3, RX4, RX5, input pins
No.A1056-13/64
LC89058W-E
Characteristics Table 8.4: Characteristics Ta=-30 70°C, AVDD=DVDD=3.0 3.6V, AGND=DGND=0V
Parameter RX0, frequency frequency RX0, pulse width pulse width duty factor clock frequency RMCK clock frequency RMCK clock jitter RMCK, RBCK delay RBCK, RDATA delay RMCK, SBCK delay SBCK, RDATA delay Symbol fRFS1 fRFS2 tWDI1 tWDI2 tDUY fMCK tMBO tBDO tMBO tBDO 8-4-2 8-4-3 8-4-1 Conditions Ratings Unit
8-4-1 frequency compatible with XINSEL setting must applied XIN. 8-4-2: When RMCK SBCK source clocks identical 8-4-3: When SBCK source clock
RX0-6 RMCK (RMCKP=0) RBCK RLRCK RDATA
tWDI tWDI tDUY
tDUY
FMCK tBDO
tMBO
Figure Characteristics Demodulation function
No.A1056-14/64
LC89058W-E
Microcontroller Interface Characteristics Table 8.5: Microcontroller Interface Characteristics Ta=-30 70°C, AVDD=DVDD=3.0 3.6V, AGND=DGND=0V
Parameter XMODE pulse width, pulse width, pulse width, High setup time hold time hold time setup time hold time hold time delay time delay time pulse width Symbol tRST setup hold hold setup hold hold 8-5-3 8-5-1 8-5-2 Conditions Ratings Unit
8-5-1: lower before when normal clock. 8-5-2: Only when data write with normal clock. 8-5-3: period reset period when normal
DVDD AVDD tRSTdw XMODE tCLuw tCLdw
tCEsetup tCEhold tDIdw tCEtoDO Hi-z tCLtoDO tDIsetup tDIhold tCLhold
Figure Microcontroller Interface Characteristics
No.A1056-15/64
LC89058W-E
Initial System Settings
System Reset (XMODE) system operates correctly when XMODE after 3.0V higher supply voltage applied. When XMODE after power turned system reset. chip address, master/slave, pins I/O, pull-down pull-up resistors must connected MOUT, AUDIO CKST, none MOUT, AUDIO CKST, pulled down pulled their state will unstable when settings entered, resulting wrong setting. Pull-up pull-down resistors must connected these pins without fail. Table 9.1: Names Settings
Setting Chip address Master/slave setting Pins setting Pins MOUT AUDIO CKST
Normal system operation range Setting completed 3.0V DVDD 200s XMODE Resetting Setting completed
state
Undefined
Setting input state
Output state
Setting input state
Output state
Figure Setting Timing Chart Function Setting Input Pins
Table 9.2: Output State When XMODE Reset (XMODE=L)
name RXOUT1 RMCK RBCK RLRCK RDATA SBCK SLRCK XMCK State output output output High output output output High output output name MOUT AUDIO CKST RERR RXOUT2 State Input state Input state Input state Input state High output Hi-z output output
No.A1056-16/64
LC89058W-E
Chip Address Settings (MOUT, AUDIO) LC89058W-E comes with function unique chip address allow several LC89058W-E same microcontroller interface bus. chip address setting, connect pull-down pull-up resistor MOUT AUDIO. this setting, kinds chip addresses maximum. Chip addresses microcontroller interface with provided first bits side. corresponds lower chip address higher chip address. Command writing enabled making chip address settings with MOUT AUDIO identical chip addresses sent from microcontroller. chip address setting required even when only LC89058W-E used system. chip address set, chip address undefined microcontroller cannot control system. When microcontroller used, chip address-setting pin_ open while XMODE "L". sure connect either pull-down resistor input pull-up resistor MOUT AUDIO.
AUDIO Pull-down Pull-down Pull-up Pull-up
Table 9.3: Chip Address Settings (Resistor Connection)
MOUT Pull-down Pull-up Pull-down Pull-up
LC89058W-E
MOUT AUDIO CKST
pull-up
Connect different circuits
pull-down
Setting Contents Above Figure Chip address setting Master slave setting Pins input output setting CAL=CAU=0 Master Pins output pins
Figure Setting Example Function Setting Input
No.A1056-17/64
LC89058W-E
Master/Slave Settings (CKST) master/slave function that allows multi-channel synchronized transfer using multiple LC89058W-Es included. this setting, connects either pull-down pull-up resistor CKST. master mode normally, when single LC89058W-E used. When multiple LC89058W-Es used, them master mode others slave mode. multi-channel synchronous transfer mode using multiple LC89058W-Es, connect RBCK RLRCK (output) master side RBCK RLRCK (input) slave side. Also connect XMCK master side slave side. this time, polarity RBCK RLRCK, frequency XMCK must identical. master/slave function runs correctly with multiple LC89058W-Es connected. sure connect either pull-down resistor pull-up resistor CKST. Always supply clock RBCK RLRCK when slave function set. Table 9.4: Master/Slave Switching (Register Connection)
CKST Pull-down Pull-up Mode Master Slave
Table 9.5: Clock State
RMCK RBCK RLRCK Master mode Output Output Output Slave mode Output Input Input
Pins settings Pins provided with bidirectional buffer. When setting function pins connect pull-down pull-up resistor sure connect either pull-down resistor pull-up resistor Table 9.6: Pins Settings (Resistor Connection)
Pull-down Pull-up Mode Input. Output.
No.A1056-18/64
LC89058W-E
Description Demodulation Function
10.1 Clocks 10.1.1 (LPF) LC89058W-E incorporates (Voltage Controlled Oscillator) that stopped with PLLOPR synchronizes with sampling frequencies (fs) from 32kHz 192kHz with data with transfer rate from 4MHz 25MHz. locked 512fs. loop filter. Connect following resistance capacitance shown figure.
0.1F 0.022F
Figure 10.1 Loop Filter Configuration 10.1.2 Oscillation amplifiers (XIN, XOUT, XMCK) LC89058W-E features built-in oscillation amplifier. Connecting quartz resonator, feedback resistor, load capacitance XOUT configure oscillation circuit. When connecting quartz resonator, with fundamental wave. aware that load capacitance depends quartz resonator characteristics. built-in oscillation amplifier used oscillation module used clock source instead, connect output external clock supply source XIN. this time, necessary connect feedback resistor between XOUT. Always supply with 12.288MHz 24.576MHz clock with XINSEL. supplying other frequencies XIN, necessary that result change sampling frequency input data with FSERR reflected error flag. this setting, operation functions properly. Since recommended frequency, cannot used input calculations. setting XINSEL must completed prior S/PDIF input. Supply with clocks time used following applications. Detection presence absence S/PDIF input Clock source while unlocked Calculation input data sampling frequency Time definition when switching input data External source supply clock (clock converter, etc.) source mode. Polling processing performed when setting general-purpose input function oscillation amplifier runs even when locked. Therefore, data detection calculation input sampling frequency become possible while locked. that case, both oscillation amplifier clock clock signals coexist, then user must attention make sure sound quality adversely affected. adverse effects sound quality recognized, possible with AMPOPR [1:0] that oscillation amplifier automatically stop operation while locked. Therefore, setting AMPOPR [1:0] must completed either prior S/PDIF input while unlocked. oscillation amplifier stopped unnecessary. However, when normal operation resumed, must wait 10ms longer until resonator oscillation gets stable. XMCK outputs clock. XMCK output with XMSEL [1:0]. clock 1/1, 1/2, 1/4, muted output. only oscillation amplifier, input quartz resonator XOUT external clock XIN, electric potential digital data input pins RX6, with RISEL [2:0] that inputs deselected.
No.A1056-19/64
LC89058W-E
10.1.3 Switching between master clock clock source RMCK, RBCK, RLRCK (hereunder, system), SBCK SLRCK (hereunder, system) clock sources selected between following master clocks. source (512fs) source (12.288MHz 24.576MHz) Clock source switching with systems interlocked. This setting carried with OCKSEL. clock source automatically switched clock locking/unlocking PLL. clock source switched with OCKSEL, regardless status. Table 10.1: Relationship between Clock Source Switch Commands Clock Sources when Locked/Unlocked
OCKSEL System Clock Source Locked Unlocked System Clock Source Locked Unlocked
status always monitored with RERR even after switching source. Moreover, processed information read with microcontroller interface regardless status. 10.1.4 Points notice about switching clock source while locked necessary oscillation amplifier continuous operation mode same time with AMPOPR [1:0] clock switch source with OCKSEL when oscillation amplifier stopped state where locked. clock output when switching clock source without executing this setting. state where locked, clock switched source with OCKSEL while oscillator amplifier stopped, RERR temporarily outputs error (high level) indication. When switched source, oscillator amplifier switched operating state same time. RERR temporality outputs error level) indication when oscillation amplifier switches from stop condition continuous mode. Consequently input calculation restarts. this time, previous calculation value reset compared with newly calculated value. Then those values found identical, that's error temporarily issued.
No.A1056-20/64
LC89058W-E
10.1.5 Master clock block diagram (XIN, XOUT, RMCK, XMCK) relationships between types source master clocks, switching, frequency division function described below. contents quotation marks "*** switch function blocks correspond write command names. Lock/Unlock automatically switched locking/unlocking.
"PLLOPR" S/PDIF 512fs
"PLLDV1" "PLLDV2" Auto (N=1,2,4) "PLLACC"
Lock/Unlock
(N=1,2,4) XOUT "PRSEL[1:0]" "XINSEL" "AMPOPR[1:0]" GPIO0 12.288M 24.567M "XRSEL[1:0]" (N=1,2,4)
"OCKSEL"
"RMCKP"
RMCK
"EXTSEL" "EMCKP" "XMSEL[1:0]" (N=1, XMCK
Figure 10.2 Master Clock Block Diagram
No.A1056-21/64
LC89058W-E
10.1.6 clock output clock output controlled PLLACC, PLLDV1, PLLDV2, PRSEL[1:0]. PLLACC used generate lock frequency each S/PDIF input sampling frequency band.
S/PDIF Input
512fs Lock detection Lock calculation
Unlock
output Free-run
When data judged exceed value FSLIM [1:0] which limits reception frequency input S/PDIF, processing similar unlocking carried processing does proceed subsequent step. clock source automatically switched source.
"PLLACC" fixation output "PRSEL=00": 256fs "PRSEL=01": 512fs "PRSEL=10": 128fs
32k, 44.1k,
64k, 88.2k,
"PLLDV0"
128k, 176.4k, 192k output 128fs
"PLLDV1" output 256fs output 512fs output 512fs output 256fs
output 256fs
Figure 10.3 Clock Output Control Table 10.2: Clock Output Frequencies (Bold settings recommended values.)
Output S/PDIF PLLACC=0 (Fixed multiple outputs input PRSEL=00 (256fs) 32kHz 44.1kHz 48kHz 64kHz 88.2kHz 96kHz 128kHz 176.4kHz 192kHz 8.19MHz 11.28MHz 12.28MHz 16.38MHz 22.57MHz 24.57MHz 32.76MHz 45.15MHz 49.15MHz PRSEL=01 (512fs) 16.38MHz 22.57MHz 24.57MHz 32.76MHz 45.15MHz 49.15MHz 65.53MHz 90.31MHz 98.30MHz PRSEL=10 (128fs) 4.09MHz 5.64MHz 6.14MHz 8.19MHz 11.28MHz 12.28MHz 16.38MHz 22.57MHz 24.57MHz PLLACC=1 (Fixed multiple outputs each input band) PLLDV0=0 PLLDV1=0 16.38MHz 22.57MHz 24.57MHz 16.38MHz 22.57MHz 24.57MHz 16.38MHz 22.57MHz 24.57MHz PLLDV0=1 PLLDV1=0 8.19MHz 11.28MHz 12.28MHz 16.38MHz 22.57MHz 24.57MHz 16.38MHz 22.57MHz 24.57MHz PLLDV0=0 PLLDV1=1 16.38MHz 22.57MHz 24.57MHz 32.76MHz 45.15MHz 49.15MHz 16.38MHz 22.57MHz 24.57MHz PLLDV0=1 PLLDV1=1 8.19MHz 11.28MHz 12.28MHz 32.76MHz 45.15MHz 49.15MHz 16.38MHz 22.57MHz 24.57MHz
128kHz, 176.4kHz 192kHz input received when PLLACC PRSEL [1:0] characteristics output directly sent RMCK cannot guaranteed. such case, frequency half quarter clock frequency (PRSEL [1:0]=00 10).
No.A1056-22/64
LC89058W-E
10.1.7 Output clocks (RMCK, RBCK, RLRCK, SBCK, SLRCK) LC89058W-E features clock systems systems) order supply various needed clocks peripheral devices such converter DSP. clock output settings systems done with PLLACC, PLLDV1, PLLVD2, PRSEL[1:0], XRSEL[1:0], XRBCK[1:0], XRLRCK[1:0], PSBCK[1:0], PSLRCK[1:0], XSBCK[1:0], XSLRCK[1:0]. Setting range each clock output when used source RMCK: Selection from 1/1, 1/2, PLLACC, PLLDV0, PLLDV1, 512fs RBCK: 64fs output RLRCK: output SBCK: Selection from 128fs, 64fs, 32fs, 16fs (5)SLRCK: Selection from 2fs, 1/2fs, 1/4fs Setting range each clock output pins when used source RMCK: Selection from 1/1, 1/2, 12.288MHz 24.576MHz RBCK: Selection from 12.288MHz, 6.144MHz, 3.072MHz SBCK: Selection from 12.288MHz, 6.144MHz, 3.072MHz RLRCK: Selection from 192kHz, 96kHz, 48kHz SLRCK: Selection from 192kHz, 96kHz, 48kHz polarity RMCK reversed with RMCKP. polarity RBCK, RLRCK, SBCK, SLRCK reversed with RBCKP, RLRCKP, SBCKP, SLRCKP. Table 10.3 List Output Clock Frequencies (Bold Items Initial Settings)
Output Name Source (Internal 512fs 512fs RMCK 256fs 128fs RBCK 64fs Source (XIN input 12.288MHz 12.288MHz 6.144MHz 12.288MHz 6.144MHz 3.072MHz RLRCK 128fs SBCK 64fs 32fs 16fs SLRCK fs/2 fs/4 24.576MHz 24.576MHz 12.288MHz 6.144MHz (RMCK=24.576MHz) (RMCK12.288MHz) (RMCK6.144MHz)
192kHz 96kHz 48kHz 12.288MHz 6.144MHz 3.072MHz (RMCK=24.576MHz) (RMCK12.288MHz) (RMCK6.144MHz)
192kHz 96kHz 48kHz
Notes: RBCK SBCK output clock must quicken more than RMCK output clock frequency. Also, RBCK SBCK output clock become less RMCK output clock source. doesn't follow these conditions, RBCK SBCK clocks output.
No.A1056-23/64
LC89058W-E
10.1.8 Output clocks block diagram (RMCK, RBCK, RLRCK, SBCK, SLRCK, XMCK) relationships between output clock switch function shown below. figure indicates source source. contents quotation marks switch function blocks correspond write command names. broken lines connecting switches indicate coordinated switching. Lock/Unlock switched automatically locking/unlocking.
"PLLDV0" "PLLDV1" Input Lock Unlock "OCKSEL" "EXTSEL"
Master Clock Generator Source 512fs
512fs
Auto "PLLACC"
X'tal Source 12.288MHz 24.576MHz
512fs 256fs 128fs Mute
"PRSEL[1:0]"
12.288MHz 24.576MHz
"XINSEL"
"RMCKP" "XRSEL[1:0]" Mute
"EMCKP" GPIO0
RMCK
"XMSEL[1:0]" Mute
XMCK
64fs
"XRBCK[1:0]" 12.288MH 6.144MHz 3.072MHz Mute
GPIO1 RBCK
"XRLRCK[1:0]" 192kHz 96kHz 48kHz Mute
GPIO2 RLRCK
"PSBCK[1:0]" 128fs 64fs 32fs 16fs
"SBCKP" Master Slave
"XSBCK[1:0]" 12.288MH 6.144MHz 3.072MHz Mute "PSLRCK[1:0]" fs/2 fs/4
SBCK
"SLRCKP"
"XSLRCK[1:0]" 192kHz 96kHz 48kHz Mute
SLRCK
Figure 10.4 Clock Output Block Diagram
No.A1056-24/64
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10.1.9 Output clock switch transition signal (CKST) CKST outputs pulse when output clock changes lock/unlock. polarity CKST pulse output reversed with CKSTP. Subsequently, CKSTP assumed lock-in stage, CKST falls word clock generated from clock after locked following detection input data, rises same timing RERR after designated period. unlock stage, CKST falls same timing RERR, lock detection signal, rises after word clocks generated from clock counted designated period. Change lock status timing clock change seen detecting rising falling edges pulses CKST. clock switched after lock condition tested identified. timing this clock switching determined setting PTOXW [1:0]. initial value such that clock switched 2.7ms after falling edge CKST. value, however, assumes that oscillation amplifier permanent operation mode. oscillation amplifier stopped after locking, startup time before oscillation amplifier stabilizes after unlocking, added. free-running clock output from clock output immediately after unlocking.
status clock clock UNLOCK
Digital data LOCK
After lock CKST RERR RMCK clock (a): Lock-in stage (CKSTP=0)
144ms
2.7ms
clock
status clock clock
Digital data LOCK UNLOCK
Same timing RERR CKST RERR RMCK clock When PTOXW[1:0]=00 (max.) (b): Unlock stage (CKSTP=0)
5.3ms
2.7ms**
clock
Figure 10.5 Clock Switch Timing
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10.1.10 Output clocks generated when input S/PDIF reception limited same processing performed when unlocked carried S/PDIF input exceeding reception range limit (which defined FSLIM[1:0]) supplied. clock source then switched clock clocks output from respective clock pins.
DIN0-6 status RERR RMCK RBCK RLRCK
fs=44.1kHz LOCK
fs=192kHz LOCK
fs=96kHz LOCK
clock
clock When FSLIM[1:0]=00 limit inputs) clock
clock
UNLOCK fs=96kHz LOCK
DIN0-6 status RERR RMCK RBCK RLRCK
fs=44.1kHz LOCK
fs=192kHz LOCK
clock
clock
clock
When FSLIM[1:0]=01 (Receive frequency limited 96kHz lower)
DIN0-6 status RERR RMCK RBCK RLRCK
fs=44.1kHz LOCK
fs=192kHz LOCK
fs=96kHz LOCK
clock
clock
When FSLIM[1:0]=10 (Receive frequency limited 48kHz lower)
Figure 10.6 Output Clocks Generated When Input Data Reception Limited
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10.2 S/PDIF 10.2.1 Reception range S/PDIF input guaranteed reception range input data shown below. Table 10.4: S/PDIF Reception Range (FSLIM [1:0]=00)
Output Clock Setting 512fs Input Data Reception Range 30kHz 192kHz
Note: Reception range 32kHz 96kHz. output clock frequency-divided with PLLACC, PLLDIV PRSEL [1:0] output from RMCK. reception range input data limited within range output clocks stated above. This setting carried with FSLIM [1:0]. When this function adopted, input data exceeding range considered error, clock source automatically switched source, RDATA output data subject RDTSEL setting. 10.2.2 S/PDIF pins (RX0 RX6, RXOUT1, RXOUT2) S/PDIF input pins inputs maximum. coaxial-compatible input pin. When using RX1, connect GND. RX0, RX2, RX3, RX4, RX5, input level pins with 5V-tolerance voltage. Make sure that selected pins input-open. points notice RX1, following subsection. unselected pins pulled down with their internal resistors. demodulation input S/PDIF through-output pins RXOUT1 RXOUT2 data selected independently. demodulation data selected with RISEL[2:0]. RXOUT1 output data selected with ROSEL[2:0]. RXOUT2 output data selected with RXSEL[2:0]. possible deselect with RISEL[2:0] (RISEL[2:0]=111). RXOUT1 RXOUT2 muted with RXOSEL[2:0] RXSEL[2:0], respectively. Muting recommended reduce jitter when RXOUT1 RXOUT2 used. data input state monitored with RXMON setting. status each data input stored address 0xEA output registers DO7. Moreover, latest information read with microcontroller setting interrupt processing command INDET. details, Chapter Microcontroller Interface. frequencies input data that monitored with this setting from 32kHz 192kHz. data detection function applies IEC60958 compatible S/PDIF data. frequency clock supplied when RXMON limited 24.576MHz. LC89058W-E does clock frequency other than 24.576MHz. Moreover, since this function uses clock, oscillation amplifier must continuous operation mode when RXMON set. When data input monitoring specified, input pins, except RX1pin those which selected demodulation, pulled down. This preclude input-open when detecting connection input pins. peripheral circuit pin, following page.
No.A1056-27/64
LC89058W-E
10.2.3 S/PDIF input circuits (RX0 RX6) RX0, RX2, RX3, RX4, RX5, received data 32kHz 192kHz. received 96kHz data. with built-in amplifier used coaxial input pin, malfunction occur influence from adjacent input pins. avoid influences from those pins, "L". addition, pull-down resistor inserted after coupling capacitor noise measures, when signal connected with selected. When selected input signal always fixed either (Toslink etc), processes required. RX0, RX2, RX3, RX4, RX5, input level compatible S/PDIF input pins with 5V-tolerance voltage. LC89058W-E
Coaxial
470k
Optical etc.
Coaxial input circuit
Optical
LC89058W-E
Optical etc.
Optical input circuit
Figure 10.7 S/PDIF Input Circuits
No.A1056-28/64
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10.3 Serial Audio Data 10.3.1 Output data format (RDATA) output format with OFDSEL. initial value output format I2S. Output data output synchronized with RLRCK edge immediately after RERR output becomes "L".
L-ch RLRCK RBCK RDATA 24bit (0): data output
R-ch
24bit
L-ch RLRCK RBCK RDATA 24bit 24bit (1): MSB-first front-loading data output
R-ch
Figure 10.8 Data Output Timing
No.A1056-29/64
LC89058W-E
10.3.2 Serial audio data input format (SDIN) LC89058W-E provided with serial data input SDIN. format serial audio data input SDIN demodulation data output format must identical. initial value modulation data output format I2S. SDIN data input must synchronization with RBCK RLRCK clocks. data input from SDIN through-output RDATA pin. SDIN must connected when used.
24bit SDIN RLRCK RBCK RDATA
24bit R-ch
L-ch
(0): data output
24bit SDIN RLRCK RBCK RDATA L-ch
24bit R-ch
(1): MSB-first front-loading data input
Figure 10.9 Serial Audio Data Input Timing
No.A1056-30/64
LC89058W-E
10.3.3 Output data switching (SDIN, RDATA) RDATA outputs demodulation data when locked, outputs SDIN input data when unlocked. This output automatically switched according locked/unlocked status. details, timing charts below. When SDIN input data selected, switch clock source synchronized SDIN data. With RDTSTA setting, SDIN input data output RDATA regardless locked/unlocked status PLL. With RDTMUT setting, RDATA output data also muted forcibly. Even when clock source with OCKSEL RCKSEL, continues operating long stopped with PLLOPR. this time, status continuously output from RERR unless error output forcibly with RESTA. Moreover, processed information read with microcontroller interface regardless status.
status CKST RERR RDATA CKSTP=0
UNLOCK
LOCK
SDIN data
Muted (a): Lock-in stage
Demodulation data
status CKST RERR RDATA CKSTP=0
LOCK
UNLOCK
Demodulation data (b): Unlock stage
Muted
SDIN data
Figure 10.10 Timing Chart RDATA Output Data Switching
No.A1056-31/64
LC89058W-E
10.3.4 Data block diagram (RX0 RX6, RXOUT1, RXOUT2, RDATA, SDIN) Select demodulated data SDIN input data with RDTSEL RDTSTA, mute processing performed with RDTMUT. Moreover, GPIO0 input data selected with EXTSEL. Also, GPIO0 subject mute processing with EDTMUT. Chapter selector function general-purpose pins (GPIO0 GP1O3).
"ROSEL[2:0]"
S/PDIF
"ROSEL[2:0]=111" RXOUT1
"RXSEL[2:0]"
S/PDIF
"RXSEL[2:0]=111" RXOUT2
"RISEL[2:0]"
"RDTSEL" "RDTSTA" "RDTMUT" "EXTSEL" RDATA
SDIN GPIO3 "EDTMUT"
Figure 10.11 Data System Diagram 10.3.5 Calculation input data sampling frequency (MOUT) input data sampling frequency calculated using clock. mode where oscillation amplifier automatically stops according lock status PLL, input data sampling frequency calculated during RERR error period completed when oscillation amplifier stops with holding value. Therefore, value remains unchanged until becomes unlocked. oscillation amplifier continuous operation mode, calculation repeated constantly. Even sampling changes within capture range input data whose channel status sampling information does change, calculation results that follow input data read. calculation results readout MOUT with microcontroller interface. Since MOUT also used generate emphasis information, contents MOUT output MOSEL. calculation output MOUT limited. FSSEL[1:0] sets contents MOUT output. Table 10.5: MOUT Output Mode Settings
FSSEL1 FSSEL0 MOUT Output Conditions When calculating 32kHz, 44.1kHz 48kHz When calculating 88.2kHz 96kHz When calculating 176.4kHz 192kHz When calculating 88.2kHz, 96kHz higher
No.A1056-32/64
LC89058W-E
10.4 Error Output Processing 10.4.1 Lock error data error output (RERR) RERR outputs error flag when lock error data error occurs. possible treat non-PCM data reception error RESEL setting. RERR output conditions with RESTA. Since status output times, status always monitored, even when clock source XIN. 10.4.2 lock error gets unlocked input data that lost bi-phase modulation regularity, input data which preambles cannot detected. However, even preambles detected timing does conform IEC60958, unlocked processed. example, period preamble every192 frames. RERR turns when lock error occurs returns when data demodulation returns normal held somewhere between 144ms. This holding time determined with ERWT[1:0] setting. rising falling edges RERR synchronized with RLRCK. 10.4.3 Input data parity error number errors among parity bits input data input parity errors detected. input parity error occurs more times succession, RERR turns indicating that locked, after holding somewhere between 144ms, returns "L". error flag output format selected with REDER, when input parity error output less than times succession. 10.4.4 Other errors Even RERR turns "L", channel status bits (sampling frequency) always fetched data previous block compared with current data. Moreover, input data sampling frequency calculated from clock extracted from input data, calculated value compared same described above. difference detected these data, RERR instantly made same processing lock errors carried out. causes lock error when changes described above. However, order support sources with variable (for example player with variable pitch function), possible with FSERR output error flag unless changes exceeding capture range. FSERR setting, when locked, RERR turned without reflecting calculation result error flag concerning input data within reception range FSLIM [1:0]. Moreover, data comparison channel status bits described above performed. setting which regard non-PCM data input error made with RESEL, RERR turns when non-PCM data input detected. this time, locked status various output clocks subject input data, output data muted.
No.A1056-33/64
LC89058W-E
10.4.5 Data processing upon occurrence errors (lock error, parity error) data processing upon occurrence error described below. fewer input parity errors occur succession transfer data audio data, data replaced saved each L-ch R-ch previous frame. However, transfer data non-PCM data, error data output Non-PCM data data when (audio sample word) channel status turns based data detected prior occurrence input parity error. Output data muted when lock error occurs parity error occurs more times succession. channel status output, data previous block held 1-bit units when parity error occur fewer times succession. Table 10.6 Data Processing upon Error Occurrence
Data Demodulation data calculation result Channel status Lock Error Input Parity Error Output Input Parity Error Previous value data Output Previous value data Input Parity Error Output Output Previous value data
Input parity error (a): occurs more times succession Input parity error (b): occurs fewer times succession, case audio data Input parity error (c): occurs fewer times succession, case non-PCM burst data
1occurrence Input data
RERR
RLRCK
RDATA
R-ch Previous value data
L-ch R-ch Previous value data
times more: Muting
Figure 10.12 Example Data Processing upon Parity Error Occurrence
No.A1056-34/64
LC89058W-E
10.4.6 Processing during error recovery When preambles detected, becomes locked data demodulation begins. Demodulation data output from RLRCK edge after RERR turns "L".
RERR Lock Signal RLRCK RDATA 144ms
Data
Output start from RWCK edge immediately after RERR lowered
Figure 10.13 Data Processing When Data Demodulation Starts
10.5 Data Delimiter Output AUDIO AUDIO outputs channel status data delimiter information. Outputs channel status that indicates whether input bi-phase data audio data. AUDIO immediately output upon detection RERR even during output period. OR-output with IEC61937 with DTS-CD/LD detection flag also possible with AOSEL.
AUDIO
Table 10.7 AUDIO Output
Output Conditions audio data "L") Non-audio data "H")
10.6 Emphasis Information Output (EMPHA) MOUT output whether there 50/15s emphasis parameter consumer switching contents MOUT output MOSEL. MOUT immediately output upon detection RERR even during output. Table 10.8 MOUT Output
MOUT Output Conditions pre-emphasis 50/15s pre-emphasis
10.7 IEC61937, DTS-CD/LD Detection Flag Output function output IEC61937 DTS-CD/LD detection flag non-PCM data provided. DTS-CD/LD compatible with "14-bit format." When channel status non-PCM data, IEC61937 sync signal detected detection flag output. data, detection flag output. DTS-CD/LD sync signal detection done based sync pattern base frequency. sync pattern checked every 4096th frame, detection status held until sync pattern longer verified. IEC61937 DTS-CD/LD detection flags readout with microcontroller interface addition output AUDIO AOSEL. When UNPCM non-PCM signal output setting selected through output contents setting, interrupt signal output from detecting IEC61937 DTS-CD/LD sync signal. Reading output register from this information details Non-PCM signal. This information used read output register identify details non-PCM signal detection flags cleared when changed when lock error data error occurs.
No.A1056-35/64
LC89058W-E
Description General-purpose Function (GPIO0, GPIO1, GPIO2, GPIO3)
11.1 Initial Settings When setting general-purpose I/Os input, pull down with resistors. When settings general-purpose I/Os output, pull with resistor. Chapter settings. general-purpose I/Os output pin, serial data input from microcontroller interface converted parallel data output from GPIO0, GPIO1, GPIO2, GPIO3. general-purpose I/Os input pin, select functions listed below with GPIOS. Store parallel data input from GPIO0, GPIO1, GPIO2, GPIO3 internal register readout contents that register through microcontroller interface (GPIOS=0). Configure 2-to-1 bits wide) selector that selects either audio format data clock that input GPIO0, GPIO1, GPIO2, GPIO3 pins, data clock demodulated block. RMCK, RBCK, RLRCK, RDATA outputs from selector (GPIOS=1). 11.2 Output Function data output directed GPIO0, GPIO1, GPIO2, GPIO3 stored address 0xE8, command address input register bits DI12 DI15, register PI[3:0]. data stored PI[3:0] transmitted GPIO0, GPIO1, GPIO2, GPIO3 pins. 11.3 Input Function 11.3.1 GPIOS=0 data input GPIO0, GPIO1, GPIO2, GPIO3 taken into address 0xEB, output register bits DO3, register PO[3:0]. data must readout setting interrupt source GPIO arbitrary timing. which data taken into register depends readout. 11.3.1.1 GPIO=1 (using must always given specified clock continuous operating mode (default). data inputs GPIO0, GPIO1, GPIO2, GPIO3 taken into register 24kHz clock. When state data inputs changes, turns suspends data transfer register. interrupt sources address 0xEA, output register DO14, register OGPIO must verified. turns data held register immediately when address 0xEA readout. read data from PO[3:0] transferred microcontroller. same time, data register cleared. contents register updated turns before P0[3:0] readout. 11.3.1.2 GPIO=0 (not using data inputs GPIO0, GPIO1, GPIO2, GPIO3 pins taken when address 0xEB set. data read from PO[3:0] transferred microcontroller. same time, data register cleared.
No.A1056-36/64
LC89058W-E
11.3.2 GPIOS=1 figure below shows relationship between GPIO0, GPIO1, GPIO2, GPIO3 which input selector block signal, RMCK, RBCK, RLRCK, RDATA which output from selector control signal.
Lock judgment "EXTSEL" RMCK RBCK RLRCK RDATA
SDIN XIN-MCK XIN-BCK XIN-LRCK PLL-MCK PLL-BCK PLL-LRCK PLL-DATA "EMCKP"
radio
GPIO0 GPIO1 GPIO2 GPIO3 "EDTMUT"
Figure 11.1 Selector Configuration Diagram Table 11.1 Selector Signals
Input Input Signal EXTSEL=1 Lock State GPIO0 (pin GPIO1 (pin GPIO2 (pin GPIO3 (pin PLL-MCK PLL-BCK PLL-LRCK PLL-DATA EXTSEL=0 Unlock State XIN-MCK XIN-BCK XIN-LRCK SDIN RMCK (pin RBCK (pin RLRCK (pin RDATA (pin Output
Note: selector output generated when locked changed clock system setting OCKSEL RCSEL. EXTSEL enabled setting GPIOS=1. When GPIOS=0 set, state EXTSEL=0 output from each pin. clock input GPIO0 inverted EMCKP sent RMCK. data input GPIO3 must conform PLL-DATA SDIN audio format. data input GPIO3 muted EDTMUT. EMCKP EDTMUT enabled when GPIOS=1 set. above settings valid only when master mode must when slave mode set.
No.A1056-37/64
LC89058W-E
Microcontroller Interface
12.1 Description Microcontroller Interface 12.1.1 Interrupt output INT) Interrupts output when change occurred lock status output data information. Interrupt output consists register selecting interrupt source, that outputs that state transition, registers that store interrupt source data. Normally held output upon occurrence interrupt. Following output, cleared returns immediately when interrupt source output register readout. interrupt sources selected among following items. Multiple sources selected same time with contents address 0xE8 command address outputs calculation result selected interrupt sources. output (selected source (selected source (selected source Table 12.1 Interrupt Source Setting Contents
Command Name ERROR INDET FSCHG CSRNW UNPCM PCRNW GPIO EMPF Output when RERR status changed Output when input data status changed (subject oscillation amplifier operation condition) Output when input calculation result changed. (subject oscillation amplifier condition) Output when channel status data first bits have updated Output when AUDIO status changed Output when burst preamble been updated Output when state input data changes when general-purpose parallel input set. Output when emphasis information changed Description
contents interrupt source saved output registers DO15 address 0xEA, when source occurs. However, read registers source items each status RERR AUDIO pins output time reading. Other data except source items saved registers upon occurrence interrupt source. Concerning source items oscillation amplifier clock used. Therefore, status monitored even while the_ locked, oscillation amplifier must continuous operation mode. Clearing same time readout output register carried immediately after output register 0xEA set. However, cleared other than 0xEA setting.
No.A1056-38/64
LC89058W-E
12.1.2 interface interface SANYO's original serial format based LSB-first communication, three-state employed instead open-drain data output format LC89058W-E. Data input/output performed following address input. same address cannot used both read write operation. Table 12.2 Relationship between Register Contents Addresses
Register contents Function setting data input Input detection, interrupt output data output data output data output Write Read Read Read Read address 0xE8 0xEA 0xEB 0xEC 0xED
12.1.3 Data write procedure Input performed following sequence: addresses chip addresses DI1, command addresses DI7, data DI15. reserved system. input must doing "0". chip addresses, corresponds (low-order), (high-order). details, section 9.2. 12.1.4 Data read procedure Read data output from high impedance state when "L", begins outputting from rising edge after output setting established address. then returns high impedance state falling edge outputs shared using multiple LC89058W-E units, possible outputs LC89058W-E units which data read always high impedance state with DOEN. With this setting, only targeted outputs read. 12.1.5 Points notices when normal clock used interface uses normal clock, also possible normal clock. However, input clock based microcontroller interface characteristics. lowered before raised when data reads.
No.A1056-39/64
LC89058W-E
12.1.6 timing
DI10
DI15
Hi-Z
Figure 12.1 Input Timing Chart (Normal clock)
DI10 DI11 DI12
DI15
Hi-Z
Figure 12.2 Input Timing Chart (Normal clock) need lowered before raised.)
Hi-Z
Figure 12.3 Output Timing Chart (Normal clock)
Hi-Z
Figure 12.4 Output Timing Chart (Normal clock) lowered before raised, need read with port)
No.A1056-40/64
LC89058W-E
12.2 Write Data 12.2.1 List write commands list write commands shown below. write commands shown following table, address 0xE8. Table 12.3 Write Register
Add. Setting Items System setting System setting Master clock system output clock system output clock Source switch Data Output format INTsource selection RERR condition setting General-purpose TEST System setting Data clock TEST DI15 TES0 AMPOPR1 XRLRCK1 XSLRCK1 SLRCKP EMPF ERWT1 FSSEL1 DI14 AMPOPR0 XRLRCK0 XSLRCK0 RDTMUT ROSEL2 SBCKP GPIO ERWT0 RXSEL2 FSSEL0 DI13 FSLIM1 XRBCK1 XSBCK1 RDTSTA ROSEL1 RLRCKP PCRNW FSERR CKSTP RXSEL1 DI12 FSLIM0 PLLOPR XRBCK0 XSBCK0 RDTSEL ROSEL0 RBCKP UNPCM RESTA RMCKP RXSEL0 DI11 RXMON XMSEL1 XRSEL1 PSLRCK1 CSRNW EDTMUT PTOXW1 DI10 AOSEL XMSEL0 XRSEL0 PSLRCK0 RISEL2 FSCHG PLLDV1 EMCKP PTOXW0 DOEN XINSEL PRSEL1 PSBCK1 OCKSEL RISEL1 INDET REDER PLLDV0 EXTSEL SYSRST MOSEL PRSEL0 PSBCK0 RISEL0 OFDSEL ERROR RESEL PLLACC GPIOS
Addr: Command address shaded parts DI15 command area reserved bits. Input must doing "0". Command addresses reserved testing purposes. Writing these addresses prohibited.
No.A1056-41/64
LC89058W-E
12.2.2 Details write commands address: 0xE8; Command address: System setting
DI15 TES
DI14
DI13
DI12
DI11
DI10
DOEN
SYSRST
SYSRST
System reset Don't reset (initial value) Reset circuits other than command registers output setting Output (initial value) Always high impedance state (read disabled) Test mode setting Normal operation (initial value) Enter test mode
DOEN
TES
When reset SYSRST performed, RBCK outputs BLRCK outputs "H."
address: 0xE8; Command address: System setting
DI15
DI14
DI13 FSLIM1
DI12 FSLIM0
DI11 RXMON
DI10 AOSEL
MOSEL
MOSEL
MOUT output contents setting Output channel status emphasis information (initial value) Output input data calculation results (output conditions given FSSEL[1:0].)
AUDIO output mode Only output channel status (initial value) Output channel status IEC61937 DTS-CD/LD detection flag
AOSEL
RXMON
Setting digital audio data (S/PDIF) input status monitoring Don't monitor S/PDIF input status (initial value). Monitor S/PDIF input status Setting sampling frequency reception range input digital signal limit (initial value) fs96kHz (when exceeded, data muted clock system output) fs48kHz (when exceeded, data muted clock system output) Reserved
FSLIM[1:0]
No.A1056-42/64
LC89058W-E
address: 0xE8; Command address: Master clock setting
DI15 AMPOPR1
DI14 AMPOPR0
DI13
DI12 PLLOPR
DI11 XMSEL1
DI10 XMSEL0
XINSEL
XINSEL
input frequency setting 12.288MHz (initial value) 24.576MHz XMCK output frequency setting input frequency (initial value) input frequency input frequency Muted (VCO) operation setting Operate (initial value) Stop Oscillation amplifier operation setting Permanent continuous operation (initial value) Reserved Automatic stopping oscillation amplifier while locked Stop
XMSEL [1:0]
PLLOPR
AMPOPR [1:0]
order replace LC89057W-VF4A-E, setting contents AMPOPR[1:0] different from those LC89057W-VF4A-E.
No.A1056-43/64
LC89058W-E
address: 0xE8; Command address: system output clock setting
DI15 XRLRCK1
DI14 XRLRCK0
DI13 XRBCK1
DI12 XRBCK0
DI11 XRSEL1
DI10 XRSEL0
PRSEL1
PRSEL0
PRSEL [1:0]
Setting RMCK output frequency while locked (enabled when PLLACC "0") (256fs) (initial value) (512fs) (128fs) Muted Setting RMCK output frequency during source input frequency (initial value) input frequency input frequency Muted Setting RBCK output frequency during source 3.072MHz output (RMCK6.144MHz) (initial value) 6.144MHz output (RMCK12.288MHz) 12.288MHz output (RMCK=24.576MHz) Muted Setting RLRCK output frequency during source 48kHz output (initial value) 96kHz output 192kHz output Muted
XRSEL [1:0]
XRBCK [1:0]
XRLRCK [1:0]
Don't setting which RMCK=3.072MHz output XRSEL [1:0]=10(1/4 output) setting when XIN=12.288MHz input because doesn't satisfy output setting condition RBCK SBCK. Setting XRBCK [1:0] relate setting RMCK output clock. RBCK output clock become less RMCK output clock source.
No.A1056-44/64
LC89058W-E
address: 0xE8; Command address: system output clock setting
DI15 XSLRCK1
DI14 XSLRCK0
DI13 XSBCK1
DI12 XSBCK0
DI11 PSLRCK1
DI10 PSLRCK0
PSBCK1
PSBCK0
PSBCK [1:0]
Setting SBCK frequency while locked 64fs output (initial value) 128fs output 32fs output 16fs output Setting SLRCK frequency while locked output (initial value) output fs/2 output fs/4 output Setting SBCK frequency during source 3.072MHz output (RMCK6.144MHz) (initial value) 6.144MHz output (RMCK12.288MHz) 12.288MHz output (RMCK=24.576MHz) Muted
PSLRCK [1:0]
XSBCK [1:0]
XSLRCK [1:0] SLRCK output frequency setting during source 48kHz output (initial value) 96kHz output 192kHz output Muted Setting XSBCK [1:0] relate setting RMCK output clock. SBCK output clock become less RMCK output clock source.
No.A1056-45/64
LC89058W-E
address: 0xE8; Command address: Clock source switching; RDATA output setting
DI15
DI14 RDTMUT
DI13 RDTSTA
DI12 RDTSEL
DI11
DI10
OCKSEL
OCKSEL
Clock source setting clock source while unlocked (initial value) clock source regardless status RDATA output setting while unlocked Output SDIN data while unlocked (initial value) Mute while unlocked RDATA output setting According RDTSEL (initial value) Output SDIN input data regardless status RDATA mute setting Output data selected with RDTSEL (initial value) Muted
RDTSEL
RDTSTA
RDTMUT
When oscillation amplifier permanent continuous operation mode with AMPOPR [1:0] changes reflected error flag with FSERR, OCKSEL switch clock source while maintaining RERR status. phase system clock system clock synchronize. input data SDIN, select clock synchronized with SDIN input data. source switched while maintaining locked status. However, since switching between clock data output independently; recommended select mute SDIN data output data when source switched. oscillation amplifier stop automatically when gets locked, source switching from locked status disables clock output. sure oscillation amplifier continuous operation mode when switching clock source source.
No.A1056-46/64
LC89058W-E
address: 0xE8; Command address: Data setting
DI15
DI14 ROSEL2
DI13 ROSEL1
DI12 ROSEL0
DI11
DI10 RISEL2
RISEL1
RISEL0
RISEL [2:0]
Data demodulation input setting 000: selection (initial value) 001: selection 010: selection 011: selection 100: selection 101: selection 110: selection 111: None selected (all inputs connected through pull-down resistors.) RXOUT1 output data setting 000: input data (initial value) 001: input data 010: input data 011: input data 100: input data 101: input data 110: input data 111: fixed output
ROSEL [2:0]
No.A1056-47/64
LC89058W-E
address; 0xE8; Command address: Data output format setting
DI15 SLRCKP
DI14 SBCKP
DI13 RLRCKP
DI12 RBCKP
DI11
DI10
OFDSEL
OFSEL
Audio data output format setting data output (initial value) bits, first, left-justification output RBCK output polarity setting Falling RDATA data change (initial value) Rising RDATA data change RLRCK output polarity setting period: L-channel data; period: R-channel data (initial value) period: R-channel data; period: L-channel data SBCK output polarity setting Falling RDATA data change (initial value) Rising RDATA data change SLRCK output polarity setting period: L-channel data; period: R-channel data (initial value) period: R-channel data; period: L-channel data
RBCKP
RLRCKP
SBCKP
SLRCKP
No.A1056-48/64
LC89058W-E
address: 0xE8; Command address: output contents setting
DI15 EMPF
DI14 GPIO
DI13 PCRNW
DI12 UNPCM
DI11 CSRNW
DI10 FSCHG
INDET
ERROR
ERROR
RERR signal output setting Don't output (initial value) Output RERR status change Input data detection output setting Don't output (initial value) Output input data status change Setting updated flag output lock frequency calculation result Don't output (initial value) Output updated flag lock frequency calculation result Output setting updated flag first 48-bit channel status data Don't output (initial value) Output update flag first 48-bit channel status data Output setting change flag non-PCM data detection Don't output (initial value) Output AUDIO status change Output setting updated flag burst preamble Don't output (initial value) Output updated flag burst preamble Input data updated flag output setting when general-purpose parallel input (GPIOS=0) Don't output (initial value) Output input data updated flag Output setting emphasis detection flag Don't output (initial value) Output emphasis detection flag
INDET
FSCHG
CSRNW
UNPCM
PCRNW
GPIO
EMPF
input data detection output setting functions when INDET=1 with clock 24.576MHz supplied terminal (XINSEL=1) digital data input state monitoring function (RXMON=1) made effective. channel status update flag compares first bits data previous block with those current block. these data identical, outputs flag, considering data been updated. burst preamble update flag also compares bits data previous block with those current data. they identical, update flag output. 4-bit input data updated flag when general-purpose parallel input set, output only when change occurred sampling data with clock 24kHz.
No.A1056-49/64
LC89058W-E
address: 0xE8, Command address: RERR output setting
DI15 ERWT1
DI14 ERWT0
DI13 FSERR
DI12 RESTA
DI11
DI10
REDER
RESEL
RESEL
RERR output contents setting lock error data error (initial value) lock error data error non-PCM data Setting parity error flag output within times Output only when non-PCM data recognized (initial value) Output only during sub-frame which error generated RERR output condition setting Output status time (Output status even during source) (initial status) Forcibly output error (Set RERR forcibly) Setting error flag output condition according change Reflect changes error flag (initial value) Don't reflect changes error flag Setting RERR wait time after locked Cancel error after preamble counted (initial value) Cancel error after preamble counted Cancel error after preamble counted Cancel error after preamble counted
REDER
RESTA
FSERR
ERWT [1:0]
Non-PCM data identical detection data output AUDIO. Output data muted error occurs non-PCM data with RESEL. RESTA setting reflected output pins data clock. FSERR, calculation result obtained while oscillation amplifier stopped reflected. this case, changes consist only channel status information. ERWT[1:0] defines interval time RERR output error cancellation ("L") after locked. Since demodulated audio data output after RERR cancels error, need change this setting situation that head data missing problem.
No.A1056-50/64
LC89058W-E
address: 0xE8; Command address: General-purpose function
DI15
DI14
DI13
DI12
DI11
DI10
Contents data output GPIO0 when general-purpose parallel output (initial value) Contents data output GPIO1 when general-purpose parallel output (initial value) Contents data output GPIO2 when general-purpose parallel output (initial value) Contents data output GPIO3 when general-purpose parallel output (initial value)
No.A1056-51/64
LC89058W-E
address: 0xE8; Command address: System settings
DI15
DI14
DI13 CKSTP
DI12 RMCKP
DI11
DI10 PLLDV1
PLLDV0
PLLACC
PLLACC
clock lock frequency setting Manual setting (initial value) Automatic control (see 10.1.6.) clock generated when 32kHz, 44.1kHz 48kHz received with PLLACC=1 512fs output (initial value) 256fs output clock generated when 88.2kHz 96kHz received with PLLAC=1 256fs output (initial value) 512fs output block RMCK output setting Normal output (initial value) Inverted output CKST output polarity setting Normal high output (initial value) Normal output
PLLDV0
PLLDV1
RMCKP
CKSTP
No.A1056-52/64
LC89058W-E
address: 0xE8; Command address: Data setting
DI15
DI14 RXSEL2
DI13 RXSEL1
DI12 RXSEL0
DI11 EDTMUT
DI10 EMCKP
EXTSEL
GPIOS
GPIOS
Setting pins input function (when pull-down set) General-purpose parallel input (initial value) Selector input RMCK, RBCK, RLRCK, RDATA output setting Output data clock function (initial value). Output input signals GPIO0, GPIO1, GPIO2, GPIO3 (GPIOS=1) GPIO0 output polarity setting (GPIOS=1) Normal output (Initial value) Inverted output GPIO3 mute setting (GPIOS=1) Normal output (initial value) Muted RXOUT2 output data setting 000: fixed output (initial value) 001: input data 010: input data 011: input data 100: input data 101: input data 110: input data 111: input data
EXTSEL
EMCKP
EDTMUT
RXSEL[2:0]
GPIOS setting needed when RMCK, RBCK, RLRCK, RDATA output changed with EXTSEL. RMCK, RBCK, RLRCK, RDATA output don't change even sets EXTSEL=1 state GPIOS=0.
No.A1056-53/64
LC89058W-E
address: 0xE8; Command address: clock
DI15 FSSEL1
DI14 FSSEL0
DI13
DI12
DI11 PTOXW1
DI10 PTOXW0
PTOXW[1:0]
Setting clock switch wait time Clock switching after 2.67ms from when lock status identified (initial value) Clock switching after 1.33ms from when lock status identified Clock switching after 0.67ms from when lock status identified Clock switching after when lock status identified MOUT output contents setting (output when unlock status when value other than those listed below calculated) Output when 32kHz/44.1kHz/48kHz calculated (Initial value) Output when 64kHz/88.2kHz/96kHz calculated Output when 128kHz/176.4kHz/192kHz calculated Output "H"when 64kHz/88.2kHz/96kHz higher calculated
FSSEL[1:0]
No.A1056-54/64
LC89058W-E
12.3 Read Data 12.3.1 List read commands possible read following items. Interrupt data output Monitor output digital data input status Input data output when general-purpose parallel input mode Output calculation result Output first bits channel status Output burst preamble data Table 12.4 Read Register
0xEA DO10 DO11 DO12 DO13 DO14 DO15 DO16 DO17 DO18 DO19 DO20 DO21 DO22 DO23 DO24 DO25 DO26 RXDET0 RXDET1 RXDET2 RXDET3 RXDET4 RXDET5 RXDET6 OERROR OINDET OFSCHG OCSRNW OUNPCM OPCRNW OGPIO OEMPF CSBIT1 IEC1937 DTS51 DTSES 0xEB FSC0 FSC1 FSC2 FSC3 0xEC bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit8 bit9 bit10 bit11 bit12 bit13 bit14 bit15 bit16 bit17 bit18 bit19 bit20 bit21 bit22 bit23 bit24 bit25 bit26 0xED bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit8 bit9 bit10 bit11 bit12 bit13 bit14 bit15
DO45 DO46 DO47
bit45 bit46 bit47
No.A1056-55/64
LC89058W-E
12.3.2 Read register 0xEA (S/PDIF input detection, interrupt flag) output address: 0xEA, Contents read register output
RXDET6 RXDET5 RXDET4 RXDET3 RXDET2 RXDET1 RXDET0
RXDET0
input detection input data Input data exist input detection input data Input data exist input detection input data Input data exist input detection input data Input data exist input detection input data Input data exist input detection input data Input data exist input detection input data Input data exist
RXDET1
RXDET2
RXDET3
RXDET4
RXDET5
RXDET6
readout RXDET[10:0], RXMON must beforehand.
No.A1056-56/64
LC89058W-E
address; 0xEA; Contents read register output
DO15 OEMPF DO14 OGPIO DO13 OPCRNW DO12 OUNPCM DO11 OCSRNW DO10 OFSCHG OINDET OERROR
OERROR
RERR output (Output status during readout) transfer error while locked Transfer error exists unlocked Status change data input (clear after readout) change status data input Change exists status data input Result updating input calculation (clear after readout) update input calculation Input calculation updated Update result first bits channel status (clear after readout) updated Updated
OINDET
OFSCHG
OCSRNW
OUNPCM
AUDIO output (output status during readout) Non-PCM signal detected Non-PCM signal detected Update result burst preamble (clear after readout) updated Updated Update result input date when general-purpose parallel input mode (GPIOS=0) (clear after readout) updated Updated Channel status emphasis detection (output status during readout) pre-emphasis 50/15s pre-emphasis exists
OPCRNW
OGPIO
OEMPF
Concerning OERROR OUNPCM, status RERR AUDIO that subject RESEL setting read regardless INToutput setting.
No.A1056-57/64
LC89058W-E
address: 0xEA; Contents read register output
DO23 DO22 DO21 DO20 DO19 DTSES DO18 DTS51 DO17 IEC1937 DO16 CSBIT1
CSBIT1
Channel status detection Non-PCM IEC61937 burst preamble detection detected detected DTS-CD/LD channel sync signal detection DTS-CD/LD sync signal detected DTS-CD/LD sync signal detected ES-CD/LD channel sync signal detection ES-CD/LD sync signal detected ES-CD/LD sync signal detected
IEC1937
DTS51
DTSES
No.A1056-58/64
LC89058W-E
12.3.3 Read register 0xEB (General-purpose parallel input contents, calculation results) output address: 0xEB, Contents read register output
FSC3 FSC2 FSC1 FSC0
Contents input GPIO0 when general-purpose parallel input mode (GPIOS=0). Contents input GPIO1 when general-purpose parallel input mode (GPIOS=0). Contents input GPIO2 when general-purpose parallel input mode (GPIOS=0). Contents input GPIO3 when general-purpose parallel input mode (GPIOS=0). Input data calculation result "xxxx": code table.
[3:0]
Table 12.5 Code Table Input Calculation Result 25°C, AVDD DVDD
FSC3 FSC2 FSC1 FSC0 Target Frequency range 32kHz 44.1kHz 48kHz 64kHz 88.2kHz 96kHz 128kHz 176.4kHz 192kHz
No.A1056-59/64
LC89058W-E
12.3.4 Read register 0xEC (Readout first bits channel status) output first 48bits channel status read. readout channel status data output with first. readout, address 0xEC. channel status data cannot updated after address set. relation between read registers channel status data shown below. Table 12.6 Read Registers First bits Channel Status
Register DO10 DO11 DO12 DO13 DO14 DO15 DO16 DO17 DO18 DO19 DO20 DO21 DO22 DO23 Channel number Source number Category code defined Contents Application Control Register DO24 DO25 DO26 DO27 DO28 DO29 DO30 DO31 DO32 DO33 DO34 DO35 DO36 DO37 DO38 DO39 DO40 DO41 DO42 DO43 DO44 DO45 DO46 DO47 defined Word length defined Clock accuracy Contents Sampling frequency
No.A1056-60/64
LC89058W-E
12.3.5 Read register 0xED (Burst preamble data) output burst preamble data read with demodulation function. bit-data burst preamble output with first. readout, address OxED. relation between read register burst preamble data shown below. Table 12.7 Burst Preamble Read Registers
Register DO10 DO11 DO12 DO13 DO14 DO15 stream number Error Data type dependent Information Reserved Contents Data type
No.A1056-61/64
LC89058W-E
12.3.6 Burst Preamble Field burst preamble field shown below. latest information, refer official specifications. Table 12.8 Burst Preamble Field
Register Value DO6, DO12 DO15 NULL data Dolby AC-3 data Reserved Pause MPEG-1, layer data MPEG-1, layer data, non-extended MPEG-2 Extended MPEG-2 data Reserved MPEG-2, layer sampling rate MPEG-2, layer sampling rate Reserved type1 type2 type3 ATRAC ATRACK2/3 Reserved Reserved (MPEG-4, data) MPEG-2, data Reserved Reserved (set "0") Error flag indicating effective burst payload Error flag indicating burst payload error Data type dependent information stream number. (set "0") Contents
No.A1056-62/64
LC89058W-E
Application Example
12.288MHz 24.576MHz Chip address Chip address Master/Slave Expand/Selector
RERR CKST AUDIO MOUT DGND DVDD
M-computer
HDMI
XMODE DGND DVDD GPIO0 GPIO1 GPIO2 GPIO3 RXOUT2
DGND
XOUT XMCK DVDD
LC89058W-E
SQFP48 (9X9)
SDIN SLRCK SBCK RDATA RLRCK DVDD DGND RBCK RMCK AGND AVDD
Coaxial Input
Optical Input
Element Symbol
Recommended Parameter 0.1F 33pF 0.1F 0.01F
RXOUT1 DGND DVDD DVDD DGND
Table 13.1 Application Example
Application Power supply de-coupling Function setting Quarts resonator load Oscillation amplifier feedback Oscillation amplifier current limit Coaxial input Coaxial input termination loop filter loop filter loop filter Section 10.1.1) Section 10.1.1) Section 10.1.1) Ceramic capacitor Remarks Ceramic capacitor Pull-down/pull-up resistor Ceramic capacitor with characteristics
No.A1056-63/64
LC89058W-E
SANYO Semiconductor Co.,Ltd. assumes responsibility equipment failures that result from using products values that exceed, even momentarily, rated values (such maximum ratings, operating condition ranges, other parameters) listed products specifications SANYO Semiconductor Co.,Ltd. products described contained herein. SANYO Semiconductor Co.,Ltd. strives supply high-quality high-reliability products, however, semiconductor products fail malfunction with some probability. possible that these probabilistic failures malfunction could give rise accidents events that could endanger human lives, trouble that could give rise smoke fire, accidents that could cause damage other property. When designing equipment, adopt safety measures that these kinds accidents events cannot occur. Such measures include limited protective circuits error prevention circuits safe design, redundant design, structural design. event that SANYO Semiconductor Co.,Ltd. products described contained herein controlled under applicable local export control laws regulations, such products require export license from authorities concerned accordance with above law. part this publication reproduced transmitted form means, electronic mechanical, including photocopying recording, information storage retrieval system, otherwise, without prior written consent SANYO Semiconductor Co.,Ltd. information described contained herein subject change without notice product/technology improvement, etc. When designing equipment, refer "Delivery Specification" SANYO Semiconductor Co.,Ltd. product that intend use. Information (including circuit diagrams circuit parameters) herein example only; guaranteed volume production. Upon using technical information products described herein, neither warranty license shall granted with regard intellectual property rights other rights SANYO Semiconductor Co.,Ltd. third party. SANYO Semiconductor Co.,Ltd. shall liable claim suits with regard third party's intellectual property rights which resulted from technical information products mentioned above.
This catalog provides information April, 2009. Specifications information herein subject change without notice.
No.A1056-64/64

LC89058W-E Overview Digital Audio Interface Receiver LC

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