LC87F6D64A CMOS FROM byte, 2048 byte on-chip 8-bit 1-chip Mi

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LC87F6D64A CMOS FROM byte, 2048 byte on-chip 8-bit 1-chip Mi

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Ordering number ENA1007
LC87F6D64A
CMOS FROM byte, 2048 byte on-chip
8-bit 1-chip Microcontroller
SANYO LC87F6D64A 8-bit microcomputer with following on-chip functional blocks: CPU: operable minimum cycle time 100ns 64K-byte flash (re-writeable board/On-chip debugger) On-chip RAM: 2048 byte automatic display controller/driver 16-bit timer/counter (can divided into 8-bit timers) 8-bit timer with prescaler timer date/time clock Day-Minute-Second Counter (DMSC) System clock divider function Synchronous serial port (with automatic block transmit /receive function) Asynchronous/synchronous serial port Remote control receive function converter 14-source 10-vectored interrupt system above functions fabricated single chip.
Features
Flash Single power supply, writeable on-board. Block erase byte units 65536 bits 2048 bits
This product licensed from Silicon Storage Technology, Inc. (USA), manufactured sold SANYO Semiconductor Co., Ltd.
SANYO Semiconductor Co.,Ltd. products described contained herein are, with regard "standard application", intended general electronics equipment (home appliances, equipment, communication device, office equipment, industrial equipment etc.). products mentioned herein shall intended "special application" (medical equipment whose purpose sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level reliability directly threaten human lives case failure malfunction product cause harm human bodies, shall they grant guarantee thereof. should intend products applications outside standard applications customer considering such and/or outside scope intended standard applications, please consult with prior intended use. there consultation inquiry before intended use, customer shall solely responsible use. Specifications SANYO Semiconductor Co.,Ltd. products described contained herein stipulate performance, characteristics, functions described products independent state, guarantees performance, characteristics, functions described products mounted customer' products equipment. verify symptoms states that cannot evaluated independent device, customer should always evaluate test devices mounted customer' products equipment.
Ver.1.21
30508HKIM 20071127-S00004 No.A1007-1/19
LC87F6D64A
Minimum Cycle Time 100ns (10MHz) VDD=3.0 5.5V 150ns (4MHz) VDD=2.5 5.5V Note: cycle time indicates read time. Minimum Instruction Cycle Time (tCYC) 300ns (10MHz) VDD=3.0 5.5V 750ns (4MHz) VDD=2.5 5.5V Ports Input/output ports Data direction programmable each individually: (P1n, P7n) Data direction programmable nibble units: (P0n) (When N-channel open drain output selected, data input units.) output ports Large current outputs digits: (S0/T0 S8/T8) Large current outputs digits/segments: (S9/T9 S15/T15) Digit/segment outputs: (S16 S23) Segment outputs: (S24 S53) Oscillator pins: (CF1/XT1, CF2/XT2) Reset pin: (RES) Power supply: (VSS1, VDD1 VDD3) power supply: (VP) Automatic Display Controller Programmable segment/digit output pattern Output switched between digit/segment waveform output (pins used output digit waveforms). parallel-drive available large current VFD. 16-step dimmer function available Timers Timer 16-bit timer/counter with capture register Mode channel 8-bit timer with programmable 8-bit prescaler 8-bit capture register Mode 8-bit timer with 8-bit programmable prescaler 8-bit capture register 8-bit counter with 8-bit capture register Mode 16-bit timer with 8-bit programmable prescaler 16-bit capture register Mode 16-bit counter with 16-bit capture register Timer 8-bit timer with 6-bit prescaler Timer 8-bit timer with 6-bit prescaler Base Timer clock signal selected from following. Sub-clock (32.768kHz crystal oscillator), system clock, prescaler output from timer Interrupts selected occur five different times. time counter Using with base timer, used 65000 minute second counter. 8-bit synchronous serial interface first /MSB first function available Internal 8-bit baud-rate generator (maximum transmit clock period tCYC) Consecutive automatic data communication bits (communication available each bit) (stop reopening available each byte)) 8-bit asynchronous/synchronous serial interface Mode Synchronous 8-bit serial (2-wire 3-wire, transmit clock tCYC) Mode Asynchronous serial (half duplex, data bits, stop bit, baud rate 2048 tCYC) Mode mode (start bit, data bits, transmit clock tCYC) Mode mode (start detection, data bits, stop detection)
No.A1007-2/19
LC87F6D64A
Converter: bits channels Remote Control Receiver Circuit (sharing pins with P70/INT0/RMIN) Noise rejection function (Units noise rejection filter: about 120s, when selecting 32.768kHz crystal oscillator clock.) Supporting reception formats with guide-pulse half-clock/clock/none. Determines reception detecting no-signal periods carrier). (Supports same reception format with different length.) X'tal HOLD mode release function Watchdog Timer watching timer period using external Watchdog timer produce interrupt, system reset. Clock Output Function Able output selected oscillation clock 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 system clock. Able output oscillation clock clock. Interrupts: sources, vector interrupts Three priority (low, high highest) multiple interrupts supported. During interrupt handling, equal lower priority interrupt request refused. interrupt requests more vector addresses occur once, higher priority interrupt takes precedence. case equal priority levels, vector with lowest address takes precedence.
Vector 00003H 0000BH 00013H 0001BH 00023H 0002BH 00033H 0003BH 00043H 0004BH Selectable Level SIO0 SIO1 Port0/T4/T5 INT0 INT1 INT2/T0L/remote control receiver INT3/Base timer Interrupt Signal
Priority Level: X>H>L equal priority levels, vector with lowest address takes precedence. Subroutine Stack Levels: 1024 levels maximum (Stack located RAM.) High-speed Multiplication/Division Instructions bits bits tCYC execution time) bits bits tCYC execution time) bits bits tCYC execution time) bits bits tCYC execution time) Oscillation Circuits On-chip oscillation circuit system clock use. On-chip oscillation circuit* system clock use. built On-chip Crystal oscillation circuit* speed system clock use. built Frequency variable oscillation circuit (internal) system clock. Adjustable (typ) step from selected center frequency. Measures oscillation clock using input signal from reference. oscillation terminal crystal oscillation terminal cannot used same time because commonness.
No.A1007-3/19
LC87F6D64A
System Clock Divider Function Able reduce current consumption Available minimum instruction cycle time: 300ns, 600ns, 1.2s, 2.4s, 4.8s, 9.6s, 19.2s, 38.4s, 76.8s. (Using 10MHz main clock) Standby Function HALT mode HALT mode used reduce power consumption. Program execution stopped. Peripheral circuits still operate display some serial transfer operations stop. Oscillation circuits stopped automatically. Release occurs system reset interrupt. HOLD mode HOLD mode used reduce power consumption. Both program execution peripheral circuits stopped. X'tal frequency variable oscillators automatically stop operation. Release occurs following conditions. input reset goes "Low" specified level input least INT0, INT1, INT2 interrupt condition arises port X'tal HOLD mode. X'tal HOLD mode used reduce power consumption. Program execution stopped. peripheral circuits except base-timer stopped. frequency variable oscillation circuits stop automatically. Crystal oscillator maintained state HOLD mode inception. Release occurs following conditions. input reset goes "Low" Setting least INT0, INT1 INT2 pins specified level Having interrupt source established port Having interrupt source established base timer circuit Having interrupt source established remote control receiver circuit On-chip Debugger Supports software debugging with mounted target board. Package Form Lead-free type Development Tools On-chip debugger: TCB87- type-B LC87F6D64A
No.A1007-4/19
LC87F6D64A
Package Dimensions
unit (typ) 3255
17.2
(0.83) 0.65 0.25
0.15
3.0max
(2.7)
SANYO QFP80(14X14)
Assignment
VDD3 P10/SO0 P11/SI0/SB0 P12/SCK0
14.0 17.2
14.0
P13/SO1 P14/SI1/SB1 P15/SCK1 P16/INT2/T0IN P17/INT3/T0IN VSS1 CF1/XT1 CF2/XT2 VDD1 P00/AN0 P01/AN1 P02/AN2 P03/AN3 P04/AN4 P05/AN5 P06/AN6 P07/AN7 P70/INT0/T0LCP/RMIN INT1/T0HCP
LC87F6D64A
VDD2 S15/T15 S14/T14 S13/T13 S12/T12 S11/T11 S10/T10 S9/T9 S8/T8 S7/T7 S6/T6 S5/T5 S4/T4 S3/T3 S2/T2 S1/T1 S0/T0
view
SANYO: "Lead-free Type"
No.A1007-5/19
LC87F6D64A
System Block Diagram
Interrupt control
Standby control
Flash
VMRC
Clock generator
X'tal
SIO0
interface
SIO1
Port
register
Port
register
Timer
Base timer
Remote control receiver circuit
Controller
DMSC
Timer
INT0 Noise Rejection Filter
Timer
Stack pointer
Watchdog timer
On-chip debugger
No.A1007-6/19
LC87F6D64A
Description
name VSS1 VDD1 VDD2 VDD3 PORT0 Power supply Power supply Function Option
Power supply 8bit input/output port Data direction programmable nibble units pull-up resistor specified nibble units Input HOLD release Input port interrupt Other functions P04: clock output (system clock/can selected from clock) On-chip debugger pins: DBGP0 DBGP2 (P05 P07)
PORT1
8bit input/output port Data direction programmable each pull-up resistor specified each Other functions P10: SIO0 data output P11: SIO0 data input/bus input/output P12: SIO0 clock input/output P13: SIO1 data output P14: SIO1 data input/bus input/output P15: SIO1 clock input/output P16: INT2 P17: INT3/Buzzer output following types interrupt detection possible: Rising INT2 INT3 enable enable Falling enable enable Rising/ Falling enable enable level disable disable level disable disable
PORT7
2bit input/output port Data direction specified each pull-up resistor specified each Other functions P70: INT0 input/HOLD release input/Timer capture input/ output watchdog timer/Remote control receiver input P71: INT1 input/HOLD release input/Timer capture input following types interrupt detection possible: Rising INT0 INT1 enable enable Falling enable enable Rising/ Falling disable disable level enable enable level enable enable
S0/T0 S8/T8 S9/T9 S15/T15 CF1/XT1
Large current output display controller digit (can used segment) Large current output display controller segment/digit Output display controller segment Reset terminal <ceramic oscillator selected> Input terminal ceramic oscillator crystal oscillator selected> Input 32.768kHz crystal oscillation When use, connect VDD1.
CF2/XT2
<ceramic oscillator selected> Output terminal ceramic oscillator crystal oscillator selected> Output 32.768kHz crystal oscillation When use, oscillation mode leave open circuit.
No.A1007-7/19
LC87F6D64A
Port Output Types
Output configuration pull-up/pull-down resistor options shown following table. Input/output possible even when port output mode.
Terminal (Note each Option Selected Units each Options S0/T0 S15/T15 None None None CMOS Nch-open drain CMOS Nch-open drain Nch-open drain CMOS High voltage Pch-open drain Output Format Pull-up Resistor Programmable Programmable Programmable Programmable Programmable Programmable Pull-down Resistor Fixed
Note Programmable pull-up resisters Port attached nibble units (P00 P03, P07). Note: Connect follows reduce noise increase back-up time. VSS1 must connected together grounded.
VDD1 Power supply
Back-up capacitors
VDD2 VDD3
powers
VSS1
No.A1007-8/19
LC87F6D64A
Absolute Maximum Ratings 25°C, VSS1
Parameter Supply voltage Input voltage Symbol VI(1) VI(2) Output voltage VO(1) VO(2) Input/Output voltage Peak output current IOPH(2) IOPH(3) IOPH(4) Average output current IOMH(2) High level output current IOMH(3) IOMH(4) Total output current IOAH(1) IOAH(2) IOAH(3) IOAH(4) IOAH(5) IOAH(6) IOAH(7) IOAH(8) IOAH(9) IOAH(10) IOAH(11) Peak output level output current current Total output current Total output current IOPL(1) IOPL(2) IPML(1) IOML(2) IOAL(1) IOAL(2) IOAL(3) IOAL(4) Maximum power dissipation Operating temperature range Storage temperature range Tstg +125 Topr Port S0/T0 S15/T15 Port Port Ports Port S0/T0 S15/T15 S0/T0 S15/T15 Ports Port Ports Port Port Port Port Ports Total pins Total pins Total pins Total pins Current each Current each Current each Current each Total pins Total pins Total pins Total pins Ta=-40 +85°C IOMH(1) Port S0/T0 S15/T15 Ports IOPH(1) Ports CMOS output selected Current each Current each Current each Current each CMOS output selected Current each Current each Current each Current each Total pins Total pins Total pins Total pins Total pins Total pins Total pins VIO(1) Pin/Remarks VDD1, VDD2, VDD3 CF1/XT1, S0/T0 S15/T15 CF2/XT2 Ports Conditions VDD[V] VDD1=VDD2=VDD3 -0.3 -0.3 VDD-45 VDD-45 -0.3 -0.3 -7.5 Specification +6.5 VDD+0.3 VDD+0.3 VDD+0.3 VDD+0.3 VDD+0.3 unit
No.A1007-9/19
LC87F6D64A
Allowable Operating Conditions -40°C +85°C, VSS1
Specification Parameter Operating supply voltage range (Note 2-1) Hold voltage Pull-down supply voltage Input high voltage VIH(2) VIH(3) Input voltage VIL(1) Port Watchdog timer XT1/CF1, Ports Port Port port input/interrupt VIL(2) VIL(3) Operation cycle time External system clock frequency FEXCF(1) open circuit system clock divider external clock DUTY=50±5% open circuit system clock divider external clock DUTY=50±5% Oscillation stabilizing time period (Note 2-2) FmCF(2) CF1, FmCF(1) CF1, 10MHz ceramic resonator oscillation Refer figure 4MHz ceramic resonator oscillation Refer figure FmRC FmVMRC FsX'tal XT1, oscillation Frequency variable oscillation circuit 32.768kHz crystal resonator oscillation Refer figure 32.768 tCYC Port Watchdog timer XT1/CF1, Output disable 0.300 0.735 0.8VDD -1.0 0.25VDD Output disable 0.1VDD +0.4 Output disable VIH(1) Ports Output disable VDD1 register data kept HOLD mode. 0.3VDD +0.7 0.9VDD 0.75VDD Symbol VDD(1) VDD(2) Pin/Remarks VDD1=VDD2=VDD3 Conditions VDD[V] 0.300stCYC200s 0.735stCYC200s unit
Note 2-1: Re-writeable board VDD4.5V. Note 2-2: oscillation constant shown table table oscillation terminal crystal oscillation terminal cannot used same time because commonness.
No.A1007-10/19
LC87F6D64A
Electrical Characteristics -40°C +85°C, VSS1
Parameter Input high current Symbol IIH(1) Pin/Remarks Ports Conditions VDD[V] Output disable Pull-up resister OFF. VIN=VDD (including state leak current output Tr.) IIH(2) IIH(3) Input current IIL(1) CF1/XT1 Ports VIN=VDD VIN=VDD Output disable Pull-up resister OFF. VIN=VSS (including state leak current output Tr.) IIL(2) IIL(3) Output high voltage VOH(1) VOH(2) VOH(3) VOH(4) VOH(5) VOH(6) VOH(7) CF1/XT1 Port CMOS output option Ports Port S0/T0 S15/T15 VIN=VSS VIN=VSS IOH=-1.0mA IOH=-0.5mA IOH=-0.1mA IOH=-0.4mA IOH=-20.0mA IOH=-10.0mA IOH=-1.0mA single over 1mA. VOH(8) VOH(9) VOH(10) IOH=-5.0mA IOH=-2.5mA IOH=-1.0mA single over 1mA. Output voltage VOL(1) VOL(2) VOL(3) VOL(4) Pull-up resistor Port Ports Ports IOL=10mA IOL=5mA IOL=1.6mA IOL=1mA VOH=0.9VDD Output P-ch VOUT=VSS Output P-ch VOUT=VDD-40V Pull-down resistor S0/T0 S15/T15 Hysteresis voltage capacitance VHYS(1) Ports pins f=1MHz other terminals connected VSS. Ta=25°C Output P-ch VOUT=3V Vp=-30V 0.1VDD Output off-leak current IOFF(2) IOFF(1) S0/T0 S15/T15, VDD-1 VDD-1.8 VDD-1.8 VDD-1 VDD-1 VDD-1 VDD-0.5 VDD-1 VDD-1.8 VDD-1.8 Specification unit
No.A1007-11/19
LC87F6D64A
Serial Characteristics -40°C +85°C, VSS1
SIO0 Serial Characteristics (Note 4-1-1)
Parameter Frequency level Input clock pulse width High level pulse width tSCKHA(1) Continuous data transmission/reception mode Serial clock Fig. (Note 4-1-2) Frequency level Output clock pulse width High level pulse width tSCKHA(2) Continuous data transmission/reception mode CMOS output selected Fig. Data setup time Serial input tsDI(1) SB0(P11), SI0(P11) Data hold time thDI(1) Output delay Input clock time tdD0(2) tdD0(1) SO0(P10), SB0(P11) Continuous data transmission/reception mode (Note 4-1-3) Synchronous 8-bit mode (Note 4-1-3) tdD0(3) Output clock (Note 4-1-3) (1/3)tCYC +0.05 0.03 Must specified with respect rising edge SIOCLK. Fig. 0.03 tSCKH(2) +2tCYC tSCKH(2) tSCK(2) tSCKL(2) SCK0(P12) CMOS output selected Fig. tSCK tSCKH(2) +(10/3) tCYC tCYC tSCKH(1) Symbol tSCK(1) tSCKL(1) Pin/ Remarks SCK0(P12) Fig. Conditions VDD[V] tCYC Specification unit
(1/3)tCYC +0.05 1tCYC +0.05
Serial output
Note 4-1-1: These specifications theoretical values. margin depending use. Note 4-1-2: serial-clock-input continuous trans/rec mode, time from SI0RUN being when serial clock first negative edge serial clock must longer than tSCKHA. Note 4-1-3: Must specified with respect falling edge SIOCLK. Must specified time beginning output state change open drain output mode. Fig.
No.A1007-12/19
LC87F6D64A
SIO1 Serial Characteristics (Note 4-2-1)
Parameter Frequency Input clock level pulse width High level pulse width Frequency Output clock level pulse width High level pulse width Data setup time Serial input tsDI(2) SB1(P14), SI1(P14) Data hold time thDI(2) Must specified with respect rising edge SIOCLK. Fig. Output delay time Serial output tdD0(4) SO1(P13), SB1(P14) Must specified with respect falling edge SIOCLK. Must specified time beginning output state change open drain output mode. Fig. (1/3)tCYC +0.05 0.03 0.03 tSCKH(4) tSCK(4) tSCKL(4) SCK1(P15) CMOS output selected Fig. tSCKH(3) Symbol tSCK(3) tSCKL(3) Pin/ Remarks SCK1(P15) Conditions VDD[V] Fig. tCYC tSCK Specification unit
Serial clock
Note 4-2-1: These specifications theoretical values. margin depending use.
Pulse Input Conditions -40°C +85°C, VSS1
Parameter High/low level pulse width Symbol tPIH(1) tPIL(1) tPIH(2) tPIL(2) tPIH(3) tPIL(3) tPIH(4) tPIL(4) tPIL(5) Pin/Remarks INT0(P70), INT1(P71), INT2(P16) INT3(P17) (Noise rejection ratio 1/1.) INT3(P17) (Noise rejection ratio 1/32.) INT3(P17) (Noise rejection ratio 1/128.) Reset possible Interrupt acceptable Events timer input. Interrupt acceptable Events timer input. Interrupt acceptable Events timer input. tCYC Conditions VDD[V] Interrupt acceptable Events timer input. Specification unit
No.A1007-13/19
LC87F6D64A
Converter Characteristics -40°C +85°C, VSS1
Parameter Resolution Absolute precision Conversion time tCAD conversion (ADCR2=0) (Note 6-2) conversion (ADCR2=1) (Note 6-2) Analog input voltage range Analog port input current IAINH IAINL VAIN=VDD VAIN=VSS VAIN Symbol Pin/Remarks AN0(P00) AN7(P07) (Note 6-1) Conditions VDD[V] 15.62 (tCYC= 0.488s) 23.52 (tCYC= 0.735s) 18.82 (tCYC= 0.294s) 47.04 (tCYC= 0.735s) Specification ±1.5 97.92 (tCYC= 3.06s) 97.92 (tCYC= 3.06s) 97.92 (tCYC= 1.53s) 97.92 (tCYC= 1.53s) unit
Note 6-1: Absolute precision including quantizing error (±1/2 LSB). Note 6-2: Conversion time means time from executing conversion instruction loading complete digital value register.
Consumption Current Characteristics -40°C +85°C, VSS1
Parameter Current dissipation during basic operation (Note 7-1) IDDOP(2) Symbol IDDOP(1) Pin/ Remarks VDD1 =VDD2 =VDD3 Conditions VDD[V] FmCF=10Hz ceramic resonator oscillation System clock: 10MHz Internal oscillation stopped. frequency division ratio CF1=15MHz external clock System clock: oscillation Internal oscillation stopped. frequency division ratio IDDOP(3) FmCF=4MHz ceramic resonator oscillation System clock: 4MHz Internal oscillation stopped. frequency division ratio IDDOP(4) FmCF=0Hz oscillation) System clock: oscillation Divider IDDOP(5) FsX'tal=32.768kHz crystal oscillation System clock: 32.768KHz Internal oscillation stopped. frequency division ratio 0.53 0.72 Specification unit
10.5
Note 7-1: currents output transistors pull-up transistors ignored.
Continued next page.
No.A1007-14/19
LC87F6D64A
Continued from preceding page.
Parameter Current dissipation HALT mode (Note 7-1) Symbol IDDHALT(1) Pin/ Remarks VDD1 =VDD2 =VDD3 HALT mode FmCF=10MHz Ceramic resonator oscillation System clock 10MHz Internal oscillation stopped. Divider: IDDHALT(2) HALT mode CF1=15MHz external clock System clock oscillation Internal oscillation stopped. Divider IDDHALT(3) HALT mode FmCF=4MHz Ceramic resonator oscillation System clock 4MHz Internal oscillation stopped. Divider: IDDHALT(4) HALT mode FmCF=0Hz (When oscillation stops.) System clock oscillation Divider: IDDHALT(5) HALT mode FsX'tal=32.768kHz crystal oscillation Internal oscillation stopped. System clock 32.768kHz Divider: Current dissipation HOLD mode Current dissipation Date/time clock HOLD mode IDDHOLD(2) VDD1 IDDHOLD(1) VDD1 HOLD mode CF1=VDD open circuit (when using external clock) Date/time clock HOLD mode CF1=VDD open circuit (when using external clock) FsX'tal=32.768kHz crystal oscillation 0.10 0.02 1600 1100 12.5 Conditions VDD[V] Specification unit
Note 7-1: currents output transistors pull-up transistors ignored.
F-ROM Programming Characteristics +10°C +55°C, VSS1
Parameter On-board writing current Writing time tFW(1) tFW(2) Symbol IDDFW(1) Pin/ Remarks VDD1 Conditions VDD[V] current dissipation microcomputer excluded. Erase time Writing time Specification unit
No.A1007-15/19
LC87F6D64A
Characteristics Sample Main System Clock Oscillation Circuit
characteristics table bellow based following conditions: standard evaluation board SANYO provided. peripheral parts with indicated value externally. peripheral parts value recommended value oscillator manufacturer. Table Characteristics Sample Main System Clock Oscillator Circuit with Ceramic Oscillator
Circuit Parameters Frequency Manufacturer Oscillator [pF] 10MHz MURATA CSTCE10M0G52-R0 CSTLS10M0G53-B0 4MHz MURATA CSTCR4M00G53-R0 CSTLS4M00G53-B0 [pF] 2.2k 2.2k Operating Supply Voltage Range Oscillation Stabilizing Time [ms] 0.029 0.028 0.034 0.030 [ms] Notes
oscillation stabilizing time period until oscillation becomes stable after becomes higher than minimum operating voltage. (Refer Figure
Characteristics Sample Subsystem Clock Oscillator Circuit
characteristics table bellow based following conditions: standard evaluation board SANYO provided. peripheral parts with indicated value externally. peripheral parts value recommended value oscillator manufacturer Table Characteristics Sample Subsystem Clock Oscillator Circuit with Crystal Oscillator
Circuit Parameters Frequency Manufacturer Oscillator [pF] [pF] Operating Supply Voltage Range Oscillation Stabilizing Time Notes
oscillation stabilizing time period until oscillation becomes stable after executing instruction which starts sub-clock oscillation after releasing HOLD mode. (Refer Figure Notes: Since circuit pattern affects oscillation frequency, place oscillation-related parts close oscillation pins possible with shortest possible pattern length.
X'tal
Figure Ceramic Oscillation Circuit
Figure Crystal Oscillation Circuit
0.5VDD
Figure Timing Measurement Point
No.A1007-16/19
LC87F6D64A
limit Power supply Reset time
Internal oscillation tmsCF
CF1, tmsX'tal
XT1,
Operating mode
Unfixed
Reset
Instruction execution
Reset Time Oscillation Stabilization Time
HOLD release signal
Witout HOLD release signal
HOLD reset signal VALID
Internal oscillation tmsCF
CF1,CF2 tmsX'tal
XT1,
Operating mode
HOLD
HALT
HOLD Reset Signal Oscillation Stabilization Time Figure Oscillation Stabilization Time
No.A1007-17/19
LC87F6D64A
RRES
Note: CRES, RRES values such that reset time exceeds 200s.
CRES
Figure Reset Circuit
SIOCLK:
DATAIN:
DATAOUT:
Data transmission period (only SIO0)
tSCK tSCKL SIOCLK: tsDI DATAIN: tdDO DATAOUT: Data transmission period (only SIO0) tSCKL SIOCLK: tsDI DATAIN: tdDO DATAOUT: thDI tSCKHA thDI tSCKH
Figure Serial Waveform
tPIL
tPIH
Figure Pulse Input Timing Signal Waveform
No.A1007-18/19
LC87F6D64A
SANYO Semiconductor Co.,Ltd. assumes responsibility equipment failures that result from using products values that exceed, even momentarily, rated values (such maximum ratings, operating condition ranges, other parameters) listed products specifications SANYO Semiconductor Co.,Ltd. products described contained herein. SANYO Semiconductor Co.,Ltd. strives supply high-quality high-reliability products, however, semiconductor products fail malfunction with some probability. possible that these probabilistic failures malfunction could give rise accidents events that could endanger human lives, trouble that could give rise smoke fire, accidents that could cause damage other property. When designing equipment, adopt safety measures that these kinds accidents events cannot occur. Such measures include limited protective circuits error prevention circuits safe design, redundant design, structural design. event that SANYO Semiconductor Co.,Ltd. products described contained herein controlled under applicable local export control laws regulations, such products require export license from authorities concerned accordance with above law. part this publication reproduced transmitted form means, electronic mechanical, including photocopying recording, information storage retrieval system, otherwise, without prior written consent SANYO Semiconductor Co.,Ltd. information described contained herein subject change without notice product/technology improvement, etc. When designing equipment, refer "Delivery Specification" SANYO Semiconductor Co.,Ltd. product that intend use. Information (including circuit diagrams circuit parameters) herein example only; guaranteed volume production. Upon using technical information products described herein, neither warranty license shall granted with regard intellectual property rights other rights SANYO Semiconductor Co.,Ltd. third party. SANYO Semiconductor Co.,Ltd. shall liable claim suits with regard third party's intellectual property rights which resulted from technical information products mentioned above.
This catalog provides information December, 2007. Specifications information herein subject change without notice.
No.A1007-19/19

LC87F6D64A CMOS FROM byte, 2048 byte on-chip 8-bit 1-chip Mi

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