LC78622NE Compact Disc Player Overview LC78622NE CMOS t
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Ordering number EN6015
LC78622NE
Compact Disc Player
Overview
LC78622NE CMOS that implements signal processing servo control required compact disc players. same time providing circuit, 1-bit converter, analog low-pass filter LC78622NE realizes optimal costperformance tradeoff low-end players strictly limiting functionality basic signal-processing servo system functionality. LC78622NE signal-processing system provides demodulation signal from pickup, de-interleaving, error detection correction, digital filters that prove useful reducing cost products. LC78622NE servo control system processes servo commands sent from control microprocessor. LC78622NE improved version LC78622E that adds oversampling digital filters, three generalpurpose output ports (that also have specific shared functions) PCCL (pin 34). However, some handling general-purpose ports differ from that LC78622E, therefore care must taken.(Refer pages 21).
Functions
Input signal processing: LC78622NE takes signal input, digitizes (slices) that signal precise level, converts that signal signal, generates clock with average frequency 4.3218 comparing phases that signal internal VCO. Precise reference clock necessary internal timing generation using external 16.9344 crystal oscillator Disk motor speed control using frame phase difference
signal generated from playback clock reference clock Frame synchronization signal detection, protection interpolation assure stable data readout signal demodulation conversion 8-bit symbol data Subcode data separation from demodulated signal output that data external microprocessor Subcode signal output microprocessor over serial interface after performing error check (LSB first) Demodulated signal buffering internal handle frames disk rotational jitter Demodulated signal reordering prescribed order data unscrambling de-interleaving Error detection, correction, flag processing (error correction scheme: dual plus dual correction) Sets flags based flags check, then performs signal interpolation muting depending flags. interpolation circuit uses dual-interpolation scheme. previous value held flags indicate errors more times consecutively. Support command input from control microprocessor: commands include track jump, focus start, disk motor start/stop, muting on/off track count serial input) Built-in digital output circuits. Arbitrary track counting support high-speed data access converter outputs with data continuity improved oversampling digital filters. Built-in third-order converters analog lowpass filter built in.)
SANYO products described contained herein have specifications that handle applications that require extremely high levels reliability, such life-support systems, aircraft's control systems, other applications whose failure reasonably expected result serious physical and/or material damage. Consult with your SANYO representative nearest before using SANYO products described contained herein such applications. SANYO assumes responsibility equipment failures that result from using products values that exceed, even momentarily, rated values (such maximum ratings, operating condition ranges, other parameters) listed products specifications SANYO products described contained herein.
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
11999RM (OT) 6015-1/31
LC78622NE Built-in digital attenuator bits alpha, steps) Built-in digital de-emphasis Zero cross muting Supports implementation double-speed dubbing function. Support bilingual applications. General-purpose ports: pins
Package Dimensions
unit: 3159-QFP64E
[LC78622NE]
17.2 14.0 0.35
0.15
Features
single-voltage power supply
17.2 14.0
3.0max
15.6
SANYO: QFP64E (QIP64E)
Equivalent Circuit Block Diagram
6015-2/31
LC78622NE Assignment
Specifications
Absolute Maximum Ratings
Parameter Maximum supply voltage Input voltage Output voltage Allowable power dissipation Operating temperature Storage temperature Symbol VOUT Topr Tstg Conditions Ratings +125 Unit
6015-3/31
LC78622NE Allowable Operating Ranges
Parameter Symbol Supply voltage Input level voltage Data setup time Data hold time High level clock pulse width level clock pulse width Data read access time Command transfer time Subcode read enable time Subcode read cycle time Subcode read enable time Port input data setup time Port input data hold time Port input clock setup time Port output data delay time Input level Operating frequency range Crystal oscillator frequency tRAC tRWC tSQE tCSU tCHD tRCQ tCDD Conditions VDD, XVDD, LVDD, RVDD, VVDD: During normal-speed playback VDD, XVDD, LVDD, RVDD, VVDD: During double-speed playback DEFI, COIN, RES, HFL, TES, SBCK, RWC, CQCK, TAI, TEST1 TEST5, CONT1 CONT5, PCCL EFMIN DEFI, COIN, RES, HFL, TES, SBCK, RWC, CQCK, TAI, TEST1 TEST5, CONT1 CONT5, PCCL EFMIN COIN, RWC: Figure COIN, RWC: Figure SBCK, CQCK: Figures SBCK, CQCK: Figures SQOUT, Figures RWC: Figure WRQ: Figure with signal SFSY: Figure SFSY: Figure CONT1 CONT5, RWC: Figure CONT1 CONT5, RWC: Figure RWC, CQCK: Figure CONT1 CONT8, RWC: Figure EFMIN: Slice level control XIN: Capacitor-coupled input EFMIN XIN, XOUT 16.9344 1200 Unit
1000 11.2
Input high level voltage
Vp-p Vp-p
Electrical Characteristics
Parameter Current drain Input high level current Symbol Input level current Output high level voltage Output level voltage IOFF Output leakage current IOFF Charge pump output current IPDOH IPDOL Conditions VDD, XVDD, LVDD, RVDD, VVDD DEFI, EFMIN, COIN, RES, HFL, TES, SBCK, RWC, CQCK: TEST1: TAI, TEST2 TEST5, PCCL: DEFI, EFMIN, COIN, RES, HFL, TES, SBCK, RWC, CQCK: TAI, TEST1 TEST5, PCCL: EFMO, CLV+, CLV-, V/P, PCK, FSEQ, TOFF, TGL, JP+, JP-, EMPH/CONT6, EFLG, FSX: MUTEL/CONT7, MUTER/CONT8, C2F, SBSY, SFSY, WRQ, SQOUT, TST11, 16M, 4.2M, CONT1 CONT5: -0.5 DOUT: EFMO, CLV+, CLV-, V/P, PCK, FSEQ, TOFF, TGL, JP+, JP-, EMPH/CONT6, EFLG, FSX: MUTEL/CONT7, MUTER/CONT8, C2F, SBSY, SFSY, WRQ, SQOUT, TST11, 16M, 4.2M, CONT1 CONT5: DOUT: PDO, CLV+, CLV-, JP+, JP-, CONT1 CONT5: VOUT PDO, CLV+, CLV-, JP+, JP-, CONT1 CONT5: VOUT PDO: RISET PDO: RISET Unit
6015-4/31
LC78622NE One-Bit Converter Analog Characteristics LVDD RVDD LVSS RVSS
Parameter Total harmonic distortion Symbol Conditions LCHO, RCHO; kHz: data input, using low-pass filter (AD725D built LCHO, RCHO; kHz: data input, using low-pass filter filter (AD725D built LCHO, RCHO; kHz: data input, using low-pass filter filter (AD725D built LCHO, RCHO; kHz: data input, using low-pass filter (AD725D built 0.009 0.012 Unit
Dynamic range
Signal-to-noise ratio
Crosstalk
Note: Measured with normal-speed playback mode Sanyo one-bit converter block reference digital attenuator circuit (hexadecimal).
Figure Command Input
6015-5/31
LC78622NE
Figure Subcode Output
Figure Subcode Output
Figure General-Purpose Port Input Timing
Figure General-Purpose Port Output Timing
6015-6/31
LC78622NE Functions
Symbol DEFI VVSS ISET VVDD EFMO EFMIN TEST2 CLV+ CLV- TOFF FSEQ CONT1 CONT2 CONT3 CONT4 CONT5 EMPH/CONT6 DOUT TEST3 TEST4 pins Function Defect detection signal (DEF) input. (Must connected when unused.) Test input. pull-down resistor built Must connected Internal control phase comparator output Internal ground. Must connected output current adjustment resistor connection Internal power supply frequency range adjustment Digital system ground. Must connected Slice level control signal output signal input Test input. pull-down resistor built Must connected Disc motor control output. Three-value output also possible when specified microprocessor command. Output states during reset Undefined Low-level output Low-level output
Rough servo/phase control automatic switching monitor output. Outputs high level during rough servo Low-level output level during phase control. Track detection signal input. This Schmitt input. Tracking error signal input. This Schmitt input. Tracking output Tracking gain switching output. Increase gain when low. Track jump output. Three-value output also possible when specified microprocessor command. data playback clock monitor. Outputs 4.3218 when phase locked. Synchronization signal detection output. Outputs high level when synchronization signal detected from signal internally generated synchronization signal agree. Digital system power supply. General-purpose General-purpose General-purpose General-purpose General-purpose De-emphasis monitor pin. high level indicates playback emphasis disk./general-purpose port flag output Digital output. (EIAJ format) Test input. pull-down resistor built Must connected Test input. pull-down resistor built Must connected General-purpose command identification pin. pull-down resistor built only same functions those provided LC78622E used, this must left open connected High: Only general-purpose port commands allowed. Low: commands allowed. Left channel mute output/general-purpose port Left channel one-bit converter Left channel power supply Left channel output Left channel ground. Must connected Right channel ground. Must connected Right channel one-bit converter Right channel output Right channel power supply Right channel mute output/general-purpose port Crystal oscillator power supply. Connections 16.9344 crystal oscillator element Crystal oscillator ground. Must connected Subcode block synchronization signal output single double error correction monitor Subcode output Subcode frame synchronization signal output. This signal falls when subcodes standby state. Controlled serial data commands from microprocessor. these that unused must either input ports connected output ports left open. High-level output Undefined Low-level output Low-level output Low-level output Undefined Input Input Input Input Input Low-level output Undefined Undefined
PCCL
MUTEL/CONT7 LVDD LCHO LVSS RVSS RCHO RVDD MUTER/CONT8 XVDD XOUT XVSS SBSY EFLG SFSY
High-level output High-level output Undefined Undefined Undefined Undefined
Continued next page. 6015-7/31
LC78622NE
Continued from preceding page.
Symbol SBCK SQOUT COIN CQCK TST11 4.2M TEST5 TEST1 Function Subcode readout clock input. This Schmitt input. (Must connected when unused.) Output 7.35 synchronization signal divided from crystal oscillator Subcode output standby output Read/write control input. This Schmitt input. Subcode output Command input from control microprocessor Input both command input clock subcode readout clock. This Schmitt input. Chip reset input. This must briefly after power first applied. Test output. Leave open. (Normally outputs level.) 16.9344 output. 4.2336 output Test input. pull-down resistor built Must connected Chip select input. pull-down resistor built Must connected controlled. Test input. pull-down resistor. Must connected Output states during reset Undefined Undefined Undefined Low-level output Clock output Clock output
Note: same potential must supplied power supply pins, i.e., VDD, VVDD, LVDD, RVDD, XVDD.
Applications Signal Input Circuit; EFMIN, EFMO, DEFI, CLV+ signal (NRZ) sliced optimal level acquired inputting signal EFMIN. LC78622NE handles defects follows. When high level input DEFI (pin EFMO (pin pins (the slice level control outputs) high-impedance state, slice level held. However, note that this function only valid phase control mode, that when (pin low. This function used combination with LA9240M LA9241M pins. Note: EFMIN CLV+ signal lines close each other, unwanted radiation result error rate degradation. recommend laying ground shield line between these lines. Clock Generation Circuit; PDO, ISET, Since LC78622NE includes circuit, circuit formed connecting external circuit. ISET charge pump reference current, circuit loop filter, resistor that determines frequency range. (Reference values)
6015-8/31
LC78622NE Monitor; monitor that outputs average frequency 4.3218 MHz, which divided from frequency. Synchronization Detection Monitor; FSEQ goes high when frame synchronization positive polarity synchronization signal) from signal read timing generated counter (the interpolation synchronization signal) agree. This thus synchronization detection monitor. held high single frame.) Servo Command Function; RWC, COIN, CQCK Commands executed setting high inputting commands COIN synchronization with CQCKclock. Note that commands executed falling edge RWC. Focus start Track jump Muting control Disk motor control Miscellaneous control Track check Digital attenuator General-purpose I/O, One-byte commands
One-byte commands
Two-byte command (RWC twice) Two-byte commands (RWC once)
Two-byte commands (RWC twice: track checking)
6015-9/31
LC78622NE Two-byte commands (RWC once: Sets digital attenuation general-purpose ports)
Command noise rejection
Command COMMAND INPUT NOISE REDUCTION MODE RESET NOISE EXCLUSION MODE
This command reduces noise CQCK clock signal. While this effective noise pulses shorter than CQCK timings tWL, tWH, tSU, must least Servo Circuit; CLV+, CLV-,
Command DISC MOTOR START (accelerate) DISC MOTOR (CLV) DISC MOTOR BRAKE (decelerate) DISC MOTOR STOP (stop)
CLV+ provides signal that accelerates disk forward direction CLV- provides signal that decelerates disk. Commands from control microprocessor select four modes; accelerate, decelerate, stop. table below lists CLV+ CLV- outputs each these modes.
Mode Accelerate Decelerate Stop CLV+ High
Pulse output
CLV- High
Pulse output
Note: servo control commands TOFF only mode. That will high level other times. Control TOFF microprocessor command only valid mode.
6015-10/31
LC78622NE mode mode LC78622NE detects disk speed from signal provides proper linear speed using several different control schemes switching internal modes. reference period corresponds frequency 7.35 kHz. outputs high level during rough servo level during phase control.
Internal mode Rough servo (velocity low) Rough servo (velocity high) Phase control (PCK locked) CLV+ High CLV- High High High
Rough servo gain switching
Command DISC DISC
disks, rough servo mode control gain about lower than gain used disks. Phase control gain switching
Command PHASE COMPARATOR DIVISOR: PHASE COMPARATOR DIVISOR: PHASE COMPARATOR DIVISOR: PHASE COMPARATOR DIVISOR USED RES=
phase control gain changed changing divisor used dividers stage immediately preceding phase comparator.
6015-11/31
LC78622NE three-value output
Command THREE VALUE OUTPUT VALUE OUTPUT (the scheme used previous products)
three-value output command allows controlled single pin.
Internal brake modes
Command INTERNAL BRAKE INTERNAL BRAKE INTERNAL BRAKE CONTROL INTERNAL BRAKE CONTINUOUS MODE RESET CONTINUOUS MODE MODE DURING INTERNAL BRAKING RESET MODE
Issuing internal brake-on (C5H) command sets LC78622NE internal brake mode. this mode, disk deceleration state monitored from when brake command (06H) executed. this mode disk deceleration state determined counting signal density single frame, when signal count falls under four, CLV- dropped low. same time signal, which functions brake completion monitor, goes high. When microprocessor detects high level signal, should issue STOP command fully stop disk. internal brake continuous mode (CBH), CLV- high-level output braking operation continues even after brake completion monitor goes high. Note that errors occur deceleration state determination noise signal, problem rectified changing signal count from four eight with internal brake control command (A3H). TOFF output disabled mode (CDH), TOFF held during internal brake operations. recommend using this feature, since effective preventing incorrect detection disk mirror surface.
6015-12/31
LC78622NE
Note: focus lost during execution internal brake command, pickup must first refocussed then internal brake command must reissued. Since incorrect deceleration state determination possible depending signal playback state (e.g., disk defects, access progress), recommend using these functions combination with microprocessor. Track Jump Circuit; HFL, TES, TOFF, TGL, JP+, LC78622NE supports track count modes listed below.
Command TRACK COUNT (using TES/HFL combination) STANDARD TRACK COUNT (directly counts signal)
earlier track count function uses signal directly internal track counter clock. reduce counting errors resulting from noise rising falling edges signal, track count function prevents noise induced errors using combination signals, implements more reliable track count function. However, dirt scratches disk result signal dropouts that result missing track count pulses. Thus care required when using this function.
6015-13/31
LC78622NE commands
Command STANDARD TRACK JUMP TRACK JUMP TRACK JUMP TRACK JUMP TRACK JUMP TRACK JUMP TRACK JUMP TRACK JUMP TRACK JUMP TRACK JUMP TRACK JUMP TRACK JUMP TRACK JUMP TRACK JUMP TRACK JUMP TRACK JUMP TRACK JUMP TRACK JUMP TRACK JUMP TRACK JUMP TRACK JUMP TRACK JUMP TRACK CHECK TOFF TRACK JUMP BRAKE TOFF OUTPUT MODE DURING PULSE PERIOD RESET TOFF OUTPUT MODE DURING PULSE PERIOD
When LC78622NE receives track jump instruction servo command, first generates accelerating pulses (period next generates deceleration pulses (period passage braking period (period completes specified jump. During braking period, LC78622NE detects beam slip direction from inputs. TOFF used components signal that aggravate slip. jump destination track captured increasing servo gain with TGL. during TOFF output mode pulse period TOFF signal held high during pulse generation period. Note: modes related disk motor control, TOFF only goes mode, will high during accelerate, stop, decelerate modes.Note that TOFF turned independently microprocessor issued commands. However, this function only valid when disk motor control mode.
6015-14/31
LC78622NE Track jump modes table lists relationships between acceleration pulses (the period) deceleration pulses (the period), braking period (the period).
Command TRACK JUMP (OUT) TRACK JUMP (OUT) TRACK JUMP (OUT) track jump period track jump period track jump period None track jump period track jump period track jump period track jump period track jump period Standard track jump mode This period does exist. TOFF during period. None track jump period track jump period track jump period track jump period track jump period track jump period track jump period track jump period track jump period same time same time same time same time same time same time track jump period track jump period track jump period track jump mode This period does exist. TOFF during period.
TRACK JUMP (OUT)
TRACK JUMP (OUT) TRACK JUMP (OUT) TRACK JUMP (OUT) TRACK JUMP (OUT) TRACK JUMP (OUT) TRACK JUMP (OUT)
None track jump period track jump period track jump period track jump period
TRACK CHECK TRACK JUMP BRAKE
TOFF goes high during period when tracks passed over. pulses output. There periods.
60ms
TOFF goes high during period when tracks passed over. pulses output. There periods.
Note: indicated table, actuator signals output during TRACK CHECK function. This mode which signal counted tracking loop state. Therefore, feed motor forwarding required. servo command register automatically reset after cycle track jump sequence completes. another track jump command issued during track jump operation, content that command will executed starting immediately. TRACK JUMP mode does have braking period (the period). Since brake mode must generated external circuit, care required when using this mode. While there braking period (the period) LC78620E/21E track jump command TRACK JUMP (OUT)", this been changed this LSI, which period
THLD signal generated LA9230M, LA9231M, LA9240M, tracking signal held during pulse period.
6015-15/31
LC78622NE
Tracking brake chart shows relationships between TES, HFL, TOFF signals during track jump period. TOFF signal extracted from signal signal edges. When signal high, pickup over mirror surface, when low, pickup over data bits. Thus braking applied based TOFF signal being high when pickup moving from mirror region data region being when pickup moving from data region mirror region.
three-value output
Command THREE VALUE OUTPUT VALUE OUTPUT (earlier scheme)
three-value output command allows track jump operation controlled from single pin.
Track check mode
Command TRACK CHECK TRACK CHECK BYTE COMMAND RESET
LC78622NE will count specified number tracks plus when microprocessor sends arbitrary binary value range after issuing either track check track check command. Note: Data desired track count must general-purpose command $DF.
6015-16/31
LC78622NE
Note: When desired track count been input binary, track check operation started fall RWC. During track check operation TOFF goes high tracking loop turned off. Therefore, feed motor forwarding required. When track check in/out command issued function signal switches from normal mode subcode standby monitor function track check monitor function. This signal goes high when track check half completed, goes when check finishes. control microprocessor should monitor this signal level determine when track check completes. two-byte reset command issued, track check operation will repeat. That skip over 20,000 tracks, issue track check command once, then count signal times. This will check 20,000 tracks. After performing track check operation, brake command have pickup lock onto track.
Error Flag Output; EFLG,
signal generated dividing crystal oscillator clock, 7.35 frame synchronization signal. error correction state each frame output from EFLG. low-level period indicates correction state, high-level period indicates correction state. playback OK/NG state easily determined from extent high level that appears here. Subcode Output Circuit; SBSY, SFSY, SBCK subcode signal output pin, codes, read sending eight clocks SBCK within after fall SFSY. signal that appears changes rising edge SBCK. clock applied SBCK, code will output from SFSY signal that output each subcode frame cycle, falling edge this signal indicates standby output subcode symbol Subcode data output fall this signal.
SBSY signal output each subcode block. This signal goes high synchronization signals. fall this signal indicates subcode synchronization signals start data subcode block. (EIAJ format)
6015-17/31
LC78622NE Subcode Output Circuit; WRQ, RWC, SQOUT, CQCK,
Command ADDRESS FREE ADDRESS
Subcode read from SQOUT applying clock CQCKpin. eight bits subcode, signal used song (track) access display. will high only data passed error check subcode format internal address control microprocessor read data from SQOUT order shown below detecting this high level applying CQCK. When CQCK applied disables register update internally. microprocessor should give update permission setting high briefly after reading completed. will fall this time. Since falls 11.2 after going high, CQCK must applied during high period. Note that data read first format. Note: That state will ignored address free command input. This provided handle CD-ROM applications.
Note: Normally, indicates subcode standby state. However, used different monitoring purpose track check mode during internal braking. (See items track counting internal braking details.) LC78622NE becomes active when low, subcode data output from SQOUT pin. When high, SQOUT goes high-impedance state.
6015-18/31
LC78622NE Bilingual Function
Command CONT CONT CONT
Following reset when stereo (28H) command been issued, left right channel data output left right channels respectively. When (29H) command issued, left right channels both output left channel data. When (2AH) command issued, left right channels both output right channel data. De-Emphasis; EMPH/CONT6 preemphasis on/off subcode control information output from EMPH pin. When this high, LC78622NE internal de-emphasis circuit operates digital filters converter output deemphasized data. Digital Attenuator Digital attenuation applied audio data setting high inputting corresponding two-byte command COIN synchronization with CQCK clock.
Command DATA STEP STEP DOWN STEP STEP DOWN STEP STEP DOWN DATA (MUTE
Attenuation setup Since attenuation level muted state muting specified attenuation coefficient 00H) after attenuation level reset, attenuation coefficient must directly (using DATA command) output audio signals. Note that attenuation level values from EEH. These two-byte commands differ from two-byte commands used track counting that only necessary once two-byte command reset required. After inputting target attenuation level value range EEH, sending attenuator step up/down command will cause attenuation level approach target value steps units specified synchronization with rising edges LRSY input. However, DATA command sets target value directly. data value input during transition, value begins approach target value that point. Note that UP/DOWN distinction significant here.
6015-19/31
LC78622NE DATA [dB] 100H
Audio output level
example, formula below calculates time required attenuation level increase from when 4STEP command executed. Note that control microprocessor must provide enough time margin this operation complete before issuing next attenuation level command. level 4STEP 21.6 44.1 Note: Setting attenuation level values higher disallowed prevent overflows one-bit converter calculations from causing noise. Mute Output; MUTEL/CONT7, MUTER/CONT8 Flag Output; output flag information 8-bit units. Digital Output Circuit; DOUT This output with digital audio interface. Data output EIAJ format. This signal been processed interpolation muting circuits. This built-in driver circuit directly drive transformer.
Command DOUT DOUT UBIT UBIT CDROM-XA ROMXA-RST
DOUT locked level issuing DOUT command. UBIT information DOUT data locked zero issuing UBIT command. DOUT data switched data which interpolation muting processing have been performed issuing CD-ROM command. When searching when returning pickup initial position, there cases when frequency output data will contain parity error locking lost temporarily. prevent this, recommend directly executing UBIT ($41) command then directly executing UBIT ($40) command when searching when returning pickup initial position. Mute Control Circuit
Command MUTE: MUTE:
Inputting above command mutes audio level (MUTE dB). Since zero-cross muting used, there very little noise associated with this operation. defines zero cross ranges where upper bits data zeros ones. Note that MUTE instruction supported LC78620E been removed from this product.
6015-20/31
LC78622NE Interpolation Circuit Outputting incorrect audio data that could corrected error detection correction circuit would result loud noises being output. minimize this noise, LC78622NE replaces incorrect data with linearly interpolated data based correct data either side incorrect data. flags indicate errors, above replacement performed, more sets flags indicate errors, holds previous value. However, when correct data output following more consecutive flags indicating errors, data point between correct data data output points previously (the held value) replaced with value computed linearly interpolating those values.
General-Purpose Ports; CONT1, CONT2, CONT3, CONT4, CONT5, EMPH/CONT6, PCCL, MUTEL/CONT7, MUTER/CONT8 LC78622NE provides five ports CONT1 CONT5 three output ports CONT6 CONT8. After reset, these five ports function input pins three output ports function EMPH, MUTEL, MUTER pins, respectively. Unused ports must connected ground function input ports function output ports.
Code PORT READ PORT PORT OUTPUT Enable CONT6 function Enable EMPH function Enable CONT7 CONT8 functions Enable MUTEL MUTER functions PORT Command
port information read from SQOUT synchronization with falling edge CQCK signal order CONT1 CONT5 using PORT READ command. When enters level subcode output while controlling general-purpose port, data subcode should invalid another subcode should read out. This command 1-byte command format. Command control limited only general-purpose ports possible using PCCL setting, even during track check, track jump, internal braking operations. When using general-purpose port command control function during track check similar operations, PCCL high input desired general-purpose ports commands (codes through $DF). (Only general-purpose port commands accepted when PCCL high.) PCCL must input command other than general-purpose port command. However, track check other command applied when PCCL level, operation that being performed will interrupted. state PCCL must only changed when low. However, must changed during subcode readout. Note: When track checking, same number desired tracks general-purpose port commands (codes $DF) applied with PCCL held level, general-purpose port command well track count operation desired track count will executed. Therefore, desired tarack count data should codes with PCCL held level when track checking.
6015-21/31
LC78622NE
Additionally, CONT1 CONT5 ports individually function control output pins with PORT OP-E/D command. ports selected using lower bits 1Byte data. bits data correspond CONT1 CONT5 order starting with 1Byte data. This command Two- byte command. (RWC once)
Command PORT OP-E/D
Sets CONTn output Sets CONTn input care Ports output pins output high levels independently. bits Byte data correspond those ports. bits data correspond CONT1 CONT8 order starting with Byte data. CONT6 through CONT8 output ports, port functions must with commands. This command two-byte command. (RWC once)
Command PORT DATA
Sets CONTn output Sets CONTn input care Clock Oscillator; XIN, XOUT
XTAL NORMAL-SPEED PLAYBACK DOUBLE-SPEED PLAYBACK Command
clock that used time base generated connecting 16.9344 oscillator element between these pins. command turns both crystal oscillators. system control microprocessor issue double-speed normal-speed playback command when application implements double-speed playback system.
4.2M Pins; 16M, 4.2M Both normal- double-speed playback modes, buffer outputs 16.9344 external crystal oscillator 16.9344 signal. 4.2M supplies LA9240M LA9241M system clock, normally outputting 4.2336 signal. When oscillator turned both these pins will fixed either high low.
6015-22/31
LC78622NE Reset Circuit; When power first applied, this should briefly then high. This will muting stop disk motor.
Constant linear velocity servo Muting control subcode address conditions Track jump mode Track count mode Digital attenuator Playback speed Digital filter normal speed START Address Standard Standard DATA Normal speed STOP BRAKE
Address free DATA Double speed
Setting sets LC78622NE settings enclosed boxes table.
Other Pins; 2:TAI, TEST1, TEST2, TEST3, TEST4, TEST5, TST11 These pins used testing internal circuits. Even though pull-down resistors built into TEST2 TEST5 input circuits, these pins must connected during normal operation. TST11 output should normally left open. Since TEST input without pull-down resistor built sure connect
6015-23/31
LC78622NE Circuit Block Operating Descriptions address control LC78622NE incorporates 8-bit 2k-word chip. This demodulated data jitter handling capacity frames implemented using address control. LC78622NE continuously checks remaining buffer capacity controls data write address fall center buffer capacity making fine adjustments frequency divisor side servo circuit. frame buffer capacity exceeded, LC78622NE forcibly sets write address position. However, since errors that occur this operation cannot handled with error flag processing, applies muting output frame period.
Position less more Division ratio processing Force Force Decrease ratio Standard ratio Increase ratio
Error Correction LC78622NE writes demodulated data internal compensate jitter then performs following processing with uniform timing based crystal oscillator clock. First, LC78622NE performs error checking correction block, determines flags, writes flag register. Next, LC78622NE performs error checking correction block, determines flags, writes data internal RAM.
flag errors error errors errors more flag errors error errors errors more Error correction flag processing correction required Flag reset Correction Flag reset Correction Flag Correction possible Flag Error correction flag processing correction required Flag reset Correction Flag reset Depends flags*1 Depends flags*2
Note: positions errors determined check agree with those specified flags, correction performed flags cleared. However, number flags higher, correction fail. this case correction performed flags taken flags without change. Error correction possible error position agrees other does not. Furthermore, number flags under, check result seen unreliable. Accordingly, flags will this case. Cases where number flags more handled same way, flags taken flags without change. When there even agreement between error positions, error correction course, impossible. Here, number flags under, data that seen correct after correction seen incorrect data. flags this case. other cases, flags taken flags without change. When data determined have three more errors uncorrectable, correction course, impossible. Here, number flags under, data that seen correct after correction seen incorrect data. flags this case. other
6015-24/31
LC78622NE Command Summary Table Blank entry: Illegal command, Changed added command, Latching commands (mode setting commands), Commands shared with (LA9220M/30M/40M other processor), Items parentheses commands (provided reference purposes)
00000000 (ADJ.reset) TOFF mode TOFF high mode TRACK COUNT TRACK COUNT 01000000 01000001 01000010 01000011 01000100 01000101 01000110 01000111 01001000 01001001 01001010 01001011 01001100 01001101 01001110 01001111 UBIT UBIT DOUT DOUT 01100000 01100001 01100010 01100011 01100100 01100101 01100110 01100111 01101000 01101001 01101010 01101011 01101100 01101101 normal speed 01101111
MUTE 00000010 MUTE
DISC START DISC DISC STOP FOCUS START ADDRESS FREE 00001010 00001011 00001100 00001101 00001110 TRACKING 00010000 00010001 00010010 00010011 00010100 00010101 00010110 00010111 00011000 00011001 00011010 00011011 00011100 00011101 00011110 00011111 128TJ 16TJ 64TJ 256TC 128TJ 16TJ 64TJ 00100101 DISC BRAKE 00100111 CONT CONT CONT 00101011 00101100 00101101 00101110 00101111
00110000 00110001 00110010 00110011 00110100 00110101 00110110 00110111 00111000 00111001 00111010 00111011 00111100 00111101 00111110 00111111
32TJ
01010000 01010001 01010010 01010011 01010100 01010101 01010110 01010111
01110000 01110001 01110010 01110011 01110100 01110101 01110110 01110111 01111000 01111001 01111010 01111011 01111100 01111101 01111110 01111111
32TJ
01011000 01011001 01011010 01011011 01011100 01011101 01011110 01011111
Continued next page.
6015-25/31
LC78622NE
Continued from preceding page.
Blank entry: Illegal command, Changed added command, Latching commands (mode setting commands), Commands shared with (LA9240M/41M other processor), Items parentheses commands (provided reference purposes)
10000000 DATA 4STP 4STP 8STP 8STP 16STP 16STP #CDROMXA ADDRESS 10001010 #ROMXA 10001100 TRACK 10100010 11000000 11000001 Double-speed playback Normal-speed playback 11100000 11100001 11100010 11100011 Internal Internal 11100100 11100101 11100110 11100111 11101000 11101001
FOCUS START 11000011 11000100 11000101 11000110 11000111 11001000 11001001 11001010 11001011 11001100 11001101 11001110 11001111
Internal BRAKE CONT 10100100 10100101 10100110 10100111 DISC DISC 10101010 10101011 10101100 10101101 10101110 10101111
Internal BRK-DMC Internal BRK-DMC high TOFF during internal BRAKE during internal BRAKE Xtal 11101100 11101101 Command noise rejecter Command noise rejecter TRCK CHECK (2BYTE DETECT) 11110001 11110010 11110011 11110100 11110101 11110110 11110111 TRCK CHECK (2BYTE DETECT) #CONT6 #EMPH #PORT 11111001 11111010 11111011
TRACKING
F.OFF.ADJ.ST)
CLV-PH mode
11010000
F.OFF.ADJ.OFF) T.OFF.ADJ.ST) T.OFF.ADJ.OFF) LSR.ON)
CLV-PH mode CLV-PH mode CLV-PH mode
11010001 11010010 11010011
CLV3ST output 11010101 11010110
LSR.OF/F.SV.ON) CLV3ST output LSR.OF/F.SV.OF) JP3ST output SP.8CM) SP.12CM) 10111000
JP3ST output 11011000
SP.OFF) SLED.ON) SLED.OFF) EF.BAL.START) T.SERVO.OFF) T.SERVO.ON) 10011111
10111001 10111010 10111011 10111100 10111101 10111110 10111111
11011001 11011010 11011011 11011100 11011101 11011110 11011111
#PORT OUTPUT #PORT READ #CONT7, #MUTEL, 11111101 NOTHING 2BYTE
Note: command should issued case voltage power supply application.
6015-26/31
LC78622NE Sample Application Circuit
6015-27/31
LC78622NE CD-DSP Functional Comparison
Product Function EFM-PLL Playback speed Digital output Interpolation Zero-cross muting Level meter peak search Bilingual Digital attenuator Digital filters Digital de-emphasis Output Generalpurpose port support Anti-shock interface Anti-shock control text CD-ROM interface 1-bit L.P.F Supply voltage Package LC786021E Built-in QFP80E LC78625E Built-in QFP80E LC78630E Built-in QFP80E LC78624E Built-in QFP64E LC78626E (LC78626KE) Built-in (8fs) required 4MDRAM (max 16MDRAM) (3.0 QFP100E QFP64E LC78622E LC78622NE
Built-in QFP64E
Notes Application Design While goes without saying that achieve system reliability absolute maximum ratings allowable operating conditions specified this must strictly adhered adequate consideration must also given operating environmental conditions, such ambient temperature static electricity, mounting conditions used. This section presents items that require special care during application design mounting. Handling Unused Pins unused input pins this left open state during operation, there times when enter unstable state. Always follow directions handling unused pins included documentation this Also, connect output pins power supply, ground, other output lines. general-purpose ports must either output state output level software, must left input state pulled pulled down fixed input level. Latch-up Prevention structure this supply voltage pins must supplied with same potential. Also supply same potential servo system ASP. slice level control circuit shared with this application same potential necessary. Also, same potential must supplied supply voltage pins Latch-up occur discrepancy occurs timing rise supply voltage applied different supply voltage pins. allow timing discrepancies occur when power first applied. allow voltages input output pins exceed fall lower than VSS. timing signal application requires special care power assure that this condition met. allow overvoltages abnormal noise applied this
continued next page. 6015-28/31
LC78622NE
Continued from preceding page.
general, latch-up prevented tying unused pins either VSS. However, sure follow special instructions provided with this unused handling. short outputs. Interface When inputs outputs devices different types connected, incorrect operation occur discrepancies between input VIL/VIH output VOL/VOH values. Insert level shifters between devices that have different supply voltages prevent device destruction systems that dual power-supply systems. Load Capacitance Output Current When load with large capacitance connected, since load short that lasts extended period, fused output lines caused. Also, high charge discharge currents result noise which degrade product performance result incorrect operation. Always recommended load capacitances. Large output sink source currents also cause same types problems described previous item. recommended currents, while taking maximum allowable power dissipation into account. Notes Power Application Reset There points that require care that related power application, period during which reset applied, period after reset cleared. Refer specific notes provided specification sheets individual products, design products with these points mind. output states, settings, contents registers, other aspects this guaranteed when power first applied. Aspects that defined reset operation settings only guaranteed once reset setting been performed. Applications that this should apply reset immediately after power applied. states register values that undefined differ between samples, change between lots over time. Applications should depend undefined states values. general-purpose ports input state during reset. pins that must fixed high fail-safe design considerations, pulling pulling down through individual resistor effective design. When 4.2MHz output used microcontroller master clock, reset circuit will shared with microcontroller. Since microcontroller will reset unless clock signal applied, control reset input this from microcontroller output port. this been reset, 4.2-MHz output guaranteed, microcontroller reset. This result incorrect application system operation. Notes Thermal Design failure rate semiconductor devices significantly accelerated increases ambient temperature power dissipation. assure high reliability, designs must include adequate margins take possible changes ambient conditions into account. Notes Printed Circuit Board Patterns possible, influence common impedances should reduced separating ground lines each system. ground lines should wide short possible lower their high-frequency impedance. Ideally, decoupling capacitors (0.01 should inserted between each ground pair. These capacitors should located extremely close their corresponding power supply system pins. Additionally, appropriate insert capacitor about between ground low-frequency filter. However, note that using excessively large capacitors here result latch-up. servo systems, VREF lines should handled same manner ground lines. Driver ground lines should particularly wide, recommended driver pattern should used direct under power devices taking heat radiation effect into consideration. current output type pickup used, locate optical sensor connector input close together possible. voltage output type pickup used, locate conversion resistor close input side possible.
Continued next page. 6015-29/31
LC78622NE
Continued from preceding page.
signal lines should kept short possible, either adjacent lines should avoided ground shield lines should between adjacent signal lines. Since slice level controller output (EFMO) clock output (4.2MHz) lines easily disrupt signal lines, resistors connected output pins should located extremely close pin. Note that smaller these resistors, larger amount spurious radiation emitted. Inversely, output level adversely influenced resistors made large. Design 4.2MHz output according input level requirements. (Design center: p-p) Noise microcontroller interface signal lines result incorrect operation. While best method reducing noise depends application itself, general, interface lines should made short possible inductances capacitances minimized. However, designs must also take crosstalk into account. long interface lines must used, noise problem, inserting noise exclusion circuit effective. Design noise filters with interface timing taken into account. Issuing command noise reduction command [$EF] also effective. Cover area around crystal oscillator element with ground pattern. Notes Software Design Always follow recommendations software design provided documentation techniques specifically forbidden. digital outputs used, issue UBIT [$41] command this during initialization. UBIT [$40] should only used during playback prevent unlock incorrect subcode recognition. During initialization, after clearing reset, after turning this IC's oscillator issue 2-byte reset command [$FF] LA9230M Series LA9240M Series command register. Since LA9230M Series LA9240M Series 4.2MHz output from this their master clock, additional setup time required after oscillator stabilization time during initialization, after clearing reset, after turning this IC's oscillator This setup time also required after issuing reset command [$00] ASP. Since command timing LA9230M Series LA9240M Series slower than that this sure refer documentation when designing application software. Other Notes have questions, please hesitate contact your Sanyo representative, your Sanyo semiconductor sales outlet. Since this specifically designed players, specifications differ from those standard logic other general-purpose products. recommend adopting failsafe design techniques applications, also recommend debugging applications application equipment itself.
6015-30/31
LC78622NE
Specifications SANYO products described contained herein stipulate performance, characteristics, functions described products independent state, guarantees performance, characteristics, functions described products mounted customer's products equipment. verify symptoms states that cannot evaluated independent device, customer should always evaluate test devices mounted customer's products equipment. SANYO Electric Co., Ltd. strives supply high-quality high-reliability products. However, semiconductor products fail with some probability. possible that these probabilistic failures could give rise accidents events that could endanger human lives, that could give rise smoke fire, that could cause damage other property. When designing equipment, adopt safety measures that these kinds accidents events cannot occur. Such measures include limited protective circuits error prevention circuits safe design, redundant design, structural design. event that SANYO products (including technical data, services) described contained herein controlled under applicable local export control laws regulations, such products must exported without obtaining export license from authorities concerned accordance with above law. part this publication reproduced transmitted form means, electronic mechanical, including photocopying recording, information storage retrieval system, otherwise, without prior written permission SANYO Electric Co., Ltd. information described contained herein subject change without notice product/technology improvement, etc. When designing equipment, refer "Delivery Specification" SANYO product that intend use. Information (including circuit diagrams circuit parameters) herein example only; guaranteed volume production. SANYO believes information herein accurate reliable, guarantees made implied regarding infringements intellectual property rights other rights third parties.
This catalog provides information January, 1999. Specifications information herein subject change without notice. 6015-31/31
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