LC897194 CD-ROM Decoder with Built-In ATAPI (IDE) Interfaces

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LC897194 CD-ROM Decoder with Built-In ATAPI (IDE) Interfaces

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Ordering number *EN5572
LC897194
CD-ROM Decoder with Built-In ATAPI (IDE) Interfaces
Preliminary Overview
LC897194 provides CD-ROM functionality includes built-in ATAPI (IDE) interfaces.
Package Dimensions
unit:
3214-SQFP144
[LC897194]
Function
CD-ROM functionality, ATAPI (IDE) interface (the register other blocks), interface
Features
ATAPI (IDE) interface interface Supports playback (when using 70-ns 16-bit data path DRAM) Transfer rate: 16.6 MB/s (when using 60-ns 16-bit data path DRAM) Transfer rate: 8.33 MB/s (when using 70-ns 8-bit data path DRAM) Between Mbits DRAM used buffer RAM. user freely main channel flags buffer RAM. Built-in batch transfer function (function transferring main channel flags operation) Built-in multiple transfer function (function automatically transferring multiple blocks single operation)
SANYO: SQFP144
Specifications
Absolute Maximum Ratings
Parameter Maximum supply voltage voltages Allowable power dissipation Operating temperature Storage temperature Soldering heat resistance (pins only) Maximum power Note: basic cell. Symbol Topr Tstg seconds 25°C 70°C Conditions 25°C Ratings -0.3 +7.0 -0.3 +0.3 +125 ±20* Unit
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, Chome, Ueno, Taito-ku, TOKYO, JAPAN
22897HA (OT) 5572-1/11
LC897194 Allowable Operating Ranges +70°C,
Parameter Supply voltage Input voltage range Symbol Conditions Ratings Unit
Characteristics +70°C,
Parameter Input high-level voltage Input low-level voltage Input high-level voltage Input low-level voltage Input high-level voltage Input low-level voltage Input high-level voltage Input low-level voltage Input high-level voltage Input low-level voltage Output high-level voltage Output low-level voltage Output high-level voltage Output low-level voltage Output high-level voltage Output low-level voltage Output high-level voltage Output low-level voltage Input leakage current Output leakage current Pull-up resistance Pull-down resistance Symbol VIH1 VIL1 VIH2 VIL2 VIH3 VIL3 VIH4 VIL4 VIH5 VIL5 VOH1 VOL1 VOH2 VOL2 VOH3 VOL3 VOH4 VOL5 Applicable pins (see below) compatible: compatible: compatible, with pull-up resistor: (12) compatible, with pull-up resistor: (12) compatible, with pull-down resistor: compatible, with pull-down resistor: compatible, Schmitt characteristics: (3), (5), (13), (14) compatible, Schmitt characteristics: (3), (5), (13), (14) CMOS compatible, Schmitt characteristics: CMOS compatible, Schmitt characteristics: (7), (10), (12) (7), (10), (12) (8), (13) (8), (13) (9), (14) (11) VSS, (1), (2), (3), (4), (5), (12), (13), (14) When output high impedance: (9), (11), (13), (14) (12) Ratings Unit
Note: applicable pins follows: INPUT CSCTRL, RSSEL, HDB0 SUA0 TEST0 ZDMACK, ZHRST, ZRESET, BCK, C2PO, LRCK, SDATA, ZCS1FX, ZCS3FX ZCS, ZRD, ZDIOR, ZDIOW, DRESP, WFCK, SCOR OUTPUT MCK, MCK2 ZINT0, ZINT1 DMARQ, HINTRQ IORDY, ZIOCS16 (10) ZCAS0 ZRAS0 ZLWE, ZUWE, ZOE, DREQ (11) ZRSTCPU, ZRSTIC, ZSWAIT INOUT (12) (13) (14) ZDASP, ZPDIAG characteristics apply XTAL XTALCK pins.
5572-2/11
LC897194 Recommended Oscillator Circuit Example
With crystal with resonant frequency 16.9344 MHz, None With crystal with resonant frequency 33.8688 MHz. third harmonics problem 33.8688-MHz recommended circuit, consult with manufacturer crystal exact component values, since those values will influenced printed circuit board used.
5572-3/11
LC897194 Block Diagram
BCK, SDATA, LRCK, C2PO DD15, ZDASP, ZPDIAG ZCS1FX, ZCS3FX, DA2, ZDIOR, ZDIOW, ZDMACK DMARQ, HINTRQ, ZIOCS16, IORDY, ZHRST ZRD, ZWR, SUA0 SUA6, ZCS, CSCTRL IO15 RA9, ZRAS0, ZRAS1, ZCAS0, ZCAS1, ZOE, ZUWE, ZLWE DREQ HDB0 HDB7, DRESP WFCK, SCOR HISIDE (WD25C32) made WESTERN DIGITAL.
5572-4/11
LC897194 Functions
Input Output Bidirection Power connected
Symbol VSS0 ZRAS0 ZRAS1 VSS0 ZCAS0 ZCAS1 VSS0 ZUWE ZLWE VSS0 TEST0 TEST1 TEST2 TEST3 TEST4 VSS0
Type Data to/from data buffer DRAM Pull-up resistors built used data buffer DRAM address. Buffer output enable Buffer upper write enable Buffer lower write enable used data buffer DRAM address.
Function signal output buffer DRAM (Output normally used.) signal output buffer DRAM signal output buffer DRAM (Output normally used.) signal output buffer DRAM
Used testing. There should connections these pins. These pins must left open.
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LC897194
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Symbol IO10 IO11 IO12 IO13 IO14 IO15 VSS0 WFCK SCOR VSS0 DREQ DRESP HDB7 HDB6 VSS0 HDB5 HDB4 HDB3 HDB2 HDB1 HDB0 SDATA LRCK C2PO MCK2 CSCTRL RSSEL VSS0 XTALCK XTAL VSS0 VSS0 ZRSTIC ZRESET ZINT1 ZINT0 Type Reset output driver reset reset input Microcontroller data read signal input Microcontroller data write signal input Register chip select signal input from microcontroller ATAPI block interrupt output (selected register) Interrupt request signal output microcontroller Outputs XTALCK signal times 1/2, stopped. Crystal oscillator circuit input Crystal oscillator circuit output Outputs XTALCK signal times 1/1, 1/2, 1/512, stopped. Microcontroller chip select signal active high selection Direct indirect addressing selection Interface with digital signal processor data input data request output data latch signal input data input Subcode input Subcode input Data to/from data buffer DRAM Pull-up resistors built Function
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5572-6/11
LC897194
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Symbol SUA0 SUA1 SUA2 SUA3 SUA4 SUA5 SUA6 VSS0 VSS0 ZRSTCPU ZSWAIT ZHRST ZDASP ZCS3FX ZCS1FX VSS0 ZPDIAG ZIOCS16 HINTRQ ZDMACK VSS1 IORDY ZDIOR ZDIOW DMARQ DD15 VSS1 DD14 Type ATAPI data ATAPI data ATAPI control signals ATAPI control signals Reset signal output WAIT signal output microcontroller ATAPI control signals Microcontroller data signals Pull-up resistors built Microcontroller register selection signals SUA0 functions indirect address mode. Function
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5572-7/11
LC897194
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Symbol VSS1 DD13 DD12 VSS1 DD11 DD10 VSS1 VSS1 Type ATAPI data ATAPI data ATAPI data ATAPI data Function
pins must left open. Make connections these pins. symbols that start with letter negative logic signals. VSS0 logic system ground VSS1 interface driver ground.
5572-8/11
LC897194 Descriptions ATAPI Pins ZCS1FX (input) Chip select signal used select command block register. ZCS3FX (input) Chip select signal used select control block register. (input) Address used access ATAPI registers. ZDASP(input/output) Drive output, drive input. Signal used indicate drive that drive exists. external pull-up resistor must provided. DD15 (input/output) Data with width bits. Data transferred 8-bit 16-bit units. ZDIOR (input) Read strobe signal from host. ZDIOW (input) Write strobe signal from host. ZDMACK (input) Acknowledge signal from host response drive DMARQ request signal during transfers. There internal pull-up resistor circuit. DMARQ (output) Drive request signal during transfers. HINTRQ (output) Drive interrupt signal sent host. ZIOCS16 (output) This signal asserted drive when drive support 16-bit transfers. This signal asserted during transfers. IORDY (output) Signal that indicates that drive completed response preparation during data transfers. This signal will when preparation completed. ZPDIAG (input/output) Signal asserted drive inform drive that diagnostics have completed. external pull-up resistor must provided. ZHRST (input) Reset signal from host. There internal pull-up resistor circuit. Microcontroller Interface Pins (input) Chip select signal from microcontroller. CSCTRL (input) Signal that selects logic chip select from microcontroller. High signal functions active-low signal. signal functions active-high signal. ZRD, ZWR, SUA0 SUA6 (input) Microcontroller interface control pins. SUA0 SUA6 pins used addressing. SUA0 functions (the register select pin) indirect addressing. When SUA0 low, address read write operation performed, when high, data read write operation performed. RSSEL (input) Signal that selects direct indirect addressing. High Indirect addressing selected. Direct addressing selected. ZSWAIT (output) When microcontroller accessing RAM, sub-CPU must wait when this low. (input/output) Microcontroller data bus. Pull-up resistors built ZINT0 (output) Interrupt request signal microcontroller. active level (high low) changed setting register. default setting active low. ZINT1 (output) Interrupt request signal from block microcontroller.
5572-9/11
LC897194 Buffer Pins IO15 (input/output) Data buffer DRAM. Pull-up resistors built (output) Buffer address pins. ZRAS0, ZRAS1 (ZCS0, ZCS1) (output) Buffer DRAM output pins. Although ZRAS0 used normally, applications that (64K bits) DRAMs, ZRAS0 ZRAS1 signals connected each DRAM pins. ZCAS0, ZCAS1 (output) Buffer DRAM output pins. Although ZCAS0 used normally, applications that two-CAS DRAMs, ZCAS0 connected DRAM UCAS pin, ZCAS1 DRAM LCAS pin. (output) buffer DRAM read output pin. ZUWE, ZLWE (output) Buffer DRAM write output signals. Connect these pins corresponding pins DRAMs. When two-CAS DRAMs used, connect ZLWE write enable signal. Subcode Interface Pins WFCK, SCOR (input) Subcode interface pins. connecting these pins DSP, subcode sync detected main channel buffering started according that sync. Subcode data buffering performed. Data Pins BCK, SDATA, LRCK, C2PO (input) Connect these pins acquire CD-ROM data. C2PO flag pin. interface pins DRESP (input) data latched falling edge this signal. HDB0 HDB7 (input) data input pins. DREQ (output) data request output. Other Pins ZRESET (input) LC897194 reset pin. reset when level applied. Applications must hold this least when power first applied. XTALCK, XTAL These pins drive external crystal either 16.9344 33.8688 MHz. external clock frequency also input XTALCK pin. (output) Outputs either XTALCK frequency that frequency divided This output stopped. MCK2 (output) Outputs either XTALCK frequency that frequency divided (with opposite phase pin) XTALCK frequency divided 512. This output stopped. ZRSTIC (output) This output level either setting microcontroller register (ZSYSRES) (0), setting ZHRST (pin 103) low. This output high-impedance state when both ZSYSRES ZHRST high. Since this open-drain circuit, external pull-up resistor must provided. ZRSTCPU (output) low-going pulse about (when XTALCK MHz, about when XTALCK MHz) generated this when ATAPI soft reset command (08H) received. interrupt issued microcontroller this time. ZRESET (pin functioning with activelow logic, ZRESET signal output without change ZRSTCPU. Since this open-drain circuit, external pull-up resistor must provided.
5572-10/11
LC897194
products described contained herein intended surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment like, failure which directly indirectly cause injury, death property loss. Anyone purchasing products described contained herein above-mentioned shall: Accept full responsibility indemnify defend SANYO ELECTRIC CO., LTD., affiliates, subsidiaries distributors their officers employees, jointly severally, against claims litigation damages, cost expenses associated with such use: impose responsibility fault negligence which cited such claim litigation SANYO ELECTRIC CO., LTD., affiliates, subsidiaries distributors their officers employees jointly severally. Information (including circuit diagrams circuit parameters) herein example only; guaranteed volume production. SANYO believes information herein accurate reliable, guarantees made implied regarding infringements intellectual property rights other rights third parties. This catalog provides information February, 1997. Specifications information herein subject change without notice. 5572-11/11

LC897194 CD-ROM Decoder with Built-In ATAPI (IDE) Interfaces

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