LC89977M Delay Line Preliminary Overview LC89977M delay

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LC89977M Delay Line Preliminary Overview LC89977M delay

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Ordering number EN5545
LC89977M
Delay Line
Preliminary Overview
LC89977M delay line television system that includes chrominance signal crosstalk exclusion filter luminance signal delay line chip.
Package Dimensions
unit:
3111-MFP14S
[LC89977M]
Features
single-voltage power supply Built-in frequency multiplier circuit allows 3fsc operation from (4.43 MHz) input. switched between PAL/GBI, 4.43NTSC formats setting control values. Includes built-in crosstalk exclusion comb filter chrominance signal that provides high-precision comb characteristics adjustment-free circuit. Peripheral circuits provided chip operation with minimum external components. Positive-phase signal input, positive-phase signal output (luminance signal)
SANYO: MFP14S
Functions
shift registers (for chrominance luminance signals) Timig generator clock driver Delay time selective circuit signal adder Auto-bias circuit Sync clamp circuit (luminance signal) Center bias circuit (chrominance signal) Sample-and-hold circuit frequency multiplier circuit 3fsc clock output circuit High voltage generator Reset Drain (RD)
Specifications
Absolute Maximum Ratings
Parameter Supply voltage Allowable power dissipation Operating temperature Storage temperature Symbol Topr Tstg Conditions Ratings -0.3 +6.0 +125 Unit
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, Chome, Ueno, Taito-ku, TOKYO, JAPAN
N3096HA(OT) 5545-1/7
LC89977M Allowable Operating Ranges
Parameter Supply voltage Clock input amplitude Clock frequency Chrominance signal input amplitude Luminance signal input amplitude Symbol VCLK FCLK VIN-C VIN-Y Sine wave Conditions Ratings 4.75 5.00 4.43361875 5.25 1000 Unit mVp-p mVp-p mVp-p
Assignment
Block Diagram
5545-2/7
LC89977M Control Functions
CONT High Mode (representative) PAL/GBI 4.43NTSC Chrominance signal delay (number stages) (1703.5) (845.5) Luminance signal delay (number stages) (848) (842)
Switching Voltage Levels
Parameter Switching voltage level: Switching voltage level: high Symbol Conditions Ratings -0.3 +0.5 Unit
Note: *Since control pins have built-in pull-down resistors (about leaving these pins opens effectively sets them level.
Function 3FSC This provides 3fsc clock signal generated frequency multiplier circuit.
Electrical Characteristics FCLK 4.43361875 MHz, VCLK mVp-p
Parameter Symbol IDD-1 IDD-2 VINC-1 output voltage VINC-2 VOUTC-1 VOUTC-2 Voltage gain GVC-1 GVC-2 CD-1 CD-2 LNC-1 LNC-2 LCK3C-1 LCK3C-2 LCK1C-1 LCK1C-2 NC-1 NC-2 ZOC-1 ZOC-2 TDC-1 TDC-2 Switch states Test conditions -0.3 Ratings Unit
Supply current
[Chrominance signal characteristics] (with input Y-IN)
Comb depth
Linearity
+0.3
Clock leakage (3fsc)
mVrms
Clock leakage (fsc)
mVrms
Noise
mVrms
Output impedance
delay time
Continued next page.
5545-3/7
LC89977M
Continued from preceding page.
Parameter Symbol Switch states Test conditions Ratings Unit
[Luminance signal characteristics] (With signals input C-IN1 C-IN2) VINY-1 output voltage VINY-2 VOUTY-1 VOUTY-2 Voltage gain GVY-1 GVY-2 GFY-1 GFY-2 DGY-1 DGY-2 DPY-1 DPY-2 LSY-1 LSY-2 LCK3Y-1 LCK3Y-2 LCK1Y-1 LCK1Y-2 NY-1 NY-2 ZOY-1 ZOY-2 TDY-1 TDY-2
Frequency response
Differential gain
Differential phase
Linearity
Clock leakage (3fsc)
mVrms
Clock leakage (fsc)
mVrms
Noise
mVrms
Output impedance
63.81 63.36
Delay time
Test Conditions supply current with input signal output voltage (the center bias voltage) with input signal Measure C-OUT output when 350-mVp-p sine wave input C-IN1 C-IN2. 20log C-OUT output [mVp-p] [mVp-p] [dB]
Test frequencies: GVC-1: 4.429662 (PAL/GBI) GVC-2: 4.425694 (4.43NTSC) Measure comb depth from C-OUT output when 350-mVp-p sine wave with frequency input C-IN1 C-IN2, when sine wave frequency input. [dB] C-OUT output input [mVp-p] Test Frequencies CD-1: 4.429662 4.425756 (PAL/GBI) 4.417819 (4.43NTSC) GD-2: 4.425694 20log C-OUT output input [mVp-p]
5545-4/7
LC89977M Measure C-OUT output when 200-mVp-p sine wave input C-IN1 C-IN2, when 500-mVp-p sine wave input, calculate gain difference follows: 20log
Test Frequencies LNC-1 4.429662MHz (PAL/GBI) LNC-2 4.425694MHz (4.43NTSC)
output 500-mVp-p input [mVp-p] [mVp-p]
output 200-mVp-p input [mVp-p] [mVp-p]
[dB]
Measure 3fsc (13.3 MHz) (4.43 MHz) components C-OUT output with input signal. Measure noise C-OUT output with input signal. Measure noise with noise meter with 200-kHz high-pass filter 5-MHz low-pass filter. Input 350-mVp-p sine wave C-IN1 C-IN2. C-OUT output when position, C-OUT output when position. [dB] [mVp-p] Test Frequencies ZOC-1: 4.429662 (PAL/GBI) ZOC-2: 4.425694 (4.43NTSC) delay time C-OUT output with respect C-IN1 input. This 1-bit delay. output voltage (clamp voltage) with input signal. Measure Y-OUT output with 200-kHz 400-mVp-p sine wave input Y-IN. 20log Y-OUT output [mVp-p] [mVp-p] [dB] [mVp-p] [mVp-p]
Measure Y-OUT output when 200-kHz 200-mVp-p sine wave input Y-IN, when 3.3-MHz 200-mVp-p sine wave input. 20log Y-OUT output 3.3-MHz input [mVp-p] Y-OUT output 200-kHz input [mVp-p] [dB]
Here, adjust Vbias that clamp level +250 Apply 5-step staircase wave figure below) Y-IN, measure differential gain differential phase Y-OUT output using vector scope.
5545-5/7
LC89977M Apply 5-step staircase wave figure below) Y-IN, measure luminance level sync level Y-OUT output. [mV] [mV]
Measure 3fsc (13.3 MHz) (4.43 MHz) components Y-OUT output with input signal. Measure noise Y-OUT output with input signal. Measure noise with noise meter with 200-kHz low-pass filter, 5-MHz low-pass filter, 4.43-MHz trap filter. Input 200-kHz, 400-mVp-p sine wave Y-IN1. V-OUT output when position, Y-OUT output when position. [mVp-p] [mVp-p] [mVp-p]
Measure delay time Y-OUT output with respect input Y-IN.
5545-6/7
LC89977M Test Circuit
products described contained herein intended surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment like, failure which directly indirectly cause injury, death property loss. Anyone purchasing products described contained herein above-mentioned shall: Accept full responsibility indemnify defend SANYO ELECTRIC CO., LTD., affiliates, subsidiaries distributors their officers employees, jointly severally, against claims litigation damages, cost expenses associated with such use: impose responsibility fault negligence which cited such claim litigation SANYO ELECTRIC CO., LTD., affiliates, subsidiaries distributors their officers employees jointly severally. Information (including circuit diagrams circuit parameters) herein example only; guaranteed volume production. SANYO believes information herein accurate reliable, guarantees made implied regarding infringements intellectual property rights other rights third parties. This catalog provides information August, 1997. Specifications information herein subject change without notice. 5545-7/7

LC89977M Delay Line Preliminary Overview LC89977M delay

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