LC78625E Compact Disc Player Overview LC78625E CMOS tha
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Ordering number EN5502
LC78625E
Compact Disc Player
Overview
LC78625E CMOS that implements signal processing servo control required compact disc players, laser discs, CD-V, CD-I related products. LC78625E provides several types signal processing, including demodulation optical pickup signal, de-interleaving, error detection correction, digital filters that help reduce cost player units. also processes rich servo system commands sent from control microprocessor. also incorporates EFM-PLL circuit one-bit converter. This improved version LC78620E. addition supporting low-voltage operation, on/off control de-emphasis function bilingual function have been enabled certain additional modes.
Demodulated signal buffering internal handle frames disc rotational jitter Demodulated signal reordering prescribed order data unscrambling de-interleaving Error detection, correction, flag processing (error correction scheme: dual plus dual correction) LC78625E sets flags based flags check, then performs signal interpolation muting depending flags. interpolation circuit uses quadruple interpolation scheme. output value converges muting level when four more consecutive flags occur.
Package Dimensions
unit:
3174-QFP80E
[LC78625E]
Functions
LC78625E takes signal input, digitizes (slices) that signal precise level, converts that signal signal, generates clock with average frequency 4.3218 comparing phases that signal internal VCO. precise reference clock necessary internal timings generated using external 16.9344 crystal oscillator. Disc motor speed control using frame phase difference signal generated from playback clock reference clock Frame synchronization signal detection, protection, interpolation assure stable data readout signal demodulation conversion 8-bit symbol data Subcode data separation from demodulated signal output that data external microprocessor Subcode signal output (LSB first) microprocessor over serial interface after performing error check
SANYO: QFP80E
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, Chome, Ueno, Taito-ku, TOKYO, JAPAN
22897HA (OT) 5502-1/35
LC78625E Support command input from control microprocessor: commands include track jump, focus start, disk motor start/stop, muting on/off track count (8-bit serial input) Built-in digital output circuits. Arbitrary track counting support high-speed data access converter outputs with data continuity improved oversampling digital filters. (These filters function oversampling filters during double-speed playback.) Built-in converter implemented third-order noise shaper circuit (for output) Built-in digital attenuator bits alpha, steps) Built-in digital de-emphasis circuit that controlled externally some modes Zero-cross muting Support dubbing Support bilingual applications General-purpose ports: pins (when antishock mode turned off)
Features
single-voltage power supply Low-voltage operation: operated ±10% normal playback speed) 80-pin package Equivalent Circuit Block Diagram
5502-2/35
LC78625E Assignment
Specifications
Absolute Maximum Ratings 25°C,
Parameter Maximum supply voltage Maximum input voltage Maximum output voltage Allowable power dissipation Operating temperature Storage temperature Symbol VOUT Topr Tstg Conditions Ratings +7.0 +125 Unit
Allowable Operating Ranges 25°C,
Parameter Symbol Supply voltage Conditions VDD, XVDD, LVDD, RVDD, VVDD normal playback speed VDD, XVDD, LVDD, RVDD, VVDD playback speed DEFI, FZD, ASDACK/P0, ASFIN/P1, ASDEPC/P2, ASLRCK/P3, COIN, RES, HFL, TES, SBCK, RWC, CQCK, TAI, TEST1 TEST5, DEMO, EFMIN DEFI, FZD, ASDACK/P0, ASFIN/P1, ASDEPC/P2, ASLRCK/P3, COIN, RES, HFL, TES, SBCK, RWC, CQCK, TAI, TEST1 TEST5, DEMO, EFMIN COIN, Figure COIN, Figure SBCK, CQCK Figuires SBCK, CQCK Figuires SQOUT, Figuires Ratings Unit
Input high-level voltage
Input low-level voltage
Data setup time Data hold time High-level clock pulse width Low-level clock pulse width Data read access time
tRAC
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LC78625E
Continued from preceding page.
Parameter Command transfer time Subcode read enable time Subcode read cycle Subcode read enable time Port input data setup time Port input data hold time Port input clock setup time Port output data delay time Input level Operating frequency range Crystal oscillator frequency Symbol tRWC tSQE tPSU tPHD tRCQ tPDD Figure WRQ: Figure with signal SFSY Figure SFSY Figure ASDACK/P0, ASFIN/P1, ASDEPC/P2, ASLRCK/P3, Figure ASDACK/P0, ASFIN/P1, ASDEPC/P2, ASLRCK/P3, Figure CQCK, Figure ASDACK/P0, ASFIN/P1, ASDEPC/P2, ASLRCK/P3, Figure EFMIN Capacitor coupled input EFMIN XIN, XOUT mode 16.9344 1200 Conditions Ratings 1000 11.2 Unit Vp-p Vp-p
Electrical Characteristics 25°C,
Parameter Current drain Symbol Input high-level current DEFI, EFMIN, FZD, ASDACK/P0, ASFIN/P1, ASDEPC/P2, ASLRCK/P3, COIN, RES, HFL, TES, SBCK, RWC, CQCK TAI, TEST1 TEST5, DEMO, DEFI, EFMIN, FZD, ASDACK/P0, ASFIN/P1, ASDEPC/P2, ASLRCK/P3, COIN, RES, HFL, TES, SBCK, RWC, CQCK, TAI, TEST1 TEST5, DEMO, EFMO, EFMO, CLV+, CLV-, V/P, FOCS, PCK, FSEQ, TOFF, TGL, THLD, JP+, JP-, EMPH, EFLG, MUTEL, MUTER, LRCKO, DFORO, DFOLO, DACKO, TST10, ASDACK/P0, ASFIN/P1, ASDEPC/P2, ASLRCK/P3, LRSY, CK2, ROMXA, C2F, SBSY, SFSY, WRQ, SQOUT, TST11, 16M, 4.2M, CONT -0.5 LASER DOUT LCHP, RCHP, LCHN, RCHN EFMO, EFMO, CLV+, CLV-, V/P, FOCS, PCK, FSEQ, TOFF, TGL, THLD, JP+, JP-, EMPH, EFLG, MUTEL, MUTER, LRCKO, DFORO, DFOLO, DACKO, TST10, ASDACK/P0, ASFIN/P1, ASDEPC/P2, ASLRCK/P3, LRSY, CK2, ROMXA, C2F, SBSY, SFSY, WRQ, SQOUT, TST11, 16M, 4.2M, CONT, LASER DOUT LCHP, RCHP, LCHN, RCHN PDO, CLV+, CLV-, JP+, JP-, VOUT PDO, CLV+, CLV-, JP+, RISET RISET
Conditions
Ratings
Unit
Input low-level current
Output high-level voltage
Output low-level voltage
Output leakage current IOFF IOFF Charge pump output current IPDOH IPDOL
0.75 -150 -125 -100
Note: guaranteed operation, oscillator frequency range adjustment resistor must 1.20 ±5.0% tolerance resistor.
5502-4/35
LC78625E One-Bit Converter Analog Characteristics 25°C, LVDD RVDD LVSS RVSS
Parameter Symbol Conditions LCHP, RCHP, LCHN, RCHN; kHz: data input, using low-pass filter (AD725D built LCHP, RCHP, LCHN, RCHN; kHz: data input, using low-pass filter filter (AD725D built LCHP, RCHP, LCHN, RCHN; kHz: data input, using low-pass filter filter (AD725D built LCHP, RCHP, LCHN, RCHN; kHz: data input, using low-pass filter (AD725D built Ratings 0.008 0.0010 Unit
Total harmonic distortion
Dynamic range
Signal-to-noise ratio
Crosstalk
Note: Measured with normal-speed playback mode digital attenuator Sanyo one-bit converter block reference circuit.
Figure Command Input
Figure Subcode Output
Figure Subcode Output
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LC78625E
Figure General-Purpose Port Input Timing
Figure General-Purpose Port Output Timing
5502-6/35
LC78625E One-Bit Converter Output Block Reference Circuit
5502-7/35
LC78625E Functions
Symbol DEFI VVSS ISET VVDD EFMO EFMO EFMIN TEST2 CLV+ CLV- FOCS FSEQ TOFF THLD TEST3 DEMO TEST4 EMPH LRCKO DFORO DFOLO DACKO TST10 Digital filter outputs Slice level control pins Function Defect detection signal (DEF) input (This must connected unused.) Test input. pull-down resistor built (This must connected normal operation.) External control phase comparator output Internal ground. (This must connected output current adjustment resistor connection Internal power supply. frequency range adjustment Digital system ground. (This must connected signal inverted output signal output signal input Test input. pull-down resistor built This must connected normal operation. Spindle servo control output. Acceleration when CLV+ high, deceleration when CLV- high. Three-value output also possible when specified microprocessor command. Rough servo/phase control automatic switching monitor output. Outputs high level during rough servo level during phase control. Focus servo on/off output. Focus servo when output low. Focus start pulse output. This open-drain output. Focus error zero cross signal input. (This must connected unused.) Track detection signal input. This Schmitt input. Tracking error signal input. This Schmitt input. data playback clock monitor. Outputs 4.3218 when phase locked. Synchronization signal detection output. Outputs high level when synchronization signal detected from signal internally generated synchronization signal agree. Tracking output Tracking gain switching output. Increase gain when low. Tracking hold output Test input. pull-down resistor built (This must connected Digital system power supply. Track jump output. high level output from indicates acceleration during outward jump deceleration during inward jump. high level output from indicates acceleration during inward jump deceleration during outward jump. Three-value output also possible when specified microprocessor command. Sound output function input used product adjustment manufacturing steps. pull-down resistor built (This must connected Test input. pull-down resistor built (This must connected De-emphasis monitor pin. high level indicates playback de-emphasis disk. Word clock output Right channel data output Left channel data output clock output Test output. Leave open. (Normally outputs level.)
Continued next page.
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LC78625E
Continued from preceding page.
Symbol ASDACK/P0 ASDFIN/P1 ASDEPC/P2 ASLRCK/P3 LRSY ROMXA MUTEL LVDD LCHP LCHN LVSS RVSS RCHN RCHP RVDD MUTER DOUT SBSY EFLG SFSY SBCK SQOUT COIN CQCK TST11 LASER 4.2M CONT TEST5 XVSS XOUT XVDD TEST1 Connections 16.9344 crystal oscillator Crystal oscillator power supply Test input. pull-down resistor built (This must connected Digital output Subcode block synchronization signal output single double error correction monitor Subcode output Subcode frame synchronization signal output. This signal falls when subcodes standby state. Subcode readout clock input. This Schmitt input. (This must connected unused.) Output 7.35 synchronization signal divided from crystal oscillator Subcode output standby output Read/write control input. This Schmitt input. Subcode output Command input from control microprocessor Input command input acquisition clock SQOUT subcode readout clock input. This Schmitt input. Reset input. This must briefly after power first applied. Test output. Leave open. (Normally outputs level.) Laser on/off output. Controlled serial data commands from control microprocessor. 16.9344 output 4.2336 output Supplementary control output. Controlled serial data commands from control microprocessor. Test input. pull-down resistor built (This must connected Chip select input. pull-down resistor built This must connected unused. Crystal oscillator ground. Must connected One-bit converter signals When antishock mode used, these pins used generalI/O purpose ports P3). They must either input mode connected output mode left open, unused. ROMXA application output signals Function clock input Left right channel data input antishock inputs antishock mode. Sets built-in de-emphasis filter off. (High: low: off) clock input clock output clock output (after reset) Interpolation data output (after reset) flag output Left channel mute output Left channel power supply Left channel output Left channel output Left channel ground. Must connected Right channel ground. Must connected Right channel output Right channel output Right channel power supply Right channel mute output Inverted polarity clock output (during CK2CON mode) data output (during ROMXA mode)
Note: power-supply pins (VDD, VVDD, LVDD, RVDD, XVDD) must connected same potential.
5502-9/35
LC78625E System Block Diagrams
Applications signal input circuit; EFMIN, EFMO, EFMO, DEFI, CLV+ signal (NRZ) sliced optimal level acquired inputting signal EFMIN. LC78625E handles defects follows. When high level input DEFI (pin EFMO (pin EFMO (pin pins (the slice level control outputs) high-impedance state, slice level held. However, note that this function only valid phase control mode, that when (pin low. This function used combination with LA9230/40 series pin. Note: EFMIN CLV+ signal lines close each other, unwanted adiation result error rate degradation. recommend laying ground shield line between these lines.
clock generation circuit; PDO, ISET, Since LC78625E includes circuit, circuit formed connecting external circuit. ISET charge pump reference current, circuit loop filter, resistor that determines frequency range. (Reference values) Note: recommend using ±5.0% tolerance carbon film resistor
5502-10/35
LC78625E monitor; monitor that outputs average frequency 4.3218 MHz, which frequency divided two. Synchronization detection monitor; FSEQ goes high when frame synchronization positive polarity synchronization signal) from signal read timing generated counter (the interpolation synchronization signal) agree. This thus synchronization detection monitor. held high single frame.) Servo command function; RWC, COIN, CQCK Commands executed setting high inputting commands COIN synchronization with CQCK clock. Note that commands executed falling edge RWC. Focus start Track jump Muting control Disc motor control Miscellaneous control Track check Digital attenuator General-purpose port data setup One-byte commands
byte commands
Two-byte command (RWC twice) Two-byte commands (RWC once)
Two-byte commands (RWC twice)
Two-byte commands (RWC once)
5502-11/35
LC78625E Command noise rejection
Code COMMAND Command input noise reduction mode Reset above mode.
This command reduces noise CQCK clock signal. While this effective noise pulses shorter than CQCK timings tWL, tWH, (see page figures must least Focus servo circuit; FOCS, FST, FZD, LASER
Code COMMAND FOCUS START FOCUS START LASER LASER NOTHING
FOCS, FST, pins required when LC78625E used combination with LA9230/40 Series LSI. should connected when these pins used. LA9230/40 Series focus start command identical LC78625E FOCUS START command. NOTHING This command used initialize LC78625E inputting (hexadecimal: Hexadecimal constants written with dollar sign prefix). Note that reset command LA9230/40 Series, should used with care since clears result automatic adjustment process returns these chips their initial states. Laser control LASER extended output port.
Focus start When LC78625E used combination with LA9230/40 Series LSI, focus start operation executed completely servo side commands from control microprocessor. following section describes this operation when LC78625E used combination with LA9210M LA9211M. When focus start instruction (either FOCUS START FOCUS START input servo command, first charge capacitor discharged objective lens lowered. Next, capacitor charged FOCS, lens slowly raised. falls when lens reaches focus point. When this signal received, FOCS reset focus servo turns After sending command, microprocessor should check in-focus detection signal (the LA9210 signal) confirm focus before proceeding next part program. focus achieved time fully charged, microprocessor should issue another focus command iterate focus servo operation.
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LC78625E
Note:* Values parentheses FOCUS START command. only difference period. falling edge will accepted during period that low. After issuing focus start command, initialization will performed high. Therefore, issue next command during focus start until focus coil drive curve completed. When focus cannot achieved (i.e., when does low) FOCS signal will remain high state lens will remain raised, microprocessor should initialize system issuing NOTHING command. When low, LASER high directly. Focus start using DEMO executes mode focus start.
5502-13/35
LC78625E servo circuit; CLV+, CLV-,
Code COMMAND DISC MOTOR START (accelerate) DISC MOTOR (CLV) DISC MOTOR BRAKE (decelerate) DISC MOTOR STOP (stop)
CLV+ provides signal that accelerates disk forward direction CLV- provides signal that decelerates disk. Commands from control microprocessor select four modes accelerate, decelerate, stop. table below lists CLV+ CLV- outputs each these modes.
Mode Accelerate Decelerate Stop CLV+ Pulse output CLV- Pulse output
Note: servo control commands TOFF only mode. That will high level other times. Control TOFF microprocessor command only valid mode.
mode mode LC78625E detects disk speed from signal provides proper linear speed using several different control schemes switching internal modes. period corresponds frequency 7.35 kHz. outputs high level during rough servo level during phase control.
Internal Mode Rough servo (When determined under speed) Rough servo (When determined over speed) Phase control (PCK locked) CLV+ CLV-
Rough servo gain switching
Code COMMAND DISC DISC
discs, rough servo mode control gain about lower than gain used discs.
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LC78625E Phase control gain switching
Code COMMAND phase comparator divisor: phase comparator divisor: phase comparator divisor: phase comparator divisor used
phase control gain changed changing divisor used dividers stage immediately preceding phase comparator.
three-value output
Code COMMAND three-value output two-value output (the scheme used previous products)
three-value output command allows controlled single pin. However, spindle gain lower when this used, applications must increase gain servo system.
5502-15/35
LC78625E Internal brake modes
Code COMMAND Internal brake Internal brake Internal brake CONT Internal brake continuous mode Reset continuous mode mode during internal braking Reset mode
Issuing internal brake command ($C5) sets LC78625E internal brake mode. this mode, disc deceleration state monitored from when brake command ($06) executed. this mode disc deceleration state determined counting signal density single frame, when signal count falls under four, CLV- dropped low. same time signal, which functions brake completion monitor, goes high. When microprocessor detects high level signal, should issue STOP command fully stop disc. internal brake continuous mode, CLV- high-level output braking operation continues even after brake completion monitor goes high. Note that errors occur deceleration state determination noise signal, problem rectified changing signal count from four eight with internal brake control command ($A3). internal braking mode, TOFF held during internal brake operations. recommend using this feature, since effective preventing incorrect detection disc mirror surface.
Note:
focus lost during execution internal brake command, pickup must first refocussed then internal brake command must reissued. Since incorrect deceleration state determination possible depending signal playback state (e.g., disc defects, access progress), recommend using these functions combination with microprocessor.
Track jump circuit; HFL, TES, TOFF, TGL, THLD, JP+, LC78625E supports track count modes listed below.
Code COMMAND track count mode (using TES/HFL combination) Previous track count mode (directly counts signal)
earlier track count function uses signal directly internal track counter clock. reduce counting errors resulting from noise rising falling edges signal, track count function prevents noise induced errors using combination signals, implements more reliable track count function. However, dirt scratches disc result signal dropouts that result missing track count pulses. Thus care required when using this function.
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LC78625E commands
Code COMMAND Previous track jump track jump TRACK JUMP TRACK JUMP TRACK JUMP TRACK JUMP TRACK JUMP TRACK JUMP TRACK JUMP TRACK JUMP TRACK JUMP TRACK JUMP TRACK JUMP TRACK JUMP TRACK JUMP TRACK JUMP TRACK JUMP TRACK JUMP TRACK JUMP TRACK JUMP TRACK JUMP TRACK JUMP TRACK CHECK TOFF TRACK JUMP BRAKE THLD period TOFF output mode Reset THLD period TOFF output mode
When LC78625E receives track jump instruction servo command, first generates accelerating pulses (period next generates deceleration pulses (period passage braking period (period completes specified jump. During braking period, LC78625E detects beam slip direction from inputs. TOFF used components signal that aggravate slip. jump destination track captured increasing servo gain with TGL. THLD period TOFF output mode TOFF signal held high during period when THLD high. Note: modes related disc motor control, TOFF only goes mode, will high during start, stop, brake operations. Note that TOFF turned independently microprocessor issued commands. However, this function only valid when disc motor control mode.
5502-17/35
LC78625E Track jump modes table lists relationships between acceleration pulses, deceleration pulses, braking period.
Previous Track Jump Mode Item TRACK JUMP (OUT) TRACK JUMP (OUT) TRACK JUMP (OUT) TRACK JUMP (OUT) TRACK JUMP (OUT) TRACK JUMP (OUT) TRACK JUMP (OUT) TRACK JUMP (OUT) TRACK JUMP (OUT) TRACK JUMP (OUT) track jump period track jump period track jump period track jump period track jump period track jump period track jump period track jump period None track jump period track jump period track jump period track jump period This period does exist. TOFF during period. track jump period track jump period track jump period track jump period track jump period track jump period track jump period track jump period track jump period Track Jump Mode track jump period track jump period track jump period track jump period track jump period track jump period track jump period track jump period track jump period This period does exist. TOFF during period. note.
TRACK CHECK TRACK JUMP BRAKE
TOFF goes high during period when tracks passed over. pulses output. There periods.
TOFF goes high during period when tracks passed over. pulses output. There periods.
Note:* Applications select whether braking period (period present. Code selects operation without braking period, code selects operation with 60-ms braking period. LC78625E defaults braking period operation after reset. indicated table, actuator signals output during TRACK CHECK function. This mode which signal counted tracking loop state. Therefore, feed motor forwarding required. servo command register automatically reset after cycle track jump sequence completes. another track jump command issued during track jump operation, contents that command will executed immediately. TRACK JUMP TRACK JUMP modes (the earlier modes) have braking period (the period). Since brake mode must generated external circuit, care required when using this mode.
When LC78625E used combination with LA9230/40 Series LSI, since THLD signal generated LA9230/40, THLD (pin will unused, should left open.
5502-18/35
LC78625E Tracking brake chart shows relationships between TES, HFL, TOFF signals during track jump period. TOFF signal extracted from signal signal edges. When signal high, pickup over mirror surface, when low, pickup over data bits. Thus braking applied based TOFF signal being high when pickup moving from mirror region data region being when pickup moving from data region mirror region.
three-value output
Code COMMAND three-value output two-value output (earlier scheme)
three value output command allows track jump operation controlled from single pin. However, kick gain lower when this used, applications must increase gain servo system.
Track check mode
Code COMMAND Track check Track check Two-byte command reset
LC78625E will count specified number tracks when microprocessor sends arbitrary binary value range after issuing either track check track check command.
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LC78625E
Note:*When desired track count been input binary, track check operation started fall RWC. During track check operation TOFF goes high tracking loop turned off. Therefore, feed motor forwarding required. When track check in/out command issued function signal switches from normal mode subcode standby monitor function track check monitor function. This signal goes high when track check half completed, goes when check finishes. control microprocessor should monitor this signal level determine when track check completes. two-byte reset command issued, track check operation will repeat. That skip over 20,000 tracks, issue track check command once, then count signal times. This will check 20,000 tracks. After performing track check operation, brake command have pickup lock onto track.
Error flag output; EFLG,
signal generated dividing crystal oscillator clock, 7.35 frame synchronization signal. error correction state each frame output from EFLG. playback OK/NG state easily determined from extent high level that appears here. Subcode output circuit; SBSY, SFSY, SBCK subcode signal output pin, codes, read sending eight clocks SBCK within after fall SFSY. signal that appears changes rising edge SBCK. clock applied SBCK, code will output from SFSY signal that output each subcode frame cycle, falling edge this signal indicates standby output subcode symbol Subcode data output fall this signal.
SBSY signal output each subcode block. This signal goes high synchronization signals. fall this signal indicates subcode synchronization signals start data subcode block. (EIAJ format)
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LC78625E Subcode output circuit; WRQ, RWC, SQOUT, CQCK,
Code COMMAND ADDRESS FREE ADDRESS
Subcode read from SQOUT applying clock CQCK pin. eight bits subcode, signal used song (track) access display. will high only data passed error check subcode format internal address (Note control microprocessor read data from SQOUT order shown below detecting this high level applying CQCK. When CQCK applied disables register update internally. microprocessor should give update permission setting high briefly after reading completed. will fall this time. Since falls 11.2 after going high, CQCK must applied during high period. Note that data read first.
Note: These conditions will ignored address free command sent. This provided handle CD-ROM applications.
CONT INDEX (POINT)* FRAME ZERO
Items parentheses refer read-in area.
AMIN (PMIN)* /PKMIN ASEC (PSEC)* /PKSEC AFRAME (PFRAME)* /PKFRAME LVM/PKM 16-bit data data/PKM data data/PKM data
Note: Normally, indicates subcode standby state. However, used different monitoring purpose track check mode during internal braking. (See items track counting internal braking details.) LC78625E becomes active when low, subcode data output from SQOUT pin. When high, SQOUT goes high-impedance state.
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LC78625E Level meter (LVM) data peak meter (PKM) data readout
Code COMMAND (LVM Reset) (PKM Reset) mask mask reset
Level meter (LVM) command ($2C) sets LC78625E mode. data 16-bit word which indicates polarity low-order bits absolute value data. indicates left channel data zero indicates right channel data. data appended after bits subcode data, read applying clock cycles CQCK pin. Each time data read left/right channel state inverted. Data held independently both left right channels. particular, largest value that occurs between readouts each channel held. Peak meter (PKM) command ($2B) sets LC78625E mode. data 16-bit word which always zero low-order bits absolute value data. This functions detects maximum value that occurs data, whichever channel that value occurs data read same manner data. However, data updated result readout operation. absolute time mode subcode data computed holding absolute time (ATIME) detected after maximum value occurred sending that value. (Normal operation uses relative time.) possible LC78625E ignore values larger than already recorded value issuing mask command, even mode. This function cleared issuing mask reset command. (This used search memory track.) Mute control circuit
Code COMMAND MUTE MUTE MUTE
attenuation (MUTE full muting (MUTE applied issuing appropriate command from table. Since zero cross muting used, there minimal noise associated with this function. Zero cross defined this function seven bits being ones zeros. Interpolation circuit Outputting incorrect audio data that could corrected error detection correction circuit would result loud noises being output. minimize this noise, LC78625E replaces incorrect data with linearly interpolated data based correct data either side incorrect data. More precisely, LC78625E uses this technique flags occurred three times row. flags occurred four more times row, LC78625E converges output level muting level. However, when correct data finally output following four more flag occurrences, LC78625E replaces data items between data output four items previously correct data with linearly interpolated data.
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LC78625E Bilingual function
Code COMMAND CONT CONT CONT
Following reset when stereo command ($28) been issued, left right channel data output left right channels respectively. When command ($29) issued, left right channels both output left channel data. When command ($2A) issued, left right channels both output right channel data. De-emphasis; EMPH pre-emphasis on/off subcode control information output from EMPH pin. When this high, LC78625E internal de-emphasis circuit operates digital filters converter output deemphasized data. Digital attenuator Digital attenuation applied audio data setting high inputting corresponding twobyte command COIN synchronization with CQCK clock.
Code COMMAND DATA 4STEP 4STEP 8STEP 8STEP 16STEP 16STEP DOWN DOWN DOWN DATA (MUTE -dB)
Attenuation setup Since attenuation level muted state muting specified attenuation coefficient 00H) after LC78625E reset, attenuation coefficient must directly (using DATA command) output audio signals. Note that attenuation level values from EEH. These two-byte commands differ from two-byte commands used track counting that only necessary once two-byte command reset required. (See item two-byte commands (RWC once) page 11.)
After inputting target attenuation level value range EEH, sending attenuator step up/down command will cause attenuation level approach target value steps units specified synchronization with rising edges LRSY input. However, DATA command sets target value directly. data value input during transition, value begins approach target value that point. Note that UP/DOWN distinction significant here.
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LC78625E
DATA Audio output level 100H
[dB]
example, formula below calculates time required attenuation level increase from when 4STEP command executed. Note that control microprocessor must provide enough time margin this operation complete before issuing next attenuation level command. levels steps =21.6 44.1 (LRSY)
Note: Setting attenuation level values higher disallowed prevent overflows one-bit converter calculations from causing noise.
Mute output; MUTEL, MUTER These pins output high level when attenuator coefficient data each channel been zero certain period. data input occurs once again, these pins immediately. Digital filter outputs; LRCKO, DFORO, DFOLO, DACKO Data with external converter output first from DFORO DFOLO synchronization with falling edge DACKO. These pins provided that external converter used desired.
Although this output from oversampling filters normal-speed playback, digital oversampling filters used double-speed playback.
5502-24/35
LC78625E One-bit converter LC78625E block outputs single data value range once every 64fs period. reduce carrier noise, this block adopts output format which each data switching block adjusted that output level does invert. Also, attenuator block detects data enters muting mode that only value duty signal) output. This block outputs positive phase signal LCHP (RCHP) negative phase signal LCHN (RCHN) pin. High-quality analog signals acquired taking differences these output pairs using external low-pass filters. LC78625E includes built-in extraneous radiation suppression resistors each LCHP/N RCHP/N pins. output format
output example
CD-ROM outputs; LRSY, CK2, ROMXA, Although LC78625E initially setup output audio data from interpolation circuit first from ROMXA synchronization with LRSY signal, circuit switched output CD-ROM data issuing CD-ROM command. Since this data been processed interpolation, muting, other digital circuits, appropriate input CD-ROM encoder LSI. 2.1168 clock, data output falling edge. However, this clock polarity inverted issuing polarity inversion command. flag information data 8-bit units. Note that CD-ROM reset command same function CONT (pin 73). one-bit converter switches muted mode when CD-ROMXA command input.
Code COMMAND CD-ROMXA CONT CD-ROM reset polarity inversion
LC78625E CD-ROM encoder (LC895XX) interface
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LC78625E Digital output circuit; DOUT This output with digital audio interface. Data output EIAJ format. This signal been processed interpolation muting circuits. This built-in driver circuit directly drive transformer.
Code COMMAND DOUT DOUT
UBIT UBIT
DOUT locked level issuing DOUT command. UBIT information DOUT data locked zero issuing UBIT command. DOUT data switched data which interpolation muting processing have been performed issuing CD-ROM command. Antishock mode; ASDACK, ASDFIN, ASDEPC, ADLRCK, LRSY, CK2, ROMXA, Antishock mode mode which antishock processing applied data that been output once. That data returned output once again audio playback signal. also possible only audio playback block (the attenuator, oversampling digital filter, one-bit converter circuits) thus share audio playback block with other systems synchronizing other system with this LSI's clock. Note that de-emphasis on/off switching controlled level applied ASDEPC pin. De-emphasis turned high level. ASDACK (pin 38), ASDFIN (pin 39), ASDEPC (pin 40), ASLRCK (pin pins used generalpurpose ports (see page this mode used.
Code COMMAND ANTIC ANTIC
normal speed (only antishock mode) normal speed (only antishock mode)
possible input signals from ROMXA (pin 44), (pin 45), LRSY (pin 42), (pin pins antishock (the Sanyo LC89151) re-input signals output antishock ASDFIN (pin 39), ASLRCK (pin 41), ASDACK (pin pins. These signals then processed attenuator, oversampling digital filter, one-bit converter circuits output audio signals.
antishock systems, signal-processing block must operate double-speed playback mode data output antishock LSI, audio playback block (the attenuator, oversampling digital filter, one-bit converter circuits) must operate normal speed. This means that control microprocessor must issue both ANTIC command ($6C) well normal speed command ($6F). ANTIC command ($6B) clears antishock mode.
5502-26/35
LC78625E Note that LC78625E adds general-purpose port function that shares ASDACK, ASDFIN, ASDEPC, ASLRCK pins. Applications that LC78625E with antishock mode turned must (ASDACK), (ASDFIN), (ASDEPC), (ASLRCK) pins input mode issuing port switching command ($DB0x). this case,Pins cannot used input pins. default state following reset, pins input ports. only data that handled this circuit digital data input interface antishock mode data that 48fs clock rate, 16-bit data length, MSB-first format, back-packed format. figure below shows timing.
General-purpose ports; When antichock mode used, pins used general-purpose ports After reset, these pins input ports. Unused ports must either left input ports connected output ports left open.
Code COMMAND PORT READ PORT PORT OUTPUT PORT
port data read order then from SQOUT synchronization with falling edges CQCK issuing PORT READ command. This command one-byte command format.
Another point here that these pins independently used control output pins with PORT command. ports selected with lower bits byte data. byte data corresponds starting with order bit. This command two-byte command format (RWC once). byte data PORT
Sets output pin. Sets input pin. Ports output pins independently output either high level. order bits byte data correspond those ports. byte data corresponds starting with low-order bit. This command two-byte command format (RWC once). byte data PORT
Outputs high level from which output. Outputs level from which output.
5502-27/35
LC78625E CONT pin; CONT
Code COMMAND CONT CONT CD-ROM reset
CONT goes high when CONT command issued. Clock oscillator; XIN, XOUT
Code COMMAND XTAL Normal-speed playback Double-speed playback
clock that used time base generated connecting 16.9344 oscillator element between these pins. command turns both crystal oscillators. Double-speed playback specified microprocessor command.
Connect 16.9344 oscillator element between (pin XOUT (pin pins double-speed systems. playback speed normal-speed playback double-speed playback commands. Recommended crystal ceramic oscillator elements
Load capacitance Cin/Cout (Cin Cout) (±10%) (±10%) (Built-in capacitor type) Damping resistor (±10%) (±10%)
Manufacturer Citizen Watch Co., Ltd. (crystal oscillator elements) TDK, Ltd. (ceramic oscillator elements)
Product CSA-309 (16.9344 MHz) 16.93M2G (16.93 MHz) 16.93MCG (16.93 MHz)
Since conditions load capacitors Cout used vary with printed circuit board, this circuit must tested printed circuit board actually used. 4.2M pins; 16M, 4.2M normal- double-speed playback modes, buffer outputs 16.9344 external crystal oscillator 16.9344 signal. 4.2M supplies LA9230/40 Series system clock, continuously outputting 4.2336 signal. When oscillator turned both these pins will fixed either high low.
5502-28/35
LC78625E Reset circuit; When power first applied, this should briefly then high. This will muting stop disc motor.
servo related Muting control Subcode address condition Laser control CONT Track jump mode Track count mode Digital attenuator Playback speed Antishock mode Digital filter normal speed Note: START Address Previous Previous DATA Normal speed STOP Address Free DATA Double speed BRAKE
Setting sets LC78625E settings enclosed boxes table.
Sound output function adjustment during manufacturing; DEMO
DEMO used when LC78625E used combination with LA9210M LA9211M. setting this high, muting disc motor CLV, focus start operation performed, even without issuing commands from control microprocessor. Also, since LASER becomes active, mechanism servo systems complete, signal acquired with only this equipment, audio signal produced without presence microprocessor. However, since digital attenuation 100H, this technique appropriate evaluating audio quality.
5502-29/35
LC78625E Other pins; 2:TAI, TEST1, TEST2, TEST3, TEST4, TEST5 These pins used testing LSI's internal circuits. Although pins TEST1 TEST5 have built-in pull-down resistors, they should connected ground safety. Circuit Block Operating Descriptions address control LC78625E incorporates 8-bit 2k-word chip. This demodulated data jitter handling capacity frames implemented using address control. LC78625E continuously checks remaining buffer capacity controls data write address fall center buffer capacity making fine adjustments frequency divisor side servo circuit. frame buffer capacity exceeded, LC78625E forcibly sets write address position. However, since errors that occur this operation cannot handled with error flag processing, applies muting output frame period.
Position lower greater Divisor Handling Forcibly moves Forcibly moves Decreasing divisors Standard divisor Advancing divisors
error correction LC78625E writes demodulated data internal compensate jitter then performs following processing with uniform timing based crystal oscillator clock. First, LC78625E performs error checking correction block, determines flags, writes flag register. Next, LC78625E performs error checking correction block, determines flags, writes data internal RAM.
Check errors Single error Dual errors Three more errors Correction Flag Processing Correction required flags cleared Correction performed flags cleared Correction performed flags Correction possible flags
Check errors Single error Dual errors Three more errors
Correction Flag Processing Correction required flags cleared Correction performed flags cleared flags referenced. Note flags referenced. Note
Note: positions errors determined check agree with those specified flags, correction performed flags cleared. However, number flags higher, correction fail. this case correction performed flags taken flags without change. Error correction possible error position agrees other does not. Furthermore, number flags under, check result seen unreliable. Accordingly, flags will this case. Cases where number flags more handled same way, flags taken flags without change. When there even agreement between error positions, error correction course, impossible. Here, number flags under, data that seen correct after correction seen incorrect data. flags this case. other cases, flags taken flags without change. When data determined have three more errors uncorrectable, correction course, impossible. Here, number flags under, data that seen correct after correction seen incorrect data. flags this case. other cases flags taken flags without change.
5502-30/35
LC78625E Command Summary Table Blank entry: Illegal command, Command added since changed from LC78620/1E specifications, Latching commands (mode setting commands), Commands shared with (LA9230M/31M other processor), Items parentheses commands (provided reference purposes)
CONT TRACKING 16TJ 64TJ 256TC 128TJ 16TJ 64TJ (ADJ. RESET) MUTE MUTE MUTE DISC START DISC DISC BRAKE DISC STOP FOCUS START ADDRESS FREE LASER CONT CONT CONT RESET TOFF TOFF TRACK COUNT TRACK COUNT UBIT UBIT DOUT DOUT normal speed normal speed ANTIC "OFF" ANTIC "ON"
32TJ
32TJ
128TJ
Continued next page.
5502-31/35
LC78625E
Continued from preceding page.
DATA 4STP 4STP 8STP 8STP 16STP 16STP CDROMXA ADDRESS LASER CONT, ROMXA TRACK TRACKING OFF. ADJ. OFF. ADJ. OFF) OFF. ADJ. OFF. ADj. OFF) (LSR. (LSR. OF/F. (LSR. OF/F. (SP. 8CM) (SP. 12CM) (SP. OFF) (SLED. (SLED. OFF) (EF. BAL. START) SERVO. OFF) SERVO. CLV-PH mode CLV-PH mode CLV-PH mode CLV-PH mode CLV3ST output CLV3ST output JP3ST output JP3ST output *PLL *PLL DISC DISC TRACK TRACK FOCS START Internal BRKE CONT *PORT OP-ED *PORT DATA polarity inverted Internal BRK-DMC Internal BRK-DMC Internal TOFF Internal XTAL Internal Internal Double speed Normal speed NOTHING 2BYTE period mode period present mode TRACK CHECK (2BYTE DETECT) Command noise Command noise TRACK CHECK (2BYTE DETECT)
Note: supplementary command low-voltage operation.
5502-32/35
LC78625E Sample Application Circuit
5502-33/35
LC78625E Differences between LC78625E LC78620E
LC78625E Item Content change Bilingual processing antishock input data possible antishock mode. same bilingual control commands those used LC78620E used. Bilingual function (Command code) $28: $29: $2A: (Command mode) Stereo output (Initial state after reset) Both left right output left channel Both left right output right channel LC78620E
bilingual processing function provided antishock input data antishock mode.
de-emphasis filters turned input level ASDEPC/P2 antishock mode. De-emphasis function (ASDEPC/P2) (De-emphasis filter) on/off state de-emphasis filter cannot controlled from external pin.
High level applied: level applied: command added that allows presence absence braking period (the period) selected during two-track jumps (new track jump mode only). Track jump function (Command code) $F6: $F7: period) None (Initial state after reset) Present
There period during two-track jumps track jump mode).
When antishock mode used, antishock input pins used general-purpose pins. support this functionality, names were changed commands were added. (These command codes identical those LC78622E.) name changes: (LC78625E) ASDACK/P0 ASDFIN/P1 ASDEPC/P2 ADLRCK/P3 General-purpose ports added Added commands: $DB0X: switching command bytes) $DC0Y: Port output data setup command bytes) $DD: Port input command byte) Here represent 4-bit data items that control order starting with order bit. zero specifies input specifies output. (These pins default input after reset.) zero specifies low-level output, specifies high-level output. frequency range increased over that supported LC78620E. (The range identical that LC78622E) This resulted change value resistor used pin: Addition supplementary command low-voltage operation. circuit $AC: DIVIDER (Low-voltage operation supplementary command) $AD: DIVIDER (Initial state after reset) such commands supported. (LC78620E) ASDACK ASDFIN ASDFIR ASLRCK There general-purpose ports.
circuit
resistor connected pin.
5502-34/35
LC78625E Digital Signal Processor Functional Comparison
Type LC7860KA Function EFM-PLL 16KRAM Digital outputs Interpolation Zero cross muting Level meter peak search Bilingual function Digital attenuator Digital de-emphasis One-bit converter LC7861NE LC7861KE LC7867E LC7868E LC7868KE LC7869E LC78681E LC78681KE LC78620E LC78621E LC78625E Built-in
When used along When used along When used along When used along When used along When used along with analog ASP. with analog ASP. with analog ASP. with analog ASP. with analog ASP. with analog ASP. External
products described contained herein intended surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment like, failure which directly indirectly cause injury, death property loss. Anyone purchasing products described contained herein above-mentioned shall: Accept full responsibility indemnify defend SANYO ELECTRIC CO., LTD., affiliates, subsidiaries distributors their officers employees, jointly severally, against claims litigation damages, cost expenses associated with such use: impose responsibility fault negligence which cited such claim litigation SANYO ELECTRIC CO., LTD., affiliates, subsidiaries distributors their officers employees jointly severally. Information (including circuit diagrams circuit parameters) herein example only; guaranteed volume production. SANYO believes information herein accurate reliable, guarantees made implied regarding infringements intellectual property rights other rights third parties. This catalog provides information February, 1997. Specifications information herein subject change without notice. 5502-35/35
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