LC78711E Graphics Display Processor Overview LC78711E C
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Ordering number EN5476
LC78711E
Graphics Display Processor
Overview
LC78711E CMOS that provides graphics display drawing functions. addition implementing graphics display NTSC signals, provides 32-dot sprite display patterns easily implement wide range displays.
Package Dimensions
unit: 3159-QFP64E
[LC78711E]
Features
Two-chip structure consisting this LSI, LC78711E, external 64-K 4-bit RAM. encoder built in.) Graphics drawing controlled microprocessor over serial interface. Includes crystal oscillator systems, NTSC PAL, these system easily switched using provided control pin. standard clocks necessary internal timings generated connecting crystals, 14.31818-MHz crystal NTSC, 17.734476-MHz crystal PAL. 32-dot sprite patterns provided. sprites displayed, either different types same pattern different locations. colors from palette 4096 colors displayed graphics screens, seven colors displayed sprite patterns. signal outputs (two 8-bit converter outputs) Supports superimpose function, provides timing signal output. Provides color signal output function. Adopts 8-bit serial data input format external control input.
SANYO: QFP64E
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, Chome, Ueno, Taito-ku, TOKYO, JAPAN
63096HA (OT) 5476-1/43
LC78711E Assignment
Specifications
Absolute Maximum Ratings
Parameter Maximum supply voltage Symbol AVDD1, DVDD1 Conditions Ratings Unit
Maximum input voltage
TEST1, TEST2, TEST4, TEST5, TEST6, TEST7, DB3, LINE, FSCIN, TEST9, 4FSC2, TEST12, PALID, HRESET, VRESET, INIT, RESET, N/P1, N/P2, SON, XIN1, XIN2 TEST3, PSC1, PSC2, WAIT, INT, RAS, DB3, CAS, TEST8, BFP, VSYNC, CSYNC, TEST10, TEST11, FSC0, XOUT1, XOUT2 25°C +125
Maximum output voltage Allowable power dissipation Operating temperature Storage temperature
VOUT Topr Tstg
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LC78711E Allowable Operating Ranges
Parameter Supply voltage Symbol VIH1 Input high-level voltage VIH2 VIH3 VIL1 Input low-level voltage VIL2 VIL3 FSCIN1 FSCIN2 Input frequency FSCIN3 FSCIN4 Input amplitude VIN1 VIN2 AVDD1, DVDD1 TEST1, TEST2, TEST4, TEST5, TEST6, TEST7, LINE, TEST9, TEST12, PALID, HRESET, VRESET, N/P1, N/P2, INIT, RESET TEST1, TEST2, TEST4, TEST5, TEST6, TEST7, LINE, TEST9, TEST12, PALID, HRESET, VRESET, N/P1, N/P2, INIT, RESET XIN1 XIN2 4FSC2: NTSC mode 4FSC2: mode FSCIN: NTSC mode FSCIN: mode FSCIN, 4FCS2 XIN1, XIN2 Conditions Ratings VDD1 VDD1 VSS1 VSS1 VSS1 14.31818 17.73447 14.31818 17.73447 3.57954 4.43361 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 Unit Vp-p Vp-p
Electrical Characteristics DVDD1 AVDD1 unless otherwise specified.
Parameter Symbol Conditions TEST1, TEST2, TEST4, TEST5, TEST6, TEST7, DB3, LINE, PALID, HRESET, VRESET, INIT, RESET, N/P1, N/P2, SON: DVDD1 TEST9, TEST12: DVDD1 TEST1, TEST2, TEST4, TEST5, TEST6, TEST7, DB3, LINE, TEST9, TEST12, HRESET, VRESET, INIT, RESET, N/P1, N/P2, SON: DVSS1 PALID: DVSS1 TEST3, PSC1, PSC2, WAIT, INT, BFP, RAS, CAS, DB3, TEST8, VSYNC, CSYNC, TEST10, TEST11, FSCO: -0.5 TEST3, PSC1, PSC2, WAIT, INT, BFP, RAS, CAS, DB3, TEST8, VSYNC, CSYNC, TEST10, TEST11, FSCO: XIN1, XIN2, FSCIN, 4FSC2 FSCIN, 4FSC2 VIDEO1, VIDEO2 VIDEO1, VIDEO2 AVDD1 DVDD1 2.30 Ratings Unit
Input high-level current
IIH1 IIH2
Input low-level current
IIL1 IIL2
-200 VDD1
-100
VDD1
Output high-level voltage
Output low-level voltage Output leakage current Internal feedback resistance Clock duty 8-bit converter reference voltage 8-bit converter output resistance Operating current drain
IOFF fduty VREF IDD1 IDD2
2.50
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LC78711E Electrical Characteristics Fscp 15.625
Parameter Symbol tDOS tWT1 tWT2 tWORD Conditions high-level pulse width low-level pulse width Serial data acquisition time Serial data restart time word bits) 1.35 Ratings Unit
Minimum input pulse width Data setup time Data hold time setup time hold time setup time Data acquisition time Data restart time Single word write time
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LC78711E Basic Specifications
TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 DVDD1 PSC1 PSC2 WAIT TEST7 DVSS1 TEST8 AVSS1 AVDD1 VIDEO1 BIAS VIDEO2 LINE FSCIN VSYNC TEST9 CSYNC 4FSC2 TEST10 TEST11 Test input Test input Test output Test input Test input Test input Power supply Enable input Data output Data input Clock input Monitor output Monitor output Wait signal output Wait signal output Test input Ground DRAM output DRAM output DRAM output DRAM output DRAM output DRAM output DRAM output DRAM output DRAM output DRAM output DRAM input output DRAM output DRAM input output DRAM output DRAM input output DRAM input output Color selection Test output Ground Power supply Video signal output Capacitor connection Video signal output Burst flag signal output Line count selection Clock input Vertical synchronization output Test input Superimpose output Composite synchronization output Clock input Test output Test output type Polarity Positive Positive Positive Positive Positive Positive Positive Positive Positive Positive Positive Positive Negative Negative Positive Negative Negative Positive Positive Positive Positive Positive Positive Positive Positive Positive Negative Positive Negative Positive Positive Positive Positive Positive Positive Negative Positive Negative Negative Positive Positive Positive function Test input. Must connected ground during normal operation. Test input. Must connected ground during normal operation. Test output Test input. Must connected ground during normal operation. Test input. Must connected ground during normal operation. Test input. Must connected ground during normal operation. Digital system power supply Serial data control input Serial data output Serial data input Serial data clock input Serial input monitor signal output Command monitor signal output Serial input wait signal output (for with maps) Serial input wait signal output (for with sprite function) Test input. Must connected ground during normal operation. Digital system ground DRAM write enable signal output DRAM address strobe signal output DRAM address (A0) output (Functions input test mode.) DRAM address (A1) output (Functions input test mode.) DRAM address (A2) output (Functions input test mode.) DRAM address (A3) output (Functions input test mode.) DRAM address (A4) output (Functions input test mode.) DRAM address (A5) output (Functions input test mode.) DRAM address (A6) output (Functions input test mode.) DRAM address (A7) output (Functions input test mode.) DRAM data (D0) input output DRAM column address strobe signal output DRAM data (D1) input output DRAM read enable signal output DRAM data (D2) input output DRAM data (D3) input output Low: normal mode, high: color output pull-down resistor built in.) Test output Analog system ground Analog system power supply Video (luminance) signal (analog) output (D/A converter output) Connections ripple exclusion capacitor Video (chrominance) signal (analog) output (D/A converter output) Burst signal output timing flag output Line count selection NTSC mode Low: 263H, high: 262H mode Low: 314H, high: 312H Superimpose subcarrier clock input feedback resistor built in.) Vertical synchronizing signal output Test input. Must connected ground during normal operation. pull-down resistor built in.) Superimpose control output Composite synchronizing signal output External clock input superimpose function feedback resistor built in.) Test output Test output
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LC78711E
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TEST12 PALID HRESET Test input mode external control input External horizontal synchronization input Clock output External vertical synchronization input Initialization input Reset input NTSC/PAL selection NTSC/PAL selection Superimpose control Crystal oscillator element connections Crystal oscillator element connections type Polarity Positive Positive Negative function Test input. Must connected ground during normal operation. External superimpose function control input mode pull-up resistor built in.) External horizontal synchronization timing control input Subcarrier clock output NTSC mode: 3.579545 mode: 4.433619 External vertical synchronization timing control input System initialization signal input System reset signal input NTSC/PAL selection input (RGB encoder block) High: NTSC, low: NTSC/PAL selection input (decoder block) High: NTSC, low: Superimpose function on/off control input High: superimpose Connections crystal oscillator element 17.734476 MHz) Connections NTSC crystal oscillator element 14.31818 MHz)
FSCO
Positive
VRESET INIT RESET N/P1 N/P2 XIN2 XOUT2 XIN1 XOUT1
Negative Negative Negative Positive Positive Positive
Timing Characteristics (DRAM access timing) DVDD1
Parameter Random read/write cycle Page mode cycle access time access time Output turn delay precharge time pulse width pulse width (page mode) hold time hold time pulse width precharge time precharge time address setup time address hold time Column address setup time Column address hold time Read command setup time Read command hold time Read command hold time Write command setup time Write command hold time Write command pulse width Write data setup time Write data setup time setup time hold time precharge active time Refresh time Symbol tRAC tCAC tOFF tRAS tRASP tRSH tCSH tCAS tCPN tASR tRAH tASC tCAH tRCS tRCH tRRH tWCS tWCH tCSR tCHR tRPC tREF before before Referenced Referenced Page mode 18000 Conditions Ratings Unit
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LC78711E DRAM read cycle
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LC78711E DRAM Early write cycle
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LC78711E DRAM page mode read cycle
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LC78711E DRAM page mode write cycle
DRAM before refresh cycle
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LC78711E Block Diagram
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LC78711E Function Overview Crystal clock oscillator; XIN1, XOUT1, XIN2, XOUT2, N/P1, N/P2, FSCO XIN1 XOUT1 pins connections NTSC 14.31818-MHz crystal element, XIN2 XOUT2 pins connections 17.734476-MHz crystal element. N/P1 switches LC78711E encoder block between NTSC modes, N/P2 switches decoder block between NTSC modes. FSCO outputs clock signal that crystal oscillator frequency divided table below enumerates states LC78711E operating modes.
XIN1, XOUT1 14.31818 14.30244 XIN2, XOUT2 17.734476 N/P1 N/P2 format NTSC/M PAL/GBIDH PAL/M FSCO 3.579545 4.433619 3.575611
Display format; N/P1, N/P2, LINE, CSYNC, SON, 4FSC2, FSCIN, VRESET, HRESET, PALID LC78711E supports both NTSC modes, with N/P1 N/P2 pins being used mode. item above states NTSC modes. LINE switches number scan lines period. SON, 4FSC2, FSCIN, VRESET, HRESET, PALID pins used with superimpose function. 4FSC2 inputs frequency, FSCIN inputs frequency. VRESET HRESET pins input external video signal VSYNC HSYNC. internal counters reset falling edges these signals, respectively. image disrupted 4FSC2 signal locked with VRESET HRESET signals. used switch video signal. PALID used burst waveform phase matching mode.
DRAM interface Interface pins: DB3, RAS, CAS, external 4-bit DRAM must used. Video outputs: VIDEO1, VIDEO2 luminance signal acquired from VIDEO1 pin. chrominance signal acquired from VIDEO2 pin.
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LC78711E Color output; input high, color signal will output from VIDEO1 VIDEO2 pins. table below lists content color signal.
White Gray Yellow Cyan Green Magenta Blue Border (black)
Color signal output level Luminance signal output level signal: VIDEO1,
Data value
Output voltage 4.990 4.648 4.434 4.268 4.014 3.848 3.691 3.525 3.271 3.125 2.500
Luminance level (IRE) 121.9 85.7 74.9 58.4 47.6 37.5 26.7 10.2
Note: AVDD1 5.00
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LC78711E Chrominance signal output level signal: VIDEO2,
Data value
Output voltage 4.990 4.560 4.463 4.306 4.121 3.750 3.379 3.193 3.037 2.939 2.500
Luminance level (IRE) 81.2 52.7 46.3 36.2 24.1 -24.1 -36.2 -46.3 -52.7 -81.2
Note: AVDD1 5.00
Drawing Display Functions Operating mode (scan operation, display operation) NTSC mode: Non-interlaced (262 lines) clock 2fsc: 7.15909 139.67 System clock 4fsc: 14.31818 mode: Non-interlaced (312 lines) clock 4fsc 2/5: 7.09379 140.97 System clock 4fsc: 17.734476 Display functions Display resolution dots Screen data area dots 16-color display colors selected from palette 4096 colors
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LC78711E Sprite screen (cursor display) Sprite screen: types, dots Sprite color: Seven display colors plus transparent display colors selected from 4096 colors) This color setting selects colors that independent bit-mapped screens. Cross cursor display coordinates set. cross cursor displayed point corresponding specified coordinates. Display window area function rectangular window specified specifying coordinates points. Either area within display window, area outside display window specified transparent (border color display). Scrolling display function Scrolling vertical horizontal directions scroll amount set. scroll amount units dots horizontal direction dots vertical direction. Text with characters horizontal direction characters vertical direction single character units. Graphics display format
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LC78711E Writing graphics data point (Xs, Ys): 9-bit address. point (Xe, Ye): 8-bit address. Begin writing color codes from origin coordinate address (Xs, Ys). direction address (Xs) matches endpoint address (Xe), reset address origin address (Xs). same time, increment address count. Terminate writing when endpoint address (Xe, reached. termination, reset address origin address (Xs, exit. Terminate writing even gone low. this case, address will endpoint address plus algorithm will exit. address manipulations described above, case where automatic address incrementing been command. When writing graphics display area, specify address origin address endpoint When writing rectangular area, origin endpoint arbitrary values. When filling specified command, data will first specified color code. this case, suffices write color code that specified that point. However, condition that color code setting must changed during fill operation. When writing straight line, either (horizontal) values (vertical) values origin endpoint same value. example, draw straight line vertical direction, origin (Xs, endpoint (Xs, Ye). draw straight line horizontal direction, origin (Xs, endpoint (Xe, Ys). Filling must specified command write straight lines. addresses follows write scroll data. example, scroll down, specify origin endpoint [B]. scroll right, specify origin endpoint [B]. scroll left, specify origin endpoint [B]. scroll specify origin endpoint [B]. Reading color codes specific bits possible read (not write) color code given using command origin address (Xs, Ys). Executing read command latches data into serial output shift register. command manipulation terminates when data single been read out. (The command register reset.) Graphics display priority order Cross cursor Sprite pattern Sprite pattern Graphics screen Border screen Background screen (not displayed during graphics display) Note: There cases where same pattern displayed sprite patterns Thus LC78711E state accessing same sprite RAM. Therefore, time difference must sprite pattern accesses (reads) patterns.
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LC78711E Microprocessor Interface Data transfer format (for command transfers) command identification code (control item) must transferred before data transferred when setting commands, positions (coordinates), color codes (color table). continuous data transfer mode then data transfers data sprite (cursor) data also require that command identifier code (control item) transferred before data transferred. Transfer format (example)
Command identification code (control item) Command register setup data Serial transfer completes
Transfer format (when continuous data transfer mode been Continuous data transfer mode must data byte) that follows command identification code (control item). When data transfer command data transfer started, data that follows byte units) acquired data. Note: continuous data transfer mode write address must command) automatic increment mode. Transfer format (example)
Command identification code (control item) Command register setup data data Serial transfer completes continuous data transfer mode cleared.
Note: When continuous data transfer mode cleared, command register setting reset. control microprocessor immediately issues data transfer command starts data transfer, LC78711E will switch continuous data transfer mode once again.
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LC78711E Transfer format (when check command issued) Transfer format (example)
Control item (address first byte: 11hex) Data (check flags)
Control Commands
First byte Command Register 00hex (Mode setup) Register 01hex (Screen position fine adjustment) Register 04hex (Color: settings) Register 05hex (Color: settings) Register 06hex (Burst phase setting; when Register 07hex output phase adjustment) Register 08hex (External synchronization on/off) Register 09hex (Subtitle scrolling: up/down) Register 0Ahex (Subtitle scrolling: left/right) Register 8Bhex (Scrolling control: vertical direction) Register 8Chex (Scrolling control: horizontal direction) Register 0Dhex (Graphics mode setup) Register 0Ehex (Pin PSC1 output control) Register 0Fhex (Pin PSC2 output control) Register 11hex Control item code INIT CRG3 CROS MVMD SCRV SCRH SCP2 CRG2 CRKY EXSN SCRV SCRH SCP1 CRG1 BGCL SCH5 SCP0 CRG0 SCV4 SCH4 Second byte Data CRR3 CRB3 TST3 SCV3 SCH3 SRFV CRSM CRR2 CRB2 TST2 SCV2 SCH2 SRFV SRFH DCRS SPBM VBLK CRR1 CRB1 TST1 SCV1 SCH1 SRFV SRFH DSPB SPAM EXEC VRAM/ CRR0 CRB0 TST0 SCV0 SCH0 SRFV SRFH DSPA GPHM
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LC78711E
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First byte Command Register 20hex (Color data settings: Register 21hex (Color data settings: Register A2hex (Color data settings) Register A3hex (Border color setting) Register 24hex (Bit address setting) Register 25hex (Bit address setting) Register 26hex (Write control setting) Register A7hex (Bit data setting) Register 28hex (Color data settings: Register 29hex (Color data settings: Register AAhex (Sprite settings) Register 2Bhex (Sprite address setting) Register 2Chex (Sprite address setting) Register 2Dhex (Write control settings) Register AEhex (Sprite data setting) Register 2Fhex (Sprite settings) Register 30hex (Sprite display address setting) Register 31hex (Sprite display address setting) Register 32hex (Sprite display address setting control) Register 33hex (Display window setting: Register 34hex (Display window setting: Register 35hex (Display window: display area settings) Register 36hex (Cross cursor display position setting: Register 37hex (Cross cursor display position setting: Control item code SGCG BMAY BMAX BMD7 SSPG SPDA SPDA WDYS WDXS CRAX CRAY SGCG BMAY BMAX BMD6 SSPG SPD6 SPDA SPDA WDYS WDXS CRAX CRAY SGCG BMAY BMAX BMD5 SSPG SPD5 SPDA SPDA WDYS WDXS WDEN CRAX CRAY SGCG BMAY BMAX STRP/ ENDP BMD4 SSPG SPAR SPAR SPD4 SPDA SPDA WDYS WDXS WDAR CRAX CRAY Second byte Data SGCR SGCB SCPC SBDC BMAY BMAX FILL COLR BMD3 SSPR SSPB SPAR SPAR WSP2 SPDA SPDA WSPB WDYS WDXS CRAX CRAY SGCR SGCB SCPC SBDC BMAY BMAX BMAI BMD2 SSPR SSPB SSPC SPAR SPAR WSP1 SPD2 SPRT SPDA SPDA WSPA WDYS WDXS SADR/ EADR CRAX CRAY SGCR SGCB SCPC SBDC BMAY BMAX BMDF BMD1 SSPR SSPB SSPC SPAR SPAR SPAI SPD1 SPSB SPDA SPDA WDYS WDXS CRAX CRAY SGCR SGCB SCPC SBDC BMAY BMAX BMAX BMD0 SSPR SSPB SSPC SPAR SPAR SPDF SPD0 SPSA SPDA SPDA SPDA WDYS WDXS WDXS CRAX CRAY
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LC78711E Command Descriptions Note: After hardware reset, always first send register command, only then issue various commands. LC78711E operate incorrectly register command issued. Note: data transfers must performed first. Note: notations second byte indicate default values. Register 00hex
Data7: INIT Function: System reset Operation: INIT LC78711E internal state reset (normal operation continues) INIT internal state reset (The display blue background screen.) Data6: SCP2 Data5: SCP1 Data4: SCP0 Function: output (pin control Operation: SCP2 When (SCP0, SCP1) (0,0) (0,1), whole screen (transparent) comparison condition hold. SCP2 When (SCP0, SCP1) (0,0) (0,1), whole screen high (display) comparison condition hold. superimpose mode comparison condition determined SCP1 SCP2 setting. (Only valid when SON,
SCP1 SCP0 Comparison condition output operation setting) comparison performed border color black, high (display) sections that match border color, (transparent) other sections. Sets high sections that match chroma color, other sections.
Data3: Function: Color screen output setting Operation: graphics signal output. color signal output. Data2: Operation: This must always LC78711E operate correctly this Data1: Operation: This must always LC78711E operate correctly this Data0: VRAM/BG Function: Switches displayed screen Operation: VRAM/BG Displays contents VRAM VRAM/BG Displays background color
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LC78711E Register 01hex
Data7: Data6: Data5: Data4: Function: These bits vertical direction display start position. Operation: Sets display position complement value with positive indicating vertical direction. position units, supporting range from dots from center position. Data3: Data2: Data1: Data0: Function: These bits horizontal direction display start position. Operation: Sets display position complement value with positive indicating left horizontal direction. position units, supporting range from dots from center position. Register 04hex
Data7: CRG3 Data6: CRG2 Data5: CRG1 Data4: CRG0 Function: Operation: Data3: CRR3 Data2: CRR2 Data1: CRR1 Data0: CRR0 Function: Operation:
green color data setting Specifies green color data. There values range (hexadecimal).
color data setting Specifies color data. There values range (hexadecimal).
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LC78711E Register 05hex
Data7: CROS Function: Cross cursor display color setting Operation: Acquires color bits CRR3:0, CRG3:0, CRB3:0 cross cursor display color. Data6: CRKY Function: Chroma color setting Operation: Acquires color bits CRR3:0, CRG3:0, CRB3:0 chroma color. Data5: BGCL Function: Background color setting Operation: Acquires color bits CRR3:0, CRG3:0, CRB3:0 background color. Data4: Unused (Must Data3: CRB3 Data2: CRB2 Data1: CRB1 Data0: CRB0 Function: blue color data setting Operation: Specifies blue color data. There values range (hexadecimal). Register 06hex
Data7: Function: Color burst phase timing setting during superimpose operation Operation: rising edge 4fsc clock falling edge 4fsc clock Data6: Unused (Must Data5: Unused (Must Data4: Unused (Must Data3: Unused (Must Data2: BSTON Function: Color burst signal output control setting during superimpose operation Operation: BSTON Burst signal output turned BSTON Burst signal output turned
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LC78711E Data1: Data0: Function: Color burst signal phase setting during superimpose operation Operation:
Phase 180° 270°
Register 07hex
Data7: Unused (Must Data6: Unused (Must Data5: Unused (Must Data4: Unused (Must Data3: Data2: Data1: Data0: Function: (pin output phase adjustment setting Operation: Sets output timing single 4fsc clock units. default phase setting identical that video output. Register 08hex
Data7: MVMD Function: Moving display area setting during superimpose operation Operation: MVMD Only display area moves MVMD area including border area moves (only left right motion possible with this setting.)
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LC78711E Data6: EXSN Function: Synchronizing signal reset control setting external synchronization mode, i.e., when Operation: EXSN Reset executed falling edge HRESET (pin VRESET (pin signals. EXSN Reset executed falling edge VRESET (pin signal. (The HRESET signal required.) Data5: Unused (Must Data4: Unused (Must Data3: TST3 Data2: TST2 Data1: TST1 Data0: TST0 Function: Test mode settings Operation: These bits must during normal operation. Register 09hex
Data7: Unused (Must Data6: Unused (Must Data5: Unused (Must Data4: SCV4 Data3: SCV3 Data2: SCV2 Data1: SCV1 Data0: SCV0 Function: Subtitle scrolling amount (vertical direction setting character units) Operation: Scrolls screen display position character units. scrolling amount value range characters, where single character vertical dots Register 0Ahex
Data7: Unused (Must Data6: Unused (Must
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LC78711E Data5: SCH5 Data4: SCH4 Data3: SCH3 Data2: SCH2 Data1: SCH1 Data0: SCH0 Function: Subtitle scrolling horizontal direction setting Operation: Scrolls screen display position left character units. scrolling amount value range characters, where single character horizontal dots. Register 8Bhex
Data7: SCRV1 Data6: SCRV0 Function: Scrolling function vertical direction setting Operation:
SCRV0 SCRV1 Scroll direction scroll Scroll down Scroll Illegal value
Data5: Unused (Must Data4: Unused (Must Data3: SRFV3 Data2: SRFV2 Data1: SRFV1 Data0: SRFV0 Function: Scrolling adjustment setting units Operation: Scrolls screen display position down units. amount scrolling dots.
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LC78711E Register 8Chex
Data7: SCRH1 Data6: SCRH0 Function: Scrolling left/right motion units Operation:
SCRH0 SCRH1 Scroll direction scroll Scroll right Scroll left Illegal value
Data5: Unused (Must Data4: Unused (Must Data3: Unused (Must Data2: SRFH2 Data1: SRFH1 Data0: SRFH0 Function: Scroll adjustment setting units) Operation: Scrolls screen display position left right units. amount scrolling dots. Register 0Dhex
Data7: Unused (Must Data6: Unused (Must Data5: Unused (Must Data4: Unused (Must Data3: Unused (Must Data2: DCRS Function: Cross cursor display control setting Operation: DCRS Cursor display DCRS Cursor display
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LC78711E Data1: DSPB Function: Sprite pattern display control setting Operation: DSPB Sprite display DSPB Sprite display Data0: DSPA Function: Sprite pattern display control setting Operation: DSPA Sprite display DSPA Sprite display Register 0Ehex
Data7: Unused (Must Data6: Unused (Must Data5: Unused (Must Data4: Unused (Must Data3: Unused (Must Data2: Unused (Must Data1: Unused (Must Data0: SROENM Function: Output signal setting PSC1 (pin Operation: Controls whether serial output data setup complete flag output from PCS1 pin. SROENM flag output. SROENM flag output. Register 0Fhex
Data7: Unused (Must Data6: Unused (Must Data5: Unused (Must Data4: Unused (Must Data3: CRSM Function: Output signal setting PSC2 (pin Operation: Controls whether PSC2 output monitors cross cursor display state. CRSM cursor state monitored. CRSM cross cursor display state monitored. high level output when cross cursor displayed.
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LC78711E Data2: SPBM Function: Output signal setting PSC2 (pin Operation: Controls whether PSC2 output monitors sprite pattern display state. SPBM sprite state monitored. SPBM sprite display state monitored. high level output when sprite pattern displayed. Data1: SPAM Function: Output signal setting PSC2 (pin Operation: Controls whether PSC2 output monitors sprite pattern display state. SPAM sprite state monitored. SPAM sprite display state monitored. high level output when sprite pattern displayed. Data0: GPHM Function: Output signal setting PSC2 (pin Operation: Controls whether PSC2 output monitors state graphics display mode setting. GPHM display state monitored. GPHM graphics display mode setting state monitored. high level output when LC78711E operating graphics display mode. Register 11hex
Data7: Data6: Data5: Data4: Data3: Data2: VBLK Function: Vertical blanking (vertical return) period indicator Operation: Outputs during vertical blanking period. VBLK vertical blanking period. VBLK Display vertical blanking period. NTSC mode: period mode: period Data1: EXEC Function: Command execution state Operation: Outputs LC78711E command execution state. EXEC Command execution progress EXEC Command wait state Data0:
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LC78711E Register 20hex
Data7: SGCG3 Data6: SGCG2 Data5: SGCG1 Data4: SGCG0 Function: Drawing color setting (Green level setting color palette specified color) Operation: These bits specify green level. (0hex Fhex) Data3: SGCR3 Data2: SGCR2 Data1: SGCR1 Data0: SGCR0 Function: Drawing color setting (Red level setting color palette specified color) Operation: These bits specify level. (0hex Fhex) Register 21hex
Data7: Unused (Must Data6: Unused (Must Data5: Unused (Must Data4: Unused (Must Data3: SGCB3 Data2: SGCB2 Data1: SGCB1 Data0: SGCB0 Function: Drawing color setting (Blue level setting color palette specified color) Operation: These bits specify blue level. (0hex Fhex)
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LC78711E Register A2hex
Data7: Unused (Must Data6: Unused (Must Data5: Unused (Must Data4: Unused (Must Data3: SCPC3 Data2: SCPC2 Data1: SCPC1 Data0: SCPC0 Function: Color palette color setting Operation: Sets color specified registers color palette address specified these bits. Register A3hex
Data7: Unused (Must Data6: Unused (Must Data5: Unused (Must Data4: Unused (Must Data3: SBDC3 Data2: SBDC2 Data1: SBDC1 Data0: SBDC0 Function: Border color specification Operation: Selects border color from colors color palette.
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LC78711E Register 24hex
Data7: BMAY7 Data6: BMAY6 Data5: BMAY5 Data4: BMAY4 Data3: BMAY3 Data2: BMAY2 Data1: BMAY1 Data0: BMAY0 Function: address specification Operation: Specifies vertical direction coordinate). range valid settings from 00hex B7hex (00oct 215oct). Values B8hex larger illegal. Register 25hex
Data7: BMAX7 Data6: BMAX6 Data5: BMAX5 Data4: BMAX4 Data3: BMAX3 Data2: BMAX2 Data1: BMAX1 Data0: BMAX0 Function: address specification Operation: These bits plus Data0 (BMAX8) register 26hex (for total bits), specify horizontal direction coordinate). range valid settings from 000hex 12Bhex (000oct 299oct). Values 12Chex larger illegal.
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LC78711E Register 26hex
Data7: Unused (Must Data6: Function: data area read/write mode setting Operation: Sets data read write mode. data area write mode data area read mode Data5: Unused (Must Data4: STRP/ENDP Function: data setup area start stop coordinate selection Operation: Loads coordinates registers 24hex, 25hex, Data0 (BMAX8) this register into data setup area start stop address. STRP/ENDP Sets start coordinates. STRP/ENDP Sets stop coordinates. Data3: FILLCOLR Function: area color palette color fill operation setup Operation: Fills area specified with STRP/ENDP with color palette color specified bits Data3 Data0 (BMD3 BMD0) register A7hex. execution fill operation starts after color palette with register A7hex. FILLCOLR Fill operation FILLCOLR Sets fill operation. Data2: BMAI Function: Automatic address increment during data write setting Operation: Specifies whether address automatically incremented during data write operations. automatic incrementing specified, application must specify address registers 24hex, 25hex, 26hex after every data transfer. BMAI address automatically incremented. BMAI address automatically incremented. Data1: BMDF Function: data transfer item count setting Operation: Specifies whether data transferred units two-dot units during data transfers. This setting that determines whether only lower bits bits transferred register A7hex data transfers. BMDF Takes only lower bits data. BMDF Takes bits data. Here, lower bits data taken first data item, upper bits taken next data item. Note: BMDF must when BMAI i.e. when automatic address incrementing used.
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LC78711E Data0: BMAX8 Function: address specification Operation: This plus Data0 Data7 bits (BMAX0 BMAX7) register 25hex (for total bits), specify horizontal direction coordinate). range valid settings from 000hex 12Bhex (000oct 299oct). Values 12Chex larger illegal. Register A7hex
Data7: BMD7 Data6: BMD6 Data5: BMD5 Data4: BMD4 Function: data setting Operation: color palette color specified these bits loaded into specified coordinate, i.e., written VRAM. This data valid when BMAI BMDF Data3: BMD3 Data2: BMD2 Data1: BMD1 Data0: BMD0 Function: data setting Operation: color palette color specified these bits loaded into specified coordinates, i.e., written VRAM. Register 28hex
Data7: SSPG3 Data6: SSPG2 Data5: SSPG1 Data4: SSPG0 Function: Sprite color setting (Sets green level specified color sprite color palette.) Operation: These bits specify green level. (0hex Fhex)
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LC78711E Data3: SSPR3 Data2: SSPR2 Data1: SSPR1 Data0: SSPR0 Function: Sprite color setting (Sets level specified color sprite color palette.) Operation: These bits specify level. (0hex Fhex) Register 29hex
Data7: Unused (Must Data6: Unused (Must Data5: Unused (Must Data4: Unused (Must Data3: SSPB3 Data2: SSPB2 Data1: SSPB1 Data0: SSPB0 Function: Sprite color setting (Sets blue level specified color sprite color palette.) Operation: These bits specify blue level. (0hex Fhex) Register AAhex
Data7: Unused (Must Data6: Unused (Must Data5: Unused (Must Data4: Unused (Must Data3: Unused (Must Data2: SSPC2 Data1: SSPC1 Data0: SSPC0 Function: Sprite color palette color setting Operation: color specified registers stored color palette address specified these bits.
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LC78711E Register 2Bhex
Data7: Unused (Must Data6: Unused (Must Data5: Unused (Must Data4: SPARY4 Data3: SPARY3 Data2: SPARY2 Data1: SPARY1 Data0: SPARY0 Function: Sprite pattern address specification Operation: Specifies sprite pattern vertical direction coordinate). range valid settings from 00hex 1Fhex (00oct 31oct). Register 2Chex
Data7: Unused (Must Data6: Unused (Must Data5: Unused (Must Data4: SPARX4 Data3: SPARX3 Data2: SPARX2 Data1: SPARX1 Data0: SPARX0 Function: Sprite pattern address specification Operation: Specifies sprite pattern horizontal direction coordinate). range valid settings from 00hex 1Fhex (00oct 31oct).
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LC78711E Register 2Dhex
Data7: Unused (Must Data6: Unused (Must Data5: Unused (Must Data4: Unused (Must Data3: WSP2 Function: Data write sprite pattern setup. Operation: Sets data writes sprite pattern WSP2 Does data writes sprite pattern WSP2 Sets data writes sprite pattern Data2: WSP1 Function: Data write sprite pattern setup Operation: Sets data writes sprite pattern WSP1 Does data writes sprite pattern WSP1 Sets data writes sprite pattern Data1: SPAI Function: Automatic increment setting sprite address during sprite data writes Operation: Specifies whether sprite address automatically incremented during sprite data writes. automatic incrementing specified, application must specify address registers 2Bhex 2Chex after every data transfer. SPAI address automatically incremented. SPAI address automatically incremented. Data0: SPDF Function: Setting number data items transferred during sprite data transfers Operation: Specifies whether data transferred units units during sprite data transfers. This setting that determines whether only lower bits lower bits upper bits transferred register AEhex data transfers. SPDF Takes only lower bits data. SPDF Also process bits Data6 Data4 data. Here, lower bits data processed first data item, upper bits become data next address. Note: SPDF must when SPAI i.e. when automatic address incrementing used.
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LC78711E Register AEhex
Data7: Unused (Must Data6: SPD6 Data5: SPD5 Data4: SPD4 Function: data settings Operation: color palette color specified these bits loaded specified sprite coordinate. This data valid when SPAI SPDF Data3: Unused (Must Data2: SPD2 Data1: SPD1 Data0: SPD0 Function: data settings Operation: color palette color specified these bits loaded specified sprite coordinate. Register 2Fhex
Data7: Unused (Must Data6: Unused (Must Data5: Unused (Must Data4: Unused (Must Data3: Unused (Must Data2: SPRTARA Function: Sprite pattern display area setting Operation: Sets whether sprite pattern display area limited drawing area whole image area, i.e., sprite pattern also displayed outside drawing area. SPRTARA Display only drawing area. SPRTARA Display outside drawing area also allowed. Data1: SPSB Function: Selection sprite pattern sprite display pattern Operation: Selects whether sprite pattern displayed sprite display pattern. This selection pattern whose display turned Data1 (DSPB) register 0Dhex. SPSB Sprite pattern displayed. SPSB Sprite pattern displayed.
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LC78711E Data0: SPSA Function: Selection sprite pattern sprite display pattern Operation: Selects whether sprite pattern displayed sprite display pattern. This selection pattern whose display turned Data0 (DSPA) register 0Dhex. SPSA Sprite pattern displayed. SPSA Sprite pattern displayed. Note: When same pattern selected both sprites instances same pattern displayed. Register 30hex
Data7: SPDAY7 Data6: SPDAY6 Data5: SPDAY5 Data4: SPDAY4 Data3: SPDAY3 Data2: SPDAY2 Data1: SPDAY1 Data0: SPDAY0 Function: Sprite display address setting Operation: Specifies sprite display vertical direction coordinate). range valid settings from 00hex B7hex (00oct 215oct). Values B8hex larger illegal. Register 31hex
Data7: SPDAX7 Data6: SPDAX6 Data5: SPDAX5 Data4: SPDAX4 Data3: SPDAX3 Data2: SPDAX2 Data1: SPDAX1 Data0: SPDAX0 Function: Sprite display address setting Operation: These bits plus Data0 (SPDAX8) register 32hex (for total bits), specify sprite display horizontal direction coordinate). range valid settings from 000hex 12Bhex (000oct 299oct). Values 12Chex larger illegal.
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LC78711E Register 32hex
Data7: Unused (Must Data6: Unused (Must Data5: Unused (Must Data4: Unused (Must Data3: WSPB Function: Sprite display start address write control Operation: Sets address specified sprite display address sprite display start address. WSPB setting performed. WSPB Sets address. Data2: WSPA Function: Sprite display start address write control Operation: Sets address specified sprite display address sprite display start address. WSPA setting performed. WSPA Sets address. Data1: Unused (Must Data0: SPDAX8 Function: Sprite address specification Operation: Data0 Data7 bits (SPDAX0 SPDAX7) register this this register (for total bits) specify sprite horizontal direction coordinate). range valid settings from 000hex 12Bhex (000oct 299oct). Values 12Chex larger illegal. Register 33hex
Data7: WDYS7 Data6: WDYS6 Data5: WDYS5 Data4: WDYS4 Data3: WDYS3 Data2: WDYS2 Data1: WDYS1 Data0: WDYS0 Function: Display window address specification Operation: Specifies display window vertical direction coordinate). range valid settings from 00hex B7hex (00oct 215oct). Values B8hex larger illegal.
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LC78711E Register 34hex
Data7: WDXS7 Data6: WDXS6 Data5: WDXS5 Data4: WDXS4 Data3: WDXS3 Data2: WDXS2 Data1: WDXS1 Data0: WDXS0 Function: Sprite display address specification Operation: These bits plus Data0 (WDXS8) register 35hex (for total bits), specify horizontal direction coordinate). range valid settings from 000hex 12Bhex (000oct 299oct). Values 12Chex larger illegal. Register 35hex
Data7: Unused (Must Data6: Unused (Must Data5: WDEN Function: Display window display setting Operation: Sets display window display. WDEN display window displayed. WDEN display window displayed. Data4: WDAR Function: Display window display area setting Operation: Sets display window display area. WDAR Displays inside display window WDAR Displays outside display window Data3: PAL60 Function: PAL60 mode setting (Valid only when N/P1 N/P2 Operation: PAL60 mode PAL60 PAL60 mode
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LC78711E Data2: SADR/EADR Function: Display window display coordinates setting Operation: Sets display window display area. SADR/EADR Sets display window start address. SADR/EADR Sets display window address. Data1: Unused (Must Data0: WDXS8 Function: Display window address setting Operation: Data0 Data7 bits (WDXS0 WDXS7) register this this register (for total bits) specify sprite horizontal direction coordinate). range valid settings from 000hex 12Bhex (000oct 299oct). Values 12Chex larger illegal. Register 36hex
Data7: CRAX7 Data6: CRAX6 Data5: CRAX5 Data4: CRAX4 Data3: CRAX3 Data2: CRAX2 Data1: CRAX1 Data0: CRAX0 Function: Cross cursor position setting Operation: Specifies horizontal direction coordinate) cross cursor intersection point. This setting sets position 2-dot units.
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LC78711E Register 37hex
Data7: CRAY7 Data6: CRAY6 Data5: CRAY5 Data4: CRAY4 Data3: CRAY3 Data2: CRAY2 Data1: CRAY1 Data0: CRAY0 Function: Cross cursor position setting Operation: Specifies vertical direction coordinate) cross cursor intersection point. This setting sets position 2-dot units. Note: register 0Dhex Data (DCRS) setting required execution cross cursor display function.
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LC78711E NTSC Sample Application Circuit
products described contained herein intended surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment like, failure which directly indirectly cause injury, death property loss. Anyone purchasing products described contained herein above-mentioned shall: Accept full responsibility indemnify defend SANYO ELECTRIC CO., LTD., affiliates, subsidiaries distributors their officers employees, jointly severally, against claims litigation damages, cost expenses associated with such use: impose responsibility fault negligence which cited such claim litigation SANYO ELECTRIC CO., LTD., affiliates, subsidiaries distributors their officers employees jointly severally. Information (including circuit diagrams circuit parameters) herein example only; guaranteed volume production. SANYO believes information herein accurate reliable, guarantees made implied regarding infringements intellectual property rights other rights third parties. This catalog provides information December, 1997. Specifications information herein subject change without notice. 5476-43/43
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