8-BIT CMOS MICROCONTROLLER USER'S MANUAL Revision Important Notic
|
|
|
Top Searches for this datasheet
S3C9454B/F9454B
8-BIT CMOS MICROCONTROLLER USER'S MANUAL Revision
Important Notice
information this publication been carefully checked believed entirely accurate time publication. Samsung assumes responsibility, however, possible errors omissions, consequences resulting from information contained herein. Samsung reserves right make changes products product specifications with intent improve function design time without notice required update this documentation reflect such changes. This publication does convey purchaser semiconductor devices described herein license under patent rights Samsung others. Samsung makes warranty, representation, guarantee regarding suitability products particular purpose, does Samsung assume liability arising application product circuit specifically disclaims liability, including without limitation consequential incidental damages. "Typical" parameters vary different applications. operating parameters, including "Typicals" must validated each customer application customer's technical experts. Samsung products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure Samsung product could create situation where personal injury death occur. Should Buyer purchase Samsung product such unintended unauthorized application, Buyer shall indemnify hold Samsung officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising either directly indirectly, claim personal injury death that associated with such unintended unauthorized use, even such claim alleges that Samsung negligent regarding design manufacture said product.
S3C9454B/F9454B 8-Bit CMOS Microcontroller User's Manual, Revision Publication Number: 21-S3-C9454B/F9454B-200409 2004 Samsung Electronics rights reserved. part this publication reproduced, stored retrieval system, transmitted form means, electric mechanical, photocopying, recording, otherwise, without prior written consent Samsung Electronics. Samsung Electronics' microcontroller business been awarded full ISO-14001 certification (BVQ1 Certificate FM9300). semiconductor products designed manufactured accordance with highest quality standards objectives. Samsung Electronics Co., Ltd. Nongseo-Ri, Giheung-Eup Yongin-City, Gyeonggi-Do, Korea C.P.O. #37, Suwon 440-900 TEL: (0331) 209-1907 FAX: (0331) 209-1899 Home-Page URL: Http://www.samsungsemi.com/ Printed Republic Korea
Preface
S3C9454B/F9454B Microcontroller User's Manual designed application designers programmers using S3C9454B/F9454B microcontroller application development. organized parts: Part Programming Model Part Hardware Descriptions
Part contains software-related information familiarize with microcontroller's architecture, programming model, instruction set, interrupt structure. sections: Chapter Chapter Chapter Product Overview Address Spaces Addressing Modes Chapter Chapter Chapter Control Registers Interrupt Structure SAM88RCRI Instruction
Chapter "Product Overview," high-level introduction S3C9454B/F9454B with general product description, detailed information about individual characteristics circuit types. Chapter "Address Spaces," explains S3C9454B/F9454B program data memory, internal register file, mapped control registers, explains address them. Chapter also describes working register addressing, well system user-defined stack operations. Chapter "Addressing Modes," contains detailed descriptions addressing modes that supported CPU. Chapter "Control Registers," contains overview tables mapped system peripheral control register values, well detailed one-page descriptions standard format. these easy-to-read, alphabetically organized, register descriptions quick-reference source when writing programs. Chapter "Interrupt Structure," describes S3C9454B/F9454B interrupt structure detail further prepares additional information presented individual hardware module descriptions Part Chapter "SAM88RCRI Instruction Set," describes features conventions instruction used S3C9-series microcontrollers. Several summary tables presented orientation reference. Detailed descriptions each instruction presented standard format. Each instruction description includes more practical examples instruction when writing application program. basic familiarity with information Part will help understand hardware module descriptions Part familiar with SAM88RCRI product family reading this manual first time, recommend that first read chapter carefully. Then, briefly look over detailed information chapters Later, reference information Part necessary. Part contains detailed information about peripheral components S3C9454B/F9454B microcontrollers. Also included Part electrical, mechanical, MTP, development tools data. chapters: Chapter Chapter Chapter Chapter Chapter Clock Circuit RESET Power-Down Ports Basic Timer Timer 8-bit Chapter Chapter Chapter Chapter Chapter Converter Electrical Data Mechanical Data S3F945B Development Tools
order forms included back this manual facilitate customer order S3C9454B/F9454B microcontrollers: Mask Order Form, Mask Option Selection Form. photocopy these forms, fill them out, then forward them your local Samsung Sales Representative.
S3C9454B/F9454B MICROCONTROLLER
Table Contents
Part Programming Model
Chapter Product Overview
SAM88RCRI Product Family. S3C9454B/F9454B Microcontroller. MTP. Features Block Diagram. Assignments Descriptions Circuits
Chapter
Address Spaces
Overview Program Memory (ROM) Register Architecture. Common Working Register Area (C0H-CFH). System Stack
Chapter
Addressing Modes
Overview Register Addressing Mode Indirect Register Addressing Mode (IR) Indexed Addressing Mode (X). Direct Address Mode (DA) 3-10 Relative Address Mode (RA) 3-12 Immediate Mode (IM) 3-12
S3C9454B/F9454B MICROCONTROLLER
Table Contents (Continued)
Chapter Control Registers
Overview.4-1
Chapter
Interrupt Structure
Overview.5-1 Interrupt Processing Control Points .5-1 Enable/Disable Interrupt Instructions (EI, .5-2 Interrupt Pending Function Types.5-2 Interrupt Priority .5-2 Interrupt Source Service Sequence.5-3 Interrupt Service Routines .5-3 Generating Interrupt Vector Addresses .5-3 S3C9454B/F9454B Interrupt Structure.5-4
Chapter
SAM88RCRI Instruction
Overview.6-1 Register Addressing .6-1 Addressing Modes .6-1 Flags Register (FLAGS) .6-4 Flag Descriptions .6-4 Instruction Notation .6-5 Condition Codes .6-9 Instruction Descriptions .6-10
S3C9454B/F9454B MICROCONTROLLER
Table Contents (Continued)
Part Hardware Descriptions
Chapter Clock Circuit
Overview Main Oscillator Logic Clock Status During Power-Down Modes System Clock Control Register (CLKCON)
Chapter
RESET Power-Down
System Reset. Overview. Power-Down Modes. Stop Mode Idle Mode. Hardware Reset Values
Chapter
Ports
Overview Port Data Registers Port Port Port
Chapter
Basic Timer Timers
Module Overview 10-1 Basic Timer (BT) 10-2 Basic Timer Control Register (BTCON) 10-2 Basic Timer Function Description 10-3 Timer 10-7 Timer Control Registers (T0CON). 10-7 Timer Function Description 10-8
S3C9454B/F9454B MICROCONTROLLER
Table Contents (Continued)
Chapter 8-Bit
Overview.11-1 Function Description.11-1 PWM.11-1 Control Register (PWMCON) .11-5
Chapter
Converter
Overview.12-1 Using Pins Standard Digital Input.12-2 Converter Control Register (ADCON).12-2 Internal Reference Voltage Levels.12-3 Conversion Timing.12-4 Internal Conversion Procedure .12-5
Chapter
Electrical Data
Overview.13-1
Chapter
Mechanical Data
Overview.14-1
Chapter
S3F9454B
Overview 15-1 Operating Mode Characteristics 15-3
Chapter
Development Tools
Overview.16-1 SHINE.16-1 SAMA Assembler.16-1 SASM86.16-1 HEX2ROM .16-1 Target Boards .16-2 Mtps .16-2 TB9454B Target Board.16-3
viii
S3C9454B/F9454B MICROCONTROLLER
List Figures
Figure Number 1-10 1-11 3-10 3-11 3-12 3-13 Title Page Number
Block Diagram Assignment Diagram (20-Pin DIP/SOP/SSOP Package) Assignment Diagram (16-Pin DIP/SOP/SSOP Package) Circuit Type Circuit Type Circuit Type Circuit Type Circuit Type Circuit Type E-1. Circuit Type E-2. Program Memory Address Space Smart Option Internal Register File Organization 16-Bit Register Pairs Stack Operations. Register Addressing .3-2 Working Register Addressing .3-2 Indirect Register Addressing Register File.3-3 Indirect Register Addressing Program Memory .3-4 Indirect Working Register Addressing Register File.3-5 Indirect Working Register Addressing Program Data Memory .3-6 Indexed Addressing Register File .3-7 Indexed Addressing Program Data Memory with Short Offset.3-8 Indexed Addressing Program Data Memory with Long Offset .3-9 Direct Addressing Load Instructions.3-10 Direct Addressing Call Jump Instructions .3-11 Relative Addressing.3-12 Immediate Addressing .3-12 Register Description Format.4-4 S3F9-Series Interrupt Type Interrupt Function Diagram. S3C9454B/F9454B Interrupt Structure System Flags Register (FLAGS)
S3C9454B/F9454B MICROCONTROLLER
List Figures (Continued)
Figure Number 9-10 10-1 10-2 10-3 10-4 10-5 10-6 10-7 11-1 11-2 11-3 11-4 12-1 12-2 12-3 12-4 12-5 Title Page Number
Main Oscillator Circuit Oscillator with Internal Capacitor) .7-1 Main Oscillator Circuit (Crystal/Ceramic Oscillator).7-1 System Clock Control Register (CLKCON) .7-2 System Clock Circuit Diagram .7-3 Reset Block Diagram .8-2 Timing S3C9454B/F9454B After RESET .8-2 Port Data Register Format.9-2 Port Circuit Diagram .9-3 Port Control Register (P0CONH, High Byte) .9-4 Port Control Register (P0CONL, Byte).9-5 Port Interrupt Pending Registers (P0PND) .9-6 Port Circuit Diagram .9-7 Port Control Register (P1CON) .9-8 Port Circuit Diagram .9-9 Port Control Register (P2CONH, High Byte) .9-10 Port Control Register (P2CONL, Byte).9-11 Basic Timer Control Register (BTCON) .10-2 Oscillation Stabilization Time RESET.10-4 Oscillation Stabilization Time STOP Mode Release.10-5 Timer Control Registers (T0CON).10-7 Simplified Timer Function Diagram (Interval Timer Mode).10-8 Timer Timing Diagram .10-9 Basic Timer Timer Block Diagram.10-10 8-Bit Basic Waveform .11-3 8-Bit Extended Waveform .11-4 Control Register (PWMCON) .11-5 Functional Block Diagram.11-6 Converter Control Register (ADCON) .12-2 Converter Circuit Diagram .12-3 Converter Data Register (ADDATAH/L) .12-3 Converter Timing Diagram .12-4 Recommended Converter Circuit Highest Absolute Accuracy.12-5
S3C9454B/F9454B MICROCONTROLLER
List Figures (Concluded)
Figure Number 13-1 13-2 13-3 13-4 13-5 14-1 14-2 14-3 14-4 14-5 14-6 15-1 15-2 16-1 16-2 16-3 16-4 16-5 Title Page Number
Input Timing Measurement Points 13-4 Operating Voltage Range. 13-6 Schmitt Trigger Input Characteristics Diagram 13-6 Stop Mode Release Timing When Initiated RESET 13-7 Reset Timing 13-9 20-DIP-300A Package Dimensions. 14-1 20-SOP-375 Package Dimensions 14-2 20-SSOP-225 Package Dimensions 14-3 16-DIP-300A Package Dimensions. 14-4 16-SOP-BD300-SG Package Dimensions 14-5 16-SSOP-BD44 Package Dimensions 14-6 Assignment Diagram (20-Pin Package). 15-1 Assignment Diagram (16-Pin Package). 15-2 SMDS2+ SK-1000 Product Configuration 16-2 TB9454B Target Board Configuration 16-3 Switch Smart Option 16-5 20-Pin Connector TB9454B 16-6 S3C9454B/F9454B Probe Adapter 20-DIP Package. 16-6
S3C9454B/F9454B MICROCONTROLLER
List Tables
Table Number 11-1 11-2 13-1 13-2 13-3 13-4 13-5 13-6 13-7 13-8 15-1 15-2 15-3 16-1 16-2 16-3 Title Page Number
S3C9454B/F9454B Descriptions Register Type Summary. System Peripheral control Registers .4-2 Instruction Group Summary .6-2 Flag Notation Conventions .6-5 Instruction Symbols .6-5 Instruction Notation Conventions.6-6 Opcode Quick Reference .6-7 Condition Codes.6-9 Register Values After Reset S3C9454B/F9454B Port Configuration Overview Port Data Register Summary Control Data Registers 11-2 output "stretch" Values Extension Data Register (PWMDATA.1-.0) 11-3 Absolute Maximum Ratings 13-2 Electrical Characteristics. 13-3 Electrical Characteristics 13-4 Oscillator Characteristics. 13-5 Oscillation Stabilization Time 13-5 Data Retention Supply Voltage Stop Mode 13-7 Converter Electrical Characteristics 13-8 Circuit Characteristics 13-9 Descriptions Pins Used Read/Write Flash ROM. 15-3 Comparison S3F9454B S3C9454B Features 15-3 Operating Mode Selection Criteria 15-3 Power Selection Settings TB9454B 16-4 SMDS2+ Tool Selection Setting. 16-4 Using Single Header Pins Input Path External Trigger Sources 16-5
S3C9454B/F9454B MICROCONTROLLER
xiii
List Programming Tips
Description Chapter Address Spaces Page Number
Smart Option Setting. Addressing Common Working Register Area. Standard Stack Operations Using PUSH POP.2-9 Chapter RESET Power-Down
Sample S3C9454B/F9454B Initialization Routine .8-6 Chapter Basic Timer Timer
Configuring Basic Timer.10-6 Configuring Timer (Interval Mode) .10-11 Chapter 8-Bit
Programming Module Sample Specifications .11-7 Chapter Converter
Configuring Converter .12-6
S3C9454B/F9454B MICROCONTROLLER
List Register Descriptions
Register Identifier ADCON BTCON CLKCON FLAGS P0CONH P0CONL P0PND P1CON P2CONH P2CONL PWMCON STOPCON T0CON Full Register Name Page Number
Converter Control Register. Basic Timer Control Register Clock Control Register System Flags Register Port Control Register (High Byte) Port Control Register (Low Byte). 4-10 Port Interrupt Pending Register. 4-11 Port Control Register. 4-12 Port Control Register (High Byte) 4-13 Port Control Register (Low Byte). 4-14 Control Register 4-15 STOP Mode Control Register. 4-16 System Mode Register 4-16 TIMER Control Register 4-17
S3C9454B/F9454B MICROCONTROLLER
xvii
List Instruction Descriptions
Instruction Mnemonic CALL IDLE IRET LDC/LDE LDC/LDE LDCD/LDED LDCI/LDEI Full Instruction Name Page Number
with Carry. 6-11 6-12 Logical 6-13 Call Procedure. 6-14 Complement Carry Flag 6-15 Clear. 6-16 Complement. 6-17 Compare. 6-18 Decrement. 6-19 Disable Interrupts 6-20 Enable Interrupts 6-21 Idle Operation. 6-22 Increment 6-23 Interrupt Return 6-24 Jump. 6-25 Jump Relative. 6-26 Load 6-27 Load 6-28 Load Memory 6-29 Load Memory 6-30 Load Memory Decrement. 6-31 Load Memory Increment 6-32
S3C9454B/F9454B MICROCONTROLLER
List Instruction Descriptions (Continued)
Instruction Mnemonic PUSH STOP Full Instruction Name Page Number
Operation .6-33 Logical .6-34 From Stack.6-35 Push Stack .6-36 Reset Carry Flag.6-37 Return .6-38 Rotate Left .6-39 Rotate Left Through Carry.6-40 Rotate Right.6-41 Rotate Right Through Carry.6-42 Subtract With Carry .6-43 Carry Flag.6-44 Shift Right Arithmetic .6-45 Stop Operation.6-46 Subtract .6-47 Test Complement Under Mask.6-48 Test Under Mask .6-49 Logical Exclusive OR.6-50
S3C9454B/F9454B MICROCONTROLLER
S3C9454B/F9454B
PRODUCT OVERVIEW
PRODUCT OVERVIEW
SAM88RCRI PRODUCT FAMILY
Samsung's SAM88RCRI family 8-bit single-chip CMOS microcontrollers offer fast efficient CPU, wide range integrated peripherals, various mask-programmable sizes. address/data architecture large number bit-configurable ports provide flexible programming environment applications with varied memory requirements. Timer/counters with selectable operating modes included support real-time operations.
S3C9454B/F9454B MICROCONTROLLER
S3C9454B/F9454B single-chip 8-bit microcontroller designed useful converter application field. S3C9454B/F9454B uses powerful SAM88RCRI S3C9454B/F9454B architecture. internal register file logically expanded increase on-chip register space. S3C9454B/F9454B bytes on-chip program bytes RAM. S3C9454B/F9454B versatile general-purpose microcontroller that ideal wide range electronics applications requiring simple timer/counter, PWM. addition, S3C9454B/F9454's advanced CMOS technology provides power consumption wide operating voltage range. Using SAM88RCRI design approach, following peripherals were integrated with SAM88RCRI core: Three configurable ports pins) Four interrupt sources with vector interrupt level 8-bit timer/counter with time interval mode Analog digital converter with nine input channels(MAX) 10-bit resolution 8-bit output S3C9454B/F9454B microcontroller ideal wide range electronic applications requiring simple timer/counter, PWM, ADC. S3C9454B/F9454B available 20/16-pin 20/16-pin 20/16pin SSOP package.
S3F9454B (Multi Time Programmable) version S3C9454B microcontroller. S3F9454B on-chip 4-Kbyte multi-time programmable flash instead masked ROM. S3F9454B fully compatible with S3C9454B, function, D.C. electrical characteristics configuration.
PRODUCT OVERVIEW
S3C9454B/F9454B
FEATURES
SAM88RCRI core SAM88RCRI core low-end version current SAM87 core. Timer/Counters 8-bit basic timer watchdog function 8-bit timer/counter with time interval modes
Converter Memory 4-Kbyte internal program memory 208-byte general purpose register area Oscillation Frequency Instruction instructions SAM88RCRI core provides SAM87 core instruction except word-oriented instruction, multiplication, division, some one-byte instruction. external crystal oscillator Maximum clock Internal (typ.), (typ.) Nine analog input pins (MAX) 10-bit conversion resolution
Operating Temperature Range Instruction Execution Time fOSC (minimum) Operating Voltage Range Interrupts interrupt sources with vector interrupt level Smart Option General Three ports (Max pins) programmable ports Package Types S3C9454B/F9454B: 20-SSOP-225 20-DIP-300A 20-SOP-375 16-SOP-BD300-SG 16-DIP-300A 16-SSOP-BD44 (LVR disable) 5.5V (LVR enable) 25°C 85°C
8-bit High-speed 8-bit 1-ch (Max: kHz) 6-bit base 2-bit extension
Built-in Reset Circuit voltage detector safe Reset
S3C9454B/F9454B
PRODUCT OVERVIEW
BLOCK DIAGRAM
XOUT
Port Port Interrupt Control Basic Timer
P0.0/ADC0/INT0 P0.1/ADC1/INT1 P0.2/ADC2 P0.7/ADC7
P1.0 P1.1 P1.2
Timer 88RCRI SAMRI
Port
ADC0-ADC8
P0.6/PWM
Byte Register File
Port
P2.0/T0 P2.1 P2.6
NOTE:
P1.2 used input only
Figure 1-1. Block Diagram
PRODUCT OVERVIEW
S3C9454B/F9454B
ASSIGNMENTS
XIN/P1.0 XOUT/P1.1 nRESET/P1.2 P2.0/T0 P2.1 P2.2 P2.3 P2.4 P2.5
P0.0/ADC0/INT0 P0.1/ADC1/INT1 P0.2/ADC2 P0.3/ADC3 P0.4/ADC4 P0.5/ADC5 P0.6/ADC6/PWM P0.7/ADC7 P2.6/ADC8/CLO
S3C9454B/F9454B
(20-DIP-300A/ 20-SOP-375/ 20-SSOP-225)
Figure 1-2. Assignment Diagram (20-Pin DIP/SOP/SSOP Package)
S3C9454B/F9454B
PRODUCT OVERVIEW
XIN/P1.0 XOUT/P1.1 nRESET/P1.2 P2.0/T0 P2.1 P2.2 P2.3
(16-DIP-300A/ 16-SOP-BD300-SG/ 16-SSOP-BD44)
P0.0/ADC0/INT0 P0.1/ADC1/INT1 P0.2/ADC2 P0.3/ADC3 P0.4/ADC4 P0.5/ADC5 P0.6/ADC6/PWM
S3C9454B/F9454B
Figure 1-3. Assignment Diagram (16-Pin DIP/SOP/SSOP Package)
PRODUCT OVERVIEW
S3C9454B/F9454B
DESCRIPTIONS
Table 1-1. S3C9454B/F9454B Descriptions Name P0.0-P0.7 Input/ Output Description Bit-programmable port Schmitt trigger input push-pull output. Pull-up resistors assignable software. Port0 pins also used converter input, output external interrupt input. Bit-programmable port Schmitt trigger input push-pull, open-drain output. Pull-up resistors pull-down resistors assignable software. Schmitt trigger input port Bit-programmable port Schmitt trigger input pushpull, open-drain output. Pull-up resistors assignable software. Crystal/Ceramic, oscillator signal system clock. Internal external RESET Voltage input ground System clock output port External interrupt input port 8-Bit high speed output Timer0 match output converter input Type Share Pins ADC0-ADC7 INT0/INT1 XIN, XOUT
P1.0-P1.1
P1.2 P2.0-P2.6
RESET ADC8/CLO P1.0-P1.1 P1.2 P2.6 P0.0, P0.1 P0.6 P2.0 P0.0-P0.7 P2.6
XIN, XOUT nRESET VDD, INT0-INT1 ADC0-ADC8
S3C9454B/F9454B
PRODUCT OVERVIEW
CIRCUITS
P-channel N-channel
Figure 1-5. Circuit Type
Figure 1-6. Circuit Type
Data Output DIsable
Pull-up Enable Data Output Disable
Circuit Type
Digital Input
Figure 1-7. Circuit Type
Figure 1-8. Circuit Type
PRODUCT OVERVIEW
S3C9454B/F9454B
Open-drain Enable P2CONH P2CONL Alternative Output P2.x Pull-up enable
P-CH Data N-CH
Output Disable (Input Mode) Digital Input
Analog Input Enable
Figure 1-9. Circuit Type
P0CONH Alternative Output P0.x
Pull-up enable
P-CH Data N-CH
Output Disable (Input Mode) Digital Input
Interrupt Input Analog Input Enable
Figure 1-10. Circuit Type
S3C9454B/F9454B
PRODUCT OVERVIEW
Open-drain Enable Pull-up enable
P1.x Output Disable (Input Mode) Pull-down enable
Digital Input XOUT
Figure 1-11. Circuit Type
PRODUCT OVERVIEW
S3C9454B/F9454B
NOTES
1-10
S3C9454B/F9454B
ADDRESS SPACES
OVERVIEW
ADDRESS SPACES
S3C9454B/F9454B microcontroller kinds address space: Internal program memory (ROM) Internal register file 12-bit address supports program memory operations. separate 8-bit register carries addresses data between internal register file. S3C9454B/F9454B have 4-Kbytes mask-programmable on-chip program memory: which configured Internal mode, 4-Kbyte internal program memory used. S3C9454B/F9454B microcontroller general-purpose registers internal register file. Twenty-six bytes register file mapped system peripheral control functions.
ADDRESS SPACES
S3C9454B/F9454B
PROGRAM MEMORY (ROM)
Normal Operating Mode S3C9454B/F9454B have 4-Kbytes (locations 0H-0FFFH) internal mask-programmable program memory. first 2-bytes (0000H-0001H) interrupt vector address. Unused locations (0002H-00FFH except 3CH, 3DH, 3EH, 3FH) used normal program memory. 3CH, 3DH, 3EH, used smart option cell. program Reset address 0100H.
(Decimal) 4.095
(HEX) 1000H
4-Kbyte Program Memory Area
Program Start Interrupt Vector Smart option cell
0100H 0040H 003CH 0002H 0001H 0000H
Figure 2-1. Program Memory Address Space
S3C9454B/F9454B
ADDRESS SPACES
Smart Option Smart option option starting condition chip. addresses used smart option from 003CH 003FH. S3C9454B/F9454B only 003EH, 003FH. used address 003CH, 003DH should initialized initialized 00H. default value (LVR enable, internal oscillator).
Address: 003CH
Must initialized 00H. Address: 003DH
Must initialized 00H.
Address: 003EH
enable/disable bit: Disable Enable level selection bits: 11001 10010 01100
used
Address: 003FH
used.
NOTES: When external oscillator, P1.0, P1.1 must output port prevent current consumption. value unused bits 3EH, don't care. When enabled, level must appropriate value, default value.
Oscillator selection bits: External crystal/ ceramic oscillator External Internal (0.5 Internal (3.2
Figure 2-2. Smart Option
ADDRESS SPACES
S3C9454B/F9454B
PROGRAMMING Smart Option Setting
Interrupt Vector Address Vector 0000H 00H, INT_9454 S3C9454B/F9454B only interrupt vector
Smart Option Setting 003CH 0E7H 003CH, must initialized 003DH, must initialized 003EH, enable (2.3 003FH, Internal (3.2
Reset RESET: 0100H
S3C9454B/F9454B
ADDRESS SPACES
REGISTER ARCHITECTURE
upper 64-bytes S3C9454B/F9454B's internal register file addressed working registers, system control registers peripheral control registers. lower 192-bytes internal register file(00H-BFH) called general purpose register space. registers this space accessed; available generalpurpose use. many SAM88RCRI microcontrollers, addressable area internal register file further expanded additional register pages general purpose register space (00H-BFH: page0). This register file expansion implemented S3C9454B/F9454B, however. specific register types area bytes) that they occupy internal register file summarized Table 2-1. Table 2-1. Register Type Summary Register Type system control registers Peripheral, I/O, clock control data registers General-purpose registers (including 16-bit common working register area) Total Addressable Bytes Number Bytes
ADDRESS SPACES
S3C9454B/F9454B
Peripheral Control Registers Bytes Common Area
System Control Registers Working Registers
Bytes
General Purpose Register File Stack Area
Figure 2-3. Internal Register File Organization
S3C9454B/F9454B
ADDRESS SPACES
COMMON WORKING REGISTER AREA (C0H-CFH)
SAM88RCRI register architecture provides efficient method working register addressing that takes full advantage shorter instruction formats reduce execution time. This16-byte address range called common area. That locations this area used working registers operations that address location page register file. Typically, these working registers serve temporary buffers data operations between different pages. However, because S3C9454B/F9454B uses only page common area internal data operation. Register addressing mode used access this area Registers addressed either single 8-bit register paired 16-bit register. 16-bit register pairs, address first 8-bit register always even number address next register number. most significant byte 16-bit data always stored even-numbered register; least significant byte always stored next odd-numbered register.
Rn+1
Even address
Figure 2-4. 16-Bit Register Pairs
PROGRAMMING Addressing Common Working Register Area
following examples show, should access working registers common area, locations C0H-CFH, using working register addressing mode only. Examples: 0C2H,40H Invalid addressing mode! (C2H) value location Invalid addressing mode! (C3H)
working register addressing instead: R2,40H 0C3H,#45H
working register addressing instead: R3,#45H
ADDRESS SPACES
S3C9454B/F9454B
SYSTEM STACK
S3C9-series microcontrollers system stack subroutine calls returns store data. PUSH instructions used control system stack operations. S3C9454B/F9454B architecture supports stack operations internal register file. Stack Operations Return addresses procedure calls interrupts data stored stack. contents saved stack CALL instruction restored instruction. When interrupt occurs, contents FLAGS register pushed stack. IRET instruction then pops these values back their original locations. stack address always decremented before push operation incremented after operation. stack pointer (SP) always points stack frame stored stack, shown Figure 2-5.
High Address
stack stack Flags Stack contents after interrupt
Stack contents after call instruction
Address
Figure 2-5. Stack Operations Stack Pointer (SP) Register location contains 8-bit stack pointer (SP) that used system stack operations. After reset, value undetermined. Because only internal memory space implemented S3C9454B/F9454B, must initialized 8bit value range 00H-0C0H. NOTE case Stack Pointer initialized 00H, decreased when stack operation starts. This means that Stack Pointer access invalid stack area. recommend that stack pointer initialized upper address stack BFH.
S3C9454B/F9454B
ADDRESS SPACES
PROGRAMMING Standard Stack Operations Using PUSH
following example shows perform stack operations internal register file using PUSH instructions:
SP,#0C0H
(Normally, initialization routine)
PUSH PUSH PUSH PUSH
Stack address 0BFH Stack address 0BEH Stack address 0BDH Stack address 0BCH
Stack address 0BCH Stack address 0BDH Stack address 0BEH Stack address 0BFH
ADDRESS SPACES
S3C9454B/F9454B
NOTES
2-10
S3C9454B/F9454B
ADDRESSING MODES
OVERVIEW
Register
ADDRESSING MODES
Instructions that stored program memory fetched execution using program counter. Instructions indicate operation performed data operated Addressing mode method used determine location data operand. operands specified SAM88RCRI instructions condition codes, immediate data, location register file, program memory, data memory. SAM88RCRI instruction supports explicit addressing modes. these addressing modes available each instruction. addressing modes their symbols follows:
Indirect Register (IR) Indexed Direct Address (DA) Relative Address (RA) Immediate (IM)
ADDRESSING MODES
S3C9454B/F9454B
REGISTER ADDRESSING MODE Register addressing mode, operand content specified register (see Figure 3-1). Working register addressing differs from Register addressing because uses 16-byte working register space register file 4-bit register within that space (see Figure 3-2).
Program Memory 8-Bit Register File Address One-Operand Instruction (Example)
Register File
OPCODE
Point register register file Value used Instruction Execution
OPERAND
Sample Instruction: CNTR Where CNTR label 8-bit register address
Figure 3-1. Register Addressing
Register File point
Program Memory 4-Bit Working Register Two-Operand Instruction (Example) LSBs Point working register OPERAND
Selected points start working register block
OPCODE
Sample Instruction: Where registers currently selected working register area.
Figure 3-2. Working Register Addressing
S3C9454B/F9454B
ADDRESSING MODES
INDIRECT REGISTER ADDRESSING MODE (IR) Indirect Register (IR) addressing mode, content specified register register pair address operand. Depending instruction used, actual address point register register file, program memory (ROM), external memory space (see Figures through 3-6). 8-bit register indirectly address another register. 16-bit register pair used indirectly address another memory location.
Program Memory 8-Bit Register File Address
Register File
OPCODE
One-Operand Instruction (Example)
Point register register file Address operand used instruction
ADDRESS
Value used instruction execution
OPERAND
Sample Instruction: @SHIFT Where SHIFT label 8-bit register ddress
Figure 3-3. Indirect Register Addressing Register File
ADDRESSING MODES
S3C9454B/F9454B
INDIRECT REGISTER ADDRESSING MODE (Continued)
Register File
Program Memory Example Instruction References Program Memory REGISTER PAIR Point register pair 16-bit address points program memory
OPCODE
Program Memory Value used instruction
OPERAND
Sample Instructions: CALL @RR2 @RR2
Figure 3-4. Indirect Register Addressing Program Memory
S3C9454B/F9454B
ADDRESSING MODES
INDIRECT REGISTER ADDRESSING MODE (Continued)
Register File
Program Memory 4-Bit Working Register Address LSBs Point working register
OPERAND
OPCODE
Sample Instruction:
Value used instruction
OPERAND
Figure 3-5. Indirect Working Register Addressing Register File
ADDRESSING MODES
S3C9454B/F9454B
INDIRECT REGISTER ADDRESSING MODE (Concluded)
Register File
Program Memory 4-Bit Working Register Address OPCODE Next Bits Point working register pair Selects
Register Pair 16-Bit address points program memory data memory
Example instruction references either program memory data memory
Program Memory Data Memory
Value used instruction
OPERAND
Sample Instructions: R5,@RR6 R3,@RR14 @RR4, Program memory access External data memory access External data memory access
Figure 3-6. Indirect Working Register Addressing Program Data Memory
S3C9454B/F9454B
ADDRESSING MODES
INDEXED ADDRESSING MODE Indexed addressing mode adds offset value base address during instruction execution order calculate effective operand address (see Figure 3-7). Indexed addressing mode access locations internal register file external memory. short offset Indexed addressing mode, 8-bit displacement treated signed integer range 127. This applies external memory accesses only (see Figure 3-8). register file addressing, 8-bit base address provided instruction added 8-bit offset contained working register. external memory accesses, base address stored working register pair designated instruction. 8-bit 16-bit offset given instruction then added base address (see Figure 3-9). only instruction that supports Indexed addressing mode internal register file Load instruction (LD). instructions support Indexed addressing mode internal program memory, external program memory, external data memory, when implemented.
Register File
Value used instruction OPERAND
Program Memory (OFFSET) OPCODE LSBs Point working register
INDEX
Two-Operand Instruction Example
Sample Instruction: #BASE[R1] Where BASE 8-bit immediate value
Figure 3-7. Indexed Addressing Register File
ADDRESSING MODES
S3C9454B/F9454B
INDEXED ADDRESSING MODE (Continued)
Program Memory 4-Bit Working Register Address (OFFSET) OPCODE NEXT Bits Point working register pair
Register File
Register Pair 16-Bit address added offset
Selects
8-Bit 16-Bit Program Memory Data memory Value used instruction
16-Bit
OPERAND
Sample Instructions: #04H[RR2] R4,#04H[RR2] values program address (RR2 #04H) loaded into register Identical operation example, except that external program memory accessed.
Figure 3-8. Indexed Addressing Program Data Memory with Short Offset
S3C9454B/F9454B
ADDRESSING MODES
INDEXED ADDRESSING MODE (Concluded)
Program Memory (OFFSET) 4-Bit Working Register Address (OFFSET) OPCODE NEXT Bits Point working register pair Selects 16-Bit 16-Bit
Register File
Register Pair 16-Bit address added offset
Program Memory Datamemory
16-Bit Sample Instructions: #1000H[RR2] #1000H[RR2]
OPERAND
Value used instruction
values program address (RR2 #1000H) loaded into register Identical operation example, except that external program memory accessed.
Figure 3-9. Indexed Addressing Program Data Memory with Long Offset
ADDRESSING MODES
S3C9454B/F9454B
DIRECT ADDRESS MODE (DA) Direct Address (DA) mode, instruction provides operand's 16-bit memory address. Jump (JP) Call (CALL) instructions this addressing mode specify 16-bit destination address that loaded into whenever CALL instruction executed. instructions Direct Address mode specify source destination address Load operations program memory (LDC) external data memory (LDE), implemented.
Program Data Memory
Program Memory
Memory Address Used
Upper Address Byte Lower Address Byte dst/src OPCODE
Selects Program Memory Data Memory: Program Memory Data Memory
Sample Instructions: R5,1234H R5,1234H values program address (1234H)are loaded into register Identical operation example, except that external program memory accessed.
Figure 3-10. Direct Addressing Load Instructions
3-10
S3C9454B/F9454B
ADDRESSING MODES
DIRECT ADDRESS MODE (Continued)
Program Memory
Next OPCODE Program Memory Address Used Lower Address Byte Upper Address Byte OPCODE
Sample Instructions: CALL C,JOB1 DISPLAY Where JOB1 16-bit immediate address Where DISPLAY 16-bit immediate address
Figure 3-11. Direct Addressing Call Jump Instructions
3-11
ADDRESSING MODES
S3C9454B/F9454B
RELATIVE ADDRESS MODE (RA) Relative Address (RA) mode, two's-complement signed displacement between specified instruction. displacement value then added current value. result address next instruction executed. Before this addition occurs, contains address instruction immediately following current instruction. instructions that support addressing
Program Memory
Next OPCODE Program Memory Address Used
Current Instruction
Displacement OPCODE
Current Value Signed Displacement Value
Sample Instructions: ULT,$ OFFSET Where OFFSET value range
Figure 3-12. Relative Addressing
IMMEDIATE MODE (IM) Immediate (IM) addressing mode, operand value used instruction value supplied operand field itself. Immediate addressing mode useful loading constant values into registers.
Program Memory OPERAND OPCODE
(The Operand value instruction) Sample Instruction: R0,#0AAH
Figure 3-13. Immediate Addressing
3-12
S3C9454B/F9454B
CONTROL REGISTERS
OVERVIEW
CONTROL REGISTERS
this section, detailed descriptions S3C9454B/F9454B control registers presented easy-to-read format. These descriptions will help familiarize with mapped locations register file. also them quick-reference source when writing application programs. System peripheral registers summarized Table 4-1. Figure illustrates important features standard register description format. Control register descriptions arranged alphabetical order according register mnemonic. More information about control registers presented context various peripheral hardware descriptions Part this manual.
CONTROL REGISTERS
S3C9454B/F9454B
Table 4-1. System Peripheral Control Registers Register name Timer counter register Timer data register Timer control register Clock control register System flags register Stack pointer register special register Basic timer control register Basic timer counter Test mode control register System mode register Mnemonic T0CNT T0DATA T0CON CLKCON FLAGS MDSREG BTCON BTCNT FTSTCON Address Location Address RESET value (Bit)
Location mapped
Locations D6H-D8H mapped Location mapped
NOTES: mapped used, Undefined factory test mode register, FTSTCON, factory only. value should always '00H' during normal operation.
S3C9454B/F9454B
CONTROL REGISTERS
Table 4-1. System Peripheral Control Registers (Continued) Register Name Port data register Port data register Port data register Port control register (High byte) Port control register Port interrupt pending register Port control register Port control register (High byte) Port control register (Low byte) data register control register STOP .control register control register converter data register High converter data register Mnemonic P0CONH P0CONL P0PND P1CON P2CONH P2CONL PWMDATA PWMCON STOPCON ADCON ADDATAH ADDATAL Address Values After RESET
Locations E3H-E5H mapped
Locations ECH-F1H mapped
Locations F5H-F6H mapped
Locations FAH-FFH mapped
NOTE: mapped used, Undefined
CONTROL REGISTERS
S3C9454B/F9454B
number(s) that is/are appended register name addressing Name individual Register related bits Register name
Register address (hexadecimal)
FLAGS System Flags Register
Identifier RESET Value Read/Write
Carry Flag Operation dose generate carry borrow condition Operation generates carry-out borrow into high-order bit7
Zero Flag Operation result non-zero value Operation result zero
Sign Flag Operation generates positive number (MSB "0") Operation generates negative number (MSB "1")
Read-only Write-only Read/write used
Description effect specific settings
RESET value notation: used Undetermind value Logic zero Logic
number:
Figure 4-1. Register Description Format
S3C9454B/F9454B
CONTROL REGISTERS
ADCON Converter Control Register
Identifier RESET Value Read/Write .7-.4
Converter Input Selection Bits ADC0 (P0.0) ADC1 (P0.1) ADC2 (P0.2) ADC3 (P0.3) ADC4 (P0.4) ADC5 (P0.5) ADC6 (P0.6) ADC7 (P0.7) ADC8 (P2.6) Connected with internally Connected with internally Connected with internally Connected with internally Connected with internally Connected with internally Connected with internally
End-of-Conversion Status conversion progress conversion complete
.2-.1
Clock Source Selection (note) fOSC/16 (fOSC MHz) fOSC/8 (fOSC MHz) fOSC/4 (fOSC MHz) fOSC/1 (fOSC MHz)
Conversion Start meaning conversion start
NOTE: Maximum clock input MHz.
CONTROL REGISTERS
S3C9454B/F9454B
BTCON Basic Timer Control Register
Identifier RESET Value Read/Write .7-.4
Watchdog Timer Function Enable Disable watchdog timer function Enable watchdog timer function Others
.3-.2
Basic Timer Input Clock Selection Code fOSC/4096 fOSC/1024 fOSC/128 Invalid setting
Basic Timer 8-Bit Counter Clear effect Clear basic timer counter value
Basic Timer Divider Clear effect Clear both dividers
NOTE: When write BTCON.0 BTCON.1), basic timer counter basic timer divider) cleared. then cleared automatically "0".
S3C9454B/F9454B
CONTROL REGISTERS
CLKCON Clock Control Register
Identifier RESET Value Read/Write
Oscillator Wake-up Function Enable Enable main system oscillator wake-up function Disable main system oscillator wake-up function
.6-.5 .4-.3
used S3C9454B/F9454B Divided Selection Bits Clock frequency Divide (fOSC/16) Divide (fOSC/8) Divide (fOSC/2) Non-divided clock (fOSC)
.2-.0
used S3C9454B/F9454B
CONTROL REGISTERS
S3C9454B/F9454B
FLAGS System Flags Register
Identifier RESET Value Read/Write
Carry Flag Operation does generate carry borrow condition Operation generates carry-out borrow into high-order
Zero Flag Operation result non-zero value Operation result zero
Sign Flag Operation generates positive number (MSB "0") Operation generates negative number (MSB "1")
Overflow Flag Operation result Operation result
.3-.0
used S3C9454B/F9454B
S3C9454B/F9454B
CONTROL REGISTERS
P0CONH Port Control Register (High Byte)
Identifier RESET Value Read/Write .7-.6
Port P0.7/INT7 Configuration Bits Schmitt trigger input; pull-up enable Schmitt trigger input Push-pull output converter input (ADC7); Schmitt trigger input
.5-.4
Port P0.6/ADC6/PWM Configuration Bits Schmitt trigger input; pull-up enable Alternative function (PWM output) Push-pull output converter input (ADC6); Schmitt trigger input
.3-.2
Port P0.5/ADC5 Configuration Bits Schmitt trigger input; pull-up enable Schmitt trigger input Push-pull output converter input (ADC5); Schmitt trigger input
.1-.0
Port P0.4/ADC4 Configuration Bits Schmitt trigger input; pull-up enable Schmitt trigger input Push-pull output converter input (ADC4); Schmitt trigger input
CONTROL REGISTERS
S3C9454B/F9454B
P0CONL Port Control Register (Low Byte)
Identifier RESET Value Read/Write .7-.6
Port P0.3/INT3 Configuration Bits Schmitt trigger input Schmitt trigger input; pull-up enable Push-pull output converter input (ADC3); Schmitt trigger input
.5-.4
Port P0.2/ADC2 Configuration Bits Schmitt trigger input Schmitt trigger input; pull-up enable Push-pull output converter input (ADC2); Schmitt trigger input
.3-.2
Port P0.1/ADC1/INT1 Configuration Bits Schmitt trigger input/falling edge interrupt input Schmitt trigger input; pull-up enable/falling edge interrupt input Push-pull output converter input (ADC1); Schmitt trigger input
.1-.0
Port P0.0/ADC0/INT0 Configuration Bits Schmitt trigger input/falling edge interrupt input Schmitt trigger input; pull-up enable/falling edge interrupt input Push-pull output converter input (ADC0); Schmitt trigger input
4-10
S3C9454B/F9454B
CONTROL REGISTERS
P0PND Port Interrupt Pending Register
Identifier RESET Value Read/Write .7-.4
used S3C9454B/F9454B Port 0.1/ADC1/INT1 Interrupt Enable INT1 falling edge interrupt disable INT1 falling edge interrupt enable
Port 0.1/ADC1/INT1 Interrupt Pending interrupt pending (when read) Pending clear (when write) Interrupt pending (when read) effect (when write)
Port 0.0/ADC0/INT0 Interrupt Enable INT0 falling edge interrupt disable INT0 falling edge interrupt enable
Port 0.0/ADC0/INT0 Interrupt Pending interrupt pending (when read) Pending clear (when write) Interrupt pending (when read) effect (when write)
4-11
CONTROL REGISTERS
S3C9454B/F9454B
P1CON Port Control Register
Identifier RESET Value Read/Write
Part N-channel open-drain Enable Configure P1.1 push-pull output Configure P1.1 n-channel open-drain output
Port N-channel open-drain Enable Configure P1.0 push-pull output Configure P1.0 n-channel open-drain output
.5-.4 .3-.2
used S3C9454B/F9454B Port P1.1 Interrupt Pending Bits Schmitt trigger input; Schmitt trigger input; pull-up enable Output Schmitt trigger input; pull-down enable
.1-.0
Port P1.0 Configuration Bits Schmitt trigger input; Schmitt trigger input; pull-up enable Output Schmitt trigger input; pull-down enable
NOTE: When external oscillator, P1.0, P1.1 must output port prevent current consumption.
4-12
S3C9454B/F9454B
CONTROL REGISTERS
P2CONH Port Control Register (High Byte)
Identifier RESET Value Read/Write .6-.4
used S3C9454B/F9454B Port P2.6/ADC8/CLO Configuration Bits Schmitt trigger input; pull-up enable Schmitt trigger input input Push-pull output Open-drain output; pull-up enable Open-drain output Alternative function; output
.3-.2
Port Configuration Bits Schmitt trigger input; pull-up enable Schmitt trigger input Push-pull output Open-drain output
.1-.0
Port Configuration Bits Schmitt trigger input; pull-up enable Schmitt trigger input Push-pull output Open-drain output
NOTE: When noise problem important issue, better output.
4-13
CONTROL REGISTERS
S3C9454B/F9454B
P2CONL Port Control Register (Low Byte)
Identifier RESET Value Read/Write .7-.6
Part P2.3 Configuration Bits Schmitt trigger input; pull-up enable Schmitt trigger input Push-pull output Open-drain output
.5-.4
Port P2.2 Configuration Bits Schmitt trigger input; pull-up enable Schmitt trigger input Push-pull output Open-drain output
.3-.2
Port P2.1 Configuration Bits Schmitt trigger input; pull-up enable Schmitt trigger input Push-pull output Open-drain output
.1-.0
Port P2.0 Configuration Bits Schmitt trigger input; pull-up enable Schmitt trigger input Push-pull output match output
4-14
S3C9454B/F9454B
CONTROL REGISTERS
PWMCON Control Register
Identifier RESET Value Read/Write .7-.6
Input Clock Selection Bits fOSC/64 fOSC/8 fOSC/2 fOSC/1
used S3C9454B/F9454B PWMDATA Reload Interval Selection Reload from 8-bit counter overflow Reload from 6-bit counter overflow
Counter Clear effect Clear counter (when write)
Counter Enable Stop counter Start (Resume countering)
Overflow Interrupt Enable (8-Bit Overflow) Disable interrupt Enable interrupt
Overflow Interrupt Pending interrupt pending (when read) Clear pending (when write) Interrupt pending (when read) effect (when write)
NOTE: PWMCON.3 auto-cleared. must attention when clear pending bit. (refer page 11-8).
4-15
CONTROL REGISTERS
S3C9454B/F9454B
STOPCON STOP Mode Control Register
Identifier RESET Value Read/Write .7-.0
Watchdog Timer Function Enable 10100101 Other value Enable STOP instruction Disable STOP instruction
NOTE: When STOPCON register #0A5H value, STOP instruction, changed reset address.
System Mode Register
Identifier RESET Value Read/Write .7-.3
used S3C9454B/F9454B Global Interrupt Enable Disable interrupts Enable interrupt
.2-.0
Page Select Bits Page Page (Not used S3C9454B/F9454B) Page (Not used S3C9454B/F9454B) Page (Not used S3C9454B/F9454B)
4-16
S3C9454B/F9454B
CONTROL REGISTERS
T0CON TIMER Control Register
Identifier RESET Value Read/Write .7-.6
Timer Input Clock Selection Bits fOSC/4096 fOSC/256 fOSC/8 fOSC/1
.5-.4
used S3C9454B/F9454B Timer Counter Clear effect Clear timer counter (when write)
used S3C9454B/F9454B Timer Interrupt Enable Disable interrupt Enable interrupt
Timer Interrupt Pending (Capture match interrupt) interrupt pending (when read) Clear pending (when write) Interrupt pending (when read) effect (when write)
NOTES: T0CON.3 auto-cleared. must attention when clear pending bit. (refer page 10-12) match output, T0CON.3 "1". (refer page 10-7)
4-17
CONTROL REGISTERS
S3C9454B/F9454B
NOTES
4-18
S3C9454B/F9454B
INTERRUPT STRUCTURE
OVERVIEW
INTERRUPT STRUCTURE
SAM88RCRI interrupt structure basic components: vector, sources. number interrupt sources serviced through interrupt vector which assigned address 0000H.
VECTOR
SOURCES
0000H 0001H
NOTES: SAM88RCRI interrupt only vector address (0000H-0001H). numbern value expandable.
Figure 5-1. S3F9-Series Interrupt Type
INTERRUPT PROCESSING CONTROL POINTS Interrupt processing controlled ways: either globally, specific interrupt level source. system-level control points interrupt structure therefore: Global interrupt enable disable instructions) Interrupt source enable disable settings corresponding peripheral control register(s)
INTERRUPT STRUCTURE
S3C9454B/F9454B
ENABLE/DISABLE INTERRUPT INSTRUCTIONS (EI, system mode register, (DFH), used enable disable interrupt processing. SYM.3 enable disable global interrupt processing respectively, modifying SYM.3. Enable Interrupt (EI) instruction must included initialization routine that follows reset operation order enable interrupt processing. Although manipulate SYM.3 directly enable disable interrupts during normal operation, recommend that instructions this purpose. INTERRUPT PENDING FUNCTION TYPES When interrupt service routine executed, application program's service routine must clear appropriate pending before return from interrupt subroutine (IRET) occurs. INTERRUPT PRIORITY Because there interrupt priority register SAM88RCRI, order service determined sequence source which executed interrupt service routine.
"EI" Instruction Execution RESET Source Interrupts Source Interrupt Enable
Interrupt Pending Register Interrpt priority determind software polling method
Vector Interrupt Cycle
Global Interrupt Control (EI, instruction)
Figure 5-2. Interrupt Function Diagram
S3C9454B/F9454B
INTERRUPT STRUCTURE
INTERRUPT SOURCE SERVICE SEQUENCE interrupt request polling servicing sequence follows: source generates interrupt request setting interrupt request pending "1". generates interrupt acknowledge signal. service routine starts source's pending flag cleared software. Interrupt priority must determined software polling method.
INTERRUPT SERVICE ROUTINES Before interrupt request serviced, following conditions must met: Interrupt processing must enabled (EI, SYM.3 "1") Interrupt must enabled interrupt's source (peripheral control register) above conditions met, interrupt request acknowledged instruction cycle. then initiates interrupt machine cycle that completes following processing sequence: Reset (clear "0") global interrupt enable register (DI, SYM.3 "0") disable subsequent interrupts. Save program counter status flags stack. Branch interrupt vector fetch service routine's address. Pass control interrupt service routine. When interrupt service routine completed, Interrupt Return instruction (IRET) occurs. IRET restores status flags sets SYM.3 (EI), allowing process next interrupt request. GENERATING INTERRUPT VECTOR ADDRESSES interrupt vector area contains address interrupt service routine. Vectored interrupt processing follows this sequence: Push program counter's low-byte value stack. Push program counter's high-byte value stack. Push FLAGS register values stack. Fetch service routine's high-byte address from vector address 0000H. Fetch service routine's low-byte address from vector address 0001H. Branch service routine specified 16-bit vector address.
INTERRUPT STRUCTURE
S3C9454B/F9454B
S3C9454B/F9454B INTERRUPT STRUCTURE S3C9454B/F9454B microcontroller four peripheral interrupt sources: overflow Timer match P0.0 external interrupt P0.1 external interrupt
Vector
Pending Bits T0CON.0
Enable/Disable
Source Timer Match
T0CON.1 Overflow PWMCON.1 P0.0 External Interrupt P0PND.1 P0.1 External Interrupt P0PND.3
PWMCON.0 0000H 0001H P0PND.0 SYM.2 (EI,
P0PND.2
Figure 5-3. S3C9454B/F9454B Interrupt Structure
S3C9454B/F9454B
SAM88RCRI INSTRUCTION
OVERVIEW
SAM88RCRI INSTRUCTION
SAM88RCRI instruction designed support large register file. includes full complement 8-bit arithmetic logic operations. There instructions. special instructions necessary because control data registers mapped directly into register file. Flexible instructions addressing, rotate, shift operations complete powerful data manipulation capabilities SAM88RCRI instruction set. REGISTER ADDRESSING access individual register, 8-bit address range 0-255 4-bit address working register specified. Paired registers used construct 13-bit program memory data memory addresses. detailed information about register addressing, please refer Chapter "Address Spaces". ADDRESSING MODES There addressing modes: Register (R), Indirect Register (IR), Indexed (X), Direct (DA), Relative (RA), Immediate (IM). detailed descriptions these addressing modes, please refer Chapter "Addressing Modes".
SAM88RCRI INSTRUCTION
S3C9454B/F9454B
Table 6-1. Instruction Group Summary Mnemonic Operands Instruction
Load Instructions LDCD LDED LDCI LDEI PUSH dst,src dst,src dst,src dst,src dst,src dst,src dst,src Clear Load Load program memory Load external data memory Load program memory decrement Load external data memory decrement Load program memory increment Load external data memory increment from stack Push stack
Arithmetic Instructions dst,src dst,src dst,src dst,src dst,src with carry Compare Decrement Increment Subtract with carry Subtract
Logic Instructions dst,src dst,src dst,src Logical Complement Logical Logical exclusive
S3C9454B/F9454B
SAM88RCRI INSTRUCTION
Table 6-1. Instruction Group Summary (Continued) Mnemonic Operands Instruction
Program Control Instructions CALL IRET cc,dst cc,dst Call procedure Interrupt return Jump condition code Jump unconditional Jump relative condition code Return
Manipulation Instructions dst,src dst,src Test complement under mask Test under mask
Rotate Shift Instructions Rotate left Rotate left through carry Rotate right Rotate right through carry Shift right arithmetic
Control Instructions IDLE STOP Complement carry flag Disable interrupts Enable interrupts Enter Idle mode operation Reset carry flag carry flag Enter stop mode
SAM88RCRI INSTRUCTION
S3C9454B/F9454B
FLAGS REGISTER (FLAGS) flags register FLAGS contains eight bits that describe current status operations. Four these bits, FLAGS.4-FLAGS.7, tested used with conditional jump instructions; FLAGS register reset instructions long outcome does affect flags, such Load instruction. Logical Arithmetic instructions such AND, XOR, ADD, affect Flags register. example, instruction updates Zero, Sign Overflow flags based outcome instruction. instruction uses Flags register destination, then simultaneously, write will occur Flags register producing unpredictable result.
System Flags Register (FLAGS) D5H, Carry flag mapped Zero flag
Sign flag
Overflow flag
Figure 6-1. System Flags Register (FLAGS) FLAG DESCRIPTIONS 030303Overflow Flag (FLAGS.4, flag when result two's-complement operation greater than less than 128. also cleared following logic operations. Sign Flag (FLAGS.5, Following arithmetic, logic, rotate, shift operations, sign identifies state result. logic zero indicates positive number logic indicates negative number. Zero Flag (FLAGS.6, arithmetic logic operations, flag result operation zero. operations that test register bits, shift rotate operations, flag result logic zero. Carry Flag (FLAGS.7, flag result from arithmetic operation generates carry-out from borrow position (MSB). After rotate shift operations, contains last value shifted specified register. Program instructions set, clear, complement carry flag.
S3C9454B/F9454B
SAM88RCRI INSTRUCTION
INSTRUCTION NOTATION Table 6-2. Flag Notation Conventions Flag Carry flag Zero flag Sign flag Overflow flag Cleared logic zero logic cleared according operation Value unaffected Value undefined Description
Table 6-3. Instruction Symbols Symbol FLAGS Source operand Indirect register address prefix Program counter Flags register (D5H) Immediate operand register address prefix Hexadecimal number suffix Decimal number suffix Binary number suffix Opcode Description Destination operand
SAM88RCRI INSTRUCTION
S3C9454B/F9454B
Table 6-4. Instruction Notation Conventions Notation Condition code Working register only Working register pair Register working register Register pair working register pair Description Actual Operand Range list condition codes Table 6-6. 0-15) (reg 0-255, 0-15) (reg 0-254, even number only, where 0-15)
Indirect working register only
Indirect register indirect working register @reg (reg 0-255, 0-15) Indirect working register pair only Indirect register pair indirect working register pair Indexed addressing mode Indexed (short offset) addressing mode @RRp @RRp @reg (reg 0-254, even only, where #reg[Rn] (reg 0-255, 0-15) #addr[RRp] (addr range 127, where #addr [RRp] (addr range 0-8191, where addr (addr range 0-8191) addr (addr number range that offset relative address next instruction) #data (data 0-255)
Indexed (long offset) addressing mode
Direct addressing mode Relative addressing mode
Immediate addressing mode
S3C9454B/F9454B
SAM88RCRI INSTRUCTION
Table 6-5. Opcode Quick Reference OPCODE LOWER NIBBLE (HEX) LDCD r1,Irr2 r1,r2 r1,r2 r1,Ir2 r1,Ir2 r1,Irr2 r2,Irr1 LDCI r1,Irr2 R2,R1 CALL IRR1 R2,IR1 IR2,R1 IR1,IM R1,IM CALL R2,R1 R2,R1 IR2,R1 IR2,R1 R1,IM R1,IM PUSH PUSH IRR1 r1,r2 r1,r2 r1,r2 r1,r2 r1,r2 r1,r2 r1,r2 r1,r2 r1,Ir2 r1,Ir2 r1,Ir2 r1,Ir2 r1,Ir2 r1,Ir2 r1,Ir2 r1,Ir2 R2,R1 R2,R1 R2,R1 R2,R1 R2,R1 R2,R1 R2,R1 R2,R1 IR2,R1 IR2,R1 IR2,R1 IR2,R1 IR2,R1 IR2,R1 IR2,R1 IR2,R1 R1,IM R1,IM R1,IM R1,IM R1,IM R1,IM R1,IM R1,IM Irr2, Irr2, Ir1, Irr2, Irr1,
SAM88RCRI INSTRUCTION
S3C9454B/F9454B
Table 6-5. Opcode Quick Reference (Continued) OPCODE LOWER NIBBLE (HEX) r1,R2 r2,R1 cc,RA r1,IM cc,DA
IDLE
STOP IRET
r1,R2
r2,R1
cc,RA
r1,IM
cc,DA
S3C9454B/F9454B
SAM88RCRI INSTRUCTION
CONDITION CODES opcode conditional jump always contains 4-bit field called condition code (cc). This specifies under which conditions execute jump. example, conditional jump with condition code "equal" after compare operation only jumps operands equal. Condition codes listed Table 6-6. carry (C), zero (Z), sign (S), overflow flags used control operation conditional jump instructions. Table 6-6. Condition Codes Binary 0000 1000 0111 1111 0110 1110 1101 0101 0100 1100 0110 1110 1001 0001 1010 0010 1111 0111 1011 0011 Mnemonic Description Always false Always true Carry carry Zero zero Plus Minus Overflow overflow Equal equal Greater than equal Less than Greater than Less than equal Unsigned greater than equal Unsigned less than Unsigned greater than Unsigned less than equal Flags
NOTES: indicates condition codes that related different mnemonics which test same flag. example, both true zero flag set, after instruction, would probably used; after instruction, however, would probably used. operations involving unsigned numbers, special condition codes UGE, ULT, UGT, must used.
SAM88RCRI INSTRUCTION
S3C9454B/F9454B
INSTRUCTION DESCRIPTIONS This section contains detailed information programming examples each instruction SAM87RI instruction set. Information arranged consistent format improved readability fast referencing. following information included each instruction description: Instruction name (mnemonic) Full instruction name Source/destination format instruction operand Shorthand notation instruction's operation Textual description instruction's effect Specific flag settings affected instruction Detailed description instruction's format, execution time, addressing mode(s) Programming example(s) explaining instruction
6-10
S3C9454B/F9454B
SAM88RCRI INSTRUCTION
with Carry
Operation: dst,src source operand, along with setting carry flag, added destination operand stored destination. contents source unaffected. Two's-complement addition performed. multiple precision arithmetic, this instruction permits carry from addition low-order operands carried into addition high-order operands. Flags: there carry from most significant result; cleared otherwise. result "0"; cleared otherwise. result negative; cleared otherwise. arithmetic overflow occurs, that both operands same sign result opposite sign; cleared otherwise.
Format: Bytes Cycles Opcode (Hex) Addr Mode
Examples:
Given: 10H, 03H, flag "1", register 20H, register 03H, register 0AH: R1,R2 R1,@R2 01H,02H 01H,@02H 01H,#11H 14H, 1BH, Register 24H, register Register 2BH, register Register
first example, destination register contains value 10H, carry flag "1", source working register contains value 03H. statement "ADC R1,R2" adds carry flag value ("1") destination value 10H, leaving register
6-11
SAM88RCRI INSTRUCTION
S3C9454B/F9454B
Operation: dst,src source operand added destination operand stored destination. contents source unaffected. Two's-complement addition performed. Flags: there carry from most significant result; cleared otherwise. result "0"; cleared otherwise. result negative; cleared otherwise. arithmetic overflow occurred, that both operands same sign result opposite sign; cleared otherwise.
Format: Bytes Cycles Opcode (Hex) Addr Mode
Examples:
Given: 12H, 03H, register 21H, register 03H, register 0AH: R1,R2 R1,@R2 01H,02H 01H,@02H 01H,#25H 15H, 1CH, Register 24H, register Register 2BH, register Register
first example, destination working register contains source working register contains 03H. statement "ADD R1,R2" adds 12H, leaving value register
6-12
S3C9454B/F9454B
SAM88RCRI INSTRUCTION
Logical
Operation: dst,src source operand logically ANDed with destination operand. result stored destination. operation results being stored whenever corresponding bits operands both logic ones; otherwise value stored. contents source unaffected. Flags: Format: Bytes Cycles Opcode (Hex) Addr Mode Unaffected. result "0"; cleared otherwise. result set; cleared otherwise. Always cleared "0".
Examples:
Given: 12H, 03H, register 21H, register 03H, register 0AH: R1,R2 R1,@R2 01H,02H 01H,@02H 01H,#25H 02H, 02H, Register 01H, register Register 00H, register Register
first example, destination working register contains value source working register contains 03H. statement "AND R1,R2" logically ANDs source operand with destination operand value 12H, leaving value register
6-13
SAM88RCRI INSTRUCTION
S3C9454B/F9454B
CALL Call Procedure
CALL Operation:
current contents program counter pushed onto stack. program counter value used address first instruction following CALL instruction. specified destination address then loaded into program counter points first instruction procedure. procedure return instruction (RET) used return original program flow. pops stack back into program counter. Flags: Format: Bytes Cycles Opcode (Hex) Addr Mode flags affected.
Examples:
Given: 15H, 21H, 1A47H, 0B2H: CALL 1521H 0B0H (Memory locations 1AH, 4AH, where address that follows instruction.) 0B0H (00H 1AH, 49H)
CALL
@RR0
first example, program counter value 1A47H stack pointer contains value 0B2H, statement "CALL 1521H" pushes current value onto stack. stack pointer points memory location 00H. then loaded with value 1521H, address first instruction program sequence executed. contents program counter stack pointer same first example, statement "CALL @RR0" produces same result except that stored stack location (because two-byte instruction format used). then loaded with value 1521H, address first instruction program sequence executed.
6-14
S3C9454B/F9454B
SAM88RCRI INSTRUCTION
Complement Carry Flag
Operation: carry flag complemented. "1", value carry flag changed logic zero; "0", value carry flag changed logic one. Flags: Complemented. other flags affected.
Format: Bytes Cycles Opcode (Hex)
Example:
Given: carry flag "0": carry flag "0", instruction complements FLAGS register (0D5H), changing value from logic zero logic one.
6-15
SAM88RCRI INSTRUCTION
S3C9454B/F9454B
Clear
Operation: destination location cleared "0". Flags: Format: Bytes Cycles Opcode (Hex) Addr Mode flags affected.
Examples:
Given: Register 4FH, register 02H, register 5EH: @01H Register Register 02H, register
Register addressing mode, statement "CLR 00H" clears destination register value 00H. second example, statement "CLR @01H" uses Indirect Register (IR) addressing mode clear register value 00H.
6-16
S3C9454B/F9454B
SAM88RCRI INSTRUCTION
Complement
Operation: contents destination location complemented (one's complement); "1s" changed "0s", vice-versa. Flags: Format: Bytes Cycles Opcode (Hex) Addr Mode Unaffected. result "0"; cleared otherwise. result set; cleared otherwise. Always reset "0".
Examples:
Given: register 0F1H: 0F8H 07H, register
first example, destination working register contains value (00000111B). statement "COM complements bits logic ones changed logic zeros, vice-versa, leaving value 0F8H (11111000B). second example, Indirect Register (IR) addressing mode used complement value destination register (11110001B), leaving value (00001110B).
6-17
SAM88RCRI INSTRUCTION
S3C9454B/F9454B
Compare
Operation: dst,src source operand compared (subtracted from) destination operand, appropriate flags accordingly. contents both operands unaffected comparison. Flags: "borrow" occurred (src dst); cleared otherwise. result "0"; cleared otherwise. result negative; cleared otherwise. arithmetic overflow occurred, that operands were opposite signs sign result same sign source operand; cleared otherwise.
Format: Bytes Cycles Opcode (Hex) Addr Mode
Examples:
Given: 03H: R1,R2 flags
Destination working register contains value source register contains value 03H. statement R1,R2" subtracts value (source/subtrahend) from value (destination/minuend). Because "borrow" occurs difference negative, "1". Given: 0AH: R1,R2 UGE,SKIP R3,R1
SKIP
this example, destination working register contains value which less than contents source working register (0AH). statement R1,R2" generates instruction does jump SKIP location. After statement R3,R1" executes, value remains working register
6-18
S3C9454B/F9454B
SAM88RCRI INSTRUCTION
Decrement
Operation: contents destination operand decremented one. Flags: Unaffected. result "0"; cleared otherwise. result negative; cleared otherwise. arithmetic overflow occurred, that value (80H) result value (7FH); cleared otherwise.
Format: Bytes Cycles Opcode (Hex) Addr Mode
Examples:
Given: register 10H: Register
first example, working register contains value 03H, statement "DEC decrements hexadecimal value one, leaving value 02H. second example, statement "DEC @R1" decrements value contained destination register one, leaving value 0FH.
6-19
SAM88RCRI INSTRUCTION
S3C9454B/F9454B
Disable Interrupts
Operation: zero system mode register, SYM.2, cleared "0", globally disabling interrupt processing. Interrupt requests will continue their respective interrupt pending bits, will service them while interrupt processing disabled. Flags: Format: Bytes Cycles Opcode (Hex) flags affected.
Example:
Given: 04H: value register 04H, statement "DI" leaves value register clears SYM.2 "0", disabling interrupt processing.
6-20
S3C9454B/F9454B
SAM88RCRI INSTRUCTION
Enable Interrupts
Operation: instruction sets system mode register, SYM.2 "1". This allows interrupts serviced they occur. interrupt's pending while interrupt processing disabled executing instruction), will serviced when execute instruction. Flags: Format: Bytes Cycles Opcode (Hex) flags affected.
Example:
Given: 00H: register contains value 00H, that interrupts currently disabled, statement "EI" sets register 04H, enabling interrupts. (SYM.2 enable global interrupt processing.)
6-21
SAM88RCRI INSTRUCTION
S3C9454B/F9454B
IDLE Idle Operation
IDLE Operation: IDLE instruction stops clock while allowing system clock oscillation continue. Idle mode released interrupt request (IRQ) external reset operation. Flags: Format: Bytes Cycles Opcode (Hex) Addr Mode flags affected.
Example:
instruction IDLE stops clock system clock.
6-22
S3C9454B/F9454B
SAM88RCRI INSTRUCTION
Increment
Operation: contents destination operand incremented one. Flags: Unaffected. result "0"; cleared otherwise. result negative; cleared otherwise. arithmetic overflow occurred, that value (7FH) result (80H); cleared otherwise.
Format: Bytes Cycles Opcode (Hex) Addr Mode
Examples:
Given: 1BH, register 0CH, register 0FH: Register 1BH, register
first example, destination working register contains value 1BH, statement "INC leaves value that same register. next example shows effect instruction register 00H, assuming that contains value 0CH. third example, used Indirect Register (IR) addressing mode increment value register from 10H.
6-23
SAM88RCRI INSTRUCTION
S3C9454B/F9454B
IRET Interrupt Return
IRET Operation: IRET FLAGS SYM(2) This instruction used interrupt service routine. restores flag register program counter. also re-enables global interrupts. Flags: Format: IRET (Normal) Bytes Cycles Opcode (Hex) flags restored their original settings (that settings before interrupt occurred).
6-24
S3C9454B/F9454B
SAM88RCRI INSTRUCTION
Jump
Operation: cc,dst (Conditional) (Unconditional)
true, conditional JUMP instruction transfers program control destination address condition specified condition code (cc) true; otherwise, instruction following instruction executed. unconditional simply replaces contents with contents specified register pair. Control then passes statement addressed
Flags: Format:
flags affected.
Bytes
Cycles
Opcode (Hex)
Addr Mode
NOTES: 3-byte format used conditional jump 2-byte format unconditional jump. first byte three-byte instruction format (conditional jump), condition code code both four bits.
Examples:
Given: carry flag "1", register 01H, register 20H: C,LABEL_W @00H LABEL_W 1000H, 1000H 0120H
first example shows conditional Assuming that carry flag "1", statement C,LABEL_W" replaces contents with value 1000H transfers control that location. carry flag been set, control would then have passed statement immediately following instruction. second example shows unconditional statement @00" replaces contents with contents register pair 01H, leaving value 0120H.
6-25
SAM88RCRI INSTRUCTION
S3C9454B/F9454B
Jump Relative
Operation: cc,dst true, condition specified condition code (cc) true, relative address added program counter control passes statement whose address program counter; otherwise, instruction following instruction executed (See list condition codes). range relative address 127, 128, original value program counter taken address first instruction byte following statement. Flags: Format: Bytes
(note)
flags affected.
Cycles
Opcode (Hex)
Addr Mode
NOTE: first byte two-byte instruction format, condition code code each four bits.
Example:
Given: carry flag LABEL_X 1FF7H: C,LABEL_X 1FF7H
carry flag (that condition code true), statement C,LABEL_X" will pass control statement whose address Otherwise, program instruction following would executed.
6-26
S3C9454B/F9454B
SAM88RCRI INSTRUCTION
Load
Operation: dst,src contents source loaded into destination. source's contents unaffected. Flags: Format: Bytes Cycles Opcode (Hex) Addr Mode flags affected.
6-27
SAM88RCRI INSTRUCTION
S3C9454B/F9454B
Load
Examples: (Continued) Given: 01H, 0AH, register 01H, register 20H, register 02H, LOOP 30H, register 0FFH: R0,#10H R0,01H 01H,R0 R1,@R0 @R0,R1 00H,01H 02H,@00H 00H,#0AH @00H,#10H @00H,02H R0,#LOOP[R1] #LOOP[R0],R1 20H, register Register 01H, 20H, 01H, 0AH, register Register 20H, register Register 20H, register Register Register 01H, register Register 01H, register register 0FFH, Register 0AH, 01H,
6-28
S3C9454B/F9454B
SAM88RCRI INSTRUCTION
LDC/LDE Load Memory
LDC/LDE Operation: dst,src This instruction loads byte from program data memory into working register vice-versa. source values unaffected. refers program memory data memory. assembler makes "Irr" "rr" values even number program memory number data memory. Flags: Format: Bytes
flags affected.
Cycles
Opcode (Hex)
Addr Mode
[rr]
[rr]
[rr]
[rr]
0000
0000
0001
0001
NOTES: source (src) working register pair [rr] formats cannot register pair 0-1. formats destination address [rr]" source address [rr]" each byte. formats destination address [rr]" source address [rr]" each bytes. source values formats used address program memory; second values, used formats used address data memory.
6-29
SAM88RCRI INSTRUCTION
S3C9454B/F9454B
LDC/LDE Load Memory
LDC/LDE Examples: (Continued) Given: 11H, 34H, 01H, 04H, 00H, 60H; Program memory locations 0061 AAH, 0103H 4FH, 0104H 0105H 6DH, 1104H 88H. External data memory locations 0061H BBH, 0103H 5FH, 0104H 2AH, 0105H 7DH, 1104H 98H: R0,@RR2 R0,@RR2 contents program memory location 0104H 1AH, 01H, contents external data memory location 0104H 2AH, 01H, (contents loaded into program memory location 0104H (RR2), working registers change (contents loaded into external data memory location 0104H (RR2), working registers change contents program memory location 0061H (01H RR4), AAH, 00H, contents external data memory location 0061H (01H RR4), BBH, 00H, (contents loaded into program memory location 0061H (01H 0060H) (contents loaded into external data memory location 0061H (01H 0060H)
(note) @RR2,R0
@RR2,R0
R0,#01H[RR4]
R0,#01H[RR4]
(note) #01H[RR4],R0 #01H[RR4],R0
R0,#1000H[RR2] contents program memory location 1104H (1000H 0104H), 88H, 01H, R0,#1000H[RR2] contents external data memory location 1104H (1000H 0104H), 98H, 01H, R0,1104H R0,1104H contents program memory location 1104H, contents external data memory location 1104H, (contents loaded into program memory location 1105H, (1105H) (contents loaded into external data memory location 1105H, (1105H)
(note) 1105H,R0 1105H,R0
NOTE: These instructions supported masked type devices.
6-30
S3C9454B/F9454B
SAM88RCRI INSTRUCTION
LDCD/LDED Load Memory Decrement
LDCD/LDED Operation: dst,src These instructions used user stacks block transfers data from program data memory register file. address memory location specified working register pair. contents source location loaded into destination location. memory address then decremented. contents source unaffected. LDCD references program memory LDED references external data memory. assembler makes "Irr" even number program memory number data memory. Flags: Format: Bytes Cycles Opcode (Hex) Addr Mode flags affected.
Examples:
Given: 10H, 33H, 12H, program memory location 1033H 0CDH, external data memory location 1033H 0DDH: LDCD R8,@RR6 0CDH (contents program memory location 1033H) loaded into decremented 0CDH, 10H, (RR6 0DDH (contents data memory location 1033H) loaded into decremented (RR6 0DDH, 10H,
LDED
R8,@RR6
6-31
SAM88RCRI INSTRUCTION
S3C9454B/F9454B
LDCI/LDEI Load Memory Increment
LDCI/LDEI Operation: dst,src These instructions used user stacks block transfers data from program data memory register file. address memory location specified working register pair. contents source location loaded into destination location. memory address then incremented automatically. contents source unaffected. LDCI refers program memory LDEI refers external data memory. assembler makes "Irr" even program memory data memory. Flags: Format: Bytes Cycles Opcode (Hex) Addr Mode flags affected.
Examples:
Given: 10H, 33H, 12H, program memory locations 1033H 0CDH 1034H 0C5H; external data memory locations 1033H 0DDH 1034H 0D5H: LDCI R8,@RR6 0CDH (contents program memory location 1033H) loaded into incremented (RR6 0CDH, 10H, 0DDH (contents data memory location 1033H) loaded into incremented (RR6 0DDH, 10H,
LDEI
R8,@RR6
6-32
S3C9454B/F9454B
SAM88RCRI INSTRUCTION
Operation
Operation: action performed when executes this instruction. Typically, more NOPs executed sequence order effect timing delay variable duration. flags affected.
Flags: Format:
Bytes
Cycles
Opcode (Hex)
Example:
When instruction encountered program, operation occurs. Instead, there delay instruction execution time.
6-33
SAM88RCRI INSTRUCTION
S3C9454B/F9454B
Logical
Operation: dst,src source operand logically ORed with destination operand result stored destination. contents source unaffected. operation results being stored whenever either corresponding bits operands "1"; otherwise stored. Flags: Format: Bytes Cycles Opcode (Hex) Addr Mode Unaffected. result "0"; cleared otherwise. result set; cleared otherwise. Always cleared "0".
Examples:
Given: 15H, 2AH, 01H, register 08H, register 37H, register 8AH: R0,R1 R0,@R2 00H,01H 01H,@00H 00H,#02H 3FH, 37H, 01H, register Register 3FH, register Register 08H, register 0BFH Register
first example, working register contains value register value 2AH, statement R0,R1" logical-ORs register contents stores result (3FH) destination register other examples show logical instruction with various addressing modes formats.
6-34
S3C9454B/F9454B
SAM88RCRI INSTRUCTION
From Stack
Operation: contents location addressed stack pointer loaded into destination. stack pointer then incremented one. Flags: Format: Bytes Cycles Opcode (Hex) Addr Mode flags affected.
Examples:
Given: Register 01H, register 1BH, (0D9H) 0BBH, stack register 0BBH 55H: @00H Register 55H, 0BCH Register 01H, register 55H, 0BCH
first example, general register contains value 01H. statement "POP 00H" loads contents location 0BBH (55H) into destination register then increments stack pointer one. Register then contains value points location 0BCH.
6-35
SAM88RCRI INSTRUCTION
S3C9454B/F9454B
PUSH Push Stack
PUSH Operation: PUSH instruction decrements stack pointer value loads contents source (src) into location addressed decremented stack pointer. operation then adds value stack. Flags: Format: Bytes Cycles Opcode (Hex) Addr Mode flags affected.
Examples:
Given: Register 4FH, register 0AAH, 0C0H: PUSH PUSH @40H Register 4FH, stack register 0BFH 4FH, 0BFH Register 4FH, register 0AAH, stack register 0BFH 0AAH, 0BFH
first example, stack pointer contains value 0C0H, general register value 4FH, statement "PUSH 40H" decrements stack pointer from 0BFH. then loads contents register into location 0BFH. Register 0BFH then contains value points location 0BFH.
6-36
S3C9454B/F9454B
SAM88RCRI INSTRUCTION
Reset Carry Flag
Operation: carry flag cleared logic zero, regardless previous value. Flags: Cleared "0". other flags affected. Format: Bytes Cycles Opcode (Hex)
Example:
Given: "0": instruction clears carry flag logic zero.
6-37
SAM88RCRI INSTRUCTION
S3C9454B/F9454B
Return
Operation: instruction normally used return previously executing procedure procedure entered CALL instruction. contents location addressed stack pointer popped into program counter. next statement that executed that addressed program counter value. Flags: Format: Bytes Cycles Opcode (Hex) flags affected.
Example:
Given: 0BCH, (SP) 101AH, 1234: 101AH, 0BEH
statement "RET" pops contents stack pointer location 0BCH (10H) into high byte program counter. stack pointer then pops value location 0BDH (1AH) into PC's byte instruction location 101AH executed. stack pointer points memory location 0BEH.
6-38
S3C9454B/F9454B
SAM88RCRI INSTRUCTION
Rotate Left
Operation: (n), contents destination operand rotated left position. initial value moved zero (LSB) position also replaces carry flag.
Flags:
rotated from most significant position (bit "1". result "0"; cleared otherwise. result set; cleared otherwise. arithmetic overflow occurred, that sign destination changed during rotation; cleared otherwise.
Format: Bytes Cycles Opcode (Hex) Addr Mode
Examples:
Given: Register 0AAH, register register 17H: @01H Register 55H, Register 02H, register 2EH,
first example, general register contains value 0AAH (10101010B), statement 00H" rotates 0AAH value left position, leaving value (01010101B) setting carry overflow flags.
6-39
SAM88RCRI INSTRUCTION
S3C9454B/F9454B
Rotate Left Through Carry
Operation: (n), contents destination operand with carry flag rotated left position. initial value replaces carry flag (C); initial value carry flag replaces zero.
Flags:
rotated from most significant position (bit "1". result "0"; cleared otherwise. result set; cleared otherwise. arithmetic overflow occurred, that sign destination changed during rotation; cleared otherwise.
Format: Bytes Cycles Opcode (Hex) Addr Mode
Examples:
Given: Register 0AAH, register 02H, register 17H, "0": @01H Register 54H, Register 02H, register 2EH,
first example, general register value 0AAH (10101010B), statement "RLC 00H" rotates 0AAH position left. initial value sets carry flag initial value flag replaces zero register 00H, leaving value (01010101B). register resets carry flag sets overflow flag.
6-40
S3C9454B/F9454B
SAM88RCRI INSTRUCTION
Rotate Right
Operation: contents destination operand rotated right position. initial value zero (LSB) moved (MSB) also replaces carry flag (C).
Flags:
rotated from least significant position (bit zero) "1". result "0"; cleared otherwise. result set; cleared otherwise. arithmetic overflow occurred, that sign destination changed during rotation; cleared otherwise.
Format: Bytes Cycles Opcode (Hex) Addr Mode
Examples:
Given: Register 31H, register 02H, register 17H: @01H Register 98H, Register 02H, register 8BH,
first example, general register contains value (00110001B), statement 00H" rotates this value position right. initial value zero moved leaving value (10011000B) destination register. initial zero also resets flag sign flag overflow flag also "1".
6-41
SAM88RCRI INSTRUCTION
S3C9454B/F9454B
Rotate Right Through Carry
Operation: contents destination operand carry flag rotated right position. initial value zero (LSB) replaces carry flag; initial value carry flag replaces (MSB).
Flags:
rotated from least significant position (bit zero) "1". result cleared otherwise. result set; cleared otherwise. arithmetic overflow occurred, that sign destination changed during rotation; cleared otherwise.
Format: Bytes Cycles Opcode (Hex) Addr Mode
Examples:
Given: Register 55H, register 02H, register 17H, "0": @01H Register 2AH, Register 02H, register 0BH,
first example, general register contains value (01010101B), statement "RRC 00H" rotates this value position right. initial value zero ("1") replaces carry flag initial value flag ("1") replaces This leaves value (00101010B) destination register 00H. sign flag overflow flag both cleared "0".
6-42
S3C9454B/F9454B
SAM88RCRI INSTRUCTION
Subtract With Carry
Operation: dst,src source operand, along with current value carry flag, subtracted from destination operand result stored destination. contents source unaffected. Subtraction performed adding two's-complement source operand destination operand. multiple precision arithmetic, this instruction permits carry ("borrow") from subtraction low-order operands subtracted from subtraction high-order operands. Flags: borrow occurred (src dst); cleared otherwise. result "0"; cleared otherwise. result negative; cleared otherwise. arithmetic overflow occurred, that operands were opposite sign sign result same sign source; cleared otherwise.
Format: Bytes Cycles Opcode (Hex) Addr Mode
Examples:
Given: 10H, 03H, "1", register 20H, register 03H, register 0AH: R1,R2 R1,@R2 01H,02H 01H,@02H 01H,#8AH 0CH, 05H, 03H, register Register 1CH, register Register 15H,register 03H, register Register 95H;
first example, working register contains value register value 03H, statement "SBC R1,R2" subtracts source value (03H) flag value ("1") from destination (10H) then stores result (0CH) register
6-43
SAM88RCRI INSTRUCTION
S3C9454B/F9454B
Carry Flag
Operation: carry flag logic one, regardless previous value. Flags: "1". other flags affected. Format: Bytes Cycles Opcode (Hex)
Example:
statement sets carry flag logic one.
6-44
S3C9454B/F9454B
SAM88RCRI INSTRUCTION
Shift Right Arithmetic
Operation: arithmetic shift-right position performed destination operand. zero (the LSB) replaces carry flag. value (the sign bit) unchanged shifted into position
Flags:
shifted from position (bit zero) "1". result "0"; cleared otherwise. result negative; cleared otherwise. Always cleared "0".
Format: Bytes Cycles Opcode (Hex) Addr Mode
Examples:
Given: Register 9AH, register 03H, register 0BCH, "1": @02H Register 0CD, Register 03H, register 0DEH,
first example, general register contains value (10011010B), statement "SRA 00H" shifts values register right position. zero ("0") clears flag ("1") then shifted into position (bit remains unchanged). This leaves value 0CDH (11001101B) destination register 00H.
6-45
SAM88RCRI INSTRUCTION
S3C9454B/F9454B
STOP Stop Operation
STOP Operation: STOP instruction stops both clock system clock causes microcontroller enter Stop mode. During Stop mode, contents on-chip registers, peripheral registers, port control data registers retained. Stop mode released external reset operation External interrupt input. reset operation, RESET must held level until required oscillation stabilization interval elapsed. flags affected.
Flags: Format:
Bytes
Cycles
Opcode (Hex)
Addr Mode
Example:
statement STOP halts microcontroller operations. When STOPCON register #0A5H value, STOP instruction, changed reset address. STOPCON, #0A5H
6-46
S3C9454B/F9454B
SAM88RCRI INSTRUCTION
Subtract
Operation: dst,src source operand subtracted from destination operand result stored destination. contents source unaffected. Subtraction performed adding two's complement source operand destination operand. Flags: "borrow" occurred; cleared otherwise. result "0"; cleared otherwise. result negative; cleared otherwise. arithmetic overflow occurred, that operands were opposite signs sign result same sign source operand; cleared otherwise.
Format: Bytes Cycles Opcode (Hex) Addr Mode
Examples:
Given: 12H, 03H, register 21H, register 03H, register 0AH: R1,R2 R1,@R2 01H,02H 01H,@02H 01H,#90H 01H,#65H 0FH, 08H, Register 1EH, register Register 17H, register Register 91H; Register 0BCH; "1",
first example, working register contains value register contains value 03H, statement "SUB R1,R2" subtracts source value (03H) from destination value (12H) stores result (0FH) destination register
6-47
SAM88RCRI INSTRUCTION
S3C9454B/F9454B
Test Complement Under Mask
Operation: dst,src (NOT dst) This instruction tests selected bits destination operand logic value. bits tested specified setting corresponding position source operand (mask). statement complements destination operand, which then ANDed with source mask. zero flag then checked determine result. destination source operands unaffected. Flags: Format: Bytes Cycles Opcode (Hex) Addr Mode Unaffected. result "0"; cleared otherwise. result set; cleared otherwise. Always cleared "0".
Examples:
Given: 0C7H, 02H, 12H, register 2BH, register 02H, register 23H: R0,R1 R0,@R1 00H,01H 00H,@01H 00H,#34 0C7H, 02H, 0C7H, 02H, register 23H, Register 2BH, register 02H, Register 2BH, register 02H, register 23H, Register 2BH,
first example, working register contains value 0C7H (11000111B) register value (00000010B), statement "TCM R0,R1" tests destination register value. Because mask value corresponds test bit, flag logic tested determine result operation.
6-48
S3C9454B/F9454B
SAM88RCRI INSTRUCTION
Test Under Mask
Operation: dst,src This instruction tests selected bits destination operand logic zero value. bits tested specified setting corresponding position source operand (mask), which ANDed with destination operand. zero flag then checked determine result. destination source operands unaffected. Flags: Format: Bytes Cycles Opcode (Hex) Addr Mode Unaffected. result "0"; cleared otherwise. result set; cleared otherwise. Always reset "0".
Examples:
Given: 0C7H, 02H, 18H, register 2BH, register 02H, register 23H: R0,R1 R0,@R1 00H,01H 00H,@01H 00H,#54H 0C7H, 02H, 0C7H, 02H, register 23H, Register 2BH, register 02H, Register 2BH, register 02H, register 23H, Register 2BH,
first example, working register contains value 0C7H (11000111B) register value (00000010B), statement "R0,R1" tests destination register value. Because mask value does match test bit, flag cleared logic zero tested determine result operation.
6-49
SAM88RCRI INSTRUCTION
S3C9454B/F9454B
Logical Exclusive
Operation: dst,src source operand logically exclusive-ORed with destination operand result stored destination. exclusive-OR operation results being stored whenever corresponding bits operands different; otherwise, stored. Flags: Format: Bytes Cycles Opcode (Hex) Addr Mode Unaffected. result "0"; cleared otherwise. result set; cleared otherwise. Always reset "0".
Examples:
Given: 0C7H, 02H, 18H, register 2BH, register 02H, register 23H: R0,R1 R0,@R1 00H,01H 00H,@01H 00H,#54H 0C5H, 0E4H, 02H, register Register 29H, register Register 08H, register 02H, register Register
first example, working register contains value 0C7H register contains value 02H, statement "XOR R0,R1" logically exclusive-ORs value with value stores result (0C5H) destination register
6-50
S3C9454B/F9454B
CLOCK CIRCUIT
OVERVIEW
CLOCK CIRCUIT
smart option (3FH.1-.0 ROM), user select internal oscillator external oscillator. using internal oscillator, (P1.0), XOUT (P1.1) used normal pins. internal oscillator source provides typical depending smart option. external oscillation source provides typical clock S3C9454B/F9454B. internal capacitor supports oscillator circuit. external crystal ceramic oscillation source provides maximum clock. XOUT pins connect oscillation source on-chip clock circuit. Simplified external oscillator crystal/ceramic oscillator circuits shown Figures 7-2. When external oscillator, P1.0, P1.1 must output port prevent current consumption
S3C9454B/F9454B
S3C9454B/P9454B
XOUT
XOUT
Figure 7-1. Main Oscillator Circuit Oscillator with Internal Capacitor) MAIN OSCILLATOR LOGIC
Figure 7-2. Main Oscillator Circuit (Crystal/Ceramic Oscillator)
increase processing speed reduce clock noise, non-divided logic implemented main oscillator circuit. this reason, very high resolution waveforms (square signal edges) must generated order efficiently process logic operations.
CLOCK CIRCUIT
S3C9454B/F9454B
CLOCK STATUS DURING POWER-DOWN MODES power-down modes, Stop mode Idle mode, affect clock oscillation follows: Stop mode, main oscillator "freezes", halting peripherals. contents register file current system register values retained. Stop mode released, oscillator started, reset operation external interrupt with RC-delay noise filter (for S3C9454B/F9454B, INT0-INT1). Idle mode, internal clock signal gated CPU, interrupt control timer. current status preserved, including stack pointer, program counter, flags. Data register file retained. Idle mode released reset interrupt (external internally-generated). SYSTEM CLOCK CONTROL REGISTER (CLKCON) system clock control register, CLKCON, located location D4H. read/write addressable following functions: Oscillator wake-up function enable/disable (CLKCON.7) Oscillator frequency divide-by value: non-divided, (CLKCON.4 CLKCON.3) CLKCON register controls whether external interrupt used trigger Stop mode release (This called "IRQ wake-up" function). wake-up enable CLKCON.7. After reset, external interrupt oscillator wake-up function enabled, main oscillator activated, fOSC/16 (the slowest clock speed) selected clock. necessary, then increase clock speed fOSC, fOSC/2 fOSC/8.
System Clock Control Register (CLKCON) D4H,
Oscillator wake-up enable bit: Enable main system oscillator wake-up function power mode. Disable main system oscillator wake-up function power down mode.
used S3C9454B/F9454B Divide-by selection bits clock frequency: fosc/16 fosc/8 fosc/2 fosc (non-divided)
used S3C9454B/F9454B
Figure 7-3. System Clock Control Register (CLKCON)
S3C9454B/F9454B
CLOCK CIRCUIT
Smart Option (3F.1-0 ROM)
Stop Instruction CLKCON.4-.3
Internal Oscillator (3.2 MHz) Internal Oscillator (0.5 MHz) External Crystal/ Ceramic Oscillator External Oscillator Oscillator Stop Selected Oscillator Wake-up Noise Filter P2.6/CLO CLKCON.7 P2CONH.6-.4 1/16
Clock
NOTE: external interrupt (with RC-delay noise filter) used release stop mode "wake-up" main oscillator. S3C9454B/F9454B, INT0-INT1 external interrupts this type.
Figure 7-4. System Clock Circuit Diagram
CLOCK CIRCUIT
S3C9454B/F9454B
NOTES
S39454B/F9454B
RESET POWER-DOWN
OVERVIEW
RESET POWER-DOWN
SYSTEM RESET
smart option (3EH.7 ROM), user select internal RESET (LVR) external RESET. using internal RESET (LVR), nRESET (P1.2) used normal pin. S3C9454B/F9454B RESET four ways: external power-on-reset external nRESET input pulled digital watchdog peripheral timing Voltage Reset (LVR) During external power-on reset, voltage High level nRESET forced level. nRESET signal input through Schmitt trigger circuit where then synchronized with clock. This brings S3C9454B/F9454B into known operating status. ensure correct start-up, user should take care that nRESET signal released before level sufficient allow operation chosen frequency. nRESET must held level minimum time interval after power supply comes within tolerance order allow time internal clock oscillation stabilize. minimum required oscillation stabilization time reset approximately 6.55 216/fOSC, fOSC MHz). When reset occurs during normal operation (with both nRESET High level), signal nRESET forced Reset operation starts. system peripheral control registers then their default hardware Reset values (see Table 8-1). provides watchdog timer function order ensure graceful recovery from software malfunction. watchdog timer refreshed before end-of-counter condition (overflow) reached, internal reset will activated. on-chip Voltage Reset, features static Reset when supply voltage below reference value (Typ. 2.3, 3.0, Thanks this feature, external reset circuit removed while keeping application safety. long supply voltage below reference value, there internal static RESET. start only when supply voltage rises over reference value.
RESET POWER-DOWN
S39454B/F9454B
NOTE program duration oscillation stabilization interval, must make appropriate settings basic timer control register, BTCON, before entering Stop mode. Also, want basic timer watchdog function (which causes system reset basic timer counter overflow occurs), disable writing "1010B" upper nibble BTCON. Initialization Sequence following sequence events occurs during Reset operation: interrupts disabled. watchdog function (basic timer) enabled. Ports input mode Peripheral control data registers disabled reset their initial values (see Table 8-1). program counter loaded with reset address, 0100H. When programmed oscillation stabilization time interval elapsed, address stored location 0100H (and 0101H) fetched executed.
Smart Option (3EH.7)
nRESET nRESET Internal nRESET
Watchdog nRESET
Figure 8-1. Reset Block Diagram
Oscillation Stabilization Wait Time (6.55 ms/at MHz) nRESET Input
Normal Mode Power-Down Mode RESET Operation
Idle Mode
Operation Mode
Figure 8-2. Timing S3C9454B/F9454B After RESET
S39454B/F9454B
RESET POWER-DOWN
POWER-DOWN MODES
STOP MODE Stop mode invoked instruction STOP (opcode 7FH). Stop mode, operation peripherals halted. That on-chip main oscillator stops supply current reduced less than except that LVR(Low Voltage Reset) enable. system functions halted when clock "freezes", data stored internal register file retained. Stop mode released ways: nRESET signal external interrupt. Using RESET Release Stop Mode Stop mode released when nRESET signal released returns High level. system peripheral control registers then Reset their default values contents data registers retained. Reset operation automatically selects slow clock (fOSC/16) because CLKCON.3 CLKCON.4 cleared "00B". After oscillation stabilization interval elapsed, executes system initialization routine fetching 16-bit address stored locations 0100H 0101H. Using External Interrupt Release Stop Mode External interrupts with RC-delay noise filter circuit used release Stop mode (Clock-related external interrupts cannot used). External interrupts INT0-INT1 S3C9454B/F9454B interrupt structure meet this criteria. Note that when Stop mode released external interrupt, current values system peripheral control registers changed. When interrupt release Stop mode, CLKCON.3 CLKCON.4 register values remain unchanged, currently selected clock value used. external interrupt Stop mode release, also program duration oscillation stabilization interval. this, must appropriate value BTCON register before entering Stop mode. external interrupt serviced when Stop mode release occurs. Following IRET from service routine, instruction immediately following that initiated Stop mode executed. IDLE MODE Idle mode invoked instruction IDLE (opcode 6FH). Idle mode, operations halted while select peripherals remain active. During Idle mode, internal clock signal gated CPU, interrupt logic timer/counters. Port pins retain mode (input output) they time Idle mode entered. There ways release Idle mode: Execute Reset. system peripheral control registers Reset their default values contents data registers retained. Reset automatically selects slow clock (fOSC/16) because CLKCON.3 CLKCON.4 cleared "00B". interrupts masked, Reset only release Idle mode. Activate enabled interrupt, causing Idle mode released. When interrupt release Idle mode, CLKCON.3 CLKCON.4 register values remain unchanged, currently selected clock value used. interrupt then serviced. Following IRET from service routine, instruction immediately following that initiated Idle mode executed. NOTES Only external interrupts that clock-related used release stop mode. release Idle mode, however, type interrupt (that internal external) used. Before enter STOP IDLE mode, must disabled. Otherwise, STOP IDLE current will increased significantly.
RESET POWER-DOWN
S39454B/F9454B
HARDWARE RESET VALUES
Table lists values system registers, peripheral control registers, peripheral data registers following Reset operation normal operating mode. shows Reset value logic logic zero, respectively. means that value undefined following reset. dash ("-") means that either used mapped.
Table 8-1. Register Values After Reset Register Name Timer counter register Timer data register Timer control register Clock control register System flags register Stack pointer register special register Basic timer control register Basic timer counter Test mode control register System mode register
NOTE: mapped used, undefined
Mnemonic T0CNT T0DATA T0CON CLKCON FLAGS MDSREG BTCON BTCNT FTSTCON
Address Location Address
RESET Value (Bit)
Location mapped
Locations D6H-D8H mapped Location mapped
S39454B/F9454B
RESET POWER-DOWN
Table 8-1. Register Values After Reset (Continued) Register Name Mnemonic Address Port data register Port data register Port data register Port control register (High byte) Port control register Port interrupt pending register Port control register Port control register (High byte) Port control register (Low byte) data register control register STOP control register control register converter data register (High) converter data register (Low) P0CONH P0CON P0PND P1CON P2CONH P2CONL PWMDATA PWMCON STOPCON ADCON ADDATAH ADDATAL Values After RESET
Locations E3H-E5H mapped
Locations ECH-F1H mapped
Locations F5H-F6H mapped
Locations FAH-FFH mapped
NOTE: mapped used, undefined
RESET POWER-DOWN
S39454B/F9454B
PROGRAMMING Sample S3C9454B/F9454B Initialization Routine
;-<< Interrupt Vector Address VECTOR 0000H 00H,INT_9454 S3C9454B/F9454B only interrupt vector
;-<< Smart Option 003CH 0E7H 003CH, must initialized 003DH, must initialized 003EH, enable (2.3 003FH, internal (3.2
;-<< Initialize System Peripherals RESET: 0100H BTCON,#10100011B CLKCON,#00011000B SP,#0C0H disable interrupt Watch-dog disable Select non-divided clock Stack pointer must
P0CONH,#10101010B P0CONL,#10101010B P1CON,#00001010B P2CONH,#01001010B P2CONL,#10101010B
P0.0-P0.7 push-pull output P1.0-P1.1 push-pull output P2.0-P2.6 push-pull output
;-<< Timer settings T0DATA,#50H T0CON,#01001010B MHz, interrupt interval msec fOSC/256, Timer interrupt enable
;-<< Clear data registers from RAM_CLR: R0,#0 R0,#0BFH ULE,RAM_CLR clear
;-<< Initialize other registers
Enable interrupt
S39454B/F9454B
RESET POWER-DOWN
PROGRAMMING Sample S3C9454B/F9454B Initialization Routine (Continued)
;-<< Main loop MAIN:
BTCON,#02H
Start main loop Enable watchdog function Basic counter (BTCNT) clear
CALL
KEY_SCAN
CALL
LED_DISPLAY
CALL
T,MAIN
;-<< Subroutines KEY_SCAN:
LED_DISPLAY:
JOB:
RESET POWER-DOWN
S39454B/F9454B
PROGRAMMING Sample S3C9454B/F9454B Initialization Routine (Continued)
;-<< Interrupt Service Routines INT_9454: T0CON,#00000010B Z,NEXT_CHK1 T0CON,#00000001B NZ,INT_TIMER0 Interrupt enable pending check Timer0 interrupt enable check timer0 interrupt occurred, T0CON.0 would set.
NEXT_CHK1: NEXT_CHK2: NEXT_CHK3: IRET END_INT IRET P0PND,#00001000B Z,END_INT P0PND,#00000100B NZ,INT1_INT INT1 interrupt enable check Interrupt return P0PND,#00000010B Z,NEXT_CHK3 P0PND,#00000001B NZ,INT0_INT INT0 interrupt enable check PWMCOM,#00000010B Z,NEXT_CHK2 P0PND,#00000001B NZ,PWMOVF_INT overflow interrupt enable check
Timer0 interrupt service routine INT_TIMER0:
T0CON,#11110110B Pending clear Interrupt return
IRET
overflow interrupt service routine PWMOVF_INT:
IRET
PWMCON,#11110110B
Pending clear Interrupt return
S39454B/F9454B
RESET POWER-DOWN
PROGRAMMING Sample S3C9454B/F9454B Initialization Routine (Continued)
External interrupt0 service routine INT0_INT:
IRET
P0PND,#11111110B
INT0 Pending clear Interrupt return
External interrupt1 service routine INT1_INT:
IRET
P0PND,#11111011B
INT1 Pending clear Interrupt return
RESET POWER-DOWN
S39454B/F9454B
NOTES
8-10
S3C9454B/F9454B
PORTS
OVERVIEW
Port
PORTS
S3C9454B/F9454B three ports: with pins total. access these ports directly writing reading port data register addresses. ports configured drive. (High current output: typical Table 9-1. S3C9454B/F9454B Port Configuration Overview Function Description Bit-programmable port schmitt trigger input push-pull output. Pull-up resistors assignable software. Port pins also used alternative function. (ADC input, external interrupt input). Bit-programmable port schmitt trigger input push-pull, open-drain output. Pull-up pull-down resistors assignable software. Port pins also oscillator input/output reset input smart option. P1.2 input only. Bit-programmable port schmitt trigger input push-pull, open-drain output. Pull-up resistor assignable software. Port also used alternative function (ADC input, CLO, clock output) Programmability
PORTS
S3C9454B/F9454B
PORT DATA REGISTERS Table gives overview port data register names, locations, addressing characteristics. Data registers ports have structure shown Figure 9-1. Table 9-2. Port Data Register Summary Register Name Port data register Port data register Port data register Mnemonic
NOTE: reset operation clears P0-P2 data register "00H".
Port Data Register 0-2) Pn.1 Pn.0
Pn.7
Pn.6
Pn.5
Pn.4
Pn.3
Pn.2
Figure 9-1. Port Data Register Format
S3C9454B/F9454B
PORTS
PORT Port bit-programmable, general-purpose, ports. select normal input push-pull output mode. addition, configure pull-up resistor individual pins using control register settings. designed high-current functions such direct drive. Part pins also used alternative functions (ADC input, external interrupt input output). control resisters used control Port P0CONH (E6H) P0CONL (E7H). access port directly writing reading corresponding port data register, (E0H).
Pull-up Enable P0CONH
Pull-up register typical)
Data Output DIsable (input mode) Input Data
In/Out
Circuit type
External Interrupt Input
Noise Filter
NOTE: pins have protection diodes through VSS.
Mode Output Input
Input Data
Figure 9-2. Port Circuit Diagram
PORTS
S3C9454B/F9454B
Port Control Register (High Byte) E6H,
[.7-.6] Port, P0.7/ADC7 Configuration Bits Schmitt trigger input; pull-up enable Schmitt trigger input Push-pull output converter input (ADC7); schmitt trigger input [.5-.4] Port P0.6/ADC6/PWM Configuration Bits Schmitt trigger input; pull-up enable Alternative function (PWM output) Push-pull output converter input (ADC6); schmitt trigger input [.3-.2] Port P0.5/ADC5 Configuration Bits Schmitt trigger input; pull-up enable Schmitt trigger input Push-pull output converter input (ADC5); schmitt trigger input [.1-.0] Port P0.4/ADC4 Configuration Bits Schmitt trigger input; pull-up enable Schmitt trigger input Push-pull output converter input (ADC4); schmitt trigger input
Figure 9-3. Port Control Register (P0CONH, High Byte)
S3C9454B/F9454B
PORTS
Port Control Register (Low Byte) E7H,
[.7-.6] Port P0.3/ADC3 Configuration Bits Schmitt trigger input Schmitt trigger input; pull-up enable Push-pull output converter input (ADC3); Schmitt trigger input [.5-.4] Port P0.2/ADC2 Configuration Bits Schmitt trigger input Schmitt trigger input; pull-up enable Push-pull output converter input (ADC2); Schmitt trigger input [.3-.2] Port P0.1/ADC1/INT1 Configuration Bits Schmitt trigger input/falling edge interrupt input Schmitt trigger input; pull-up enable/falling edge interrupt input Push-pull output converter input (ADC1); Schmitt trigger input [.1-.0] Port P0.0/ADC0/INT0 Configuration Bits Schmitt trigger input/falling edge interrupt input Schmitt trigger input; pull-up enable/falling edge interrupt input Push-pull output converter input (ADC0); Schmitt trigger input
Figure 9-4. Port Control Register (P0CONL, Byte)
PORTS
S3C9454B/F9454B
Port Interrupt Pending Register E8H,
[.7-.4] used S3C9454B/F9454B [.3] Port 0.1/ADC1/INT1, Interrupt Enable INT1 falling edge interrupt disable INT1 falling edge interrupt enable [.2] Port 0.1/ADC1/INT1, Interrupt Pending interrupt pending (when read) Pending clear (when write) Interrupt pending (when read) effect (when write) [.1] Port 0.0/ADC0/INT0, Interrupt Enable INT0 falling edge interrupt disable INT0 falling edge interrupt enable [.0] Port 0.0/ADC0/INT0, Interrupt Pending interrupt pending (when read) Pending clear (when write) Interrupt pending (when read) effect (when write)
Figure 9-5. Port Interrupt Pending Registers (P0PND)
S3C9454B/F9454B
PORTS
PORT Port 3-bit port with individually configurable pins. used general port (Schmitt trigger input mode, push-pull output mode n-channel open-drain output mode). addition, configure pull-up pull-down resistor individual using control register settings. designed high-current functions such direct drive. P1.0, P1.1 used oscillator input/output smart option. Also, P1.2 used RESET smart option. control register used control port P1CON (E9H). address port bits directly writing reading port data register,
Other recent searches
TDA7311 - TDA7311 TDA7311 Datasheet
REJ03G0830-0600 - REJ03G0830-0600 REJ03G0830-0600 Datasheet
MW500-1174 - MW500-1174 MW500-1174 Datasheet
MAX2990 - MAX2990 MAX2990 Datasheet
KO3407 - KO3407 KO3407 Datasheet
DS05-50304-1E - DS05-50304-1E DS05-50304-1E Datasheet
307C1223BHLABR - 307C1223BHLABR 307C1223BHLABR Datasheet
307C1223BHMABR - 307C1223BHMABR 307C1223BHMABR Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
