MODE REGISTER FIELD TABLE PROGRAM MODES Register Programmed with
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DEVICE OPERATIONS
MODE REGISTER FIELD TABLE PROGRAM MODES
Register Programmed with Address A10/AP Function W.B.L Latency
CMOS SDRAM
Burst Length
Test Mode Type Mode Register Reserved Reserved Reserved Length Burst Single
Latency Latency Reserved Reserved Reserved Reserved Reserved Reserved
Burst Type Type Sequential Interleave
Burst Length
Write Burst Length
Reserved Reserved Reserved Reserved Reserved Reserved Full Page Reserved
POWER SEQUENCE
Full Page Length 64Mb (1024), (512), (256) 128Mb (2048), (1024), (512) 256Mb: (2048), (1024), (512)
Apply power start clock, Attempt maintain CKE= "H", DQM= other pins condition inputs. Maintain stable power, stable clock input condition minimum 200us. Issue precharge commands banks devices. Issue more auto-refresh commands. Issue mode register command initialize mode register. cf.) Sequence regardless order. device ready normal operation. Note high during cycle, "Burst Read Single Write" function will enabled. (Reserved future use) should stay during cycle.
Rev.0.0 Jan. 2000
ELECTRONICS
DEVICE OPERATIONS
BURST SEQUENCE BURST LENGTH
Initial Address Sequential
CMOS SDRAM
Interleave
BURST LENGTH
Initial Address Sequential Interleave
Rev.0.0 Jan. 2000
ELECTRONICS
DEVICE OPERATIONS
DEVICE OPERATIONS
ADDRESSES 16Mb BANK ADDRESSES (BA)
case
This SDRAM organized independent banks 2,097,152 words bits memory arrays. inputs latched time assertion select bank used operation. bank addresses latched bank active, read, write, mode register precharge operations.
CMOS SDRAM
ADDRESSES 64Mb BANK ADDRESSES (BA0 BA1)
case
This SDRAM organized four independent banks 4,194,304 words bits memory arrays. inputs latched time assertion select bank used operation. bank addresses latched bank active, read, write, mode register precharge operations.
case
This SDRAM organized independent banks 1,048,576 words bits memory arrays. inputs latched time assertion select bank used operation. bank addresses latched bank active, read, write, mode register precharge operations.
case
This SDRAM organized four independent banks 2,097,152 words bits memory arrays. inputs latched time assertion select bank used operation. bank addresses latched bank active, read, write, mode register precharge operations.
case
This SDRAM organized independent banks 524,288 words bits memory arrays. inputs latched time assertion select bank used operation. bank addresses latched bank active, read, write, mode register precharge operations.
case
This SDRAM organized four independent banks 1,048,576 words bits memory arrays. inputs latched time assertion select bank used operation. bank addresses latched bank active, read, write, mode register precharge operations.
ADDRESS INPUTS A10/AP)
case
address bits required decode 2,097,152 word locations multiplexed into address input pins A10/AP). addresses latched along with during bank activate command. column addresses latched along with CAS, during read write command.
ADDRESS INPUTS A11)
case
address bits required decode 4,194,304 word locations multiplexed into address input pins A11). addresses latched along with during bank activate command. column addresses latched along with CAS, during read write command.
case
address bits required decode 1,048,576 word locations multiplexed into address input pins A10/AP). addresses latched along with during bank activate command. column addresses latched along with CAS, during read write command.
case
address bits required decode 2,097,152 word locations multiplexed into address input pins A11). addresses latched along with during bank activate command. column addresses latched along with CAS, during read write command.
case
address bits required decode 524,288 word locations multiplexed into address input pins A10/AP). addresses latched along with during bank activate command. column addresses latched along with CAS, during read write command.
case
address bits required decode 1,048,576 word locations multiplexed into address input pins A11). addresses latched along with during bank activate command. column addresses latched along with CAS, during read write command.
Rev.0.0 Jan. 2000
ELECTRONICS
DEVICE OPERATIONS
DEVICE OPERATIONS (continued)
ADDRESSES 128Mb
BANK ADDRESSES (BA0 BA1) case
This SDRAM organized four independent banks 8,388,608 words bits memory arrays. inputs latched time assertion select bank used operation. bank addresses latched bank active, read, write, mode register precharge operations.
CMOS SDRAM
ADDRESSES 256Mb
BANK ADDRESSES (BA0 BA1) case
This SDRAM organized four independent banks 16,777,216 words bits memory arrays. inputs latched time assertion select bank used operation. bank addresses latched bank active, read, write, mode register precharge operations.
case
This SDRAM organized four independent banks 4,194,304 words bits memory arrays. inputs latched time assertion select bank used operation. bank addresses latched bank active, read, write, mode register precharge operations.
case
This SDRAM organized four independent banks 8,388,608 words bits memory arrays. inputs latched time assertion select bank used operation. bank addresses latched bank active, read, write, mode register precharge operations.
case
This SDRAM organized four independent banks 2,097,152 words bits memory arrays. inputs latched time assertion select bank used operation. bank addresses latched bank active, read, write, mode register precharge operations.
case
This SDRAM organized four independent banks 4,194,304 words bits memory arrays. inputs latched time assertion select bank used operation. bank addresses latched bank active, read, write, mode register precharge operations.
ADDRESS INPUTS A11)
case
address bits required decode 8,388,608 word locations multiplexed into address input pins A11). addresses latched along with during bank activate command. column addresses latched along with CAS, during read write command.
ADDRESS INPUTS A12)
case
address bits required decode 16,777,216 word locations multiplexed into address input pins A12). addresses latched along with during bank activate command. column addresses latched along with CAS, during read write command.
case
address bits required decode 4,194,304 word locations multiplexed into address input pins A11). addresses latched along with during bank activate command. column addresses latched along with CAS, during read write command.
case
address bits required decode 8,388,608 word locations multiplexed into address input pins A12). addresses latched along with during bank activate command. column addresses latched along with CAS, during read write command.
case
address bits required decode 2,097,152 word locations multiplexed into address input pins A11). addresses latched along with during bank activate command. column addresses latched along with CAS, during read write command.
case
address bits required decode 4,194,304 word locations multiplexed into address input pins addresses latched along with during bank activate command. column addresses latched along with CAS, during read write command.
Rev.0.0 Jan. 2000
ELECTRONICS
DEVICE OPERATIONS
DEVICE OPERATIONS (continued)
CLOCK (CLK)
clock input used reference SDRAM operations. operations synchronized positive going edge clock. clock transitions must monotonic between VIH. During operation with high inputs assumed valid state (low high) duration set-up hold time around positive edge clock order function well perform specifications.
CMOS SDRAM
OPERATION
used mask input output operations. works similar during read operation inhibits writing during write operation. read latency cycles from zero cycle write, which means masking occurs cycles later read cycle occurs same cycle during write cycle. operation synchronous with clock. signal important during burst interruptions write with read precharge SDRAM. asynchronous nature
CLOCK ENABLE (CKE)
clock enable(CKE) gates clock onto SDRAM. goes synchronously with clock (set-up hold time same other inputs), internal clock suspended from next clock cycle state output burst address frozen long remains low. other inputs ignored from next clock cycle after goes low. When banks idle state goes synchronously with clock, SDRAM enters power down mode from next clock cycle. SDRAM remains power down mode ignoring other inputs long remains low. power down exit synchronous internal clock suspended. When goes high least "1CLK tSS" before high going edge clock, then SDRAM becomes active from same clock edge accepting input commands.
internal write, operation critical avoid unwanted incomplete writes when complete burst write required. Please refer timing diagram also.
MODE REGISTER (MRS)
mode register stores data controlling various operating modes SDRAM. programs latency, burst type, burst length, test mode various vendor specific options make SDRAM useful variety different applications. default value mode register defined, therefore mode register must written after power operate SDRAM. mode register written asserting RAS, (The SDRAM should active mode with already high prior writing mode register). state address pins same cycle
DEVICE DESELECT
When RAS, high, SDRAM performs operation (NOP). does initiate operation, needed complete operations which require more than single clock cycle like bank activate, burst read, auto refresh, etc. device deselect also entered asserting high. high disables command decoder that RAS, CAS, address inputs ignored.
RAS, going data written mode register. clock cycles required complete write mode register. mode register contents changed using same command clock cycle requirements during operation long banks idle state. mode register divided into various fields depending fields functions. burst length field uses burst type uses latency (read latency from column address) vendor specific options test mode A10/AP BA1. write burst length programmed using A10/ must normal SDRAM operation. Refer table specific codes various burst length, burst type latencies.
Rev.0.0 Jan. 2000
ELECTRONICS
DEVICE OPERATIONS
DEVICE OPERATIONS (continued)
BANK ACTIVATE
bank activate command used select random idle bank. asserting with desired bank address, access initiated. read write operation occur after time delay tRCD(min) from time bank activation. tRCD internal timing parameter SDRAM, therefore dependent operating clock frequency. minimum number clock cycles required between bank activate read write command should calculated dividing tRCD(min) with cycle time clock then rounding result next higher integer. SDRAM four internal banks same chip shares part internal circuitry reduce chip area, therefore restricts activation four banks simultaneously. Also noise generated during sensing each bank SDRAM high, requiring some time power supplies recover before another bank sensed reliably. tRRD(min) specifies minimum time required between activating different bank. number clock cycles required between different bank activation must calculated similar tRCD specification. minimum time required bank active initiate sensing restoring complete dynamic cells determined tRAS(min). Every SDRAM bank activate command must satisfy tRAS(min) specification before precharge command that active bank asserted. maximum time bank active state determined tRAS(max). number cycles both tRAS(min) tRAS(max) calculated similar tRCD specification.
CMOS SDRAM
burst read initiated column address active row. address wraps around initial address does start from boundary such that number outputs from each equal burst length programmed mode register. output goes into high-impedance burst, unless burst read initiated keep data output gapless. burst read terminated issuing another burst read burst write same bank other active bank precharge command same bank. burst stop command valid every page burst length.
BURST WRITE
burst write command similar burst read command used write data into SDRAM consecutive clock cycles adjacent addresses depending burst length burst sequence. asserting with valid column address, write burst initiated. data inputs provided initial address same clock cycle burst write command. input buffer deselected burst length, even though internal writing completed yet. writing completed issuing burst read blocking data inputs burst write same another active bank. burst stop command valid every burst length. write burst also terminated using blocking data procreating bank tRDL after last data input written into active row. OPERATION also.
BURST READ
burst read command used access burst data consecutive clock cycles from active active bank. burst read command issued asserting with being high positive edge clock. bank must active least tRCD(min) before burst read command issued. first output appears latency number clock cycles after issue burst read command. burst length, burst sequence latency from burst read command determined mode register which already programmed.
BANKS PRECHARGE
banks precharged same time using Precharge command. Asserting RAS, with high A10/AP after banks have satisfied tRAS(min) requirement, performs precharge banks. after performing precharge banks, banks idle state.
Rev.0.0 Jan. 2000
ELECTRONICS
DEVICE OPERATIONS
DEVICE OPERATIONS (continued)
PRECHARGE
precharge operation performed active bank asserting RAS, A10/AP with valid bank precharged. precharge command asserted anytime after tRAS(min) satisfied from bank active command desired bank. defined minimum number clock cycles required complete precharge calculated dividing with clock cycle time rounding next higher integer. Care should taken make sure that burst write completed used inhibit writing before precharge command asserted. maximum time bank active specified tRAS(max). Therefore, each bank activate command. precharge, bank enters idle state ready activated again. Entry Power down, Auto refresh, Self refresh Mode register etc. possible only when banks idle state.
CMOS SDRAM
time required complete auto refresh operation specified tRC(min). minimum number clock cycles required calculated driving with clock cycle time them rounding next higher integer. auto refresh command must followed NOP's until auto refresh operation completed. banks will idle state auto refresh operation. auto refresh preferred refresh mode when SDRAM being used normal data transactions. 16Mb SDRAM' auto refresh cycle performed once 15.6us burst 2048 auto refresh cycles once 32ms. 64Mb 128Mb SDRAM' auto refresh cycle performed once 15.6us burst 4096 auto refresh cycles once 64ms. 256Mb SDRAM' auto refresh cycle performed once 7.8us burst 8192 auto refresh cycles once 64ms.
SELF REFRESH AUTO PRECHARGE
precharge operation also performed using auto precharge. SDRAM internally generates timing satisfy tRAS(min) "tRP" programmed burst length latency. auto precharge command issued same time burst read burst write asserting high A10/AP. burst read burst write asserting high A10/AP, bank left active until command asserted. Once auto precharge command given, commands possible that particular bank until bank achieves idle state. self refresh another refresh mode available SDRAM. self refresh preferred refresh mode data retention power operation SDRAM. self refresh mode, SDRAM disables internal clock input buffers except CKE. refresh addressing timing internally generated reduce power consumption. self refresh mode entered from banks idle state asserting RAS, with high Once self refresh mode entered, only state being matters, other inputs including clock ignored order remain self refresh mode.
AUTO REFRESH
storage cells 64Mb, 128Mb 256Mb SDRAM need refreshed every 64ms maintain data 16Mb SDRAM need refreshed every 32ms maintain data. auto refresh cycle accomplishes refresh single storage cells. internal counter increments automatically every auto refresh cycle refresh rows. auto refresh command issued
self refresh exited restarting external clock then asserting high CKE. This must followed NOP's minimum time before SDRAM reaches idle state begin normal operation. system uses burst auto refresh during normal operation, recommended burst 8192 auto refresh cycles 256Mb burst 4096 auto refresh cycles 128Mb 64Mb burst 2048 auto refresh cycles 16Mb ately after exiting self refresh mode. immedi-
asserting with high auto refresh command only asserted with both banks being idle state device power down mode (CKE high previous cycle).
Rev.0.0 Jan. 2000
ELECTRONICS
DEVICE OPERATIONS
BASIC FEATURE FUNCTION DESCRIPTIONS
CMOS SDRAM
CLOCK Suspend
Clock Suspended During Write (BL=4)
Masked
Clock Suspended During Read (BL=4)
Masked
Internal DQ(CL2) DQ(CL3) Written
Internal DQ(CL2) DQ(CL3)
Suspended Dout
Operation
Write Mask (BL=4)
Masked byDQM
Read Mask (BL=4)
DQ(CL2) DQ(CL3)
DQ(CL2) DQ(CL3)
Masked Hi-Z
Hi-Z
Data-in Mask
Data-out Mask
with Clock Suspended (Full Page Read) DQ(CL2) DQ(CL3)
Hi-Z Hi-Z
Hi-Z Hi-Z
Hi-Z Hi-Z
*Note disable/enable 1CLK. makes data Hi-Z after 2CLKs which should masked masks both data-in data-out.
Rev.0.0 Jan. 2000
ELECTRONICS
DEVICE OPERATIONS
Interrupt
Read interrupted Read (BL=4) DQ(CL2) DQ(CL3)
tCCD
CMOS SDRAM
Write interrupted Write (BL=2)
Write interrupted Read (BL=2)
tCCD
tCCD
DQ(CL2) DQ(CL3)
tCDL
tCDL
*Note Interrupt", meant stop burst read/write external command before burst. "CAS Interrupt", stop burst read/write access read write. tCCD delay. (=1CLK) tCDL Last data column address delay. (=1CLK)
Rev.0.0 Jan. 2000
ELECTRONICS
DEVICE OPERATIONS
Interrupt (II) Read Interrupted Write
CL=2, BL=4 iii) CL=3, BL=4 iii) iii)
Hi-Z
CMOS SDRAM
Hi-Z
Hi-Z
Hi-Z
Hi-Z
*Note prevent contention, there should least between data data out.
Rev.0.0 Jan. 2000
ELECTRONICS
DEVICE OPERATIONS
Write Interrupted Precharge
tRDL
CMOS SDRAM
tRDL 2CLK
Masked
Masked
*Note prevent contention, should issued which makes least between data data out. inhibit invalid write, should issued. This precharge command burst write command should same bank, otherwise precharge interrupt only another bank precharge four banks operation.
Precharge
Normal Write BL=4 tRDL=1CLK
tRDL
BL=4 tRDL=2CLK
tRDL*1
Normal Read (BL=4)
DQ(CL2) DQ(CL3)
Auto Precharge
Normal Write (BL=4)
tRDL =1CLK
Normal Read (BL=4) DQ(CL2)
+20ns*4
tDAL =1CLK
DQ(CL3)
tRDL =2CLK tDAL =2CLK +20ns*4 Auto Precharge Starts @tRDL=1CLK Auto Precharge Starts@tRDL=2CLK
Auto Precharge Starts
*Note SAMSUNG support tRDL =1CLK tRDL=2CLK memory devices. SAMSUNG recommands tRDL=2 CLK. Number valid output data after precharge Latency respectively. active command precharge bank issued after from this point. read/write command other activated bank issued from this point. burst read/write with auto precharge, interrupt same bank illegal tDAL defined Last data Active delay. SAMSUNG support tDAL=1CLK+20ns 2CLK+20ns ,recommands tDAL=2CLK+20ns.
Rev.0.0 Jan. 2000
ELECTRONICS
DEVICE OPERATIONS
Burst Stop Interrupted Precharge
Normal Write BL=4 tRDL=1CLK BL=4 tRDL=2CLK
CMOS SDRAM
tRDL*1
tRDL*1
Write Burst Stop (BL=8)
STOP
Read Interrupted Precharge (BL=4) DQ(CL2) DQ(CL3)
tBDL
Read Burst Stop (BL=4) DQ(CL2) DQ(CL3)
STOP
Mode Register
2CLK
*Note SAMSUNG support tRDL=1CLK tRDL=2CLK memory devices. SAMSUNG recommands tRDL=2 CLK. tBDL Last data burst stop delay. Read write burst stop command valid every burst length. Number valid output data after precharge burst stop latency= respectively. banks precharge necessary. issued only banks precharge state.
Rev.0.0 Jan. 2000
ELECTRONICS
DEVICE OPERATIONS
Clock Suspend Exit Power Down Exit
Clock Suspend (=Active Power Down) Exit
CMOS SDRAM
Power Down (=Precharge Power Down) Exit Internal
Internal
Auto Refresh Self Refresh
Auto Refresh Self Refresh*3
Self Refresh
Note
*Note Active power down more banks active state. Precharge power down banks precharge state. auto refresh same refresh conventional DRAM. precharge commands required after auto refresh command. During from auto refresh command, other command accepted. Before executing auto/self refresh command, banks must idle state. MRS, Bank Active, Auto/Self Refresh, Power Down Mode Entry. During self refresh mode, refresh interval refresh operation performed internally. After self refresh entry, self refresh mode kept while low. During self refresh mode, inputs except will don't cared, outputs will Hi-Z state. time interval from self refresh exit command, other command accepted. Before/After self refresh mode, burst auto refresh cycle (4096 cycles) recommended.
Rev.0.0 Jan. 2000
ELECTRONICS
DEVICE OPERATIONS
About Burst Type Control
Sequential Counting Basic MODE Interleave Counting Random column Access tCCD
CMOS SDRAM
"0". BURST SEQUENCE TABLE. (BL=4, BL=1, full page. "1". BURST SEQUENCE TABLE. (BL=4, BL=4, BL=1, Interleave Counting Sequential Counting Every cycle Read/Write Command with random column address realize Random Column Access. That similar Extended Data (EDO) Operation conventional DRAM.
Random MODE
About Burst Length Control
Basic MODE Full Page Special MODE Random MODE A2,1,0 "000". auto precharge, tRAS should violated. A2,1,0 "001". auto precharge, tRAS should violated. A2,1,0 "010". A2,1,0 "011". A2,1,0 "111". Wrap around mode(infinite burst length) should stopped burst stop. interrupt interrupt "1". Read burst full page write Burst auto precharge write, tRAS should violated. tBDL= Valid after burst stop latency respectively Using burst stop command, burst length control possible. Before burst, precharge command same bank stops read/write burst with precharge. tRDL= with DQM, valid after burst stop latency respectively. During read/write burst with auto precharge, interrupt issued. Before burst, read/write stops read/write burst starts read/write burst. During read/write burst with auto precharge, interrupt issued.
BRSW Burst Stop
Interrupt MODE
Interrupt (Interrupted Precharge)
Interrupt
Rev.0.0 Jan. 2000
ELECTRONICS
DEVICE OPERATIONS
FUNCTION TRUTH TABLE (TABLE
Current State IDLE Active Read Write Read with Auto Precharge Write with Auto Precharge Precharging code ADDR A10/AP A10/AP code A10/AP A10/AP A10/AP A10/AP A10/AP A10/AP A10/AP A10/AP A10/AP A10/AP RA10 A10/AP RA10 A10/AP ILLEGAL ILLEGAL Bank) Active Latch Auto Refresh Self Refresh Mode Register Access ILLEGAL ACTION
CMOS SDRAM
Note
Begin Read latch determine Begin Write latch determine ILLEGAL Precharge ILLEGAL (Continue Burst Active) (Continue Burst Active) Term burst active Term burst, Read, Determine Term burst, Write, Determine ILLEGAL Term burst, Precharge timing Reads ILLEGAL (Continue Burst Active) (Continue Burst Active) Term burst active Term burst, read, Determine Term burst, Write, Determine ILLEGAL Term burst, precharge timing Writes ILLEGAL (Continue Burst Precharge) (Continue Burst Precharge) ILLEGAL ILLEGAL ILLEGAL ILLEGAL (Continue Burst Precharge) (Continue Burst Precharge) ILLEGAL ILLEGAL ILLEGAL ILLEGAL Idle after Idle after ILLEGAL ILLEGAL ILLEGAL Idle after
Rev.0.0 Jan. 2000
ELECTRONICS
DEVICE OPERATIONS
FUNCTION TRUTH TABLE (TABLE
Current State Activating Refreshing Mode Register Accessing ADDR A10/AP ILLEGAL Active after tRCD Active after tRCD ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Idle after Idle after ILLEGAL ILLEGAL ILLEGAL Idle after clocks Idle after clocks ILLEGAL ILLEGAL ILLEGAL ACTION
CMOS SDRAM
Note
Abbreviations Address Operation Command
Bank Address Column Address
Auto Precharge
*Note entries assume active (High) during precharge clock current clock cycle. Illegal bank specified state Function Iegal bank indicated depending state that bank. Must satisfy contention, turn around, and/or write recovery requirements. bank precharging idle state. precharge bank indicated (and A10/AP). Illegal bank idle.
Rev.0.0 Jan. 2000
ELECTRONICS
DEVICE OPERATIONS
FUNCTION TRUTH TABLE (TABLE
Current State (n-1) Self Refresh Banks Precharge Power Down Banks Idle State other than Listed above ADDR Code INVALID ACTION
CMOS SDRAM
Note
Exit Self Refresh Idle after tRFC (ABI) Exit Self Refresh Idle after tRFC (ABI) ILLEGAL ILLEGAL ILLEGAL (Maintain Self Refresh) INVALID Exit Power Down Exit Power Down ILLEGAL ILLEGAL ILLEGAL (Maintain Power Mode) Refer Table Enter Power Down Enter Power Down ILLEGAL ILLEGAL Bank) Active Enter Self Refresh Mode Register Access Refer Operations Table Begin Clock Suspend next cycle Exit Clock Suspend next cycle Maintain Clock Suspend
Abbreviations Banks Idle, Address *Note high transition asynchronous. high transition asynchronous restarts internal clock. minimum setup time 1CLK must satisfied before command other than exit. Power down self refresh entered only from both banks idle state. Must legal command.
Rev.0.0 Jan. 2000
ELECTRONICS
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