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SAM88RCRI INSTRUCTION SAM88RCRI INSTRUCTION SAM88RCRI instru


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KS86C6308/P6308 (Preliminary Spec)
SAM88RCRI INSTRUCTION
SAM88RCRI INSTRUCTION
SAM88RCRI instruction designed support large register file. includes full complement 8-bit arithmetic logic operations. There instructions. special instructions necessary because control data registers mapped directly into register file. Flexible instructions addressing, rotate, shift operations complete powerful data manipulation capabilities SAM88RCRI instruction set. REGISTER ADDRESSING access individual register, 8-bit address range 0-255 4-bit address working register specified. Paired registers used construct 13-bit program memory data memory addresses. detailed information about register addressing, please refer Section "Address Spaces". ADDRESSING MODES There addressing modes: Register (R), Indirect Register (IR), Indexed (X), Direct (DA), Relative (RA), Immediate (IM). detailed descriptions these addressing modes, please refer Section "Addressing Modes".
SAM88RCRI INSTRUCTION
KS86C6308/P6308 (Preliminary Spec)
Table 6-1. Instruction Group Summary Mnemonic Operands Instruction
Load Instructions LDCD LDED LDCI LDEI PUSH dst,src dst,src dst,src dst,src dst,src dst,src dst,src Clear Load Load program memory Load external data memory Load program memory decrement Load external data memory decrement Load program memory increment Load external data memory increment from stack Push stack
Arithmetic Instructions dst,src dst,src dst,src dst,src dst,src with carry Compare Decrement Increment Subtract with carry Subtract
Logic Instructions dst,src dst,src dst,src Logical Complement Logical Logical exclusive
KS86C6308/P6308 (Preliminary Spec)
SAM88RCRI INSTRUCTION
Table 6-1. Instruction Group Summary (Continued) Mnemonic Operands Instruction
Program Control Instructions CALL IRET cc,dst cc,dst Call procedure Interrupt return Jump condition code Jump unconditional Jump relative condition code Return
Manipulation Instructions dst,src dst,src Test complement under mask Test under mask
Rotate Shift Instructions Rotate left Rotate left through carry Rotate right Rotate right through carry Shift right arithmetic
Control Instructions IDLE STOP Complement carry flag Disable interrupts Enable interrupts Enter Idle mode operation Reset carry flag carry flag Enter Stop mode
SAM88RCRI INSTRUCTION
KS86C6308/P6308 (Preliminary Spec)
FLAGS REGISTER (FLAGS) FLAGS register contains eight bits that describe current status operations. Four these bits, FLAGS.4 FLAGS.7, tested used with conditional jump instructions; FLAGS register reset instructions long outcome does affect flags, such Load instruction. Logical Arithmetic instructions such AND, XOR, ADD, affect Flags register. example, instruction updates Zero, Sign Overflow flags based outcome instruction. instruction uses Flags register destination, then simultaneously, write will occur Flags register producing unpredictable result.
SYSTEM FLAGS REGISTER (FLAGS) D5H,
Carry flag mapped Zero flag Sign flag Overflow flag
Figure 6-1. System Flags Register (FLAGS) FLAG DESCRIPTIONS Overflow Flag (FLAGS.4, flag when result two's-complement operation greater than less than 128. also cleared following logic operations. Sign Flag (FLAGS.5, Following arithmetic, logic, rotate, shift operations, sign identifies state result. logic zero indicates positive number logic indicates negative number. Zero Flag (FLAGS.6, arithmetic logic operations, flag result operation zero. operations that test register bits, shift rotate operations, flag result logic zero. Carry Flag (FLAGS.7, flag result from arithmetic operation generates carry-out from borrow position (MSB). After rotate shift operations, contains last value shifted specified register. Program instructions set, clear, complement carry flag.
KS86C6308/P6308 (Preliminary Spec)
SAM88RCRI INSTRUCTION
INSTRUCTION NOTATION Table 6-2. Flag Notation Conventions Flag Carry flag Zero flag Sign flag Overflow flag Cleared logic zero logic cleared according operation Value unaffected Value undefined Description
Table 6-3. Instruction Symbols Symbol FLAGS Description Destination operand Source operand Indirect register address prefix Program counter Flags register (D5H) Immediate operand register address prefix Hexadecimal number suffix Decimal number suffix Binary number suffix Opcode
SAM88RCRI INSTRUCTION
KS86C6308/P6308 (Preliminary Spec)
Table 6-4. Instruction Notation Conventions Notation Condition code Working register only Working register pair Register working register Register pair working register pair Description Actual Operand Range list condition codes Table 6-6. 0-15) (reg 0-255, 0-15) (reg 0-254, even number only, where 0-15)
Indirect working register only
Indirect register indirect working register @reg (reg 0-255, 0-15) Indirect working register pair only Indirect register pair indirect working register pair Indexed addressing mode Indexed (short offset) addressing mode @RRp @RRp @reg (reg 0-254, even only, where #reg[Rn] (reg 0-255, 0-15) #addr[RRp] (addr range -128 +127, where #addr [RRp] (addr range 0-8191, where addr (addr range 0-8191) addr (addr number range +127 -128 that offset relative address next instruction) #data (data 0-255)
Indexed (long offset) addressing mode
Direct addressing mode Relative addressing mode
Immediate addressing mode
KS86C6308/P6308 (Preliminary Spec)
SAM88RCRI INSTRUCTION
Table 6-5. Opcode Quick Reference OPCODE LOWER NIBBLE (HEX) r1,r2 LDCD r1,Irr2 r1,r2 r1,Ir2 r1,Ir2 r1,Irr2 r2,Irr1 LDCI r1,Irr2 R2,R1 CALL IRR1 R2,IR1 IR2,R1 IR1,IM R1,IM CALL R2,R1 R2,R1 IR2,R1 IR2,R1 R1,IM R1,IM PUSH PUSH IRR1 r1,r2 r1,r2 r1,r2 r1,r2 r1,r2 r1,r2 r1,r2 r1,r2 r1,Ir2 r1,Ir2 r1,Ir2 r1,Ir2 r1,Ir2 r1,Ir2 r1,Ir2 r1,Ir2 R2,R1 R2,R1 R2,R1 R2,R1 R2,R1 R2,R1 R2,R1 R2,R1 IR2,R1 IR2,R1 IR2,R1 IR2,R1 IR2,R1 IR2,R1 IR2,R1 IR2,R1 R1,IM R1,IM R1,IM R1,IM R1,IM R1,IM R1,IM R1,IM Irr2, Irr2, Ir1, Irr2, Irr1,
SAM88RCRI INSTRUCTION
KS86C6308/P6308 (Preliminary Spec)
Table 6-5. Opcode Quick Reference (Continued) OPCODE LOWER NIBBLE (HEX) r1,R2 r2,R1 cc,RA r1,IM cc,DA IDLE r1,R2 r2,R1 cc,RA r1,IM cc,DA
STOP IRET
KS86C6308/P6308 (Preliminary Spec)
SAM88RCRI INSTRUCTION
CONDITION CODES opcode conditional jump always contains 4-bit field called condition code (cc). This specifies under which conditions execute jump. example, conditional jump with condition code "equal" after compare operation only jumps operands equal. Condition codes listed Table 6-6. carry (C), zero (Z), sign (S), overflow flags used control operation conditional jump instructions. Table 6-6. Condition Codes Binary 0000 1000 0111 1111 0110 1110 1101 0101 0100 1100 0110 1110 1001 0001 1010 0010 1111 0111 1011 0011 Mnemonic Description Always false Always true Carry carry Zero zero Plus Minus Overflow overflow Equal equal Greater than equal Less than Greater than Less than equal Unsigned greater than equal Unsigned less than Unsigned greater than Unsigned less than equal Flags
NOTES: Indicate condition codes that related different mnemonics which test same flag. example, both true zero flag set, after instruction, would probably used; after instruction, however, would probably used. operations involving unsigned numbers, special condition codes UGE, ULT, UGT, must used.
SAM88RCRI INSTRUCTION
KS86C6308/P6308 (Preliminary Spec)
INSTRUCTION DESCRIPTIONS This section contains detailed information programming examples each instruction SAM88RCRI instruction set. Information arranged consistent format improved readability fast referencing. following information included each instruction description: Instruction name (mnemonic) Full instruction name Source/destination format instruction operand Shorthand notation instruction's operation Textual description instruction's effect Specific flag settings affected instruction Detailed description instruction's format, execution time, addressing mode(s) Programming example(s) explaining instruction
6-10
KS86C6308/P6308 (Preliminary Spec)
SAM88RCRI INSTRUCTION
With Carry
Operation: dst,src source operand, along with setting carry flag, added destination operand stored destination. contents source unaffected. Two'scomplement addition performed. multiple precision arithmetic, this instruction permits carry from addition low-order operands carried into addition high-order operands. Flags: there carry from most significant result; cleared otherwise. result "0"; cleared otherwise. result negative; cleared otherwise. arithmetic overflow occurs, that both operands same sign result opposite sign; cleared otherwise. Always cleared "0". there carry from most significant low-order four bits result; cleared otherwise. Bytes Cycles Opcode (Hex) Addr Mode
Format:
Examples:
Given: 10H, 03H, flag "1", register 20H, register 03H, register 0AH: R1,R2 R1,@R2 01H,02H 01H,@02H 01H,#11H 14H, 1BH, Register 24H, register Register 2BH, register Register
first example, destination register contains value 10H, carry flag "1", source working register contains value 03H. statement "ADC R1,R2" adds carry flag value ("1") destination value 10H, leaving register
6-11
SAM88RCRI INSTRUCTION
KS86C6308/P6308 (Preliminary Spec)
Operation: dst,src source operand added destination operand stored destination. contents source unaffected. Two's-complement addition performed. Flags: there carry from most significant result; cleared otherwise. result "0"; cleared otherwise. result negative; cleared otherwise. arithmetic overflow occurred, that both operands same sign result opposite sign; cleared otherwise. Always cleared "0". carry from low-order nibble occurred.
Format: Bytes Cycles Opcode (Hex) Addr Mode
Examples:
Given: 12H, 03H, register 21H, register 03H, register 0AH: R1,R2 R1,@R2 01H,02H 01H,@02H 01H,#25H 15H, 1CH, Register 24H, register Register 2BH, register Register
first example, destination working register contains source working register contains 03H. statement "ADD R1,R2" adds 12H, leaving value register
6-12
KS86C6308/P6308 (Preliminary Spec)
SAM88RCRI INSTRUCTION
Logical
Operation: dst,src source operand logically ANDed with destination operand. result stored destination. operation results being stored whenever corresponding bits operands both logic ones; otherwise value stored. contents source unaffected. Flags: Unaffected. result "0"; cleared otherwise. result set; cleared otherwise. Always cleared "0". Unaffected. Unaffected.
Format: Bytes Cycles Opcode (Hex) Addr Mode
Examples:
Given: 12H, 03H, register 21H, register 03H, register 0AH: R1,R2 R1,@R2 01H,02H 01H,@02H 01H,#25H 02H, 02H, Register 01H, register Register 00H, register Register
first example, destination working register contains value source working register contains 03H. statement "AND R1,R2" logically ANDs source operand with destination operand value 12H, leaving value register
6-13
SAM88RCRI INSTRUCTION
KS86C6308/P6308 (Preliminary Spec)
CALL Call Procedure
CALL Operation:
current contents program counter pushed onto stack. program counter value used address first instruction following CALL instruction. specified destination address then loaded into program counter points first instruction procedure. procedure return instruction (RET) used return original program flow. pops stack back into program counter. Flags: Format: Bytes Cycles Opcode (Hex) Addr Mode flags affected.
Examples:
Given: 15H, 21H, 1A47H, 0B2H: CALL 1521H 0B0H (Memory locations 1AH, 4AH, where address that follows instruction.) 0B0H (00H 1AH, 49H)
CALL
@RR0
first example, program counter value 1A47H stack pointer contains value 0B2H, statement "CALL 1521H" pushes current value onto stack. stack pointer points memory location 00H. then loaded with value 1521H, address first instruction program sequence executed. contents program counter stack pointer same first example, statement "CALL @RR0" produces same result except that stored stack location (because two-byte instruction format used). then loaded with value 1521H, address first instruction program sequence executed.
6-14
KS86C6308/P6308 (Preliminary Spec)
SAM88RCRI INSTRUCTION
Complement Carry Flag
Operation: carry flag complemented. "1", value carry flag changed logic zero; "0", value carry flag changed logic one. Flags: Complemented. other flags affected. Format: Bytes Cycles Opcode (Hex)
Example:
Given: carry flag "0": carry flag "0", instruction complements FLAGS register (0D5H), changing value from logic zero logic one.
6-15
SAM88RCRI INSTRUCTION
KS86C6308/P6308 (Preliminary Spec)
Clear
Operation: destination location cleared "0". Flags: Format: Bytes Cycles Opcode (Hex) Addr Mode flags affected.
Examples:
Given: Register 4FH, register 02H, register 5EH: @01H Register Register 02H, register
Register addressing mode, statement "CLR 00H" clears destination register value 00H. second example, statement "CLR @01H" uses Indirect Register (IR) addressing mode clear register value 00H.
KS86C6308/P6308 (Preliminary Spec)
SAM88RCRI INSTRUCTION
Complement
Operation: contents destination location complemented (one's complement); "1s" changed "0s", vice-versa. Flags: Unaffected. result "0"; cleared otherwise. result set; cleared otherwise. Always reset "0". Unaffected. Unaffected.
Format: Bytes Cycles Opcode (Hex) Addr Mode
Examples:
Given: register 0F1H: 0F8H 07H, register
first example, destination working register contains value (00000111B). statement "COM complements bits logic ones changed logic zeros, vice-versa, leaving value 0F8H (11111000B). second example, Indirect Register (IR) addressing mode used complement value destination register (11110001B), leaving value (00001110B).
6-17
SAM88RCRI INSTRUCTION
KS86C6308/P6308 (Preliminary Spec)
Compare
Operation: dst,src source operand compared (subtracted from) destination operand, appropriate flags accordingly. contents both operands unaffected comparison. Flags: "borrow" occurred (src dst); cleared otherwise. result "0"; cleared otherwise. result negative; cleared otherwise. arithmetic overflow occurred, that operands were opposite signs sign result same sign source operand; cleared otherwise. Unaffected. Unaffected.
Format: Bytes Cycles Opcode (Hex) Addr Mode
Examples:
Given: 03H: R1,R2 flags
Destination working register contains value source register contains value 03H. statement R1,R2" subtracts value (source/subtrahend) from value (destination/minuend). Because "borrow" occurs difference negative, "1". Given: 0AH: SKIP R1,R2 UGE,SKIP R3,R1
this example, destination working register contains value which less than contents source working register (0AH). statement R1,R2" generates instruction does jump SKIP location. After statement R3,R1" executes, value remains working register
6-18
KS86C6308/P6308 (Preliminary Spec)
SAM88RCRI INSTRUCTION
Decrement
Operation: contents destination operand decremented one. Flags: Unaffected. result "0"; cleared otherwise. result negative; cleared otherwise. arithmetic overflow occurred, that value -128(80H) result value +127(7FH); cleared otherwise. Unaffected. Unaffected.
Format: Bytes Cycles Opcode (Hex) Addr Mode
Examples:
Given: register 10H: Register
first example, working register contains value 03H, statement "DEC decrements hexadecimal value one, leaving value 02H. second example, statement "DEC @R1" decrements value contained destination register one, leaving value 0FH.
6-19
SAM88RCRI INSTRUCTION
KS86C6308/P6308 (Preliminary Spec)
Disable Interrupts
Operation: zero system mode register, SYM.3, cleared "0", globally disabling interrupt processing. Interrupt requests will continue their respective interrupt pending bits, will service them while interrupt processing disabled. Flags: Format: Bytes Cycles Opcode (Hex) flags affected.
Example:
Given: 08H: value register 04H, statement "DI" leaves value register clears SYM.3 "0", disabling interrupt processing.
6-20
KS86C6308/P6308 (Preliminary Spec)
SAM88RCRI INSTRUCTION
Enable Interrupts
Operation: instruction sets system mode register, SYM.3 "1". This allows interrupts serviced they occur. interrupt's pending while interrupt processing disabled executing instruction), will serviced when execute instruction. Flags: Format: Bytes Cycles Opcode (Hex) flags affected.
Example:
Given: 00H: register contains value 00H, that interrupts currently disabled, statement "EI" sets register 08H, enabling interrupts (SYM.3 enable global interrupt processing).
6-21
SAM88RCRI INSTRUCTION
KS86C6308/P6308 (Preliminary Spec)
IDLE Idle Operation
IDLE Operation: IDLE instruction stops clock while allowing system clock oscillation continue. Idle mode released interrupt request (IRQ) external reset operation. Flags: Format: Bytes Cycles Opcode (Hex) Addr Mode flags affected.
Example:
instruction IDLE stops clock system clock.
6-22
KS86C6308/P6308 (Preliminary Spec)
SAM88RCRI INSTRUCTION
Increment
Operation: contents destination operand incremented one. Flags: Unaffected. result "0"; cleared otherwise. result negative; cleared otherwise. arithmetic overflow occurred, that value +127(7FH) result -128(80H); cleared otherwise. Unaffected. Unaffected.
Format: Bytes Cycles Opcode (Hex) Addr Mode
Examples:
Given: 1BH, register 0CH, register 0FH: Register 1BH, register
first example, destination working register contains value 1BH, statement "INC leaves value that same register. next example shows effect instruction register 00H, assuming that contains value 0CH. third example, used Indirect Register (IR) addressing mode increment value register from 10H.
6-23
SAM88RCRI INSTRUCTION
KS86C6308/P6308 (Preliminary Spec)
IRET Interrupt Return
IRET Operation: IRET FLAGS SYM(2) This instruction used interrupt service routine. restores flag register program counter. also re-enables global interrupts. Flags: Format: IRET (Normal) Bytes Cycles Opcode (Hex) flags restored their original settings (that settings before interrupt occurred).
6-24
KS86C6308/P6308 (Preliminary Spec)
SAM88RCRI INSTRUCTION
Jump
Operation: cc,dst (Conditional) (Unconditional)
true, conditional JUMP instruction transfers program control destination address condition specified condition code (cc) true; otherwise, instruction following instruction executed. unconditional simply replaces contents with contents specified register pair. Control then passes statement addressed
Flags: Format:
flags affected.
Bytes
Cycles
Opcode (Hex)
Addr Mode
NOTES: 3-byte format used conditional jump 2-byte format unconditional jump. first byte three-byte instruction format (conditional jump), condition code both four bits.
opcode
Examples:
Given: carry flag "1", register 01H, register 20H: C,LABEL_W @00H LABEL_W 1000H, 1000H 0120H
first example shows conditional Assuming that carry flag "1", statement C,LABEL_W" replaces contents with value 1000H transfers control that location. carry flag been set, control would then have passed statement immediately following instruction. second example shows unconditional statement @00" replaces contents with contents register pair 01H, leaving value 0120H.
6-25
SAM88RCRI INSTRUCTION
KS86C6308/P6308 (Preliminary Spec)
Jump Relative
Operation: cc,dst true, condition specified condition code (cc) true, relative address added program counter control passes statement whose address program counter; otherwise, instruction following instruction executed (See list condition codes). range relative address +127, -128, original value program counter taken address first instruction byte following statement. Flags: Format: Bytes
flags affected.
Cycles
Opcode (Hex)
Addr Mode
NOTE: first byte two-byte instruction format, condition code opcode each four bits.
Example:
Given: carry flag LABEL_X 1FF7H: C,LABEL_X 1FF7H
carry flag (that condition code true), statement C,LABEL_X" will pass control statement whose address Otherwise, program instruction following would executed.
KS86C6308/P6308 (Preliminary Spec)
SAM88RCRI INSTRUCTION
Load
Operation: dst,src contents source loaded into destination. source's contents unaffected. Flags: Format: Bytes Cycles Opcode (Hex) Addr Mode flags affected.
6-27
SAM88RCRI INSTRUCTION
KS86C6308/P6308 (Preliminary Spec)
Load
Examples: (Continued) Given: 01H, 0AH, register 01H, register 20H, register 02H, LOOP 30H, register 0FFH: R0,#10H R0,01H 01H,R0 R1,@R0 @R0,R1 00H,01H 02H,@00H 00H,#0AH @00H,#10H @00H,02H R0,#LOOP[R1] #LOOP[R0],R1 20H, register Register 01H, 20H, 01H, 0AH, register Register 20H, register Register 20H, register Register Register 01H, register Register 01H, register register 0FFH, Register 0AH, 01H,
6-28
KS86C6308/P6308 (Preliminary Spec)
SAM88RCRI INSTRUCTION
LDC/LDE Load Memory
LDC/LDE Operation: dst,src This instruction loads byte from program data memory into working register vice-versa. source values unaffected. refers program memory data memory. assembler makes 'Irr' 'rr' values even number program memory number data memory. Flags: Format: Bytes
flags affected.
Cycles
Opcode (Hex)
Addr Mode
[rr] [rr] [rr]
[rr]
0000
0000
0001
0001
NOTES: source (src) working register pair [rr] formats cannot register pair 0-1. formats destination address [rr]' source address [rr]' each byte. formats destination address [rr] source address [rr]' each bytes. source values formats used address program memory; second values, used formats used address data memory.
6-29
SAM88RCRI INSTRUCTION
KS86C6308/P6308 (Preliminary Spec)
LDC/LDE Load Memory
LDC/LDE Examples: (Continued) Given: 11H, 34H, 01H, 04H, 00H, 60H; Program memory locations 0061 AAH, 0103H 4FH, 0104H 0105H 6DH, 1104H 88H. External data memory locations 0061H BBH, 0103H 5FH, 0104H 2AH, 0105H 7DH, 1104H 98H: R0,@RR2 R0,@RR2 @RR2,R0 contents program memory location 0104H 1AH, 01H, contents external data memory location 0104H 2AH, 01H, (contents loaded into program memory location 0104H (RR2), working registers change @RR2,R0 (contents loaded into external data memory location 0104H (RR2), working registers change R0,#01H[RR4] contents program memory location 0061H (01H RR4), AAH, 00H, R0,#01H[RR4] contents external data memory location 0061H (01H RR4), BBH, 00H, (note) #01H[RR4],R0 #01H[RR4],R0 (contents loaded into program memory location 0061H (01H 0060H) (contents loaded into external data memory location 0061H (01H 0060H) R0,#1000H[RR2] contents program memory location 1104H (1000H 0104H), 88H, 01H, R0,#1000H[RR2] contents external data memory location 1104H (1000H 0104H), 98H, 01H, R0,1104H R0,1104H contents program memory location 1104H, contents external data memory location 1104H, (note) 1105H,R0 1105H,R0 (contents loaded into program memory location 1105H, (1105H) (contents loaded into external data memory location 1105H, (1105H)
NOTE: These instructions supported masked type devices.
6-30
KS86C6308/P6308 (Preliminary Spec)
SAM88RCRI INSTRUCTION
LDCD/LDED Load Memory Decrement
LDCD/LDED Operation: dst,src These instructions used user stacks block transfers data from program data memory register file. address memory location specified working register pair. contents source location loaded into destination location. memory address then decremented. contents source unaffected. LDCD references program memory LDED references external data memory. assembler makes `Irr' even number program memory number data memory. Flags: Format: Bytes Cycles Opcode (Hex) Addr Mode flags affected.
Examples:
Given: 10H, 33H, 12H, program memory location 1033H 0CDH, external data memory location 1033H 0DDH: LDCD R8,@RR6 0CDH (contents program memory location 1033H) loaded into decremented 0CDH, 10H, (RR6 LDED R8,@RR6 0DDH (contents data memory location 1033H) loaded into decremented (RR6 0DDH, 10H,
6-31
SAM88RCRI INSTRUCTION
KS86C6308/P6308 (Preliminary Spec)
LDCI/LDEI Load Memory Increment
LDCI/LDEI Operation: dst,src These instructions used user stacks block transfers data from program data memory register file. address memory location specified working register pair. contents source location loaded into destination location. memory address then incremented automatically. contents source unaffected. LDCI refers program memory LDEI refers external data memory. assembler makes 'Irr' even program memory data memory. Flags: Format: Bytes Cycles Opcode (Hex) Addr Mode flags affected.
Examples:
Given: 10H, 33H, 12H, program memory locations 1033H 0CDH 1034H 0C5H; external data memory locations 1033H 0DDH 1034H 0D5H: LDCI R8,@RR6 0CDH (contents program memory location 1033H) loaded into incremented (RR6 0CDH, 10H, LDEI R8,@RR6 0DDH (contents data memory location 1033H) loaded into incremented (RR6 0DDH, 10H,
6-32
KS86C6308/P6308 (Preliminary Spec)
SAM88RCRI INSTRUCTION
Operation
Operation: Flags: Format: Bytes Cycles Opcode (Hex) action performed when executes this instruction. Typically, more NOPs executed sequence order effect timing delay variable duration. flags affected.
Example:
When instruction encountered program, operation occurs. Instead, there delay instruction execution time.
6-33
SAM88RCRI INSTRUCTION
KS86C6308/P6308 (Preliminary Spec)
Logical
Operation: dst,src source operand logically ORed with destination operand result stored destination. contents source unaffected. operation results being stored whenever either corresponding bits operands "1"; otherwise stored. Flags: Unaffected. result "0"; cleared otherwise. result set; cleared otherwise. Always cleared "0". Unaffected. Unaffected.
Format: Bytes Cycles Opcode (Hex) Addr Mode
Examples:
Given: 15H, 2AH, 01H, register 08H, register 37H, register 8AH: R0,R1 R0,@R2 00H,01H 01H,@00H 00H,#02H 3FH, 37H, 01H, register Register 3FH, register Register 08H, register 0BFH Register
first example, working register contains value register value 2AH, statement R0,R1" logical-ORs register contents stores result (3FH) destination register other examples show logical instruction with various addressing modes formats.
6-34
KS86C6308/P6308 (Preliminary Spec)
SAM88RCRI INSTRUCTION
From Stack
Operation: contents location addressed stack pointer loaded into destination. stack pointer then incremented one. Flags: Format: Bytes Cycles Opcode (Hex) Addr Mode flags affected.
Examples:
Given: Register 01H, register 1BH, (0D9H) 0BBH, stack register 0BBH 55H: @00H Register 55H, 0BCH Register 01H, register 55H, 0BCH
first example, general register contains value 01H. statement "POP 00H" loads contents location 0BBH (55H) into destination register then increments stack pointer one. Register then contains value points location 0BCH.
6-35
SAM88RCRI INSTRUCTION
KS86C6308/P6308 (Preliminary Spec)
PUSH Push Stack
PUSH Operation: PUSH instruction decrements stack pointer value loads contents source (src) into location addressed decremented stack pointer. operation then adds value stack. Flags: Format: Bytes Cycles Opcode (Hex) Addr Mode flags affected.
Examples:
Given: Register 4FH, register 0AAH, 0C0H: PUSH PUSH @40H Register 4FH, stack register 0BFH 4FH, 0BFH Register 4FH, register 0AAH, stack register 0BFH 0AAH, 0BFH
first example, stack pointer contains value 0C0H, general register value 4FH, statement "PUSH 40H" decrements stack pointer from 0BFH. then loads contents register into location 0BFH. Register 0BFH then contains value points location 0BFH.
KS86C6308/P6308 (Preliminary Spec)
SAM88RCRI INSTRUCTION
Reset Carry Flag
Operation: carry flag cleared logic zero, regardless previous value. Flags: Cleared "0".
other flags affected. Format: Bytes Cycles Opcode (Hex)
Example:
Given: "0": instruction clears carry flag logic zero.
6-37
SAM88RCRI INSTRUCTION
KS86C6308/P6308 (Preliminary Spec)
Return
Operation: instruction normally used return previously executing procedure procedure entered CALL instruction. contents location addressed stack pointer popped into program counter. next statement that executed that addressed program counter value. Flags: Format: Bytes Cycles Opcode (Hex) flags affected.
Example:
Given: 0BCH, (SP) 101AH, 1234: 101AH, 0BEH
statement "RET" pops contents stack pointer location 0BCH (10H) into high byte program counter. stack pointer then pops value location 0BDH (1AH) into PC's byte instruction location 101AH executed. stack pointer points memory location 0BEH.
6-38
KS86C6308/P6308 (Preliminary Spec)
SAM88RCRI INSTRUCTION
Rotate Left
Operation: (n), contents destination operand rotated left position. initial value moved zero (LSB) position also replaces carry flag.
Flags:
rotated from most significant position (bit "1". result "0"; cleared otherwise. result set; cleared otherwise. arithmetic overflow occurred, that sign destination changed during rotation; cleared otherwise. Unaffected. Unaffected.
Format: Bytes Cycles Opcode (Hex) Addr Mode
Examples:
Given: Register 0AAH, register register 17H: @01H Register 55H, Register 02H, register 2EH,
first example, general register contains value 0AAH (10101010B), statement 00H" rotates 0AAH value left position, leaving value (01010101B) setting carry overflow flags.
6-39
SAM88RCRI INSTRUCTION
KS86C6308/P6308 (Preliminary Spec)
Rotate Left Through Carry
Operation: (n), contents destination operand with carry flag rotated left position. initial value replaces carry flag (C); initial value carry flag replaces zero.
Flags:
rotated from most significant position (bit "1". result "0"; cleared otherwise. result set; cleared otherwise. arithmetic overflow occurred, that sign destination changed during rotation; cleared otherwise. Unaffected. Unaffected.
Format: Bytes Cycles Opcode (Hex) Addr Mode
Examples:
Given: Register 0AAH, register 02H, register 17H, "0": @01H Register 54H, Register 02H, register 2EH,
first example, general register value 0AAH (10101010B), statement "RLC 00H" rotates 0AAH position left. initial value sets carry flag initial value flag replaces zero register 00H, leaving value (01010101B). register resets carry flag sets overflow flag.
6-40
KS86C6308/P6308 (Preliminary Spec)
SAM88RCRI INSTRUCTION
Rotate Right
Operation: contents destination operand rotated right position. initial value zero (LSB) moved (MSB) also replaces carry flag (C).
Flags:
rotated from least significant position (bit zero) "1". result "0"; cleared otherwise. result set; cleared otherwise. arithmetic overflow occurred, that sign destination changed during rotation; cleared otherwise. Unaffected. Unaffected.
Format: Bytes Cycles Opcode (Hex) Addr Mode
Examples:
Given: Register 31H, register 02H, register 17H: @01H Register 98H, Register 02H, register 8BH,
first example, general register contains value (00110001B), statement 00H" rotates this value position right. initial value zero moved leaving value (10011000B) destination register. initial zero also resets flag sign flag overflow flag also "1".
6-41
SAM88RCRI INSTRUCTION
KS86C6308/P6308 (Preliminary Spec)
Rotate Right Through Carry
Operation: contents destination operand carry flag rotated right position. initial value zero (LSB) replaces carry flag; initial value carry flag replaces (MSB).
Flags:
rotated from least significant position (bit zero) "1". result cleared otherwise. result set; cleared otherwise. arithmetic overflow occurred, that sign destination changed during rotation; cleared otherwise. Unaffected. Unaffected.
Format: Bytes Cycles Opcode (Hex) Addr Mode
Examples:
Given: Register 55H, register 02H, register 17H, "0": @01H Register 2AH, Register 02H, register 0BH,
first example, general register contains value (01010101B), statement "RRC 00H" rotates this value position right. initial value zero ("1") replaces carry flag initial value flag ("1") replaces This leaves value (00101010B) destination register 00H. sign flag overflow flag both cleared "0".
6-42
KS86C6308/P6308 (Preliminary Spec)
SAM88RCRI INSTRUCTION
Subtract With Carry
Operation: dst,src source operand, along with current value carry flag, subtracted from destination operand result stored destination. contents source unaffected. Subtraction performed adding two's-complement source operand destination operand. multiple precision arithmetic, this instruction permits carry ("borrow") from subtraction low-order operands subtracted from subtraction high-order operands. Flags: borrow occurred (src dst); cleared otherwise. result "0"; cleared otherwise. result negative; cleared otherwise. arithmetic overflow occurred, that operands were opposite sign sign result same sign source; cleared otherwise. Always "1". Cleared there carry from most significant low-order four bits result; otherwise, indicating "borrow".
Format: Bytes Cycles Opcode (Hex) Addr Mode
Examples:
Given: 10H, 03H, "1", register 20H, register 03H, register 0AH: R1,R2 R1,@R2 01H,02H 01H,@02H 01H,#8AH 0CH, 05H, 03H, register Register 1CH, register Register 15H,register 03H, register Register 95H;
first example, working register contains value register value 03H, statement "SBC R1,R2" subtracts source value (03H) flag value ("1") from destination (10H) then stores result (0CH) register
6-43
SAM88RCRI INSTRUCTION
KS86C6308/P6308 (Preliminary Spec)
Carry Flag
Operation: carry flag logic one, regardless previous value. Flags: "1". other flags affected. Format: Bytes Cycles Opcode (Hex)
Example:
statement sets carry flag logic one.
6-44
KS86C6308/P6308 (Preliminary Spec)
SAM88RCRI INSTRUCTION
Shift Right Arithmetic
Operation: arithmetic shift-right position performed destination operand. zero (the LSB) replaces carry flag. value (the sign bit) unchanged shifted into position
Flags:
shifted from position (bit zero) "1". result "0"; cleared otherwise. result negative; cleared otherwise. Always cleared "0". Unaffected. Unaffected.
Format: Bytes Cycles Opcode (Hex) Addr Mode
Examples:
Given: Register 9AH, register 03H, register 0BCH, "1": @02H Register 0CD, Register 03H, register 0DEH,
first example, general register contains value (10011010B), statement "SRA 00H" shifts values register right position. zero ("0") clears flag ("1") then shifted into position (bit remains unchanged). This leaves value 0CDH (11001101B) destination register 00H.
6-45
SAM88RCRI INSTRUCTION
KS86C6308/P6308 (Preliminary Spec)
STOP Stop Operation
STOP Operation: STOP instruction stops both clock system clock causes microcontroller enter Stop mode. During Stop mode, contents on-chip registers, peripheral registers, port control data registers retained. Stop mode released external reset operation External interrupt input. reset operation, RESET must held level until required oscillation stabilization interval elapsed. Flags: Format: Bytes Cycles Opcode (Hex) Addr Mode flags affected.
Example:
statement STOP halts microcontroller operations.
KS86C6308/P6308 (Preliminary Spec)
SAM88RCRI INSTRUCTION
Subtract
Operation: dst,src source operand subtracted from destination operand result stored destination. contents source unaffected. Subtraction performed adding two's complement source operand destination operand. Flags: "borrow" occurred; cleared otherwise. result "0"; cleared otherwise. result negative; cleared otherwise. arithmetic overflow occurred, that operands were opposite signs sign result same sign source operand; cleared otherwise. Always "1". Cleared there carry from most significant low-order four bits result; otherwise indicating "borrow".
Format: Bytes Cycles Opcode (Hex) Addr Mode
Examples:
Given: 12H, 03H, register 21H, register 03H, register 0AH: R1,R2 R1,@R2 01H,02H 01H,@02H 01H,#90H 01H,#65H 0FH, 08H, Register 1EH, register Register 17H, register Register 91H; Register 0BCH; "1",
first example, working register contains value register contains value 03H, statement "SUB R1,R2" subtracts source value (03H) from destination value (12H) stores result (0FH) destination register
6-47
SAM88RCRI INSTRUCTION
KS86C6308/P6308 (Preliminary Spec)
Test Complement Under Mask
Operation: dst,src (NOT dst) This instruction tests selected bits destination operand logic value. bits tested specified setting corresponding position source operand (mask). statement complements destination operand, which then ANDed with source mask. zero flag then checked determine result. destination source operands unaffected. Flags: Unaffected. result "0"; cleared otherwise. result set; cleared otherwise. Always cleared "0". Unaffected. Unaffected.
Format: Bytes Cycles Opcode (Hex) Addr Mode
Examples:
Given: 0C7H, 02H, 12H, register 2BH, register 02H, register 23H: R0,R1 R0,@R1 00H,01H 00H,@01H 00H,#34 0C7H, 02H, 0C7H, 02H, register 23H, Register 2BH, register 02H,
Register 2BH, register 02H, register 23H, Register 2BH,
first example, working register contains value 0C7H (11000111B) register value (00000010B), statement "TCM R0,R1" tests destination register value. Because mask value corresponds test bit, flag logic tested determine result operation.
6-48
KS86C6308/P6308 (Preliminary Spec)
SAM88RCRI INSTRUCTION
Test Under Mask
Operation: dst,src This instruction tests selected bits destination operand logic zero value. bits tested specified setting corresponding position source operand (mask), which ANDed with destination operand. zero flag then checked determine result. destination source operands unaffected. Flags: Unaffected. result "0"; cleared otherwise. result set; cleared otherwise. Always reset "0". Unaffected. Unaffected.
Format: Bytes Cycles Opcode (Hex) Addr Mode
Examples:
Given: 0C7H, 02H, 18H, register 2BH, register 02H, register 23H: R0,R1 R0,@R1 00H,01H 00H,@01H 00H,#54H 0C7H, 02H, 0C7H, 02H, register 23H, Register 2BH, register 02H,
Register 2BH, register 02H, register 23H, Register 2BH,
first example, working register contains value 0C7H (11000111B) register value (00000010B), statement "R0,R1" tests destination register value. Because mask value does match test bit, flag cleared logic zero tested determine result operation.
6-49
SAM88RCRI INSTRUCTION
KS86C6308/P6308 (Preliminary Spec)
Logical Exclusive
Operation: dst,src source operand logically exclusive-ORed with destination operand result stored destination. exclusive-OR operation results being stored whenever corresponding bits operands different; otherwise, stored. Flags: Unaffected. result "0"; cleared otherwise. result set; cleared otherwise. Always reset "0". Unaffected. Unaffected.
Format: Bytes Cycles Opcode (Hex) Addr Mode
Examples:
Given: 0C7H, 02H, 18H, register 2BH, register 02H, register 23H: R0,R1 R0,@R1 00H,01H 00H,@01H 00H,#54H 0C5H, 0E4H, 02H, register Register 29H, register Register 08H, register 02H, register Register
first example, working register contains value 0C7H register contains value 02H, statement "XOR R0,R1" logically exclusive-ORs value with value stores result (0C5H) destination register
6-50

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