ML66525 Family User's Manual CMOS 16-bit microcontroller Iss
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FEUL66525-02
ML66525 Family User's Manual
CMOS 16-bit microcontroller
Issue Date: July 2002
Preface
This user's manual describes hardware Oki-original CMOS 16-bit microcontrollers ML66525 family. addition this manual, also provides following manuals which should read with regard ML66525 family. nX-8/500S Core Instruction Manual nX-8/500S core instruction Addressing modes CC665S User's Manual Optimized compiler CC665S operation C-language specifications CC665S CL665S User's Manual Compiler loader CL665S operation RTL665S Time Library Reference time library explanation MAC66K Assembler Package User's Manual Package overview RAS66K (relocatable assembler) operation RAS66K assembly language explanation RL66K (linker) operation LIB66K (librarian) operation OH66K (object converter) operation Macroprocessor User's Manual operation Macro language Ultra-66K/E502 User's Manual Ultra-66K (Emulator) explanation PathFinder-66K (Debugger) explanation PW66K Flash Writer System User's Manual PW66K Flash Writer System operation This document subject change without notice.
Notation Classification Numeric value Unit Notation xxH, xxhex Word, byte, nibble, mega-, kilo-, kilo-, milli-, micro-, nano-, second, Description Represents hexadecimal number Represents binary number word bits byte nibbles bits nibble bits 1024 1000 10-3 10-6 10-9 second kilobyte 1024 bytes megabyte bytes 1,048,576 bytes signal level high side voltage; indicates voltage level described electrical characteristics. signal level side voltage; indicates voltage level described electrical characteristics. Operation code trap. Occurs when empty area that been assigned instruction fetched, when instruction code combination that does contain instruction addressed.
Terminology
level
level
Opcode trap
Register description
Register name Invalid Fixed name number
SCNC0
SNEX0
ADRUN0
ADCON0L reset
ADSNM02 ADSNM01 ASSNM00
Address: 009C access:
Initial value when reset
Read/Write attribute
Invalid Fixed
Indicates that does exist. Writing into this invalid. When writing, always write specified value. read, specified value will read. Values fixed bits specified "1". Read/write attribute indicates that reading possible indicates that writing possible.
Contents
Chapter
Overview
Overview. Features Block Diagram Configuration (Top View) Descriptions 1.5.1 Description Each 1.5.2 Configuration. 1-11 1.5.3 Connections Unused Pins 1-12 Basic Operational Timing 1-13
Chapter
Architecture
Overview. Memory Space 2.2.1 Memory Space Expansion 2.2.2 Program Memory Space. Accessing program memory space. Vector table area VCAL table area ACAL area 2.2.3 2.2.4 Data Memory Space. Special function register (SFR) area 2-11 Reserved area 2-11 Internal area 2-11 Fixed page (FIX) area 2-11 Local register setting area 2-13 External data memory area 2-13 Common area 2-14 EXPANDED area 2-14 Data Memory Access 2-15 Byte operations 2-15 Word operations. 2-15
Registers. 2-16 2.3.1 Arithmetic Register (ACC) 2-16 2.3.2 Control Registers 2-17 Contents
2.3.3 2.3.4 2.3.5
Program status word (PSW). 2-17 Program counter (PC) 2-21 Local register base (LRB) 2-21 System stack pointer (SSP) 2-22 Pointing Register (PR) 2-23 Local Registers ER3) 2-24 Segment Registers. 2-25 Code segment register (CSR). 2-25 Table segment register (TSR) 2-25 Data segment register (DSR) 2-26
Addressing Modes. 2-26 2.4.1 Addressing 2-26 Register addressing 2-27 Page addressing. 2-29 Direct data addressing. 2-32 Pointing register indirect addressing. 2-33 Special area addressing 2-40 2.4.2 Addressing 2-42 Immediate addressing 2-42 Table data addressing. 2-42 Program code addressing 2-44 window addressing. 2-45
Chapter
Control Functions
Overview. Standby Functions. 3.2.1 Standby Function Registers 3.2.2 Description Standby Function Registers. Stop code acceptor (STPACP) Standby control register (SBYCON) 3.2.3 3.2.4 Examples Standby Function Register Settings HALT mode setting STOP mode setting Operation Each Standby Mode HALT mode STOP mode.
Reset Function. 3-10 3.3.1 Reset Operation. 3-11 Contents
Chapter
Memory Control Functions
Overview. Memory Control Function Registers. Window Function. READY Function. 4.4.1 Ready Control Register (ROMRDY). 4.4.2 Ready Control Register (RAMRDY). EXPANDED Ready Control Register (XPDRDY).
Chapter
Port Functions
Overview. Hardware Configuration Each Port. 5.2.1 Type (P0). 5.2.2 Type (P1, P3_1, 5.2.3 Type (P3_3). 5.2.4 Type (P6, P10_0 P10_2, P10_4, P10_5, P15, P20, P21) 5.2.5 Type (P12) 5.2.6 Type (P3_2) 5.2.7 Type (P9_0). 5.2.8 Type (P10_3). 5-10 5.2.9 Type (P13) 5-11 Port Registers 5-12 5.3.1 Port Data Registers 21). 5-14 5.3.2 Port Mode Registers (PnIO 21). 5-14 5.3.3 Port Secondary Function Control Registers (PnSF 21). 5-15 Port (P0) 5-16 Port (P1) 5-18 Port (P2) 5-20 Port (P3) 5-22 Port (P4) 5-24 Port (P6) 5-26 5.10 Port (P7) 5-28 5.11 Port (P8) 5-30 5.12 Port (P9) 5-32 5.13 Port (P10) 5-34 5.14 Port (P12) 5-37
Contents
5.15 5.16 5.17 5.18
Port (P13) 5-38 Port (P15) 5-39 Port (P20) 5-41 Port (P21) 5-43
Chapter
Clock Oscillation Circuit
Overview. Clock Oscillation Circuit Configuration Clock Oscillation Circuit Registers. Oscillation Circuit Oscillation Circuit. Circuit
Chapter
Time Base Counter (TBC)
Overview. Time Base Counter (TBC) Configuration Time Base Counter Registers. Counter. 7.4.1 Description Counter Registers clock dividing counter (TBCKDV upper bits) clock divider register (TBCKDVR) 7.4.2 Example Counter-related Register Settings Time Base Counter (TBC) Operation
Chapter
General-Purpose 8/16-Bit Timers
Overview. General-Purpose 8-Bit/16-Bit Timer Configurations. General-Purpose 8-Bit/16-Bit Timer Registers Timer 8.4.1 Timer Configuration 8.4.2 Description Timer Registers General-purpose 16-bit timer counter (TM0C) General-purpose 16-bit timer register (TM0R) General-purpose 16-bit timer control register (TM0CON) 8.4.3 Example Timer 0-related Register Settings 8.4.4 Timer Operation. 8.4.5 Timer Interrupt. Timer Contents
8.5.1 8.5.2
Timer Configuration Description Timer Registers 8-10 General-purpose 8-bit timer counter (TM3C) 8-10 General-purpose 8-bit timer register (TM3R) 8-10 General-purpose 8-bit timer control register (TM3CON) 8-10
8.5.3 Example Timer 3-related Register Settings 8-12 8.5.4 Timer Operation. 8-13 8.5.5 Timer Interrupt. 8-14 Timer 8-15 8.6.1 Timer Configuration 8-15 8.6.2 Description Timer Registers 8-16 General-purpose 8-bit timer counter (TM4C) 8-16 General-purpose 8-bit timer register (TM4R) 8-16 General-purpose 8-bit timer control register (TM4CON) 8-16 8.6.3 Example Timer 4-related Register Settings 8-18 8.6.4 Timer Operation. 8-19 8.6.5 Timer Interrupt. 8-20 Timer 8-21 8.7.1 Timer Configuration 8-21 8.7.2 Description Timer Registers 8-22 General-purpose 8-bit timer counter (TM5C) 8-22 General-purpose 8-bit timer register (TM5R) 8-22 General-purpose 8-bit timer control register (TM5CON) 8-22 8.7.3 Example Timer 5-related Register Settings 8-24 8.7.4 Timer Operation. 8-25 8.7.5 Timer Interrupt. 8-26 Timer 8-27 8.8.1 Timer Configuration 8-27 8.8.2 Description Timer Registers 8-28 General-purpose 8-bit timer counter (TM6C) 8-28 General-purpose 8-bit timer register (TM6R) 8-28 General-purpose 8-bit timer control register (TM6CON) 8-29 8.8.3 8.8.4 Example Timer 6-related Register Settings 8-31 Auto-reload timer mode settings. 8-31 Watchdog timer (WDT) mode settings 8-31 Timer Operation. 8-32 Auto-reload timer mode 8-32 Watchdog timer (WDT) mode 8-32 Contents
8.8.5 Timer Interrupt (During Auto-Reload Timer Mode). 8-35 Timer 8-36 8.9.1 Timer Configuration 8-36 8.9.2 Description Timer Registers 8-37 General-purpose 8-bit timer counter (TM9C) 8-37 General-purpose 8-bit timer register (TM9R) 8-37 General-purpose 8-bit timer control register (TM9CON) 8-37 8.9.3 Example Timer 9-related Register Settings 8-39 8.9.4 Timer Operation. 8-40 8.9.5 Timer Interrupt. 8-41 8.10 Timer 8-42 8.10.1 Timer Configuration 8-42 8.10.2 Description Timer Registers 8-43 General-purpose 16-bit timer counter (TM7C) 8-43 General-purpose 16-bit timer register (TM7R) 8-43 General-purpose 16-bit timer control register (TM7CON) 8-43 8.10.3 8.10.4 8.10.5 Example Timer 7-related Register Settings 8-45 Timer Operation. 8-46 Timer Interrupt. 8-47
Chapter
Real-Time Counter (RTC)
Overview. Real-Time Counter Configuration Real-Time Counter Control Register (RTCCON). Example Real-Time Counter Register Settings Real-Time Counter Operation. Real-Time Counter Interrupt.
Chapter
Function
10.1 Overview. 10-1 10.2 Configuration. 10-1 10.3 Register. 10-2 10.3.1 Description Registers 10-3 counters (PWC0, PWC1). 10-3 cycle registers (PWCY0, PWCY1). 10-3 registers (PWR0 PWR1) 10-4 control register (PWCON0). 10-4 control register (PWCON1). 10-6 Contents
10.3.2 Example PWM-related Register Settings 10-7 8-bit settings 10-7 16-bit settings 10-8 10.4 Operation 10-9 10.4.1 Operation During 8-Bit Mode 10-9 10.4.2 Operation During 16-Bit Mode 10-10 10.4.3 Operation During High-Speed Mode. 10-12 10.5 Interrupts. 10-14
Chapter
Serial Port Functions
11.1 Overview. 11-1 11.2 Serial Port Configuration 11-1 11.3 Serial Port Registers. 11-2 11.4 SIO6 11-3 11.4.1 SIO6 Configuration. 11-3 11.4.2 Description SIO6 Registers 11-4 SIO6 transmit control register (ST6CON) 11-4 SIO6 receive control register (SR6CON). 11-6 SIO6 status register (S6STAT) 11-8 SIO6 transmit-receive buffer register (S6BUF) 11-10 SIO6 transmit shift register, receive shift register. 11-10 11.4.3 Example SIO6-related Register Settings 11-11 11.4.3.1 UART Mode Settings. 11-11 Transmit settings 11-11 Receive settings 11-11 11.4.3.2 Synchronous Mode Settings. 11-12 Transmit settings 11-12 Receive settings 11-13 11.4.3.3 Baud Rate Generator (Timer Settings. 11-13 11.4.4 SIO6 Interrupt 11-14 11.5 SIO1 11-15 11.5.1 SIO1 Configuration. 11-15 11.5.2 Description SIO1 Registers 11-16 SIO1 transmit control register (ST1CON) 11-16 SIO1 receive control register (SR1CON). 11-18 SIO1 status register (S1STAT) 11-20 SIO1 transmit-receive buffer register (S1BUF) 11-22 SIO1 transmit shift register, receive shift register. 11-22 Contents
11.5.3 Example SIO1-related Register Settings 11-23 11.5.3.1 UART Mode Settings. 11-23 Transmit settings 11-23 Receive settings 11-23 11.5.3.2 Synchronous Mode Settings. 11-24 Transmit settings 11-24 Receive settings 11-25 11.5.3.3 Baud Rate Generator (Timer Settings. 11-25 11.5.4 SIO1 Interrupt 11-26 11.6 SIO6, SIO1 Operation. 11-27 11.6.1 Transmit Operation 11-27 11.6.2 Receive Operation. 11-35 11.7 SIO3 11-40 11.7.1 SIO3 Configuration. 11-40 11.7.2 Description SIO3 Registers 11-41 SIO3 control register (SIO3CON) 11-41 SIO3 register (SIO3R) 11-43 11.7.3 Example SIO3-related Register Settings 11-43 Transmit-receive settings 11-43 Baud rate generator (Timer settings. 11-44
11.7.4 SIO3 Operation 11-44 11.7.5 SIO3 Interrupt 11-46 11.8 SIO4 11-47 11.8.1 SIO4 Configuration. 11-47 11.8.2 Description SIO4 Registers 11-48 SIO4 control register (SIO4CON) 11-48 FIFO control register (FIFOCON) 11-50 Serial input FIFO data register (SIN4). 11-52 Serial output FIFO data register (SOUT4). 11-52 Internal Control Register (P5IO). 11-52 11.8.3 Example SIO4-related Register Settings 11-53 Master mode settings 11-53 Slave mode settings. 11-54 11.8.4 11.8.5 SIO4 Interrupt 11-55 SIO4 Operation 11-56
Contents
Chapter
Converter Functions
12.1 Overview. 12-1 12.2 Converter Configuration. 12-1 12.3 Converter Registers 12-2 12.3.1 Description Converter Registers 12-3 control register (ADCON0H) 12-3 interrupt control register (ADINT0). 12-5 result registers (ADR00 ADR03). 12-6 12.3.2 Example Converter-related Register Settings 12-6 12.4 Converter Operation. 12-7 12.5 Notes Regarding Usage Converter. 12-7 12.5.1 Considerations When Setting Conversion Time 12-7 12.5.2 Noise-Suppression Measures 12-9 12.6 Converter Interrupt. 12-10
Chapter
13.1 13.2 13.3 13.4 13.5
Peripheral Functions
Overview. 13-1 External XTCLK Input Control Function 13-1 Peripheral Control Register (PRPHCON). 13-2 Internal Control Register (P5IO). 13-3 Three Separate Power Supplies. 13-5
Chapter
External Interrupt Functions
14.1 Overview. 14-1 14.2 External Interrupt Registers 14-1 14.2.1 Description External Interrupt Registers 14-2 External interrupt control register (EXI0CON). 14-2 External interrupt control register (EXI1CON). 14-3 External interrupt control register (EXI2CON). 14-4 External interrupt control register (EX8ICON). 14-5 14.2.2 Example External Interrupt-related Register Settings. 14-6 14.3 EXINT0 EXINT9 Interrupts 14-7
Chapter
Interrupt Processing Functions
15.1 Overview. 15-1 15.2 Interrupt Function Registers. 15-2 15.3 Description Interrupt Processing. 15-3 Contents
15.3.1 15.3.2
Non-Maskable Interrupt (NMI). 15-3 Maskable Interrupts. 15-5 Interrupt request registers (IRQ0 IRQ4) 15-5 Interrupt enable registers (IE0 IE4). 15-5 Master interrupt enable flag (MIE) 15-5 Master interrupt priority flag (MIPF). 15-5 Interrupt priority control registers (IP0, IP9). 15-6
15.3.3 Priority Control Maskable Interrupts 15-10 15.4 IRQ, Register Configurations Each Interrupt 15-12 15.4.1 Interrupt Request Registers (IRQ0 IRQ4). 15-12 Interrupt request register (IRQ0). 15-12 Interrupt request register (IRQ1). 15-13 Interrupt request register (IRQ2). 15-14 Interrupt request register (IRQ3). 15-15 Interrupt request register (IRQ4). 15-16 15.4.2 15.4.3 Interrupt Enable Registers (IE0 IE4). 15-17 Interrupt enable register (IE0). 15-17 Interrupt enable register (IE1). 15-18 Interrupt enable register (IE2). 15-19 Interrupt enable register (IE3). 15-20 Interrupt enable register (IE4). 15-21 Interrupt Priority Control Registers (IP0, IP9) 15-22 Interrupt priority control register (IP0) 15-22 Interrupt priority control register (IP2) 15-23 Interrupt priority control register (IP3) 15-24 Interrupt priority control register (IP4) 15-25 Interrupt priority control register (IP5) 15-26 Interrupt priority control register (IP6) 15-27 Interrupt priority control register (IP7) 15-28 Interrupt priority control register (IP8) 15-29 Interrupt priority control register (IP9) 15-30
Chapter
Port Functions
16.1 Overview. 16-1 16.2 Port Operation 16-1 16.2.1 Port Operation When Accessing Program Memory. 16-1 16.2.2 Port Operation When Accessing Data Memory 16-2 16.3 External Memory Access 16-3 Contents
16.3.1 External Program Memory Access 16-3 16.3.2 External Data Memory Access. 16-4 16.4 External Memory Access Timing 16-5 16.4.1 External Program Memory Access Timing. 16-5 16.4.2 External Data Memory Access Timing. 16-6 16.4.3 P3_2/RDn Pin. 16-8 16.5 Notes Regarding Usage Port Function. 16-9 16.5.1 Dummy Read Strobe Output. 16-9 16.5.2 External Access Timing. 16-11
Chapter
Control Function
17.1 Overview. 17-1 17.2 Features 17-1 17.3 Functional Descriptions 17-2 17.3.1 Interface. 17-2 17.3.2 Transfer Modes 17-2 17.3.3 Endpoints FIFOs 17-3 17.3.4 Operation Control Transfer. 17-4 17.3.5 Data Packet Transmission Reception Procedure During Bulk Transfer Interrupt Transfer Modes. 17-5 17.3.6 Data Packet Transmission Reception Procedure During Isochronous Transfer Mode. 17-6 17.3.7 Packets Packet Sizes. 17-7 17.3.8 Interrupts. 17-8 17.3.9 Internal (Direct Memory Access) 17-15 17.3.10 Power-down 17-15 17.3.11 Operation 2-Layer Structure FIFO During Bulk Transfer 17-16 17.3.12 Error Processing Retry Operation 17-18 17.3.13 Pull-up Control 17-19 17.4 Registers Control Functions. 17-20 17.4.1 Description Registers Control Functions. 17-22 transmit FIFO (EP0TXFIFO) 17-22 receive FIFO (EP0RXFIFO) 17-22 FIFO (EP1FIFO) 17-23 FIFO (EP2FIFO) 17-23 FIFO (EP3FIFO) 17-24 FIFO (EP4FIFO) 17-24 FIFO (EP5FIFO) 17-25 Contents
(10) (11) (12) (13) (14) (15) (16) (17) (18) (19) (20) (21) (22) (23) (24) (25) (26) (27) (28) (29) (30) (31) (32) (33) (34) (35) (36) (37) (38) (39) (40) (41) (42) (43) (44) (45)
bmRequestType setup register (bmRequestType) 17-26 bRequest setup register (bRequest). 17-26 wValueLSB setup register (wValueLSB) 17-27 wValueMSB setup register (wValueMSB) 17-27 wIndexLSB setup register (wIndexLSB) 17-28 wIndexMSB setup register (wIndexMSB). 17-28 wLengthLSB setup register (wLengthLSB). 17-29 wLengthMSB setup register (wLengthMSB) 17-29 DMA0, control registers (DMA0CON/DMA1CON). 17-30 DMA0 interval register (DMA0INTVL) 17-31 DMA1 interval register (DMA1INTVL) 17-31 Device address register (DVCADR) 17-32 Interrupt status register (INTSTAT1) 17-33 Interrupt status register (INTSTAT2) 17-34 Interrupt enable register (INTENBL1). 17-35 Interrupt enable register (INTENBL2). 17-36 Frame number register (FRAMELSB) 17-37 Frame number register (FRAMEMSB) 17-37 System control register (SYSCON) 17-38 Polarity selection register (POLSEL). 17-39 configuration register (EP0CONF). 17-40 EP1, configuration registers (EP1, 3CONF) 17-41 EP4, configuration registers (EP4, 5CONF) 17-42 control register (EP0CONT). 17-43 EP1, control registers (EP1, 5CONT) 17-44 payload register (EP0PLD). 17-45 EP1, payload registers (EP1, 2PLD) 17-45 payload register (EP3PLD). 17-46 EP4, payload registers (EP4, 5PLD) 17-47 receive byte count register (EP0RXCNT) 17-48 EP1, receive byte count registers (EP1, 2RXCNT). 17-48 receive byte count register (EP3RXCNT) 17-49 EP4, receive byte count registers (EP4, 5RXCNT). 17-49 status register (EP0STAT). 17-50 EP1, status registers (EP1, 5STAT) 17-53 status register (EP3STAT). 17-54 Packet error register (PKTERR) 17-55 test register (OSCTEST) 17-56 Contents
17.5 Transceiver 17-57 17.5.1 Overview Transceiver Circuit 17-57 17.5.2 Method Notes Connecting Cable Terminal (D+/D-). 17-57 Length wiring between connector terminal (D+/D-). 17-57 External series resistor 17-57 Pull-up resistor line (high-speed data transfer) 17-57 Procedure required cable been connected. 17-58 17.6 Notes Using 17-59 17.6.1 Detecting Connected/Disconnected State Cable 17-59 17.6.2 Examples Control Registers Control. 17-60 Case Upon power-on reset 17-60 Case time communication started 17-61 Case time communication terminated. 17-62
Chapter
Media Control Function
18.1 Overview. 18-1 18.2 Registers Media Control Functions 18-1 18.2.1 Description Registers Media Control Functions. 18-3 Media sequencer control register (MSCTRL). 18-3 Media sequencer wait register (MSWAIT). 18-7 Media sequencer status register (MSSTS) 18-8 Media sequencer error status register (MSERR). 18-9 Media command register (MMCMD) 18-10 Media address register (MMADR) 18-10 Media data register (MMDATA) 18-11 Media selector register (MMSEL) 18-11 ECC1 line parity register (ECC1LP). 18-12 (10) ECC2 line parity register (ECC2LP). 18-12 (11) ECC1 column parity register (ECC1CP) 18-13 (12) ECC2 column parity register (ECC2CP) 18-13 (13) ECC1 error pointer register (ECC1ERR). 18-14 (14) ECC2 error pointer register (ECC2ERR). 18-14 (15) Redundancy part reserved data register (HREV1) 18-15 (16) Redundancy part reserved data register (HREV2) 18-15 (17) Redundancy part data/block status register (HSTATS) 18-16 (18) Redundancy part block address register (HBADR1) 18-17 (19) Redundancy part ECC2-High register (HECC2H) 18-18 (20) Redundancy part ECC2-Low/block address register (HECC2LA). 18-19 Contents
(21) (22)
Redundancy part ECC1-High/block address register (HECC1HA). 18-20 Redundancy part ECC1-Low register (HECC1L). 18-21
18.3 Wait Function. 18-22 18.3.1 Wait Functions during Write Operations 18-22 18.3.2 Wait Functions during Read Operations 18-24
Chapter
Internal Control Function
19.1 Overview. 19-1 19.2 Registers Internal Control Function 19-2 19.2.1 Description Registers Internal Control Function. 19-3 Current address registers (CH0ADDRESS/CH1ADDRESS) 19-3 Current word count registers (CH0WDCNT/CH1WDCNT) 19-4 Mode register (MODE). 19-5 Mask registers (CH0MSK/CH1MSK) 19-6 Interrupt status register (INTSTAT) 19-7 Interrupt enable register (INTENBL). 19-8 DREQ monitor register (DREQMON) 19-9 Option register (OPTION) 19-10 Packet size registers (CH0PKTSZ/CH1PKTSZ) 19-11 (10) Maximum packet size registers (CH0MXPKTSZ/CH1MXPKTSZ) 19-12 (11) First byte detection count registers (CH0RXCNT/CH1RXCNT). 19-13 (12) bank register (UBANK) 19-14 (13) Media bank register (MBANK) 19-15 19.3 Example Short Packet Reception Control Internal 19-16
Chapter
Flash Memory
20.1 Overview. 20-1 20.2 Features 20-1 20.3 Programming Modes. 20-2 20.4 Parallel Mode 20-3 20.4.1 Overview Parallel Mode 20-3 20.4.2 PROM Writer Setting. 20-3 20.4.3 Flash Memory Programming Conversion Adapter 20-3 20.5 Serial Mode 20-4 20.5.1 Overview Serial Mode 20-4 20.5.2 Serial Mode Settings 20-4 Pins used serial mode. 20-4 Serial mode connection circuit. 20-5 Contents
Serial mode programming method. 20-6 Setting security function 20-6
20.6 User Mode. 20-7 20.6.1 Overview User Mode. 20-7 20.6.2 User Mode Programming Registers 20-7 20.6.3 Description User Mode Registers 20-8 Flash memory address register (FLAADRS) 20-8 Flash memory acceptor (FLAACP) 20-9 Flash memory control register (FLACON). 20-9 20.6.4 User Mode Programming Example. 20-12 User mode programming flowchart example. 20-12 User mode programming program example. 20-13 Timer counter count start value. 20-14
20.6.5 Notes User Mode 20-15 20.7 Notes Program. 20-15 Programming flash memory immediately after power-on 20-15 Supply voltage sense reset function 20-15
Chapter
Electrical Characteristics (Preliminary)
21.1 Absolute Maximum Ratings 21-1 21.2 Recommended Operating Conditions 21-1 21.3 Allowable Output Current Values. 21-2 21.4 Internal Flash Programming Conditions 21-2 21.5 Characteristics 21-3 21.5.1 Characteristics (Except port). 21-3 21.5.2 Characteristics (USB port). 21-5 21.6 Characteristics 21-6 21.6.1 Characteristics (Except port). 21-6 21.7 Converter Characteristics 21-12
Chapter
Special Function Registers (SFRs)
22.1 Overview. 22-1 22.2 List SFRs 22-1
Chapter Chapter
Package Dimensions 23-1 Revision History.R-1
Contents
Chapter
Overview
ML66525 Family User's Manual Chapter Overview
Overview
Overview ML66525 family devices high-performance 16-bit CMOS microcontrollers that utilize nX-8/500S, Oki's proprietary core.
Data from personal computer with connector automatically, quickly written read from NAND type Flash Memory NAND Flash Memory I/F. ML66525 family devices support clock gear functions, sub-clock HALT/STOP mode, which suitable power applications. ML66525 family devices provided with interfaces external devices such 4-channel multi-functional serial interface with internal 32-byte FIFO high-speed interface that separate address data buses does require external address latches. wide variety internal multi-functional timers enable various timing controls such periodic timed measurements. With 16-bit core that enables high-speed arithmetic computations variety processing functions, these general-purpose microcontrollers optimally suited Digital Audio devices such players, voice recorders, handy games, peripheral control systems control devices that connected store data into memory). ML66525 family devices also include flash version device (ML66Q525B) that programmable with single power supply (2.4 [Note] ML66525A ML66Q525A supplied stock lasts.
Features ML66525 family following features.
Instruction with wide variety instructions Dual instruction 16-bit arithmetic instructions Multiply divide instructions (High speed multiplier provided) manipulate instructions logical instructions table reference instructions Variety addressing modes Register addressing Page addressing Pointing register indirect addressing Stack addressing Immediate addressing Minimum instruction cycles (2.4 32.768 (2.4
ML66525 Family User's Manual Chapter Overview
Clock oscillation circuits Main clock: (max.) crystal oscillator ceramic resonator oscillator circuit Subclock 32.768 crystal oscillator circuit
Program memory (ROM) Internal External case activated)
Data memory (RAM) Internal external 1016
ports Input ports Output port ports ports (secondary function analog input port) port ports max. (with programmable pull-up resistors)
Timers General-purpose auto reload timer bits bits 8-bit auto reload timer that also functions serial communication baud rate generator 8-bit auto reload timer that also functions watchdog timer
8-bit (can also used 16-bit PWM)
8-bit serial ports UART/Synchronous Synchronous Synchronous with 32-byte FIFO
converter 10-bit resolution, channels
controller Conforms High speed data transfer Mbps (Full-Speed) endpoints Controller Bulk/interrupt Isochronous/bulk/interrupt
Media controller NAND Flash memory circuit
ML66525 Family User's Manual Chapter Overview Interrupts Non-maskable Maskable: external vectors), internal vectors) Three levels priority Window function Standby modes HALT mode STOP mode Separate power supplies VDD_CORE: VDD_IO: VBUS: VREF: Core power supply (excluding controller section) power supply (excluding following pins: PUCTL) power supply (Vbus input pin) Power supply 10-bit converter analog section; analog reference voltage
ML66525 Family User's Manual Chapter Overview Package 100-pin plastic TQFP (TQFP100-P-1414-0.50-K) 144-pin plastic LFBGA (P-LFBGA144-1111-0.80) (For external dimensions, refer Chapter Table ML66525 Family Products
Parameter Operating temperature Power supply voltage/maximum operating frequency Minimum instruction execution time Internal size (max. external) Internal size (max. external) ports ML66525B +70°C nsec µsec 32.768 pins (with programmable pull-up resistors), input-only pins, output-only 8-bit auto-reload timer 16-bit auto-reload timer 8-bit auto-reload timer (also functions serial communication baud rate generator) 8-bit auto-reload timer (also functions watchdog timer) Watch timer 8-bit (16-bit 1ch) Synchronous (with 32-byte FIFO) Synchronous (Shift register type) Synchronous/UART 10-bit Non-maskable 1ch, Maskable Compliant with spec. version High-speed transfer Mbps Internal Internal transceiver Vbus detection circuit (connection host detect/non-detect) power available bytes, bytes), control transfer bytes bulk/interrupt transfer bytes bulk/interrupt transfer bytes), interrupt transfer bytes bulk/isochronous/interrupt transfer bytes bulk/isochronous/interrupt transfer Automatic, high-speed data transfer circuit Automatic, high-speed 512-byte data transfer levels External interface (separate address data buses) Dual clocks function Clock gear function Different powers available USB, core, port ML66Q525B
Timers
Serial port converter External interrupts
control
Media control Interrupt priority Others
Flash version
ML66525 Family User's Manual Chapter Overview
Block Diagram
EXINT0 EXINT4 EXINT8/9 Interrupt Core System Control 16-bit Timer0 RXD1 TXD1 RXC1 TXC1 RESn OSC0 OSC1n XT1n
SIO1 (UART/SYNC)
Control Registers
8-bit Timer4/BRG RXD6 TXD6 RXC6 TXC6 SIO6 (UART/SYNC)
Control
8-bit Timer3/BRG SIOI3 SIOO3 SIOCK3 SIO3 (SYNC) 8-bit Timer5/BRG SIOI4 SIOO4 SIOCK4 SIO4 (32-byte FIFO SYNC) 8-bit Timer6/WDT 16-bit Timer7 PWMOUT0 PWMOUT1 8-bit PWM0 8-bit PWM1 8-bit Timer9 VREF AGND 10-bit Converter Memory Control Pointing Registers Local Registers Instruction Decoder
Kbytes
Also functions transfer
Kbytes
Port Control
PSENn bits) bits) bits) bits) bits) bits) bits) bits) bit) bits) bits) bits) bits) bits) bits)
transfer
FLASH media transfer
Port Control
VBUS PUCTL D+/D-
(Compliant with 1.1)
(USB Transfer RAM)
Transfer (512 bytes banks)
Flash media control (Media Transfer RAM)
FRDn FWRn FCLE FALE
Figure ML66525 Family Block Diagram
ML66525 Family User's Manual Chapter Overview
Configuration (Top View)
PUCTL P20_7/FD7 P20_6/FD6 P20_5/FD5 P20_4/FD4 P20_3/FD3 P20_2/FD2 P20_1/FD1 P20_0/FD0 VDD_IO P21_4/FRB P21_3/FALE P21_2/FCLE P21_1/FWRn P21_0/FRDn AGND AI3/P12_3 AI2/P12_2 AI1/P12_1 AI0/P12_0 VREF
VBUS P9_0/VBUSIN P6_0/EXINT0 P6_1/EXINT1 P6_2/EXINT2 P6_3/EXINT3 P7_6/PWM0OUT P7_7/PWM1OUT FLAMOD P8_0/RXD1 P8_1/TXD1 P8_2/RXC1 P8_3/TXC1 VDD_IO P10_0/SIOCK3 P10_1/SIOI3 P10_2/SIOO3 P10_3/SIOCK4 P10_4/SIOO4 P10_5/SIOI4 P15_0/RXD6 P15_1/TXD6 P15_2/RXC6 P15_3/TXC6
VDD_CORE P2_3/A19 P2_2/A18 P2_1/A17 P2_0/A16 VP1_7/A15 P1_6/A14 P1_5/A13 P1_4/A12 P1_3/A11 P1_2/A10 P1_1/A9 P1_0/A8 P4_7/A7 P4_6/A6 P4_5/A5 P4_4/A4 P4_3/A3 P4_2/A2 P4_1/A1 P4_0/A0 VDD_CORE VDD_IO
symbol with suffixed indicates active pin.
Figure ML66525 Family Configuration (TQFP)
external dimensions package, refer Chapter "Package Dimensions". connections unused pins, refer Section 1.5.3.
VDD_CORE RESn VDD_IO XT1n TEST OSC0 OSC1n VDD_IO P13_0/EXINT8 P13_1/EXINT9 P0_0/D0 P0_1/D1 P0_2/D2 P0_3/D3 P0_4/D4 P0_5/D5 P0_6/D6 P0_7/D7 P3_1/PSENn P3_2/RDn P3_3/WRn
100-Pin Plastic TQFP
ML66525 Family User's Manual Chapter Overview
VDD_IO
P3_2/
P0_5/ P0_2/ P0_6/
P0_3/ P0_1/ P0_0/
P13_1/ OSC0 EXINT9
VDD_ CORE
P4_0/ P4_2/ P4_4/ P4_6/ P1_5/
P3_3/ P3_1/ P0_4/ PSENn VDD_ P0_7/ CORE P4_1/ P4_3/ P1_0/ P1_2/ P1_3/ P1_7/
VDD_IO OSC1n TEST P13_0/ EXINT8
XT1n
VDD_IO
P15_2/ P15_3/ RXC6 TXC6 P15_0/ P15_1/ RXD6 TXD6
RESn
P4_5/ P4_7/ P1_1/ P1_4/ P1_6/ P2_0/ P2_2/
P10_4/ P10_2/ P10_5/ SIOO4 SIOO3 SIOI4 P10_3/ SIOCK4 VDD_IO P8_3/ TXC1 P8_1/ TXD1
P10_0/ P10_1/ SIOCK3 SIOI3 P8_2/ RXC1 P8_0/ RXD1
P7_6/ P7_7/ PWM0 FLAMOD PWM1 P6_2/ EXINT2 P6_0/ EXINT0 P6_3/ EXINT3 P6_1/ EXINT1 P9_0/ VBUSIN
P2_1/ P2_3/
VREF
P20_1/ P20_7/ P12_1/ P12_3/ P21_4/ VDD_IO AGND P21_1/ P21_3/ FWRn FALE
P20_2/ P20_3/ P20_5/ PUCTL
VDD_ P12_0/ P12_2/ P21_0/ P21_2/ P20_0/ P20_4/ P20_6/ CORE FRDn FCLE
VBUS
symbol with suffixed indicates active pin. [Note] Don't connect pins with others. Figure ML66525 Family Configuration (LFBGA)
external dimensions package, refer Chapter "Package Dimensions". connections unused pins, refer Section 1.5.3.
ML66525 Family User's Manual Chapter Overview
Descriptions
Table lists function each ML66525 family. column, indicates input pin, indicates output pin, "I/O" indicates pin. symbol with suffixed indicates active pin. Table Descriptions (1/3)
1.5.1 Description Each
Classification Port
Symbol P0_0/D0 P0_7/D7 P1_0/A8 P1_7/A15 P2_0/A16 P2_3/A19 P3_1/PSENn
Type
I/O* P3_2/RDn P3_3/WRn P4_0/A0 P4_7/A7 P6_0/EXINT0 P6_1/EXINT1 P6_2/EXINT2 P6_3/EXINT3 P7_6/PWM0OUT P7_7/PWM1OUT
Primary function 8-bit port Pull-up resistors specified each bit. 8-bit port Pull-up resistors specified each bit. 4-bit port Pull-up resistors specified each bit. 1-bit port Pull-up resistors specified each bit. 1-bit output port
Function Type
Secondary function External memory access data port External memory access address output port External memory access address output port External program memory access read strobe output External data memory access read strobe output External data memory access write strobe output External memory access address output port External interrupt input External interrupt input External interrupt input External interrupt input PWM0 output PWM1 output SIO1 receive data input SIO1 transmit data output SIO1 receive clock SIO1 transmit clock
1-bit port Pull-up resistors specified each bit. 8-bit port Pull-up resistors specified each bit. 8-bit port Pull-up resistors specified each bit. 2-bit port Pull-up resistors specified each bit.
P8_0/RXD1 4-bit port Pull-up resistors P8_1/TXD1 specified each bit. P8_2/RXC1 P8_3/TXC1 P3_2/RDn output-only port when used emulator.
ML66525 Family User's Manual Chapter Overview
Table Descriptions (2/3)
Classification Port P9_0/VBUSIN P10_0/SIOCK3 P10_1/SIOI3 P10_2/SIOO3 P10_3/SIOCK4 P10_4/SIOO4 P10_5/SIOI4 P12_0/AI0 P12_3/AI3 P13_0/EXINT8 P13_1/EXINT9 P15_0/RXD6 P15_1/TXD6 P15_2/RXC6 P15_3/TXC6 P20_0/FD0 P20_7/FD7 P21_0/FRDn P21_1/FWRn P21_2/FCLE P21_3/FALE P21_4/FRB 4-bit input port 2-bit input port 4-bit port Pull-up resistors specified each bit. 8-bit port Pull-up resistors specified each bit. 5-bit port Pull-up resistors specified each bit. 6-bit port Pull-up resistors specified each bit. Symbol Type Primary function 1-bit port Function Type Secondary function Vbus detect input/non-detect external interrupt pin. tolerant input SIO3 transmit-receive clock SIO3 receive data input SIO3 receive data input SIO4 (with internal 32-byte FIFO) transmit-receive clock SIO4 (with internal 32-byte FIFO) transmit data output SIO4 (with internal 32-byte FIFO) receive data output converter analog input port External interrupt input External interrupt input SIO6 receive data input SIO6 transmit data output SIO6 receive clock SIO6 transmit clock NAND Flash Memory access data port NAND Flash Memory access read strobe output NAND Flash Memory access write strobe output NAND Flash Memory access strobe output NAND Flash Memory access strobe output NAND Flash Memory access Ready/Busy input
ML66525 Family User's Manual Chapter Overview
Table Descriptions (3/3)
Classification Power supply Symbol VDD_IO VDD_CORE VBUS VREF AGND Oscillation XT1n Type Function Power supply Connect VDD_IO pins.* Core Power supply Connect VDD_CORE pins.* power supply (Vbus input pin) Connect pins GND.* Analog reference voltage (Connect VDD_IO when converter used.) Analog (Connect when converter used.) Sub-clock oscillation output Connect crystal 32.768 kHz. Sub-clock oscillation output Connect crystal 32.768 kHz. clock output opposite phase XT0. Main clock oscillation input Connect crystal ceramic oscillator. When external clock used, this configured clock input pin. Main clock oscillation output Connect crystal ceramic oscillator. clock output opposite phase OSC0. Leave this unconnected when external clock used. External control output Reset input Non-maskable interrupt input Test Connect normal operation. Test Connect normal operation. Flash programming mode input When FLAMOD "L", device enters programming mode. Connect when using normal operation. External program memory access input When enabled (low level), internal program memory masked executes program code external program memory through address space.
OSC0
OSC1n
Reset Others
PUCTL RESn TEST VFLAMOD
sure supply power supply voltage VDD_IO VDD_CORE pins ground voltage pins. those pins voltage supply, normal operation device guaranteed.
ML66525 Family User's Manual Chapter Overview
1.5.2 Configuration
simplified configuration each ML66525 family shown Table Figure 1-4. Table Configuration Each
name P0_0 P0_7 P1_0 P1_7 P2_0 P2_3 P3_1 P3_2, P3_3 P4_0 P4_7 P6_0 P6_7 P7_6, P7_7 P8_0 P8_3 Type name P9_0 P10_0 P10_5 P12_0 P12_3 P13_0, P13_1 P15_0 P15_3 P20.0 P20_7 P21.0 P21_4 RESn NMI, Type
Type
Type
Schmitt inverter input Type
PULL DATA
HiZ. CONT.
Output: Push-pull output that output high impedance Type input: Schmitt inverter input (CMOS level) both RESn pins level, input pulled-up. Type input: Schmitt inverter input (CMOS level) Type
Schmitt inverter input with pull-up resistor Type A/DON
A/DON
DATA
HiZ. CONT.
Output: Push-pull output that output high impedance Input: tolerant Schmitt input (CMOS level). input enabled.
Figure Types Configurations
ML66525 Family User's Manual Chapter Overview
1.5.3 Connections Unused Pins
Table lists connections unused pins. Table Connections Unused Pins
P0_0 P0_7 P1_0 P1_7 P2_0 P2_3 P3_1 P3_3 P4_0 P4_7 P6_0 P6_3 P7_6, P7_7 P8_0 P8_3 P9_0* P10_0 P10_7 P15_0 P15_3 P20_0 P20_7 P21_0 P21_4 P13_0, P13_1 P12_0 P12_3 VREF AGND OSC1n, XT1n connection
When programmable pull-up resistor set: Open When input set: High level When output set: Open
High level VREF AGND VDD_IO High level High level GND* Open
Since P9_0 does have programmable pull-up function, handling should When input set: High level When output set: Open subclock (XT0, XT1n) used, addition connecting leaving XT1n unconnected, peripheral control register (PRPHCON) must set. details refer Chapter "Clock Oscillation Circuit."
ML66525 Family User's Manual Chapter Overview
Basic Operational Timing
ML66525 family configured such that pulse main clock (CLK) state. other words, state 41.7 MHz). instruction cycle consists more than state (S1, Sn). number states required program execution differs depending upon instruction. minimum states maximum states. (For details, refer nX-8/500S Core Instruction Manual.) achieve high-speed execution instructions, byte instruction pre-fetched. While instruction being executed, next instruction will fetched. Figure through Figure show basic timing examples. program memory accessed externally, number wait cycles cycles) specified ready control register (ROMRDY) inserted. data memory accessed externally, cycles cycle state) automatically inserted byte read write. addition, number wait cycles cycles) specified ready control register (RAMRDY) will also inserted. external memory access timings, refer Chapter "Bus Port Functions."
CPUCLK M1S1 M1S1
State
ML66525 Family User's Manual Chapter Overview
M1S1
(internal)
(port)
DATA STABLE
DATA STABLE Execute instruction ALP1 Fetch byte MOVB N8,[DP] instruction
(port)
Execute MOVB N8,[DP] instruction 0024H, LRB: internal RAM) N8[DP] (RAMP4)
Execute next instruction
Fetch instruction
Fetch Fetch byte MOVB N8,[DP] instruction instruction
Fetch byte MOVB N8,[DP] instruction
Fetch next instruction
Figure Basic Operation Timing Example (Reading Port Data)
CPUCLK M1S1 M1S1 M1S1
State
(internal)
(port)
DATA
DATA (value
DATA DATA (value #N8) Execute instruction P1AL Execute MOVB instruction P4#N8 Execute next instruction Fetch MOVB instruction Fetch byte MOVB instruction Fetch byte MOVB instruction Fetch next instruction Fetch byte next instruction
(port)
Fetch Fetch byte instruction instruction
ML66525 Family User's Manual Chapter Overview
Figure Basic Operation Timing Example (Writing Port Data)
ML66525 Family User's Manual Chapter Overview
CPUCLK M1S1 M1S1 M1S1 M1S1
State
TM0C count clock
DATA TM0CON TM0CONACCL ACCL [X1] [X1] ACCL
TM0RUN Read TM0C DATA TM0C ATM0C
TM0C
[Note] timing when TM0RUN becomes differs depending upon instruction used. timing reading TM0C differs depending upon instruction used. TM0C count timing differs depending upon selected TM0C clock. Figure Timer Operation Timing Example
CPUCLK M1S1 M1S1 M1S1 M1S1
State
TM0C count clock FFFC FFFE FFFF 0000 0001 0002 FFFD 0003 0004
TM0C
Instruction Instruction FFFD FFFE FFFF 0000 0001 0002 Instruction Instruction
Instruction Interrupt transfer cycle
TM0C
0003
0004
0005
Interrupt transfer cycle
[Note] There interrupt transfer cycles. However, program memory space been extended then there will cycles. reset interrupt transfer cycle. Figure Interrupt Transfer Timing Example
ML66525 Family User's Manual Chapter Overview
Chapter
Architecture
ML66525 Family User's Manual Chapter Architecture
Architecture
Overview ML66525 microcontroller family utilizes nX-8/500S, Oki's proprietary 16-bit core.
nX-8/500S performs various operations mainly using accumulator register set. Almost instructions addressing modes applicable both byte-format word-format data. also processing functions. Program memory space data memory space separated provided respectively. Each expanded addition, special dedicated addressing modes provided some specific portion data space such Special Function Registers area, fixed page area, current page area purpose efficient programming. further details, refer "nX-8/500S Core Instruction Manual".
Memory Space Program memory space data memory space independently. reset, (max.) accessed each. changing settings memory size control register (MEMSCON), located area, program memory space data memory space each expanded
2.2.1 Memory Space Expansion
memory size control register (MEMSCON) located register specifies size memory space. program memory space expanded setting LROM (bit "1". data memory space expanded setting LRAM (bit "1".
MEMSCON reset Address: 0011 access:
LROM LRAM
Data memory space Data memory space Program memory space Program memory space
indicates nonexistent bit. When read, value will "1".
Figure MEMSCON Configuration
ML66525 Family User's Manual Chapter Architecture write LROM MEMSCON, write "5H" then "0AH" upper bits memory size acceptor (MEMSACP) register located area. Likewise, write LRAM MEMSCON, first write "5H" then "0AH" lower bits memory size acceptor (MEMSACP).
MEMSACP
Address: 0010 access: Writing LRAM enabled writing "5H" "0AH" consecutively. Writing LROM enabled writing "5H" "0AH" consecutively.
Figure MEMSACP Configuration Note: FCAL, instruction executed while LROM being reset "0", opcode trap generated system reset will executed.
LROM LRAM bits "1", memory space expansion actually enabled after execution instruction that follows LROM LRAM write instruction. Programming examples expand program memory space listed below. SMALL memory space program memory space, data memory space) MOVB MEMSACP, #05H MOVB MEMSACP, #0AH MOVB MEMSCON, #00H (initial value) COMPACT memory space program memory space, data memory space) MOVB MEMSACP, #05H MOVB MEMSACP, #0AH MOVB MEMSCON, #01H MEDIUM memory space program memory space, data memory space) MOVB MEMSACP, #50H MOVB MEMSACP, #0A0H MOVB MEMSCON, #02H LARGE memory space program memory space, data memory space) MOVB MEMSACP, #55H MOVB MEMSACP, #0AAH MOVB MEMSCON, #03H MEMSCON written only once after reset (due RESn input, instruction execution, watchdog timer overflow, opcode trap). Therefore, change memory space model once other, reset write again MEMSCON.
ML66525 Family User's Manual Chapter Architecture
2.2.2 Program Memory Space
Program Memory Space also called "ROM space". maximum (1,048,576 bytes) program memory accessed (65,536 bytes) unit segments from segment However, more than (segments accessed, LROM MEMSCON (memory size control register) must "1". code segment register (CSR) specifies segment used, program counter (PC) specifies address segment. However, segment used execution table reference instructions (such obj) window function specified table segment register (TSR). (131,072 bytes) area segments constitutes internal area areas segments from external area. following areas assigned segment Vector table area bytes) VCAL table area bytes) addition, following area assigned each segment. ACAL area (2,048 bytes) Figure shows memory program memory space.
ML66525 Family User's Manual Chapter Architecture
Segment 0000H Vector table area bytes) 0049H 004AH 0069H 006AH 0073H 0074H 0FFFH 1000H Vector table area bytes) Vector table area bytes) 0000H Segment
Segment 0000H
Internal area
Internal area
External area
ACAL area
0FFFH 1000H 17FFH 1800H
ACAL area
0FFFH 1000H 17FFH 1800H
ACAL area
17FFH 1800H
FFFFH
FFFFH
FFFFH
Figure Memory Program Memory Space
ML66525 Family User's Manual Chapter Architecture Accessing program memory space Program memory space accessed program counter (PC) code segment register (CSR). However, when table reference instruction (such obj) window function (refer Section 4.3) executed, program memory space accessed according contents table segment register (TSR) register specified instruction. Access internal area external memory area program memory space automatically switched internal device operation depending status pin. When high level input pin, internal area accessed program address between 0000H 1FFFFH, external area accessed address between 20000H FFFFFH. When external area accessed, secondary functions external memory control pins (ports must set. area from 0000H 1FFFDH fetched internal program. Therefore, careful that final address instruction code does exceed 1FFFDH. final address table data 1FFFFH. When level input pin, external program memory area accessed program addresses. external memory area program memory space accessed, Port (data input), Port (addresses outputs), Port (addresses outputs) Port (addresses outputs) operate ports, P3_1/PSEN becomes active. Vector table area 74-byte area addresses from 0000H 0049H 10-byte area addresses from 006AH 0073H segment program memory space used vector table area that stores branch addresses types resets interrupts types) shown Table 2-1. reset interrupt occurs, corresponding 2-byte branch address, stored vector table, loaded into (The even address contains lower order data address contains upper order data.) same time, loaded into Code Segment Register (CSR) program execution starts from loaded segment address. Therefore reset interrupt occurs during execution instruction segment segment other than program control will branch address segment With reasons described above, reset routine interrupt routines must located segment This fact important medium large memory model programming. Proper alignment attribute must applied your relocatable interrupt routines. medium large memory model specified MEMSCON setting, automatically provides extra stack area contents. When instruction executed, contents stack re-stored into program execution continued same program segment. this area used vector table area, used normal program area. Table lists vector table addresses each type reset interrupt.
ML66525 Family User's Manual Chapter Architecture [Example] Program starting address 0200H RESn input
Program address 0000H 0001H
Data code (lower order data program start address) (upper order data program start address)
Table Vector Table List
Vector table starting address 0000 0002 0004 0006 0008 000A 001A 001C 001E 0020 0026 002A 002C 002E 0030 0032 0036 0038 003A 003E 0040 0042 0044 0046 0048 006A 006C 0072 Interrupt reset factor Reset RESn input Reset execution instruction Reset overflow watchdog timer Reset opcode trap input (non-maskable interrupt) EXINT0 input (external interrupt Timer overflow EXTINT1 input (external interrupt EXTINT2 input (external interrupt EXTINT3 input (external interrupt Timer overflow EXTINT4 input (Vbus detection interrupt) Interrupt from controller Interrupt from controller Interrupt from Media controller Timer overflow Timer overflow SIO1 transmit buffer empty, transmit completion, receive completion Timer overflow SIO3 transmit/receive completion SIO1 transmit buffer empty, transmit completion, receive completion SIO4 transfer completion Timer overflow conversion, select mode cancelled EXINT8/EXINT9 inputs (external interrupts Real time counter output PWC0 overflow, PWC0 PWR0 match PWC1 overflow, PWC1 PWR1 match Timer overflow
ML66525 Family User's Manual Chapter Architecture VCAL table area VCAL table area assigned 32-byte area program memory space segment from address 004AH 0069H stores branch addresses 1-byte call instructions (VCAL: types). VCAL instruction executed, next address after VCAL instruction saved onto system stack, system stack pointer (SSP) decremented corresponding 2-byte address stored vector table loaded into (The even address contains lower data address contains upper data). program begins execution from loaded address. However, program memory space been expanded decremented because value also saved same time that saved. Also, loaded with same time branch address loaded into Therefore, VCAL instruction executed segment program control will branch branch address segment program memory space (the LROM MEMSCON "0"), execution instruction will return program control from subroutine branched VCAL instruction. program memory space (the LROM "1"), execution instruction returns program control from subroutine branched VCAL instruction. this area used VCAL table area, used normal program area. Table lists VCAL vector addresses. [Example] Program starting address 0400H VCAL instruction Program address 004AH 004BH Data code (lower order data subroutine start address) (upper order data subroutine start address)
ML66525 Family User's Manual Chapter Architecture Table VCAL Vector Address List
VCAL table starting address 004A 004C 004E 0050 0052 0054 0056 0058 005A 005C 005E 0060 0062 0064 0066 0068 VCAL instruction VCAL VCAL VCAL VCAL VCAL VCAL VCAL VCAL VCAL VCAL VCAL VCAL VCAL VCAL VCAL VCAL
ACAL area area from 1000H 17FFH each program segment called ACAL area. subroutines located this area called 2-byte call instruction (ACAL). ACAL in-segment call instruction which does rewrite contents. ACAL instruction executed, address following next address after ACAL instruction saved onto system stack, system stack pointer (SSP) decremented 11-bit data included ACAL instruction code loaded into Program execution begins loaded address (1000 17FFH).
ML66525 Family User's Manual Chapter Architecture
2.2.3 Data Memory Space
maximum (1,048,576 bytes) data memory accessed. following areas assigned data memory space: special function register area (SFR: bytes), reserved area (256 bytes), fixed page area (FIX: bytes), internal area (4,096 bytes), local register setting area (2,048 bytes), EXPANDED area (3,584 bytes) external memory area (1,040,384 bytes). pointing register area (PR: bytes) special addressing area (sbafix: bytes) assigned fixed page area. window setting area (2000H 0FFFFH segment 1000H 0FFFFH segments assigned external data memory area. that data exchanged between more data segments without changing DSR, there common area that starts data memory address area, reserved area fixed page area always belong common area. Figure shows memory data memory space.
ML66525 Family User's Manual Chapter Architecture
Segment 0000H area 00FFH 0100H 01FFH 0200H 02FFH 0300H Internal area 09FFH 0A00H 11FFH 1200H 1BFFH 1C00H 1FFFH 2000H 7FFFH 8000H window setting area External data memory area window setting area Local register setting area External data memory area 0FFFH 1000H 0000H Segments Common area 03FFH Range
common area
Reserved area area
03FFH 1FFFH 3FFFH 7FFFH
Expanded area Inaccessible area 1FFFH 3FFFH 7FFFH
0FFFFH
0FFFFH
Figure Memory Data Memory Space
ML66525 Family User's Manual Chapter Architecture Special function register (SFR) area group registers with special functions such mode registers internal peripheral hardware, control registers counters assigned 256-byte area data memory space from 0000H 00FFH. Refer Chapter "Special Function Registers (SFRs)" more detailed description. Reserved area 256-byte data memory space from 0100H 01FFH reserved future expanded area. reserved area available. Internal area Internal assigned 4,096-byte area data memory space from 0200H 11FFH. Fixed page (FIX) area pointing register (PR) area special addressing (sbafix) area assigned 256-byte area data memory from 0200H 02FFH. pointing register area assigned addresses 0200H 023FH contains sets following registers. Index register (X1, Data pointer (DP) User stack pointer (USP) above 16-bit registers. addresses contain higher order data. Even addresses contain lower order data
special address area assigned addresses 02C0H 02FFH. instructions this area implemented small number bytes. Figure shows fixed page area.
ML66525 Family User's Manual Chapter Architecture
01FFH 0200H
Reserved area
0208H
Pointing register
0210H Fixed page area 0238H
0240H
02C0H area bytes 0300H
This area used JBS, instructions with sba. object
Figure Fixed Page Area
ML66525 Family User's Manual Chapter Architecture Local register setting area local register setting area area data memory from 0200H 09FFH. Local registers 8-byte units, specified lower bits (LRBL). Figure shows local register setting area.
0000H 0100H 0200H Internal area 0300H area Reserved area area
Local register setting area: Specified bits LRBL, 8-byte units
0200H 0208H
0A00H
LRBL
1200H
LRBL
External data memory area
2000H
0FFFFFH
0A00H
LRBL
Figure Local Register Setting Area
External data memory area external memory area 1,040,384-byte area data memory from 2000H 0FFFFFH. this external memory accessed, secondary functions memory related pins (ports must set. external memory accessed Port (data I/O: D7), Port (address output: A7), Port (address output: A15), Port (address output: A19), P3_3/WRn (write strobe output function) P3_2/RDn (read strobe output function) signals. 1,040,384-byte area from 2000H 0FFFFFH data memory external memory area. However, window function window setting register. window function used specified area (address 2000H above), instead accessing data data memory space, instructions (read operations) will access data program memory space same address. window function valid register (ROMWIN) that enables window function accessed (read) address external data memory.
ML66525 Family User's Manual Chapter Architecture Common area There common area data memory space enable exchange data between more data segments. common area located bottom data memory, beginning offset address each segment. range common area determined value PSW.
range common area 03FFH 1FFFH 3FFFH 7FFFH
EXPANDED area EXPANDED area assigned 3,584-byte area data memory from 1200H 1FFFH. EXPANDED includes transfer buffer (512 bytes banks), controller register, transfer register, NAND Flash Memory transfer control register, NAND Flash Memory ports. memory from 1C00H 1FFFH inaccessible area.
1200H 1400H 1600H 1800H 1A00H Bank (512 bytes) Bank (512 bytes) Bank (512 bytes) Bank (512 bytes)
EXPANDED area
ML66525 Family User's Manual Chapter Architecture
2.2.4 Data Memory Access
Examples memory access presented below cases when instruction performs byte operation word operation data memory space. Byte operations case byte operation, address obtained from instruction points targeted 8-bit data. [Example] [DP]: where contents 0335H
0332H 0333H 0334H 0335H 0336H 0337H 0338H
Word operations case word operation, corresponding address obtained from instruction, address with least significant (LSB) (even address) points lower order 8-bit data address with (odd address) points upper order 8-bit data form targeted 16-bit data. Therefore, targeted 16-bit data formed with upper oder 8-bit data address lower oder 8-bit even address accessed. (The boundary exists between bytes word operation.) such boundary limit does exist program memory space. [Example] [DP]: where contents 0334H 0335H)
0331H 0332H 0333H 0334H 0335H 0336H 0337H
ML66525 Family User's Manual Chapter Architecture
Registers Registers classified function arithmetic register, control registers, pointing registers, special function registers, local registers segment registers.
Figure shows configuration each register.
Arithmetic register Control registers Pointing registers Segment registers Local registers (ER0) (ER1) (ER2) (ER3) Special function registers (SFRs)
Figure Register Configurations
2.3.1 Arithmetic Register (ACC)
arithmetic register 16-bit accumulator (ACC), central type arithmetic operations. transfer arithmetic operation word operation, bits (bits accessed, byte operation, lower bits (bits accessed, nibble operation, lower bits (bits accessed. targeted instruction specified (such SBR, RBR, etc.), upper bits (bits within lower bits specify address offset, lower bits (bits specify position. assigned area. reset (due RESn input, instruction execution, watchdog timer overflow, opcode trap), contents become 0000H.
ML66525 Family User's Manual Chapter Architecture
2.3.2 Control Registers
Control registers group four 16-bit registers with dedicated functions program status, program sequence, local registers stack control. Program status word (PSW) 16-bit register consisting following. flag (DD) that referenced when executing instructions Flags (CY, that reset depending upon instruction execution results Flags (SCB0 SCB2) that specify pointing register setting flag (MIE) that enables ("1") disables ("0") maskable interrupts Flags (BCB0, BCB1) that specify segment common area Flags that user freely utilize flag with future expanded core functions. This flag (MAB) freely utilized user. addition 16-bit operations, 8-bit operations also performed with divided into 8-bit units PSWH (bits PSWL (bits Figure shows configuration.
Address: 0005 access: reset Address: 0004 access:
PSWH
PSWL
Figure Configuration
ML66525 Family User's Manual Chapter Architecture upper bits (PSWH) contain: flag (DD) that referenced when executing instructions flags (CY, that reset depending upon instruction execution results. Therefore, following instructions performed PSWH, flag operation change from original function. Instructions that load contents PSWH into (contents become undefined) (ii) operation instructions changes depending value immediately before execution operation instruction.) (iii) Increment, decrement, arithmetic, logic compare instructions PSWH (The contents PSWH immediately after instruction execution undefined.) interrupt occurs, automatically saved during interrupt processing automatically restored execution instruction. assigned area. reset (due RESn input, instruction execution, watchdog timer overflow, opcode trap), contents become 0000H. Each described below. Carry flag (CY) carry flag carry from occurs byte operation, borrow occurs byte operation, carry from occurs word operation, borrow occurs word operation result executing arithmetic comparison instruction. Otherwise reset "0". carry flag reset directly instructions used transmit receive data bits specified registers. addition, carry flag tested conditional branch instructions. Zero flag (ZF) zero flag when: result arithmetic instruction zero, instruction load executed load contents zero, operation instruction executed target zero. Otherwise, reset "0". zero flag tested conditional branch instructions.
ML66525 Family User's Manual Chapter Architecture Half carry flag (HC) half carry flag carry borrow from occurs result executing arithmetic comparison instruction (either byte word instruction). Otherwise, reset "0". Data descriptor (DD) This flag indicates attributes data stored ACC. When "1", bits data determined valid. When "0", lower bits data determined valid. Instructions that reference when performing arithmetic data transfer instructions with executed follows. When "1", arithmetic transfer operation performed word units. When "0", arithmetic transfer operation performed byte units. reset when data transfer instruction executed when dedicated reset instructions executed. when executing word-type load instruction when executing instruction. reset when executing byte-type load instruction when executing instruction. modified (set reset) while executing load instruction dedicated reset instruction, next instruction references modified will referenced. Since assigned PSW, overwritten instructions other than those mentioned above. this case, next instruction references will reference state prior modification. used this manner, insert instruction after instruction that directly modifies state Sign flag sign flag result executing arithmetic logic instruction "1". result "0", sign flag reset "0". User flag (F2) User flag (F1) User flag (F0) These flags reset instructions. Overflow flag (OV) overflow flag result executing arithmetic instruction exceeds range expressed compliment format (-128 +127 byte operations -32,768 +32,767 word operations). Otherwise overflow flag reset "0".
ML66525 Family User's Manual Chapter Architecture Master interrupt enable flag (MIE) master interrupt enable flag enables ("1") disables ("0") maskable interrupts. During maskable interrupt transfer cycle, after this flag saved onto system stack part PSW, reset "0", then restored execution instruction. "1", generation maskable interrupts enabled from next instruction. reset "0", generation maskable interrupts disabled from next instruction. Product-sum function bank flag (MAB) ML66525 family does have product-sam function. This utilized user flag. Bank common base (BCB1) Bank common base (BCB0) These flags specify last address common area between segments data memory space. table below shows relation between value selected common area.
range common area 03FFH 1FFFH 3FFFH 7FFFH
System control base (SCB2) System control base (SCB1) System control base (SCB0) These flags specify pointing register (PR) assigned fixed page area.
pointing register (0200H 0207H) (0208H 020FH) (0210H 0217H) (0218H 021FH) (0220H 0227H) (0228H 022FH) (0230H 0237H) (0238H 023FH)
ML66525 Family User's Manual Chapter Architecture Program counter (PC) 16-bit counter that stores next address executed program segment. normally incremented according number bytes instruction executed. branch instruction instruction that requires branch executed, loaded with immediate data, register contents, etc. value does change even incremented that overflows. reset (due RESn input, instruction execution, watchdog timer overflow, opcode trap), when interrupt generated, value from vector table loaded into Local register base (LRB) 16-bit register. lower bits (LRBL) specify data memory space from 0200H 09FFH 8-byte units (local register addressing). upper bits (LRBH) specify data memory space 256-byte units segment (segments arbitrarily specified data segment register (DSR) (current page addressing). instructions whose object sba.bit used 64-byte area current page from xxC0H xxFFH. Both LRBL (02H) LRBH (03H) assigned area. reset (due RESn input, instruction execution, watchdog timer overflow, opcode trap), their value undefined.
Address: 0003 access: reset LRBH Undefined LRBL Address: 0002 access:
Figure Configuration
bits LRBL specify data memory space from 0200H 09FFH 8-byte units.
LRBL
bits LRBL specify data memory space from 0200H 09FFH 8-byte units. (Value included instruction code.)
ML66525 Family User's Manual Chapter Architecture bits LRBH specify data memory space 256-byte units.
LRBH bits LRBH specify data memory space from 0000H 0FFFFH 256-byte units. (Value included instruction code.)
System stack pointer (SSP) 16-bit register that indicates stack address which save restore registers, etc. while processing interrupts executing call, push, return, instructions. automatically incremented decremented depending upon process executed. Since save restore operations address indicated performed word units, least significant (LSB) addressed "0". area Expanded area used stack area. (00H) assigned area. reset (due RESn input, instruction execution, watchdog timer overflow, opcode trap), contents become 0FFFFH.
ML66525 Family User's Manual Chapter Architecture
2.3.3 Pointing Register (PR)
sets registers. Index register (X1) Index register (X2) Data pointer (DP) User stack pointer (USP) consists following four 16-bit registers.
assigned internal space from 0200H 023FH. eight register sets selected SCB0 SCB2 PSWL. function used, this area used normal internal RAM. USP, even addresses lower bits following addresses upper bits.
01FFH 0200H Reserved area
0208H
Pointing register sets
0210H
0238H
0240H
ML66525 Family User's Manual Chapter Architecture
2.3.4 Local Registers ER3)
local register 8-bit register expanded local register 16-bit register. area data memory space from 0200H 09FFH specified 8-byte units lower bits local register base (LRBL). accesses byte specified bytes according bits data included local register instruction. (ERm accesses bytes according bits data included local register instruction.)
0200H 0208H
LRBL
Specified 8-byte units bits LRBL. specified bits included instruction code. specified bits included instruction code.
LRBL
0A00H
LRBL 0FFH
ML66525 Family User's Manual Chapter Architecture
2.3.5 Segment Registers
There three 8-bit segment registers: code segment register (CSR), table segment register (TSR) data segment register (DSR). These registers select segments program memory space. However, since program memory space only segments only bits valid. Bits fixed "0". Code segment register (CSR)
reset
specifies segment program memory space which program code currently being executed belongs. exists independent 8-bit register assigned area. contents overwritten FCAL, VCAL, instructions interrupts. other methods used overwrite contents CSR. FCAL instructions, branch destination addresses that within segments Each segment assigned internal segment offset address 0FFFFH. address calculation determine addressed target performed with 16-bit offset address resulting overflow underflow ignored that does change. Similarly, overflow never updates CSR. Therefore, without overwrite method described above, program execution does advance beyond code segment boundary. value reset 00H. When interrupt occurs after program memory space been expanded both current value automatically saved stack. Executing instruction restores saved value CSR. (Refer Section 2.2.1, "Memory Space Expansion".) Table segment register (TSR)
reset Address: 0008 access: indicates that value must written. read, value will obtained.
specifies segment program memory which table data belongs. 8-bit register assigned area. contents overwritten instructions that addressing. Data table segment accessed using reference instructions (LC, LCB, CMPC CMPCB). window function used, addressing utilized this table segment. Only bits valid. read, value will obtained bits writing TSR, must written bits
ML66525 Family User's Manual Chapter Architecture Each segment assigned internal segment offset address 0FFFFH. address calculation determine addressed target performed with 16-bit offset address resulting overflow underflow ignored, does change. value reset 00H. Data segment register (DSR)
reset Address: 0009 access: indicates that value must written. read, value will obtained.
specifies segment data memory space which data currently belongs. 8-bit register assigned area. contents overwritten instructions that addressing. Only bits valid. read, value will obtained bits writing DSR, must written bits
Addressing Modes ML66525 family independent memory spaces, data memory space program memory space. Addressing roughly classified into modes, corresponding each memory space.
data memory space referred "RAM space", since normally consists random access memory (RAM). addressing this space referred "RAM addressing". program memory space referred "ROM space", since normally consists read-only memory (ROM). addressing this space referred "ROM addressing". addressing classified immediate addressing contained instruction codes, table data addressing data (normally read-only data) space table, program code addressing programs space. window addressing unique method addressing. involves accessing table data space using above addressing methods. Data table segment read through data segment window specified opened program.
2.4.1 Addressing
This addressing mode specifies addresses program variables space. Available addressing formats include: register addressing, page addressing, direct data addressing, pointing register indirect addressing special area addressing.
ML66525 Family User's Manual Chapter Architecture Register addressing Accumulator addressing Control register addressing Pointing register addressing Local register addressing Accumulator addressing case word-format instruction, contents accumulator will accessed. case byte bit-format instructions, lower byte accumulator (AL) will accessed. [Word format] #1234H [Byte format] #12H [Bit format] A.3, LABEL Control register addressing Contents registers will accessed. SSP: LRB: PSW: PSWH: PSWL: System Stack Pointer Local Register Base Program Status Word Program Status Word High Byte Program Status Word Byte Carry Flag
PSW, LRB, ERn,
[Word format] FILL LRB, #401H [Byte format] CLRB PSWH INCB PSWL [Bit format] BITVAR
ML66525 Family User's Manual Chapter Architecture Pointing register addressing Contents pointing register accessed. There sets pointing registers (PR0 PR7: every bytes from 200H 23FH data memory). addressed this mode specified value system control base (SCB) field PSW. Index Register Index Register Data Pointer byte data pointer used only "JRNZ radr" instruction maintain compatibility among nX-8/100 nX-8/400 cores). USP: User Stack Pointer X1L: Index Register Byte X2L: Index Register Byte DPL: Data Pointer Byte USPL: User Stack Pointer Byte [Word format] #2000H [Byte format] DJNZ X1L, LOOP DJNZ X2L, LOOP DJNZ DPL, LOOP DJNZ USPL, LOOP JRNZ LOOP Local register addressing Contents local register accessed. There sets local registers (every bytes from 200H 9FFH data memory). addressed this mode specified value byte local register base (LRB). ER3: Expanded Local Registers Local Registers
ML66525 Family User's Manual Chapter Architecture [Word format] ER2, [Byte format] ADDB CMPB #12H INCB MOVB [Bit format] R0.0 R1.7 JBRS R7.3, LABEL Page addressing page addressing FIXED page addressing Current page addressing page addressing byte instruction code specifies offset within page (data memory addresses 0FFH). Word-format, byte-format bit-format data specified address accessed. operand described using format that addressing descriptor. descriptor omitted, however that case, assembler will page addressing only when recognizes address within page area. address symbols each type device. These symbols normally used addressing SFR. Dadr Dadr Dadr
ML66525 Family User's Manual Chapter Architecture [Word format]
0000H 00xxH page
00FFH
address specified, word-format data accessed starting following even address. (word boundary) However, depending upon SFR, there some exceptions.
[Byte format]
0000H 00xxH page
00FFH
[Bit format]
P0_3 P0_3 0000H 00xxH
page 00FFH
FIXED page addressing byte instruction code specifies offset within FIXED page (data memory addresses 200H 2FFH). Word-format, byte-format bit-format data specified address accessed. operand described using format that addressing descriptor. descriptor omitted, however that case, assembler will FIXED page addressing only when recognizes address within FIXED page area.
ML66525 Family User's Manual Chapter Architecture [Word format]
FIX_VAR FIX_VAR 0200H 02xxH
FIXED page
02FFH
address specified, word-format data accessed starting following even address.
[Byte format]
0200H 02xxH FIXED page
FIX_VAR FIX_VAR
02FFH
[Bit format]
0200H 02xxH FIXED page 02FFH
FIX_VAR.3 FIX_VAR.3
Current page addressing byte instruction code specifies offset within current page (one pages data memory specified LRBH value). Word-format, byte-format bit-format data specified address accessed. operand described using format that addressing descriptor. used instead descriptor, however bit-format data accessed area, operation will slightly different. (sbaoff Badr)
ML66525 Family User's Manual Chapter Architecture [Word format]
xx00H xxxxH xxFFH Current page
address specified, word-format data accessed starting following even address. [Byte format]
xx00H xxxxH xxFFH Current page
[Bit format]
VAR.3 VAR.3 xx00H xxxxH Current page xxFFH
Direct data addressing bytes instruction code specify address current physical segment data memory (address 0FFFFH: KB). Word-format, byte-format bit-format data specified address accessed. operand described using format that addressing descriptor. descriptor omitted, however this case, address page FIXED page specified, assembler interpret direct data addressing page addressing FIXED page addressing.
ML66525 Family User's Manual Chapter Architecture [Word format]
0000H xxxxH
FFFFH
address specified, word-format data accessed starting following even address.
[Byte format]
0000H xxxxH
FFFFH
[Bit format]
0000H xxxxH
VAR.3 VAR.3
FFFFH
Pointing register indirect addressing DP/X1 indirect addressing indirect addressing with post increment indirect addressing with post decrement DP/USP indirect addressing with 7-bit displacement X1/X2 indirect addressing with 16-bit base indirect addressing with 8-bit register displacement
[DP], [X1] [DP+] [DP-] n7[DP], n7[USP] D16[X1], D16[X2] [X1+R0], [X1+A]
ML66525 Family User's Manual Chapter Architecture DP/X1 indirect addressing contents pointing register specify address current physical segment data memory (address 0FFFFH: KB). Word-format, byte-format bit-format data specified address accessed. [DP]: [X1]: indirect addressing indirect addressing
[Word format]
[DP] [X1] 0000H xxxxH
FFFFH
address specified, word-format data accessed starting following even address.
[Byte format]
[DP] [X1] 0000H xxxxH
FFFFH
[Bit format]
[DP].3 [X1].3 0000H xxxxH
FFFFH
ML66525 Family User's Manual Chapter Architecture indirect addressing with post increment contents pointing register specify address current physical segment data memory (address 0FFFFH: KB). Word-format, byte-format bit-format data specified address accessed. After accessing target, contents pointing register incremented. word-format instructions, incremented two. byte instructions, incremented one. This addressing mode used primarily consecutively access array elements. [DP+]: indirect addressing with post increment
[Word format]
[DP+] Incremented after access 0000H xxxxH
FFFFH
address specified, word-format data accessed starting following even address. [Byte format]
[DP+] Incremented after access 0000H xxxxH
FFFFH
[Bit format]
[DP+].3 Incremented after access 0000H xxxxH
FFFFH
ML66525 Family User's Manual Chapter Architecture indirect addressing with post decrement contents pointing register specify address current physical segment data memory (addresses 0FFFFH: KB). Word-format, byte-format bit-format data specified address accessed. After accessing target, contents pointing register decremented. word-format instructions, decremented two. byte instructions, decremented one. [DP-]: [Word format]
[DP-] Decremented after access 0000H xxxxH
indirect addressing with post decrement
FFFFH
address specified, word-format data accessed starting following even address.
[Byte format]
0000H [DP-] Decremented after access xxxxH
FFFFH
[Bit format]
[DP-].3 Decremented after access FFFFH 0000H xxxxH
ML66525 Family User's Manual Chapter Architecture DP/USP indirect addressing with 7-bit displacement bits instruction code (bit used signed displacement (bit sign bit) from pointing register contents (the base value) specify address current physical data segment (address 0FFFFH: KB). accessible range from content pointing register. Word-format, byte-format bit-format data specified address accessed. Numerical expression[DP]: indirect addressing with 7-bit displacement Numerical expression[USP]: indirect addressing with 7-bit displacement numerical expression value range +63. used pointing registers. [Word format]
12[DP] 12[USP] 0000H xxxxH FFFFH
address specified, word-format data accessed starting following even address.
[Byte format]
A,12[DP] A,12[USP] 0000H xxxxH FFFFH
[Bit format]
12[DP].3 12[USP].3 0000H xxxxH FFFFH
ML66525 Family User's Manual Chapter Architecture X1/X2 indirect addressing with 16-bit base contents index register added base bytes instruction code (D16). value that generated specifies address current physical data segment (address 0FFFFH: KB). addition operation generate address performed word-format (16-bit) since overflow ignored, generated value range from 0FFFFH. Word-format, byte-format bit-format data specified address accessed. Address expression[X1]: indirect addressing with 16-bit base Address expression[X2]: indirect addressing with 16-bit base address expression value range 0FFFFH. However, assembler allows values range -8000H +0FFFFH. This means that also regarded displacement, instead base address. [Word format]
A,1234H[X1] A,1234H[X2] 0000H xxxxH FFFFH
address specified, word-format data accessed starting following even address. [Byte format]
0000H xxxxH FFFFH
A,1234H[X1] A,1234H[X2]
[Bit format]
1234H[X1].3 1234H[X2].3 0000H xxxxH FFFFH
ML66525 Family User's Manual Chapter Architecture indirect addressing with 8-bit register displacement contents byte accumulator (AL) local register (R0) added pointing register contents (the base value) generate value that specifies address current physical data segment (address 0FFFFH: KB). addition operation generate address performed word-format (16-bit). this time, 8-bit displacement obtained from register expanded unsigned. Since overflow resulting from addition ignored, generated value range from 0FFFFH. Word-format, byte-format bit-format data specified address accessed. [X1+A]: indirect addressing with 8-bit register displacement (AL) [X1+R0]: indirect addressing with 8-bit register displacement (R0) [Word format]
[X1+A] [X1+R0] 0000H xxxxH FFFFH
address specified, word-format data accessed starting following even address. [Byte format]
[X1+A] [X1+R0] 0000H xxxxH FFFFH
[Bit format]
[X1+A].3 [X1+R0].3 FFFFH 0000H xxxxH
ML66525 Family User's Manual Chapter Architecture Special area addressing Fixed page area addressing Current page area addressing Fixed page area addressing This addressing mode specifies address 512-bit area (2C0H.0 2FFH.7) located FIXED page. format data specified address accessed. This addressing mode written following instructions: JBR. [Bit format]
sbafix 2C0H.0 sbafix 1600H sbafix VAR, LABEL sbafix 2EFH.7 2C0H.0 1600H VAR, LABEL 2EFH.3, LABEL
sbafix Badr sbaoff Badr
02C0H 02xxH FIXED page area 02FFH
ML66525 Family User's Manual Chapter Architecture Current page area addressing This addressing mode specifies address 512-bit area (xxC0H.0 xxFFH.7) located current page. format data specified address accessed. This addressing mode written following instructions: JBR. [Bit format]
sbaoff 4C0H.0 sbaoff 2E80H sbaoff VAR,LABEL sbaoff 0FFFFH.3, LABEL 2C0H.0 2E80H VAR,LABEL 0FFFFH.3, LABEL
xxC0H xxxxH Current page area
xxFFH
ML66525 Family User's Manual Chapter Architecture
2.4.2 Addressing
This addressing mode specifies addressing program variables space. Available addressing formats include: immediate addressing, table data addressing program code addressing. Immediate addressing This addressing mode specifies access immediate data included instruction code. word-format instructions, bytes (N16) instruction code accessed. byte-format instructions, byte (N8) instruction code accessed. word-format, expressions have values range 0FFFFH. byte-format, expressions have values range 0FFH. assembler allows range signed unsigned expressions immediate addressing. word-format range from -8000H +0FFFFH byte-format range from -80H +0FFH. [Word format] #1234H #WORD_ARRAY_BASE
[Byte format] #12H #BYTE_ARRAY_BASE
Table data addressing This addressing mode specifies access table segment specified memory space. This mode used with operands LCB, CMPC CMPCB instructions. Direct table addressing addressing indirect table addressing addressing indirect addressing with 16-bit base Direct table addressing bytes instruction code specify address (address 0FFFFH: table segment specified TSR. Word-format byte-format data specified address accessed. This addressing mode written following instructions: LCB, CMPCB. Tadr [**] T16[**]
ML66525 Family User's Manual Chapter Architecture [Word format] CMPC
[Byte format] CMPCB
addressing indirect table addressing This indirect addressing mode uses word-format data specified addressing pointer table segment specified TSR. Table memory accessed placing pointer table memory register data memory. This addressing mode written following instructions: LCB, CMPC CMPCB. [Word format] CMPC [1234[X1]]
[Byte format] [ER0] CMPCB [VAR]
addressing indirect addressing with 16-bit base contents word-format data specified addressing added base bytes instruction code (D16). value that generated specifies address table segment specified (address 0FFFFH: KB). addition operation generate address performed word-format (16-bit) since overflow ignored, generated value range from 0FFFFH. Word-format byte-format data specified address accessed. This addressing mode written following instructions: LCB, CMPC CMPCB. [Word format] 2000H[A] CMPC 2000H[1234[X1]]
[Byte format] 2000H[ER0] CMPCB 2000H[VAR]
ML66525 Family User's Manual Chapter Architecture Program code addressing This mode specifies access current program code space. Program code addressing used with operands branch instructions. NEAR code addressing code addressing Relative code addressing ACAL code addressing VCAL code addressing addressing indirect code addressing Cadr Fadr radr Cadr11 Vadr [**]
NEAR code addressing bytes instruction code specify address (address 0FFFFH: current code segment. This addressing mode written instructions, CAL. [Usage example] 3000H LABEL code addressing Three bytes instruction code specify address (0:0 F:0FFFFH: program memory space. This addressing mode written instructions, FCAL. [Usage example] 1:3000H FCAL FARLABEL Relative code addressing sign extended value bits bits instruction code added base value current program counter (PC). generated value specifies address current code segment 0FFFFH: KB). addition operation generate address performed word-format (16-bit) since overflow ignored, generated value range from 0FFFFH. This addressing mode written instruction, conditional branch instructions, etc. [Usage example] LABEL DJNZ LABEL LABEL
ML66525 Family User's Manual Chapter Architecture ACAL code addressing
bits instruction code specify ACAL area (1000H 17FFH: current code segment. This addressing mode written only ACAL instruction. [Usage example] ACAL 1000H ACAL ACALLABEL VCAL code addressing bits instruction code specify vector table address VCAL instruction (word-format data). vector table located even addresses range 004AH 0069H. This addressing mode written only VCAL instruction. [Usage example] VCAL VCAL 0:4AH VCAL VECTOR addressing indirect code addressing This indirect addressing mode uses word-format data specified addressing pointer code segment. Indirect jumps calls performed placing pointer code memory register data memory. This addressing mode written instructions, CAL. [Usage example] [1234[X1]] window addressing This addressing mode uses addressing access table data space. this mode, data table segment specified read through data segment window specified opened program. window area allows addressing data memory, however, results cannot guaranteed instruction that writes window area executed.
Chapter
Control Functions
ML66525 Family User's Manual Chapter Control Functions
Control Functions
Overview ML66525 family control functions, standby function reset function.
standby function consists functions HALT mode STOP mode. These functions used reduce amount power consumed during operation. STOP mode quick activating STOP mode which main clock continues oscillation. reset function activated RESn signal input, (break) instruction execution, execution invalid instruction (opcode trap). addition, reset also activated overflow watchdog timer. Reset minimize effect program errors system.
Standby Functions
ML66525 family types standby functions. HALT mode: activated software, clock supply terminated STOP mode: activated software, clock supply internal peripheral modules terminated Corresponding each dual clocks, each these functions high-speed low-speed mode. Figure shows transition diagram operating states. standby modes. Table lists summary
High-speed HALT mode
Interrupt generated
High-speed main clock (OSC) operation Initial state when RESET
Subclock (XT) selection
High-speed STOP mode
(Terminate main clock oscillation: OSCS
Main clock (OSC) selection
(Operate main clock oscillation: OSCS Interrupt generated
Low-speed HALT mode
Interrupt generated
Low-speed subclock (XT) operation (Terminate main clock oscillation: OSCS (Operate main clock oscillation: OSCS
Interrupt generated
Low-speed STOP mode (Terminate main clock oscillation: OSCS (Operate main clock oscillation: OSCS
(Notes) Oscillation operation termination main clock (OSC) only. subclock (XT) terminated. initial value OSCS (bit SBYCON) "1". Stopping main clock (OSC) with OSCS effective when P9_0/VBUSIN level input; alternatively, when P9_0/VBUSIN level input control function power down state (refer Chapter 17).
Figure Transition Diagram Operating States
ML66525 Family User's Manual Chapter Control Functions Table Standby Mode Summary
Standby mode conditions HALT mode (HLT) SBYCON Interrupt RESn input change Pull-up change change High level change Pull-up Operate Operate Operate Operate Operate Operate Operate Operate Operate Operate Operate STOP mode (FLT) SBYCON (FLT) SBYCON reset (STP) SBYCON (STP) SBYCON Interrupt Interrupt RESn input RESn input
Release conditions
Operation internal functions
(primary function) (secondary function) P3_1 (primary function) P3_1 (secondary function) P3_2, P3_3 (primary function) P3_2, P3_3 (secondary function) Time base counter (TBC) 8/16-bit timers (including WDT) SIO1, SIO6 SIO3 SIO4 Real-time counter converter Media control Internal control control
High impedance Pull-up High impedance High impedance High impedance High impedance High impedance Terminate Terminate
change Pull-up change change High level change Pull-up
Output states
Terminate Operate during slave mode Terminate Operate Terminate Terminate Terminate Terminate Ready operate
condition setting STOP mode that stop code acceptor (STPACP) already been "1". P10_0 secondary function output, then P10_2 (secondary function output) will high impedance. P10_0 secondary function output, then P10_2 (secondary function output) will SIO3 data output.
ML66525 Family User's Manual Chapter Control Functions
3.2.1 Standby Function Registers
Table lists summary SFRs standby function control. Table Summary SFRs Standby Function Control
Address 000E 000F 0015 Name Stop code acceptor Standby control register Peripheral control register Symbol (byte) STPACP SBYCON PRPHCON Symbol (word) 8/16 Operation Initial value Reference page 13-2
[Notes] Addresses consecutive some places. star address column indicates missing bit. details, refer Chapter "Special Function Registers (SFRs)".
3.2.2 Description Standby Function Registers
Stop code acceptor (STPACP) stop code acceptor (STPACP) configured from bits acceptor used STOP mode. STPACP when program writes consecutively. After STPACP "1", setting (STP) standby control register (SBYCON) will change mode STOP mode. same time mode changes STOP mode, STPACP reset "0". STPACP write-only. reset (due RESn input, instruction execution, watchdog timer overflow, opcode trap), STPACP reset "0". STPACP configuration shown Figure 3-2.
STPACP
Address: 000E access: Writing SBYCON enabled writing "n5H" "nAH" sequentiaily.
Figure STPACP Configuration
ML66525 Family User's Manual Chapter Control Functions Standby control register (SBYCON) standby control register (SBYCON) 8-bit register that sets standby mode operating clock (CPUCLK). program read from write SBYCON. reset (due RESn input, instruction execution, watchdog timer overflow, opcode trap), SBYCON 08H. Figure shows configuration SBYCON. [Description each bit] (bit Setting stop code acceptor (STPACP) "1", then setting will change mode STOP mode. When interrupt generated RESn input causes reset, reset STOP mode released. (bit Setting changes mode HALT mode. When interrupt generated, RESn input causes reset, overflow watchdog timer causes reset, reset HALT mode released. (bit Setting will cause output ports (all pins output mode) high impedance state when STOP mode entered. input ports, circuit operates prevent current flow between power supply GND, even inputs left unconnected. Therefore, necessary input levels during STOP mode. However, following pins used inputs (regardless whether they primary secondary functions), circuit prevent current flow will operate. Thus, prevent undefined input states, either pull-up pull-down resistors input levels) during STOP mode. P6_0 P6_3, P9_0 P10_0 P10_1 External interrupt pins (EXINT0 EXINT4) SIO3 transmit-receive clock input SIO3 receive data input
Using above pins secondary function inputs, even STOP mode entered with ("1"), STOP mode released external interrupt input SIO3 data reception. details, refer Section 3.2.4, "Operation Each Standby Mode," STOP Mode. ML66525 Family, P9_0 being configured output Setting will cause output ports high impedance state when STOP mode entered. However, input ports, circuit prevent current flow will operate. Since P9_0 Vbus detect input pin, should used output. OSCS (bit During STOP mode when subclock (XTCLK) been selected operating clock (CPUCLK), OSCS specifies whether terminate continue oscillation main clock (OSCCLK).
ML66525 Family User's Manual Chapter Control Functions [Note] stop main clock (OSCCLK) with OSCS, following conditions also required. When P9_0/VBUSIN level input, that when unconnected. Alternatively, When P9_0/VBUSIN level input control function power down state (refer Chapter 17). attempt terminate main clock (OSCCLK) with OSCS will fail when control function operation, because clock must supplied control function. OST0, OST1 (bits cases when interrupt causes STOP mode released, when clock been changed from subclock (XTCLK) main clock (OSCCLK), OST0 OST1 specify oscillation stabilization time from oscillation start main clock (OSCCLK) until clock supply CPU. During STOP mode, even oscillation main clock (OSCCLK) terminated, settings these bits valid. [Note] OST0 OST1 "1", case changing operation mode which oscillation main clock (OSCCLK) terminated. Flash version, oscillation stabilization time more when STOP mode (only when oscillation main clock terminated) released. CLK0, CLK1 (bits CLK0 CLK1 specify clock used operating clock (CPUCLK). With consideration operating speed requirements product applications, appropriate speed internal clock that runs microcontroller selected reduce power consumption.
ML66525 Family User's Manual Chapter Control Functions
operating state STOP mode operating state HALT mode
During STOP mode, output does change During STOP mode, high impedance output
SBYCON CLK1 CLK0 OST1 OST0 OSCS reset
Address: 000F access:
Main clock (OSC) oscillation
Terminate main clock (OSC) oscillation
Main clock oscillation stabilization time (No. clocks) 32768 16384 8192 operating clock (CPUCLK) OSCCLK OSCCLK OSCCLK XTCLK
Figure SBYCON Configuration
ML66525 Family User's Manual Chapter Control Functions
3.2.3 Examples Standby Function Register Settings
HALT mode setting Standby control register (SBYCON) Setting (HLT) changes mode HALT mode. STOP mode setting Stop code acceptor (STPACP) Write n5H, consecutively. Standby control register (SBYCON) output ports high impedance during STOP mode, (FLT) "1". oscillation main clock (OSCCLK) terminated during STOP mode, reset (OSCS) "0". terminate oscillation main clock (OSCCLK), (OSCS) specify with bits (OST0 OST1) oscillation stabilization time after main clock resumes. Setting (STP) changes mode STOP mode.
3.2.4 Operation Each Standby Mode
HALT mode Setting (HLT) standby control register (SBYCON) changes mode HALT mode. HALT mode, clock (CPUCLK) supply terminated, clock (CPUCLK) supplied internal peripheral modules (TBC, WDT, general-purpose 8/16-bit timers, serial ports, etc.) their operation continues. Because halted, instructions executed. Instruction execution stops beginning next instruction (following instruction that (HLT) SBYCON "1"). HALT mode released when following occurs: interrupt request, reset RESn input, reset overflow watchdog timer. When HALT mode released interrupt request, interrupt non-maskable, HALT mode released unconditionally, processes non-maskable interrupt. case maskable interrupt, interrupt released when both interrupt request flag (IRQ bit) interrupt enable flag bit) have been "1". After HALT mode released, master interrupt enable flag (MIE PSW) been "1", processing requested maskable interrupt performed. master interrupt enable flag (MIE PSW) been reset "0", next instruction (following instruction that HALT mode (that (HLT) SBYCON "1")) executed. HALT mode released reset RESn input overflow watchdog timer, will perform reset processing.
ML66525 Family User's Manual Chapter Control Functions STOP mode Setting stop code acceptor (STPACP) consecutively writing n5H, (where then setting (STP) standby control register (SBYCON) will change mode STOP mode. STOP mode, internal peripheral modules (TBC, WDT, general-purpose 8/16-bit timers, serial ports, etc.) halted. However, SIO3 will operate slave mode been selected. Also, when dual clocks being used, real-time counter (RTC) will operate usual. Because clock supply halted, instructions executed. Instruction execution stops beginning next instruction (following instruction that (STP) SBYCON "1"). STOP mode released when either interrupt occurs input RESn causes reset. When STOP mode released interrupt request, interrupt non-maskable, STOP mode released unconditionally, processes non-maskable interrupt. case maskable interrupt, interrupt released interrupt request flag (IRQ bit) interrupt enable flag bit) have been "1". During STOP mode, following factors generate maskable interrupt requests. Interrupt caused input valid edge external interrupt (EXINT0 EXINT4) Interrupt caused completion SIO3 transfer (during slave mode) Interrupt caused real-time counter output (when dual clocks used) Interrupt from control function
ML66525 Family User's Manual Chapter Control Functions After STOP mode released, master interrupt enable flag (MIE PSW) been "1", processing requested maskable interrupt performed. master interrupt enable flag (MIE PSW) been reset "0", next instruction (following instruction that STOP mode (that (STP) SBYCON "1")) executed. However, STOP mode been during processing non-maskable interrupt routine, STOP mode released interrupt request. After being released, next instruction non-maskable interrupt routine (following instruction that changed mode STOP mode) will executed. interrupt priority (bit (MIPF) EXI2CON "1") STOP mode during high priority interrupt routine, priority interrupt request release STOP mode. However, after release priority interrupt suspended next instruction high priority interrupt routine will executed. interrupt request from high-speed STOP mode (main clock oscillation terminated) causes STOP mode released, operation will continue after waiting oscillation stabilization time main clock (OSCCLK) SBYCON. STOP mode also entered while main clock continues oscillate (quick activating STOP mode). this case, when returning from STOP mode, activation possible without waiting oscillation stabilization time main clock. Figure shows STOP mode timing diagram. STOP mode released reset RESn input, will perform reset processing. RESn input used release STOP mode with main clock oscillation halted, apply level RESn until main clock oscillation stabilizes.
STOP mode Main clock (OSCCLK) M1S1
(Signal that indicates beginning instruction)
SBYCON.STP Interrupt request (NMI,
Instruction execution
Dummy cycle Timer operation
Oscillation *Oscillation halted stabilization time
Dummy cycle Timer operation Port output mode
Instruction execution
Operating state
Timer halted
Port floating (when "1")
Port output mode
Oscillation stabilization time time until main clock starts oscillating, plus time number clocks OST0 OST1.
Figure STOP Mode Timing Diagram (When released interrupt)
ML66525 Family User's Manual Chapter Control Functions
Reset Function
ML66525 family reset following four factors. Low-level input RESn input Execution break (BRK) instruction Overflow watchdog timer (WDT) Opcode trap (OPTRP) execution invalid instruction
Resets caused above four factors processed same except that address vector address loaded program counter different. Table lists vector addresses each reset factor. Table Vector Address Each Reset Factor
Reset factor Reset caused level input RESn input Reset caused execution instruction Reset caused overflow watchdog timer Reset caused opcode trap Vector address 0000 0002 0004 0006
During reset processing, arithmetic registers, control registers, mode registers, etc. initialized, contents address pointed vector address loaded into program counter. initial values different registers, refer Chapter "Special Function Registers (SFRs)". Reset priority over other processing (interrupt processing instruction execution). Since processing aborted, register contents that time cannot guaranteed. Figure shows example reset connection.
Rpull (VDD RESn
Reset processing circuit
Example external circuit manual reset External Internal
Figure Reset Connection Example
ML66525 Family User's Manual Chapter Control Functions
3.3.1 Reset Operation
device requires self-resetting cases that follow: When power-on reset executed, When STOP mode released when specified that main clock oscillation will stopped during STOP mode When main clock oscillation stabilized figures below show time required level applied RESn high level needs applied VDD_CORE VDD_IO pins) operation timing reset. Figure corresponds case above Figure case Table shows port status during input reset signal.
Reset processing cycles) OSCCLK Program execution
RESn
level (longer than oscillation stabilization time) High impedance state Input port
Each port (EAn "H")
cycles
Figure Time Required Level Applied RESn [Notes] reset operation Flash product, processing time maximum will added internal reset processing time cycles). internal state output state device time power-on reset undefined. sure reset device after power turned When power applied disconnected from, VDD_CORE pins, VDD_IO pins, VREF pin, apply disconnect power same time pins.
Reset processing cycles) OSCCLK RESn level (more then cycles) Each port (EAn High impedance state cycles Input port Program execution
Figure Time Required Level Applied RESn
ML66525 Family User's Manual Chapter Control Functions [Note] reset operation Flash product, processing time maximum will added internal reset processing time cycles). Table Port Status During Reset Signal Input
Name Status level P3_1 Pulled-up High level P3_1 High impedance Other ports High impedance
[Note] level, P3_1 automatically change secondary function output states (bus port function) after reset.
Chapter
Memory Control Functions
ML66525 Family User's Manual Chapter Memory Control Functions
Memory Control Functions
Overview There independent memory spaces, program memory space data memory space. following three functions make memory functions easier use.
Window Function This function enables various instructions that have been stored data memory space also used program program memory space. READY Function both memory spaces used external memory, this function allows program insert wait cycles into external memory timing, according access times external memory.
Memory Control Function Registers Table lists summary SFRs memory control functions.
Table Summary SFRs Memory Control Functions
Address 000A 000B 000C 000D 0015
Name EXPANDED Ready Control Register Window Register Ready Control Register Ready Control Register Peripheral Control Register
Symbol (byte) XPDRDY ROMWIN ROMRDY RAMRDY PRPHCON
Symbol (word)
8/16 Operation
Initial value Undefined
Reference page 13-2
[Notes] Addresses consecutive some places. star address column indicates missing bit. details, refer Chapter "Special Function Registers (SFRs)".
ML66525 Family User's Manual Chapter Memory Control Functions
Window Function
window function reads contents program memory space specified window register (ROMWIN), located area, using same address data memory space window. other words, when window function enabled instruction that accesses (reads) data memory space executed, instead accessing (reading) data data memory space, data will accessed (read) same addresses segment that specified program memory space. Compared number instruction cycles required access normal data memory, accessing window once requires additional cycles byte instruction additional cycles word instruction. [Note] window function enabled write instruction executed, that result will guaranteed. However, this case additional cycles will added. Window Register (ROMWIN) window register (ROMWIN) 8-bit register. lower bits indicate start address window upper bits indicate address window. (Bits upper bits must written "1"s.) When program memory space represented hexadecimal number (HEX), each above 4-bit registers specifies upper digit digits. value lower bits zeros, window function will operate. Figure shows configuration ROMWIN.
Address: 000B access: only performed once after reset)
These bits specify start address window. (The upper digit digits when memory space represented hexadecimal format (HEX).) These bits specify address window. (The upper digit digits when memory space represented hexadecimal format (HEX).)
ROMWIN reset (undefined)
Bits must "1".
Figure ROMWIN Configuration
ML66525 Family User's Manual Chapter Memory Control Functions internal located data memory area specified window, data memory's internal will have priority. data memory space specified window area cannot used normal external data memory. window start address 2000H above segment 1000H above segments address selected among four addresses listed Table 4-2.
Table Address List
ROMWIN address 3FFF 7FFF BFFF FFFF
When reset (RESn signal input, execution instruction, overflow watchdog timer, opcode trap), ROMWIN undefined window function does operate. ROMWIN written once after reset. Additional writing attempts will ignored. Therefore, after window function been only modified after reset. ROMWIN read many times desired. [Note] relative sizes start address address written ROMWIN evaluated hardware. Therefore, sure that within program.
ML66525 Family User's Manual Chapter Memory Control Functions
READY Function
that memory general-purpose with slow access speeds connected externally, wait cycles specified inserted during external memory accesses. There registers that specify number wait cycles, ready control register (ROMRDY) ready control register (RAMRDY). ROMRDY specifies wait cycles when external mode used program memory space. RAMRDY specifies wait cycles when data memory space extended externally. Memory divided into areas address 0000H 7FFFH 8000H FFFFH, wait cycles specified each area. Table lists number wait cycles that specified RAMRDY ROMRDY.
Table Wait Cycles
Control register ROMRDY RAMRDY Number wait cycles inserted
4.4.1 Ready Control Register (ROMRDY)
ready control register (ROMRDY) consists bits. ROMRDY specifies number wait cycles with bits (ORDY0 ORDY1). ROMRDY read from written program. However, write operations invalid bits Also, writing bits they must written "0". When read, bits always bits "0". When reset (RESn signal input, execution instruction, overflow watchdog timer, opcode trap), ROMRDY becomes largest number wait cycles set. Therefore, three wait cycles will added inserted when external program memory accessed. Figure shows configuration ROMRDY.
ML66525 Family User's Manual Chapter Memory Control Functions
ROMRDY reset
Address: 000C access:
ORDY1 ORDY0
ORDY added inserted during external program memory access cycles cycle cycles cycles
indicates nonexistent bit. When read, value will "1". indicates that value must always written this bit. When read, value will "0". cycle CPUCLK.
Number wait cycles
Figure ROMRDY Configuration
4.4.2 Ready Control Register (RAMRDY)
ready control register (RAMRDY) consists bits. Bits (ARDY00 ARDY02) RAMRDY specify number wait cycles external area from 0000H 7FFFH. Bits (ARDY10 ARDY12) specify number wait cycles external area from 8000H FFFFH. number wait cycles uniform segments settings divided into areas 0000H 7FFFH (segment 2000H 7FFFH) 8000H FFFFH. RAMRDY read from written program. However, write operations invalid bits When read, bits always "1". When reset (RESn signal input, execution instruction, overflow watchdog timer, opcode trap), RAMRDY becomes largest number wait cycles set. Therefore, seven wait cycles will added inserted when external data memory accessed. Figure shows configuration RAMRDY. [Note] contrast internal data memory access, when external data memory accessed, cycles automatically inserted each byte access. RAMRDY specifies number cycles inserted addition cycles that inserted automatically inserted.
ML66525 Family User's Manual Chapter Memory Control Functions
RAMRDY reset
Address: 000D access:
ARDY12 ARDY11 ARDY10
ARDY02 ARDY01 ARDY00
ARDY0
Number wait cycles added inserted when accessing external data memory 0000H 7FFFH
cycles cycle cycles cycles cycles cycles cycles cycles
Number wait cycles added inserted when accessing external data memory 8000H FFFFH
ARDY1
cycles cycle cycles cycles cycles cycles cycles cycles indicates nonexistent bit. When read, value will "1". cycle CPUCLK.
Figure RAMRDY Configuration
ML66525 Family User's Manual Chapter Memory Control Functions
EXPANDED Ready Control Register (XPDRDY)
EXPANDED ready control register (XPDRDY) consists bits. Bits (XRDY0 XRDY2) XPDRDY specify number wait cycles EXPANDED area from 1200H 1FFFH. XPDRDY read from written program. However, write operations invalid bits When read, bits always "1". When reset (RESn signal input, execution instruction, overflow watchdog timer, opcode trap), RAMRDY becomes largest number wait cycles set. Therefore, seven wait cycles will added inserted when EXPANDED area accessed. Figure shows configuration XPDRDY.
XRDY2
Address: 000A access:
XPDRDY reset
XRDY1 XRDY0
XRDY
Number wait cycles added inserted when accessing EXPANDED area 1200H 1FFFH
cycles cycle cycles cycles cycles cycles cycles cycles
indicates nonexistent bit. When read, value will "1". cycle CPUCLK.
Figure XPDRDY Configuration [Notes] explanation below, read XRDY (XRDY2, XRDY1, XRDY0).) When main clock oscillates MHz: XRDY recommended. XRDY value from media control function used data read. When main clock oscillates MHz: XRDY recommended. XRDY value from Setting disabled. When main clock oscillates MHz: XRDY recommended. XRDY value from Setting disabled. emulator, media control function used data read, XRDY value from
Chapter
Port Functions
ML66525 Family User's Manual Chapter Port Functions
Port Functions
Overview ML66525 family pins port, pins input-only port output-only port.
Each individual ports specified input output. ports have internal pull-up resistors that programmed each individual bit. (Excluding P9_0) configured inputs, pins high impedance inputs. configured outputs, they push-pull outputs. addition port function, some ports assigned internal function (secondary function). Table shows port function summary.
ML66525 Family User's Manual Chapter Port Functions Table Port Function Summary
Type Number Secondary function P0_0 P0_7 External memory access (I/O) P1_0 P1_7 External memory access (output) P2_0 P2_3 External memory access (output) P3_1 External program memory access PSENn (output) Port P3_2* External data memory access (output) P3_3 External data memory access (output) Port P4_0 P4_7 External memory access (output) Port P6_0 P6_3 External interrupt EXINT0 EXINT3 (input) Port P7_6, P7_7 output PWM0OUT, PWM1OUT (output) P8_0 SIO1 receive data input RXD1 (input) P8_1 SIO1 transmit data output TXD1 (output) Port P8_2 SIO1 receive clock RXC1 (I/O) P8_3 SIO1 transmit clock TXC1 (I/O) Port P9_0, P9_1 External interrupt EXINT4, EXINT5 (input) P10_0 SIO3 transmit-receive clo
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