pixels matrix driver Rev. June 2008 Product data sheet PCF88
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PCF8811
pixels matrix driver
Rev. June 2008 Product data sheet
PCF8811 low-power CMOS controller driver, designed drive graphic display rows columns graphic display rows columns icon symbols. necessary functions display provided single chip, including on-chip generation supply bias voltages, resulting minimum external components power consumption. PCF8811 interface microcontrollers parallel bus, serial I2C-bus interface.
Features
Single-chip controller/driver column outputs Display data icons (row used icons extended command when icon rows enabled) power consumption; suitable battery operated systems 8-bit parallel interface, 4-line Serial Peripheral Interface (SPI) high-speed I2C-bus On-chip: Configurable voltage multiplier generating supply voltage VLCD; external VLCD also possible Linear temperature compensation VLCD; programmable temperature coefficients (extended command set); fixed temperature coefficient which default programming (basic command set) Generation intermediate bias voltage Oscillator requires external components calibration VLCD accurate frame frequency External reset input External clock input possible Multiplex rate: 1:16 1:80 steps when icon used, with icon steps used Logic supply voltage range VDD1 VSS: High-voltage multiplier supply voltage range VDD2, VDD3 VSS: Display supply voltage range VLCD VSS:
Semiconductors
PCF8811
pixels matrix driver
Programmable bottom pads mirroring; compatibility with both Tape Carrier Packages (TCP) Chip-On-Glass (COG) applications (extended command set) Status read, which allows chip recognition content checking some registers Start address line which allows, instance, scrolling displayed image Programmable display pointers variable display sizes Slim chip layout, suited applications Temperature range: Tamb CMOS compatible inputs
Applications
Automotive displays Telecom equipment Portable instruments Point-of-sale terminals
Ordering information
Table Ordering information Package Name PCF8811U/2DA/1 PCF8811MU/2DA/1 Description chip with bumps tray (not covered Motif license agreement) chip with bumps tray (sold under license from Motif) Version Type number
PCF8811_4
B.V. 2008. rights reserved.
Product data sheet
Rev. June 2008
Semiconductors
PCF8811
pixels matrix driver
Block diagram
VDD1 VDD2 VDD3 C127
COLUMN DRIVERS
DRIVERS
VLCDIN
BIAS VOLTAGE GENERATOR
DATA PROCESSING
VSS1 VSS2 VOTPPROG VLCDSENSE VLCDOUT MF[2:0]
ORTHOGONAL FUNCTION GENERATOR
RESET HIGH VOLTAGE GENERATOR DISPLAY DATA BITS OSCILLATOR
TIMING GENERATOR ADDRESS COUNTER DISPLAY ADDRESS COUNTER
COMMAND DECODER
PCF8811
BUFFER PARALLEL/SERIAL/I2C-BUS INTERFACE
mgw732
DB7/SDATA
DB5/SDO
DB3/SA1
DB2/SA0
Block diagram PCF8811
PCF8811_4
SCLH/SCE
SDAHOUT
DB6/SCLK
VOS[4:0]
PS[2:0]
E/RD
SDAH
B.V. 2008. rights reserved.
Product data sheet
Rev. June 2008
Semiconductors
PCF8811
pixels matrix driver
Pinning information
Pinning
VLCDSENSE
VLCDOUT
VLCDIN
VDD3
VDD2
VOS0 VOS1 VOS2 VOS3 VOS4
PCF8811
DB7/SDATA DB6/SCLK DB5/SDO DB3/SA1 DB2/SA0 VDD(tie-off)(1) E/RD R/W/WR
VOTPPROG
SCLH/SCE
SDAHOUT
SDAH
VSS(tie-off)(1)
VDD1
VSS2
VSS1
mgw769
VSS(tie-off) VDD(tie-off) used local tie-offs.
Bonding locations PCF8811 (bottom view)
PCF8811_4
B.V. 2008. rights reserved.
Product data sheet
Rev. June 2008
Semiconductors
PCF8811
pixels matrix driver
allocation table Symbol VSS(tie-off) SDAHOUT SDAH SCLH/SCE VOTPPROG R/W/WR E/RD VDD(tie-off) DB2/SA0 DB3/SA1 DB5/SDO Symbol DB6/SCLK DB7/SDATA VDD1 VDD2 VDD3 VSS1 VSS2 VOS4 VOS3 VOS2 VOS1 VOS0 VLCDOUT VLCDSENSE VLCDIN R79[1] C127
Table
Duplicate R79.
12.409 2.271
PCF8811
center
pitch
center
mgw768 001aag914
Alignment marker
Chip dimensions
PCF8811_4
B.V. 2008. rights reserved.
Product data sheet
Rev. June 2008
Semiconductors
PCF8811
pixels matrix driver
Bonding chip dimensions Row/Column side (µm) 51.84 42.84 29.9 98.5 (±3) (±25) (mm)[1] (mm)[2] 12.41 2.27 Interface side (µm) 54.0 32.2 93.5 (±3)
Table pitch
size (aluminium) Bump dimensions Wafer thickness (excluding bumps) size size
12.45 2.31
Fabrication identification starts with nnnnnn, where represents number between Fabrication identification starts with AXnnnn, where represents letter represents number between
Table
Alignment marker position[1] (µm) 5995 -5904 (µm) 1017 1017
position each pad, Table
description
Table Bonding description coordinates represent position center each with respect center (x/y chip; Figure Symbol VSS(tie-off)
PCF8811_4
(µm) 6092.00 5995.00 5876.00 5822.00 5768.00 5714.00 5660.00 5390.00 5012.00 4850.00 4688.00 4526.00 4364.00 4094.00 3932.00 3770.00 3608.00 3446.00
(µm) 1030.00 1017.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00
Description dummy_slanted alignment mark dummy dummy dummy dummy dummy dummy manufacturer device input manufacturer device input manufacturer device input device recognition input oscillator input extended command input parallel/serial/I2C-bus data selection input parallel/serial/I2C-bus data selection input parallel/serial/I2C-bus data selection input B.V. 2008. rights reserved.
Product data sheet
Rev. June 2008
Semiconductors
PCF8811
pixels matrix driver
Table Bonding description .continued coordinates represent position center each with respect center (x/y chip; Figure Symbol SDAHOUT SDAH SDAH SCLH/SCE SCLH/SCE VOTPPROG VOTPPROG VOTPPROG R/W/WR E/RD VDD(tie-off) DB2/SA0 DB3/SA1 DB5/SDO DB6/SCLK DB7/SDATA VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD3
PCF8811_4
(µm) 2960.00 2420.00 2366.00 1826.00 1772.00 1664.00 1610.00 1556.00 1448.00 1232.00 962.00 800.00 638.00 476.00 314.00 152.00 -10.00 -172.00 -334.00 -550.00 -712.00 -874.00 -928.00 -982.00 -1036.00 -1090.00 -1144.00 -1198.00 -1252.00 -1306.00 -1360.00 -1414.00 -1468.00 -1522.00 -1576.00 -1630.00 -1684.00 -1738.00
(µm) 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00
Description I2C-bus data output I2C-bus data input I2C-bus data input I2C-bus clock input chip enable active (6800 interface) I2C-bus clock input chip enable active (6800 interface) supply voltage (can combined with SCLH/SCE) supply voltage (can combined with SCLH/SCE) supply voltage (can combined with SCLH/SCE) external reset input data command active input read write active input (6800 interface) clock enable read active input (6800 interface) parallel data input/output parallel data input/output parallel data input/output I2C-bus slave address input parallel data input/output I2C-bus slave address input parallel data input/output parallel data input/output serial data output parallel data input/output serial clock input parallel data input/output serial data input supply voltage (logic) supply voltage (logic) supply voltage (logic) supply voltage (logic) supply voltage (logic) supply voltage (logic) supply voltage internal voltage multiplier supply voltage internal voltage multiplier supply voltage internal voltage multiplier supply voltage internal voltage multiplier supply voltage internal voltage multiplier supply voltage internal voltage multiplier supply voltage internal voltage multiplier supply voltage internal voltage multiplier supply voltage internal voltage multiplier supply voltage internal voltage multiplier supply voltage internal voltage multiplier
B.V. 2008. rights reserved.
Product data sheet
Rev. June 2008
Semiconductors
PCF8811
pixels matrix driver
Table Bonding description .continued coordinates represent position center each with respect center (x/y chip; Figure Symbol VDD3 VDD3 VDD3 VDD3 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VOS4 VOS3 VOS2 VOS1 VOS0 VLCDOUT VLCDOUT VLCDOUT VLCDOUT VLCDOUT
PCF8811_4
(µm) -1792.00 -1846.00 -1900.00 -1954.00 -2062.00 -2116.00 -2170.00 -2224.00 -2278.00 -2332.00 -2386.00 -2440.00 -2494.00 -2548.00 -2602.00 -2656.00 -2710.00 -2764.00 -2818.00 -2872.00 -2926.00 -2980.00 -3034.00 -3088.00 -3250.00 -3304.00 -3466.00 -3628.00 -3790.00 -4060.00 -4222.00 -4384.00 -4654.00 -4816.00 -4924.00 -4978.00 -5032.00 -5086.00 -5140.00
(µm) 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00
Description supply voltage internal voltage multiplier supply voltage internal voltage multiplier supply voltage internal voltage multiplier supply voltage internal voltage multiplier ground ground ground ground ground ground ground ground ground ground ground voltage multiplier ground voltage multiplier ground voltage multiplier ground voltage multiplier ground voltage multiplier ground voltage multiplier ground voltage multiplier ground voltage multiplier ground voltage multiplier ground voltage multiplier test input test input test input test input test input VLCD offset input VLCD offset input VLCD offset input VLCD offset input VLCD offset input voltage multiplier output voltage multiplier output voltage multiplier output voltage multiplier output voltage multiplier output
B.V. 2008. rights reserved.
Product data sheet
Rev. June 2008
Semiconductors
PCF8811
pixels matrix driver
Table Bonding description .continued coordinates represent position center each with respect center (x/y chip; Figure Symbol VLCDOUT VLCDOUT VLCDOUT VLCDOUT VLCDSENSE VLCDIN VLCDIN VLCDIN VLCDIN VLCDIN VLCDIN VLCDIN
PCF8811_4
(µm) -5194.00 -5248.00 -5302.00 -5356.00 -5410.00 -5464.00 -5518.00 -5572.00 -5626.00 -5680.00 -5734.00 -5788.00 -5904.00 -6004.00 -6058.00 -6112.00 -6129.24 -6077.40 -6025.56 -5973.72 -5921.88 -5870.04 -5818.20 -5766.36 -5714.52 -5662.68 -5610.84 -5559.00 -5507.16 -5455.32 -5403.48 -5351.64 -5299.80 -5247.96 -5196.12 -5144.28 -5092.44 -5040.60 -4988.76
(µm) 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1030.00 1017.00 1030.00 1030.00 1030.00 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50
Description voltage multiplier output voltage multiplier output voltage multiplier output voltage multiplier output voltage multiplier regulation input supply voltage supply voltage supply voltage supply voltage supply voltage supply voltage supply voltage alignment mark dummy dummy dummy dummy dummy dummy driver output (R79 icon when icon enabled) driver output driver output driver output driver output driver output driver output driver output driver output driver output driver output driver output driver output driver output driver output driver output driver output driver output driver output driver output
B.V. 2008. rights reserved.
Product data sheet
Rev. June 2008
Semiconductors
PCF8811
pixels matrix driver
Table Bonding description .continued coordinates represent position center each with respect center (x/y chip; Figure Symbol
PCF8811_4
(µm) -4936.92 -4885.08 -4833.24 -4781.40 -4729.56 -4677.72 -4625.88 -4574.04 -4522.20 -4470.36 -4418.52 -4366.68 -4314.84 -4263.00 -4211.16 -4159.32 -4107.48 -4055.64 -4003.80 -3951.96 -3900.12 -3640.92 -3589.08 -3537.24 -3485.40 -3433.56 -3381.72 -3329.88 -3278.04 -3226.20 -3174.36 -3122.52 -3070.68 -3018.84 -2967.00 -2915.16 -2863.32 -2811.48 -2759.64
(µm) -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50
Description driver output driver output driver output driver output driver output driver output driver output driver output driver output driver output driver output driver output driver output driver output driver output driver output driver output driver output driver output driver output duplicate column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output
B.V. 2008. rights reserved.
Product data sheet
Rev. June 2008
Semiconductors
PCF8811
pixels matrix driver
Table Bonding description .continued coordinates represent position center each with respect center (x/y chip; Figure Symbol
PCF8811_4
(µm) -2707.80 -2655.96 -2604.12 -2552.28 -2500.44 -2448.60 -2396.76 -2344.92 -2293.08 -2241.24 -2189.40 -2137.56 -2085.72 -2033.88 -1878.36 -1826.52 -1774.68 -1722.84 -1671.00 -1619.16 -1567.32 -1515.48 -1463.64 -1411.80 -1359.16 -1308.12 -1256.28 -1204.44 -1152.60 -1100.76 -1048.92 -997.08 -945.24 -893.40 -841.56 -789.72 -737.88 -686.04 -634.20
(µm) -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50
Description column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output
B.V. 2008. rights reserved.
Product data sheet
Rev. June 2008
Semiconductors
PCF8811
pixels matrix driver
Table Bonding description .continued coordinates represent position center each with respect center (x/y chip; Figure Symbol
PCF8811_4
(µm) -582.36 -530.52 -478.68 -426.84 -375.00 -323.16 -271.32 -115.80 -63.96 -12.12 39.72 91.56 143.40 195.24 247.08 298.92 350.76 402.60 454.44 506.28 558.12 609.96 661.80 713.64 765.48 817.32 869.16 921.00 972.84 1024.68 1076.52 1128.36 1180.20 1232.04 1283.88 1335.72 1387.56 1439.40 1491.24
(µm) -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50
Description column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output
B.V. 2008. rights reserved.
Product data sheet
Rev. June 2008
Semiconductors
PCF8811
pixels matrix driver
Table Bonding description .continued coordinates represent position center each with respect center (x/y chip; Figure Symbol C100 C101 C102 C103 C104 C105 C106 C107 C108 C109 C110 C111 C112 C113 C114 C115 C116 C117 C118 C119 C120 C121 C122 C123 C124 C125 C126 C127
PCF8811_4
(µm) 1646.76 1698.60 1750.44 1802.28 1854.12 1905.96 1957.80 2009.64 2061.48 2113.32 2165.16 2217.00 2268.84 2320.68 2372.52 2424.36 2476.20 2528.04 2579.88 2631.72 2683.56 2735.40 2787.24 2839.08 2890.92 2942.76 2994.60 3046.44 3098.28 3150.12 3201.96 3253.80 3461.16 3513.00 3564.84 3616.68 3668.52 3720.36 3772.20
(µm) -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50
Description column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output column driver output driver output driver output driver output driver output driver output driver output driver output
B.V. 2008. rights reserved.
Product data sheet
Rev. June 2008
Semiconductors
PCF8811
pixels matrix driver
Table Bonding description .continued coordinates represent position center each with respect center (x/y chip; Figure Symbol PCF8811_4
(µm) 3824.04 3875.88 3927.72 3979.56 4031.40 4083.24 4135.08 4186.92 4238.76 4290.60 4342.44 4394.28 4446.12 4497.96 4549.80 4601.64 4653.48 4705.32 4757.16 4809.00 4860.84 4912.68 4964.52 5016.36 5068.20 5120.04 5171.88 5223.72 5275.56 5327.40 5379.24 5431.08 5482.92 5638.44 5690.28 5742.12 5793.96 5845.80 5897.64
(µm) -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50 -1032.50
Description driver output driver output driver output driver output driver output driver output driver output driver output driver output driver output driver output driver output driver output driver output driver output driver output driver output driver output driver output driver output driver output driver output driver output driver output driver output driver output driver output driver output driver output driver output driver output driver output driver output dummy dummy dummy dummy dummy dummy
B.V. 2008. rights reserved.
Product data sheet
Rev. June 2008
Semiconductors
PCF8811
pixels matrix driver
Table Bonding description .continued coordinates represent position center each with respect center (x/y chip; Figure Symbol (µm) 5949.48 6001.32 6053.16 6105.00 (µm) -1032.50 -1032.50 -1032.50 -1032.50 Description dummy dummy dummy dummy
Functional description
functions
7.1.1 R79: driver outputs
These pads output display signals.
7.1.2 C127: column driver signals
These pads output display column signals.
7.1.3 VSS1 VSS2: negative power supply rails
VSS2 voltage multiplier These supply rails must connected together
7.1.4 VDD1 VDD3: positive power supply rails
VDD2 VDD3 supply voltages internal voltage multiplier VDD2 VDD3 have same voltage connected together outside
chip; Section
VDD1 used supply rest chip VDD1 connected together with VDD2 VDD3 internal voltage multiplier used then pads VDD2 VDD3 must
connected VDD1; Section
case that VDD1, VDD2 VDD3 connected together, care must taken with
respect supply voltage range; Section
7.1.5 VOTPPROG: power supply
Supply voltage programming; Section VOTPPROG combined with SCLH/SCE order reduce external connections.
7.1.6 VLCDOUT, VLCDIN, VLCDSENSE: power supply
Positive power supply liquid crystal display.
internal VLCD multiplier used, then three inputs must connected together VLCD multiplier disabled external voltage supplied VLCDIN, then
VLCDOUT must left open-circuit VLCDSENSE must connected VLCDIN
VDD2 VDD3 should applied according specified voltage range
PCF8811_4 B.V. 2008. rights reserved.
Product data sheet
Rev. June 2008
Semiconductors
PCF8811
pixels matrix driver
PCF8811 Power-save mode, external supply voltage
switched
7.1.7 test pads
must connected VSS. must left open-circuit. These test pads accessible user.
7.1.8
Manufacturer device pads. (Manufacturer Semiconductors).
7.1.9
Device recognition pad; Table
7.1.10 VOS4 VOS0
These input pads enable calibration offset programmed VLCD; Equation Equation Section 12.10. VOS4 VOS0 must connected VDD1 VSS1.
7.1.11 EXT: extended command
Input select basic command extended command set. Must connected module have only command enabled; Table
Table Command selection Level (VSS1) HIGH (VDD1) Description basic command extended command
Remark: Semiconductors recommends that extended command used.
7.1.12 PS0,
Parallel/serial/I2C-bus interface selection; Table
Table PS[2:0] Interface selection Interface 3-line 4-line operation 6800 parallel interface high speed I2C-bus interface 3-line serial interface
7.1.13
Input select either data command input. used 3-line serial interface, 3-line I2C-bus interface must connected VDD1 VSS1.
PCF8811_4
B.V. 2008. rights reserved.
Product data sheet
Rev. June 2008
Semiconductors
PCF8811
pixels matrix driver
7.1.14 R/W/WR
Input select read write mode when 6800 parallel interface selected. used serial I2C-bus mode must connected VDD1 VSS1.
7.1.15 E/RD
clock enable input 6800 parallel bus. used serial I2C-bus interface must connected VDD1 VSS1.
7.1.16 SCLH/SCE
Input select chip allowing data commands clocked input serial clock when I2C-bus interface selected.
7.1.17 SDAH
I2C-bus serial data input. When used, must connected VDD1 VSS1.
7.1.18 SDAHOUT
SDAHOUT serial data acknowledge output I2C-bus interface.
connecting SDAHOUT SDAH externally, SDAH line becomes fully I2C-bus
compatible
acknowledge output separated from serial data line following
reasons: applications where track resistance from SDAHOUT system SDAH line significant, potential divider generated pull-up resistor track resistance possible that during acknowledge cycle PCF8811 will able create valid level splitting SDAH input from SDAHOUT output device could used mode that ignores acknowledge applications where acknowledge cycle required, necessary minimize track resistance from SDAHOUT system SDAH line guarantee valid level
When used must connected VDD1 VSS1.
7.1.19
These input/output lines used several interfaces described below. When used serial interface I2C-bus interface they must connected VDD1 VSS1. 7.1.19.1 (parallel interface) 8-bit bidirectional bus. MSB. 7.1.19.2 DB7, (serial interface)
used serial input data (SDATA) when serial interface selected (SCLK) used serial input clock when serial interface selected used serial output serial interface (SDO)
PCF8811_4 B.V. 2008. rights reserved.
Product data sheet
Rev. June 2008
Semiconductors
PCF8811
pixels matrix driver
7.1.19.3
(I2C-bus interface) respectively inputs when I2C-bus interface selected used that four PCF8811s distinguished I2C-bus interface.
7.1.20 OSC: oscillator
When on-chip oscillator used this input must connected VDD1 external clock signal used, connected this input oscillator external clock both inhibited connecting
VSS1, display clocked left Direct Current (DC) state. avoid display, chip should always into Power-down mode before stopping clock
7.1.21 RES: reset
This signal will reset device must applied properly initialize chip. signal active LOW.
Block diagram functions
Figure block diagram layout.
7.2.1 Oscillator
on-chip oscillator provides clock signal display system. external components required, input must connected VDD1. external clock signal, used, connected this input.
7.2.2 Address counter
address counter assigns addresses display data writing. address X[6:0] address Y[3:0] separately.
7.2.3 Display data
PCF8811 contains static which stores display data.
divided into banks bytes bit) icon (when enabled) always located bank During access, data transferred parallel interface, serial
interface I2C-bus interface
There direct correspondence between address column output
number
7.2.4 Timing generator
timing generator produces various signals required drive internal circuitry. Internal chip operation affected operations data bus.
PCF8811_4
B.V. 2008. rights reserved.
Product data sheet
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Semiconductors
PCF8811
pixels matrix driver
7.2.5 Display address counter
display generated reading content rows simultaneously, depending current selected display size. This content processed with corresponding orthogonal functions generates signals switching pixels display according content. value defines number rows which simultaneously selected. possible value display sizes manually Table display status (all dots on/off normal/inverse video) bits DON, command display control; Table
7.2.6 column drivers
PCF8811 contains column drivers, which connect appropriate bias voltages sequence display accordance with data displayed.
Addressing
Data written bytes matrix PCF8811 shown Figure display matrix bits. columns addressed address pointer. address ranges are: (111 1111), (1001). address represents bank number. effective addresses programmed such order PCF8811 with different display sizes, without additional loading microprocessor. Addresses outside these ranges allowed. icon when enabled always therefore located bank
PCF8811_4
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Product data sheet
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Semiconductors
PCF8811
pixels matrix driver
DPRAM bank
bank
bank
bank
bank
mgw734
DDRAM display mapping
Display data structure
mode storing data into data depends selected command set.
8.1.1 Basic command
After write operation column address counter address) auto-increments one, wraps zero after last column written. number columns address) after which wrap around must occur programmed.
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address counter does auto-increment basic command set. counter stops when complete bank been written this case address counter must set; address, Table write next bank, Figure When only part used, both (Xmax) (Ymax) addresses set. data order basic command defined Figure
address address
mgw735
Sequence writing data bytes into (basic command set)
8.1.2 Extended command
8.1.2.1 Horizontal/vertical addressing different address modes possible with extended command set: horizontal address mode vertical address mode. horizontal address mode address increments after each byte. After last address, wraps around increments address next row; Figure number columns (last address) after which wrap around must occur programmed. Figure seen that address programmed 127, address programmed With Xmax Ymax addresses programmed while whole being used. vertical addressing mode address increments after each byte. After last address wraps around increments address next column; Figure last address, after which wraps programmed. Figure seen that address programmed 127, address programmed With Xmax Ymax addresses programmed while whole being used. After very last address, address pointers wrap around address both horizontal vertical addressing modes.
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pixels matrix driver
address
1024 1025 1026 1152 1153 1154 address 1279
mgw736
Sequence writing data bytes into with horizontal addressing; (extended command set)
address
1279 address
mgw737
Sequence writing data bytes into with vertical addressing; (extended command set)
8.1.2.2
Data order data order (DOR) defines order (LSB top) writing into RAM; Figure Figure This feature only available extended command set.
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pixels matrix driver
mgw738
byte organization, (extended command set)
mgw739
byte organization, (extended command set)
8.1.2.3
Features available both command sets Mirror (MX): allows horizontal mirroring: when address space mirrored; address then located right side (Xmax) display; Figure When mirroring disabled address located left side (column display; Figure
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pixels matrix driver
address address
mgw740
format addressing; (both command sets)
address address
mgw741
format addressing; (both command sets)
Mirror (MY): allows vertical mirroring: when address space mirrored; address then located bottom display; Figure When mirroring disabled address located display; Figure icon row, when enabled, always located bank
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PCF8811
pixels matrix driver
address address
mgw742
format addressing; (both command sets)
address address
mgw743
format addressing; (both command sets)
Parallel interface
parallel interface, which selected, 6800 series 8-bit bidirectional interface communication between microcontroller driver chip. selection this interface achieved with pads PS[2:0]; Section 7.1.12.
6800 series parallel interface
interface functions 6800 series parallel interface given Table
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pixels matrix driver
6800 series parallel interface functions R/W/WR Operation command data write read status register display data write none
Table
parallel interface timing diagram 6800 series given Section 16.1, Figure Figure timing diagrams differ because Figure clock connected enable input. Figure clock connected chip enable input (SCE) enable input tied HIGH.
Serial interfacing (SPI serial interface)
Communication with microcontroller also occur clock-synchronized Serial Peripheral Interface (SPI). possible select between either 3-line (SPI serial interface) 4-line serial peripheral interface. Selection achieved PS[2:0]; Section 7.1.12).
10.1 Serial peripheral interface lines
serial peripheral interface 3-line 4-line interface communication between microcontroller driver chip. lines are:
(chip enable) SCLK (serial clock) SDATA (serial data)
4-line serial peripheral interface separate line added. PCF8811 connected serial data (SDA) microcontroller connecting pads SDATA (data input) (data output) together.
10.1.1 Write mode
display data/command indication controlled either software select pad. When used, display data transmitted when HIGH, command data transmitted when LOW; Figure Figure When used, display data length instruction used indicate that specific number display data bytes 255) transmitted; Figure next byte after display data string handled instruction command. When 3-line interface used, display data/command controlled software. pulled HIGH during serial display data stream, interrupted byte invalid data previously transmitted data valid. next byte received will handled instruction command; Figure
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SCLK
SDATA
mgw744
Serial protocol: transmission byte
SCLK
SDATA
mgw745
Serial protocol: transmission several bytes
SCLK last data instruction
SDATA
data data
display length instruction length data (two bytes)
display data string
mgw746
Transmission several bytes
SCLK
SDATA
data data data data data data display data string
mgw747
instruction
Transmission interrupted
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pixels matrix driver
10.1.2 Read mode (only extended command set)
read mode interface means that microcontroller reads data from PCF8811. microcontroller first send command (the read status command) then PCF8811 will respond transmitting data line. After that, required HIGH; Figure PCF8811 samples SDATA data rising SCLK edges, shifts data falling SCLK edges. microcontroller supposed read data rising SCLK edges. After read status command been sent, SDATA line must 3-state later then falling SCLK edge last bit; Figure Serial interface timing diagrams shown Section 16.2.
SCLK
SDATA
instruction
read data
mgw748
Read mode 3-line 4-line
10.2 Serial interface (3-line)
serial interface also 3-line bidirectional interface communication between microcontroller driver chip. lines are:
(chip enable) SCLK (serial clock) SDATA (serial data)
PCF8811 connected microcontroller lines: SDATA (data input) (data output) which connected together.
10.2.1 Write mode
write mode interface means that microcontroller writes commands data PCF8811. Each data packet contains control (D/C) transmission byte. LOW, following byte interpreted command byte. instruction shown Table HIGH, following byte stored display data RAM. After every data byte address counter incremented automatically. Figure shows general format write mode definition transmission byte.
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pixels matrix driver
instruction sent order PCF8811; transmitted first. serial interface initialized when HIGH. this state, SCLK clock pulses have effect power consumed serial interface. falling edge enables serial interface indicates start data transmission. Figure Figure Figure show protocol write mode:
when HIGH, SCLK clocks ignored; during HIGH time serial
interface initialized
SCLK must falling edge; Figure SDATA sampled rising edge SCLK indicates, whether byte command (D/C data (D/C
sampled first rising SCLK edge
stays after last data/command byte, serial interface
receives next byte next rising edge SCLK; Figure
reset pulse interrupts transmission. data being written into
corrupted. registers cleared. after rising edge RES, serial interface ready receive data/command byte; Figure
Transmission Byte (TB) (command byte data byte)
mgu278
Serial data stream; write mode
SCLK
SDATA
001aai348
Write mode: control followed transmission byte
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PCF8811
pixels matrix driver
SCLK
SDATA
001aai349
Write mode: transmission several bytes
SCLK
SDATA
001aai350
Write mode: interrupted reset (RES)
10.2.2 Read mode (only extended command set)
read mode interface means that microcontroller reads data from PCF8811. microcontroller first send command (the read status command) then following byte transmitted opposite direction using SDO; Figure After that, required HIGH before command sent. PCF8811 samples SDATA data rising SCLK edges, shifts data falling SCLK edges. Thus microcontroller supposed read data rising SCLK edges. After read status command been sent, SDATA line must 3-state later then falling SCLK edge last bit; Figure read shorter than others because terminated rising SCLK edge; Figure last rising SCLK edge sets 3-state after delay time
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Semiconductors
PCF8811
pixels matrix driver
SCLK
SDATA
001aai351
Read mode serial interface 3-line
I2C-bus interface
11.1 Characteristics I2C-bus (Hs-mode)
I2C-bus Hs-mode bidirectional, two-line communication between different modules with speeds MHz. only difference between Hs-mode slave devices F/S-mode slave devices speed which they operate. Because this buffers SCLH SDAH have open-drain outputs. This same I2C-bus master devices which have open-drain SDAH output combination open-drain, pull-down current source pull-up circuits SCLH output. Only current source master enabled time, only during Hs-mode. Both lines must connected positive supply pull-up resistor. Data transfer initiated only when busy.
11.1.1 System configuration
system configuration shown Figure Definitions I2C-bus terminology:
transmitter: device which sends data receiver: device which receives data from master: device which initiates transfer, generates clock signals terminates
transfer
slave: device addressed master multi-master: more than master attempt control same time
without corrupting message
arbitration: procedure ensure that, more than master simultaneously tries
control bus, only allowed message corrupted
synchronization: procedure synchronize clock signals more devices
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pixels matrix driver
MASTER TRANSMITTER/ RECEIVER
SLAVE RECEIVER
SLAVE TRANSMITTER/ RECEIVER
MASTER TRANSMITTER
MASTER TRANSMITTER/ RECEIVER
mga807
System configuration
11.1.2 transfer
data transferred during each clock pulse; Figure data line must remain stable during HIGH period clock pulse changes data line this time will interpreted control signal.
data line stable; data valid change data allowed
mbc621
transfer
11.1.3 Start stop conditions
Both data clock lines remain HIGH when busy. HIGH-to-LOW transition data line, while clock HIGH defined START condition (S). LOW-to-HIGH transition data line while clock HIGH defined STOP condition (P). START STOP conditions shown Figure
START condition STOP condition
mbc622
Definition START STOP conditions
11.1.4 Acknowledge
Each byte eight bits followed acknowledge bit; Figure acknowledge HIGH signal transmitter during which time master generates extra acknowledge-related clock pulse. slave receiver which addressed must generate acknowledge after reception each byte. master receiver must also generate acknowledge after reception each byte that been clocked slave transmitter. device that acknowledges must pull-down line during acknowledge clock pulse, that line stable during HIGH period
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pixels matrix driver
acknowledge-related clock pulse (set-up hold times must taken into consideration). master receiver must signal end-of-data transmitter generating acknowledge last byte that been clocked slave. this event transmitter must leave data line HIGH enable master generate STOP condition.
data output transmitter acknowledge data output receiver acknowledge from master START condition clock pulse acknowledgement
mbc602
Acknowledge I2C-bus
11.2 I2C-bus Hs-mode protocol
PCF8811 slave receiver/transmitter. data read from device, SDAH must connected, otherwise SDAH unused. Hs-mode only commence after following conditions:
START condition 8-bit master code (0000 1xxx) Not-acknowledge
master code functions: allows arbitration synchronization between competing masters F/S-mode speeds, resulting winner. master code also indicates beginning Hs-mode transfer. These conditions shown Figure Figure
F/S-mode
Hs-mode (current-source SCLH enabled)
F/S-mode
MASTER CODE
SLAVE ADD.
DATA bytes ack.)
Hs-mode continues
SLAVE ADD.
msc616
Data transfer format Hs-mode
PCF8811_4
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Product data sheet
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Semiconductors
PCF8811
pixels matrix driver
SDAH
8-bit master code 0000 1xxx
SCLH
F/S-mode
7-bit
(8-bit data
A/A)
SDAH
SCLH
then F/S-mode (dotted lines) then Hs-mode
Hs-mode
Master current source pull-up
msc618
Resistor pull-up
Data transfer timing format F/S-mode Hs-mode
device allowed acknowledge master code, master code followed not-acknowledge (A). After this bit, SCLH line pulled HIGH level, active master switches Hs-mode enables current-source pull-up circuit SCLH signal; Figure active master will then send repeated START condition (Sr) followed 7-bit slave address (SLA) with bit, receives acknowledge from selected slave. After each acknowledge not-acknowledge active master disables current source pull-up circuit. active master re-enables current source again when devices have been released SCLH signal reaches HIGH level. rising SCLH signal done pull-up resistor therefore slower, last part SCLH rise time speeded because current source enabled. Data transfer only switches back F/S-mode after STOP condition (P). write sequence after Hs-mode selected shown Figure sequence initiated with START condition from I2C-bus master which followed slave address. slaves with corresponding address acknowledge parallel, remainder will ignore I2C-bus transfer.
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Semiconductors
PCF8811
pixels matrix driver
acknowledge from PCF8811 slave address
acknowledge from PCF8811
acknowledge from PCF8811
acknowledge from PCF8811
acknowledge from PCF8811
control byte
data byte
control byte
data byte bytes
bytes
byte
mgw749
Master transmits Hs-mode slave receiver; write mode
After acknowledgement cycle write (W), more command words will follow which define status addressed slaves. command word consists control byte, which defines continuation D/C, plus data byte; Figure Table last control byte initiated cleared MSB). control data bytes also acknowledged addressed slaves bus.
Table definitions Action last control byte sent; only stream data bytes allowed follow; this stream only terminated STOP RESTART condition another control byte will follow data byte unless STOP RESTART condition received data byte will decoded used set-up device data byte will return status byte data byte will stored display read back supported
Logic state
read sequence shown Figure again this sequence follows after Hs-mode selected. PCF8811 will immediately start output requested data until not-acknowledge transmitted master. Before read access, user appropriate value preceding write access. write access must terminated RESTART condition that Hs-mode disabled.
acknowledge from PCF8811 slave address
not-acknowledge from master
status information
STOP condition
mgw750
Master receives from slave transmitter (status register read); read mode
After last control byte, depending setting, either series display data bytes command data bytes follow. logic these display bytes stored display address specified data pointer.
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pixels matrix driver
data pointer automatically updated data directed intended PCF8811 device. last control byte logic these command bytes will decoded setting device will changed according received commands. acknowledgement after each byte made only addressed PCF8811. transmission I2C-bus master issues STOP condition switches back F/S-mode, however, reduce overhead master code, possible that master link number Hs-mode transfers, separated repeated START conditions (Sr).
11.3 Command decoder
command decoder identifies command words that received I2C-bus:
pairs bytes: information second byte, first byte determines whether information
display instruction data
Stream information bytes after display instruction data depending last
most significant control byte continuation this logic indicates that only data byte, either command data, will follow. this logic indicates that series data bytes, either command data, follow. control byte data/command D/C. When this logic indicates that data byte will transferred next. logic indicates that command byte will transferred next.
Instructions
PCF8811 interfaces 8-bit parallel interface, different 3-line serial interfaces, 4-wire serial interface I2C-bus interface. Processing instructions does require display clock. Data accesses PCF8811 broken down into areas: those that define operating mode device, those that fill display RAM. case parallel 4-wire interfaces, distinction pad. When logic chip will respond instructions defined Table When logic chip will send data RAM. When 3-wire SPI, 3-wire serial interface I2C-bus interface used, distinction between instructions which define operating mode device those that fill display RAM, made respectively display data length instruction (3-line SPI) data stream (3-line serial interface I2C-bus interface). There types instructions. Those which: Define PCF8811 functions, such display configuration etc. internal addresses Perform data transfer with internal Others. normal use, category instructions used most frequently.
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pixels matrix driver
basic extended instruction available. basic command used. HIGH extended command used. Both command sets detailed Table
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Semiconductors
Table
Instruction set[1] EXT[2] R/W/WR Command byte DB7[3] BUSY partial display 1:16 1:80 start row; 79[6] Ymax; Xmax; initial display line; 79[5] read status byte read status byte normal reverse mode pixels mirror mirror icon enable disable[4] vertical horizontal addressing[4] bottom swap[4] address; address; soft reset write data display only used 3-line operation Description
Instruction Reset Write data Display data length Status read Display control
display
data order[4]
Address commands
pixels matrix driver
Ymax3 Ymax2 Ymax1 Ymax0
Ymax6 Ymax5 Ymax4 Ymax3 Ymax2 Ymax1 Ymax0
initial display line initial partial display
PCF8811
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx
Table Instruction set[1] .continued EXT[2] setting Power control HVgen stages TC[9] Bias system Manual value Power-save Power-save Internal oscillator Internal oscillator Enter CALMM mode Reserved Reserved Test
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Semiconductors
Instruction
Command byte R/W/WR DB7[3] VPR7 VPR6 VPR5 VPR5 VPR4 VPR4 VPR3 VPR3 VPR2 VPR2 VPR1 VPR1 VPR0 VPR0
Description VOP[7][8]
VOFF2 VOFF1 VOFF0 offset VOP[7][8] VOP[4] switch HVgen on/off multiplication factor multiplication factor[4] frame rate frequency[4] temperature coefficient[4] bias system[10] manual value[4][11] Power-save mode exit Power-save mode switch internal oscillator on/off enable disable internal external oscillator[4] enter CALMM mode reserved reserved
pixels matrix driver
use; reserved testing
value without meaning. Semiconductors recommends that extended command used. MSB. Commands only available with extended command set, these commands have effect. When icon mode enabled initial display line When icon mode enabled initial line Commands only used basic command these commands have effect. must checked, when setting basic command that followed another command. programming basic command must done following order: VPR[5:0]
PCF8811
Semiconductors
PCF8811
pixels matrix driver
VOFF[2:0] must followed another command. fixed automatically basic command used.
[10] Bias system settings which received when chip used replacement Alt-Pleshko driving method (NOP). [11] Only multiplex rates 1:64 1:80. number simultaneous rows manually Table
12.1 Instruction commands
12.1.1 Common instructions basic extended command
Table X[6:0] Y[3:0] Common commands Logic display normal display normal display mirroring mirroring stop frame frequency calibration internal oscillator Logic display inverse video mode pixels mirroring mirroring start frame frequency calibration start internal oscillator Reset state 0000 0000 1111 1001 0000
address (column) writing address (bank) writing
Xmax[6:0] wrap around address (column) Ymax[3:0] wrap around address (bank) L[6:0] sets line address display; this command cannot access icon driver row, icon enabled sets initial display; this command cannot access icon driver row, icon enabled partial display mode 1:16 1:80 switch multiplier on/off charge pump multiplication factor
C[6:0]
0000
P[6:0] PC[1:0] S[1:0]
0000 (1:80)/100 0000 (1:64)
Partial displays selected steps when icon mode selected. When icon mode selected, partial displays selected steps example, without icons available partial display sizes lines. With icons there lines possible.
Table PC[1:0]
Power control register Description HVgen HVgen HVgen
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pixels matrix driver
Power-save mode (PSM), DON, combinations[1] Description oscillator off; HVgen disabled oscillator HVgen disabled display off; pads Rn/Cn VSS; oscillator off; HVgen disabled[2] normal display mode inverse display mode pixels on[3] Power-save mode: display off; pads Rn/Cn VSS; oscillator off; HVgen disabled
Table
value without meaning. only addressed after activated. priority over
Table BUSY MF[2:0] Table
Read status byte Description BUSY chip able accept commands same Table reset progress device manufacturer device recognition; Table Device recognition[1] Description driver driver
This only default setting after reset; another setting selected with `set partial display mode' command.
Table S[1:0]
Multiplication settings Description voltage multiplier voltage multiplier voltage multiplier voltage multiplier
12.1.2 Specific commands basic command
Table VPR[5:0] VOFF[2:0] Specific basic commands Description programming value VLCD offset programming value VLCD Reset state 0000
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12.1.3 Specific commands extended command
Table VPR[7:6] VPR[5:0] FR[1:0] TC[2:0] S[2:0] MP[1] Specific extended commands Logic frame rate frequency temperature coefficient charge pump multiplication factor horizontal addressing icon (multiplex rate 1:16 1:80) bottom rows mirrored multiplex rate driven value (automatic) internal oscillator vertical addressing Logic Reset state 0000 programming value VLCD
icon (multiplex rate 1:16 1:80) bottom rows mirrored
selected multiplex rate 1:64 1:80 external oscillator
Semiconductors recommends setting.
Table FR[1:0] Table TC[2:0]
Frame rate frequency Frame rate frequency Temperature coefficient[1] Temperature coefficient
further information about temperature coefficient, Table
Table S[2:0]
PCF8811_4
Multiplication settings Description voltage multiplier voltage multiplier voltage multiplier
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PCF8811
pixels matrix driver
Multiplication settings .continued Description voltage multiplier voltage multiplier voltage multiplier voltage multiplier voltage multiplier
Table S[2:0]
12.2 Initialization
Reset accomplished applying external reset pulse (active LOW) RES. When reset occurs within specified time, internal registers reset, however still undefined. state after reset described Section 12.3. must VDD1 when VDD1 reaches VDD(min) higher) within maximum time tVHRL after VDD1 goes HIGH; Figure reset also achieved sending reset command. This command used during normal operation initialize chip after power-on.
12.3 Reset function
12.3.1 Basic command
After reset driver following state:
Display setting Address commands X[6:0] Y[3:0] VLCD equal multiplier switched (PC[1:0] offset programming range (VOFF[2:0] multiplier programming (VPR[5:0] voltage multiplier (S[1:0] After power-on, data undefined, reset signal does change content outputs (display off) Initial display line line (L[6:0] Initial (C[6:0] Full display selected (P[6:0] multiplex rate 1:80 1:64) Display mirrored Internal oscillator Power-save mode frame calibration running
12.3.2 Extended command
After reset driver following state:
Display settings
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PCF8811
pixels matrix driver
Icons disabled Address counter X[6:0] Y[3:0] Temperature control mode (TC[2:0] 010) VLCD equal multiplier switched (PC[1:0] multiplier programming (VPR[7:0] voltage multiplier (S[2:0] 100) Frame-rate frequency (FR[1:0] After power-on, data undefined, reset signal does change content outputs (display off) Full display selected (P[6:0] multiplex rate 1:80 1:64) Initial display line line (L[6:0] Initial (C[6:0] Display mirrored Internal oscillator Power-save mode Horizontal addressing enabled data order swap (DOR bottom swap (BRS Internal oscillator enabled frame calibration running
12.4 Power-save mode
Power-save mode driver following state:
outputs (display off) Bias generator VLCD generator switched off; external VLCD disconnected Oscillator (external clock possible) contents cleared; data written VLCD discharged Power-down mode
There ways chip into Power-save mode:
display must (DON pixels (DAL Power-save mode command activated 12.5 Display control
bits DON, select display mode; Table
12.5.1
When display written from left right left side Xmax right side display).
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When display written from right left right side Xmax left side display). impact written horizontal mirroring display desired, must first rewritten, after changing bit.
12.5.2
When display mirrored vertically. change this immediate effect display.
12.6 address
Y[3:0] defines address display RAM.
Table address range Content bank (display RAM) bank (display RAM) bank (display RAM) bank (display RAM) bank (display RAM) bank (display RAM) bank (display RAM) bank (display RAM) bank (display RAM) bank (display RAM) Allowed range
When icon (row enabled will always bank independent multiplex rate which programmed.
12.7 address
address points columns. range (7Fh).
12.8 display start line
L[6:0] (see Table used select display line address display displayed initial row, selection L[6:0] limited steps When icon selected, selection L[6:0] limited steps When partial mode selected, selection L[6:0] also limited steps. addition, selection L[6:0] allowed when icon enabled disabled. initial can, turn, C[6:0]; Table cannot icon when enabled. example mapping from content display shown Figure content modified. This feature allows, instance, screen scrolling without rewriting RAM.
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Product data sheet Rev. June 2008
B.V. 2008. rights reserved. PCF8811_4
Semiconductors
initial display line start when address Display
mgw751
pixels matrix driver
PCF8811
Programming L[6:0] address C[6:0] address when
Semiconductors
PCF8811
pixels matrix driver
12.9 Bias levels
bias levels (Multiple Addressing) driving method with given Figure when Gmax have same value. value defines number rows which simultaneously selected.
VLCD V3_H V2_H V1_H V1_L V2_L V3_L
mgw752
Gmax VLCD 0.75Gmax 0.50Gmax 0.25Gmax -0.25Gmax -0.50Gmax -0.75Gmax -Gmax
Bias levels system with Gmax
voltage depends multiplex rate selected (number rows threshold voltage liquid (VTH), number simultaneously selected rows multiplexibility (m):
column voltages situated around common level column voltage levels equidistant from each other. Table column voltage levels given function
Table Symbol Gmax VLCD V3_H V2_H V1_H V1_L V2_L Bias levels driving method Bias voltages shifted bias voltages VLCD
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pixels matrix driver
Bias levels driving method .continued Bias voltages
Table Symbol V3_L
shifted bias voltages
voltages necessarily larger then column voltages. This depends number rows which selected, multiplexibility value However, PCF8811 designed such that maximum column voltages always equal voltages. Table VLCD different bias levels given PCF8811. VLCD voltage defined
Where defined Equation
bias system settings different display modes given Table bias levels calculated using third column Table variables given Table Programming bias levels necessary PCF8811. selection appropriate bias level voltages each display mode done automatically. Only appropriate VLCD voltage must programmed according Equation Equation display modes listed Table
Table Relationship between multiplex rates bias setting variables without icon Variable 1:16 1:24 1:32 1:40 1:48 1:56 1:64 1:72 1:80
Multiplex rate
variables calculating VLCD, when icon enabled, given Table icon only addressed extended command set. PCF8811 allows value certain multiplex rates chosen manually. This only possible multiplex rates 1:64 1:80. other multiplex rates chosen PCF8811 determines optimum value setting value manually compromise made between contrast power consumption with certain liquids high multiplex rates 1:64 1:80. However, care must taken that liquid which chosen ensures that voltages maximum column voltages equal.
PCF8811_4
B.V. 2008. rights reserved.
Product data sheet
Rev. June 2008
Semiconductors
PCF8811
pixels matrix driver
Relationship between multiplex rates bias setting variables with icon (only extended command set) Variable
Table
Multiplex rate 1:16 1:32 1:48 1:64 1:80
12.10 value
multiplex rate 1:80 optimum operation voltage liquid calculated with variables given Table Equation Equation
4.472
Where threshold voltage liquid crystal material used.
programming method value implemented differently basic command from that extended command set. basic command commands sent PCF8811: namely VPR[5:0] VOFF[2:0]. extended command only command VPR[7:0] sent PCF8811. programming basic command used when PCF8811 used replacement IAPT (Improved Alt-Pleshko Technique) driver. look-up table Table shows possible values VOFF[2:0], VPR[5:0], VOP[7:0] VLCD.
VPR[7:0] MMVOPCAL[4:0] VPR[5:0] VOFF[2:0] VLCD LOOK-UP TABLE rom_add[8:0] VOP[7:0]
mgw753
VOS[4:0]
Setting basic extended command
12.10.1 Basic command
VLCD TCUT basic command determined conversion look-up table with programmed values VPR[5:0] VOFF[2:0]. can, additionally, adjusted with VLCD offset pads VOS[4:0] obtain optimum optical performance. Example: value VLCD following values have taken; Table
PCF8811_4 B.V. 2008. rights reserved.
Product data sheet
Rev. June 2008
Semiconductors
PCF8811
pixels matrix driver
Example values VPR, VOFF VLCD Value Table Binary value 1111 0100
Table Register
VPR[5:0] VOP[7:0] VOFF[2:0]
Instead using VLCD offset pads (VOS[4:0]) VLCD adjusted with module maker calibration setting MMVOPCAL[4:0]; Section Where:
[4:0] [7:0]
TCUT reference temperature; Section 12.11 fixed constant value; Table fixed constant value; Table VOP[7:0] result conversion table VOS[4:0]/MMVOPCAL[4:0] value offset VLCD pads value stored cells
Parameters VLCD basic extended command Value 0.03 Unit
Table Symbol TCUT
PCF8811_4
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Product data sheet
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Product data sheet Rev. June 2008
B.V. 2008. rights reserved. PCF8811_4
Semiconductors
Table VOFF[000]
look-up table with values VOFF, VPR, VLCD VOFF[001] VOFF[010] VOFF[011] VOFF[100] VOFF[101] VLCD [5:0] [7:0] 8.55 8.61 8.67 8.73 8.76 8.82 8.88 8.94 9.06 9.12 9.18 9.24 9.36 9.42 9.48 9.54 9.63 9.69 9.75 9.81 9.87 9.93 9.99 VOFF[110] VLCD [5:0] [7:0] 9.57 9.63 9.69 9.78 9.84 9.96 VOFF[111] VLCD [5:0] [7:0] 10.59 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68
VLCD VLCD VLCD VLCD VLCD [5:0] [7:0] [5:0] [7:0] [5:0] [7:0] [5:0] [7:0] [5:0] [7:0] 3.39 3.42 3.45 3.45 3.48 3.51 3.54 3.57 3.57 3.63 3.66 3.66 3.69 3.72 3.75 3.75 3.78 3.81 3.84 3.87 3.87 3.93 3.96 3.96 3.99 4.02 4.05 4.44 4.47 4.53 4.56 4.59 4.62 4.65 4.68 4.71 4.74 4.77 4.83 4.86 4.89 4.92 4.95 4.98 4.98 5.04 5.07 5.13 5.16 5.19 5.22 5.25 5.28 5.46 5.49 5.52 5.58 5.61 5.64 5.67 5.76 5.79 5.82 5.85 5.91 5.94 5.97 6.06 6.09 6.12 6.15 6.18 6.24 6.27 6.33 6.39 6.42 6.45 6.48 6.48 6.54 6.57 6.63 6.66 6.69 6.75 6.78 6.84 6.87 6.93 6.96 7.02 7.05 7.11 7.14 7.23 7.29 7.32 7.35 7.41 7.44 7.53 7.59 7.62 7.68 7.71 7.56 7.62 7.68 7.71 7.77 7.83 7.86 7.92 7.98 8.01 8.07 8.13 8.19 8.22 8.28 8.34 8.37 8.43 8.49 8.52 8.58 8.64 8.73 8.79 8.85 8.88 8.94
10.02 10.08 10.17 10.23 10.29 10.35 10.41 10.47 10.56 10.62 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68
pixels matrix driver
10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68
PCF8811
10.05 10.11 10.17
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Table VOFF[000] look-up table with values VOFF, VPR, VLCD .continued VOFF[001] VOFF[010] VOFF[011] VOFF[100] VOFF[101] VLCD [5:0] [7:0] VOFF[110] VLCD [5:0] [7:0] VOFF[111] VLCD [5:0] [7:0] 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68
Product data sheet Rev. June 2008
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Semiconductors
VLCD VLCD VLCD VLCD VLCD [5:0] [7:0] [5:0] [7:0] [5:0] [7:0] [5:0] [7:0] [5:0] [7:0] 4.05 4.08 4.11 4.14 4.17 4.17 4.23 4.26 4.26 4.29 4.32 4.35 4.35 4.38 4.41 4.44 4.44 4.47 4.53 4.56 4.56 4.59 4.62 4.65 4.65 4.68 4.71 5.31 5.34 5.37 5.43 5.46 5.49 5.52 5.55 5.58 5.61 5.64 5.67 5.73 5.76 5.79 5.82 5.85 5.88 5.91 5.94 5.97 6.03 6.06 6.09 6.12 6.15 6.54 6.57 6.66 6.63 6.69 6.72 6.75 6.78 6.81 6.87 6.93 6.96 7.02 7.05 7.08 7.11 7.17 7.23 7.26 7.29 7.35 7.38 7.41 7.44 7.53 7.56 7.77 7.86 7.89 7.95 7.98 8.01 8.07 8.16 8.19 8.25 8.28 8.34 8.37 8.43 8.46 8.52 8.55 8.61 8.64 8.67 8.73 8.76 8.82 8.85 8.91 8.94 9.03 9.09 9.15 9.21 9.24 9.36 9.39 9.45 9.51 9.54 9.66 9.72 9.75 9.81 9.87 9.96
10.23 10.29 10.35 10.41 10.47 10.5 10.56 10.62 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68
10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68
pixels matrix driver
10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68 10.68
10.02 10.05 10.11 10.17 10.23 10.26 10.32 10.38 10.41
PCF8811
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Table VOFF[000] look-up table with values VOFF, VPR, VLCD .continued VOFF[001] VOFF[010] VOFF[011] VOFF[100] VOFF[101] VLCD [5:0] [7:0] VOFF[110] VLCD [5:0] [7:0] VOFF[111] VLCD [5:0] [7:0] 10.68 10.68 10.68 10.68 10.68 10.68
Product data sheet Rev. June 2008
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Semiconductors
VLCD VLCD VLCD VLCD VLCD [5:0] [7:0] [5:0] [7:0] [5:0] [7:0] [5:0] [7:0] [5:0] [7:0] 4.74 4.74 4.77 4.83 4.86 6.15 6.21 6.24 6.27 6.33 7.59 7.65 7.68 7.71 7.74 9.03 9.09 9.12 9.18 9.21 9.27
10.47 10.53 10.56 10.62 10.68 10.68
10.68 10.68 10.68 10.68 10.68 10.68
10.68 10.68 10.68 10.68 10.68 10.68
pixels matrix driver
PCF8811
Semiconductors
PCF8811
pixels matrix driver
12.10.2 Extended command
VLCD TCUT calculated using Equation extended command VPR[7:0] same value VOP[7:0]. additionally adjusted with VLCD offset pads VOS[4:0] obtain optimum optical performance. Instead using VLCD offset pads (VOS[4:0]) VLCD adjusted with module maker calibration setting MMVOPCAL[4:0]; Section Where:
[4:0] [7:0]
TCUT reference temperature; Section 12.11 fixed constant value; Table fixed constant value; Table VPR[7:0] programmed value VOS[4:0]/MMVOPCAL[4:0] value offset VLCD pads value stored cells
programming range internally generated VLCD allows values above maximum allowed VLCD user ensure while setting register selecting Temperature Compensation (TC), that under conditions including tolerances VLCD remains below This valid different command sets.
mgt847
VOP[7:0] programming, (00h FFh).
VLCD programming PCF8811
12.11 Temperature control
temperature dependency liquid crystals' viscosity, controlling voltage VLCD might have increased lower temperatures maintain optimum contrast.
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Product data sheet
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Semiconductors
PCF8811
pixels matrix driver
calculate VLCD specific temperature both command sets. VLCD TCUT) given Equation Equation depending command which used.
extended command basic command different temperature coefficients available; Figure
VLCD
TCUT
mgw754
Temperature coefficients
typical values different temperature coefficients given Section coefficients proportional programmed VLCD. basic extended command differ that temperature coefficients accessed. basic command only temperature coefficient available. However, possibility exists program default temperature coefficient means programming; Section extended command different temperature coefficients selected interface with three bits TC[2:0].
PCF8811_4
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Product data sheet
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Semiconductors
PCF8811
pixels matrix driver
Internal circuitry
VDD1 VDD2 VDD3
VSS1
VSS1 VSS2
VSS1
VSS2
VLCDIN, VLCDSENSE
VLCDOUT
VSS1 VSS1
VSS1
VOTPPROG
VLCDIN
VDD1 DB[7:0], SCLK, SDATA, SDO, SA1, SA0, R/W/WR
VSS1
outputs
VSS1
VSS1
VDD1 OSC, RES, D/C, PS[2:0], E/RD VSS1 I2C-bus pins
VDD1
VDD1
VSS1(1), VDD(2) VSS1 VSS1
001aai352
test purposes only: maximum forward current maximum reverse voltage
Device protection diagrams
Limiting values
Table Limiting values[1] accordance with Absolute Maximum Rating System (IEC 60134). Symbol VDD1 VDD2 VDD3 Parameter supply voltage supply voltage supply voltage Conditions general internal voltage generator internal voltage generator
-0.5 -0.5 -0.5
+6.5 +4.5 +4.5
Unit
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Product data sheet
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Semiconductors
PCF8811
pixels matrix driver
Table Limiting values[1] .continued accordance with Absolute Maximum Rating System (IEC 60134). Symbol VLCD VOTPPROG Ptot P/out Tstg
Parameter supply voltage input voltage voltage applied VOTPPROG input current output current ground supply current total power dissipation power dissipation output storage temperature
Conditions
-0.5 -0.5 -0.5
+6.5 +150
Unit
level level
Parameters valid over whole operating temperature range unless otherwise specified. voltages referenced unless otherwise specified. internal voltage multiplier.
Static characteristics
Table Static characteristics VDD1 VLCD Tamb unless otherwise specified. Symbol Parameter VDD1 supply voltage Conditions general basic command set; when using look-up table; Section 12.10 VDD2 VDD3 VLCDIN supply voltage supply voltage supply voltage internal voltage multiplier internal voltage multiplier voltage externally supplied (voltage multiplier disabled) voltage internally generated (voltage multiplier enabled) without calibration with calibration general internal voltage multiplier internal voltage multiplier VDD1 VDD2 VDD3
[3][4] [4][5]
Unit
VLCDOUT voltage multiplier output voltage VLCD(tol) IDD1 IDD2 IDD3 IDD(tot)
PCF8811_4
tolerance generated VLCD supply current supply current supply current total supply current input voltage LOW-level input voltage
-300
+300
[3][4] [4][5] [3][4] [4][5] [4][5]
Logic inputs; MF[2:0], VOS[4:0], DS0, EXT, PS[2:0], VDD1 0.2VDD1
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Product data sheet
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Semiconductors
PCF8811
pixels matrix driver
Table Static characteristics .continued VDD1 VLCD Tamb unless otherwise specified. Symbol Parameter Rcol Rrow Vbias(col) HIGH-level input voltage leakage current Conditions 0.8VDD1 -100 -100
-0.16 10-3 -0.33 10-3 -0.50 10-3 -0.66 10-3
VDD1 +100 +100
Unit
1/°C 1/°C 1/°C 1/°C 1/°C 1/°C 1/°C 1/°C
Column outputs column output resistance C127; VLCD output resistance bias tolerance voltage R79; VLCD C127
Vbias(row) bias tolerance voltage supply voltage multiplier voltage temperature coefficient voltage temperature coefficient voltage temperature coefficient voltage temperature coefficient voltage temperature coefficient voltage temperature coefficient voltage temperature coefficient voltage temperature coefficient input voltage LOW-level input voltage HIGH-level input voltage input voltage LOW-level input voltage HIGH-level input voltage
-0.833 10-3 -1.25 10-3 -1.66 10-3
Parallel interface; VDD1 I2C-bus IOL(SDA)
-0.5 0.8VDD1 -0.5 0.8VDD1 -0.5 0.7VDD1 0.8VDD1
VDD1 0.2VDD1 VDD1
Serial interface; VDD1 VDD1 0.2VDD1 VDD1 +3.3 0.3VDD1 VDD1 0.2VDD1 VDD1
interface; VDD1 input voltage LOW-level output current VDD1 SDAH VDD1; VDD1 LOW-level input voltage HIGH-level input voltage LOW-level output voltage HIGH-level output voltage -0.5
Output levels interfaces
maximum possible VLCD voltage that generated dependent voltage, temperature (display) load.
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PCF8811_4
Product data sheet
Rev. June 2008
Semiconductors
PCF8811
pixels matrix driver
Valid values temperature, used calibration. During power-down static currents switched off. Conditions are: VDD1 VDD2 VLCD 8.05 voltage multiplier VDD2, inputs VDD1 VSS, interface inactive, internal VLCD generation, VLCD output loaded Tamb Normal mode. only used when VDD2 VDD3 higher.
Dynamic characteristics
Table Dynamic characteristics[1] VDD1 VLCD Tamb unless otherwise specified. Symbol fext fframe tVHRL
Parameter external frequency frame frequency pulse width
Conditions external clock Tamb VDD1 Figure Figure
Unit
specified timings based VDD. before goes HIGH.
16.1 Parallel interface timing characteristics
Table Parallel interface (6800 series) timing characteristics VDD1 VLCD Tamb unless otherwise specified; Figure Figure Symbol tSU;DC tHD;DC Tcyc(DS) tDS(L) tDS(H) tSU;RW tHD;RW tSU;CE tHD;CE tSU;DAT tHD;DAT tDAT;ACC tDAT;OH Parameter data/command set-up time data/command hold time data strobe cycle time data strobe time data strobe HIGH time read/write set-up time read/write hold time chip enable set-up time chip enable hold time data set-up time data hold time data output access time data output disable time 1000 Unit
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PCF8811
pixels matrix driver
R/W/WR tSU;CE tSU;RW tHD;CE tHD;RW
tSU;DC tHD;DC
Tcyc(DS) tDS(H) tDS(L)
tSU;DAT tHD;DAT (Write) tDAT;ACC (Read)
mgw755
tDAT;OH
Parallel interface timing; 6800 series (read mode)
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Semiconductors
PCF8811
pixels matrix driver
D/C, R/W/WR tSU;RW tHD;RW
tSU;DC tHD;DC
Tcyc(DS) tDS(L) tDS(H)
tSU;DAT
tHD;DAT
(Write) tDAT;ACC (Read)
001aai347
tDAT;OH
Parallel interface timing; 6800 series (write mode)
16.2 Serial interface timing characteristics
Table Serial interface timing characteristics[1] VDD1 VLCD Tamb unless otherwise specified; Figure Figure Figure Figure Symbol fSCLK Tcyc tPWH1 tPWL1 tPWH2
PCF8811_4
Parameter clock frequency clock cycle SCLK SCLK pulse width HIGH SCLK pulse width set-up time hold time minimum HIGH time start hold time data/command set-up time data/command hold time SDATA set-up time SDATA hold time access time disable time
9.00
Unit
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Product data sheet
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Semiconductors
PCF8811
pixels matrix driver
Table Serial interface timing characteristics[1] .continued VDD1 VLCD Tamb unless otherwise specified; Figure Figure Figure Figure Symbol
Parameter hold time disable time capacitive load series resistance
Unit
specified timings based VDD. time from previous SCLK rising edge (irrespective state SCE) falling edge SCE. disable time 3-line 4-line. disable time 3-line serial interface. Maximum values fSCLK MHz. Series resistance includes track connector resistance printed-circuit board.
tPWH2
(tH5) Tcyc tPWL1 SCLK tPWH1
SDATA
mgw757
3-line serial interface timing
PCF8811_4
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Product data sheet
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Semiconductors
PCF8811
pixels matrix driver
tPWH2
(tH5)
Tcyc tPWL1 SCLK tPWH1
SDATA
mgw758
4-line serial interface timing
SCLK
SDATA
001aai353
Serial interface timing; 3-line 4-line (read mode)
PCF8811_4
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Product data sheet
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Semiconductors
PCF8811
pixels matrix driver
SCLK
SDATA
001aai354
Serial interface timing; 3-line serial interface (read mode)
16.3 I2C-bus interface timing characteristics
Table I2C-bus characteristics; F/S-mode VDD1 VLCD Tamb unless otherwise specified[1]; Figure Symbol fSCL tSU;STA tHD;STA tLOW tHIGH tSU;DAT tHD;DAT tSU;STO tBUF Parameter clock frequency set-up time repeated START condition hold time (repeated) START condition period clock HIGH period clock data set-up time data hold time rise time both signals fall time both signals capacitive load each line set-up time STOP condition pulse width spikes that must suppressed input filter free time between STOP START condition noise margin level noise margin HIGH level each connected device (including hysteresis) each connected device (including hysteresis) Conditions 1300 Unit
0.1Cb 0.1Cb 1300 0.1VDD1 0.2VDD1
specified timings based VDD.
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Product data sheet
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Semiconductors
PCF8811
pixels matrix driver
Table I2C-bus characteristics; Hs-mode VDD1 VLCD Tamb unless otherwise specified[1]; Figure Symbol fSCLH tSU;STA tHD;STA tLOW tHIGH tSU;DAT tHD;DAT trCL trCL1 Parameter SCLH clock frequency set-up time repeated START condition hold time (repeated) START condition period SCLH clock HIGH period SCLH clock data set-up time data hold time rise time SCLH signal rise time SCLH signal after repeated START condition after acknowledge fall time SCLH signal rise time SDAH signal fall time SDAH signal set-up time STOP condition pulse width spikes that must suppressed input filter capacitive load each line SDAH SCLH Conditions (max) 20[3] pF[2] 20[3] Unit
tfCL trDA tfDA tSU;STO
SDAH SCLH lines SDAH line SCLH line
0.1VDD1 0.2VDD2
0.1VDD1 0.2VDD2
noise margin level each connected device (including hysteresis) noise margin HIGH level each connected device (including hysteresis)
specified timings based VDD. line loads between timing parameters must linearly interpolated. device must internally provide data hold time bridge undefined part between falling edge SCLH signal. input circuit with threshold possible falling edge SCLH signal minimizes this hold time.
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Product data sheet
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Semiconductors
PCF8811
pixels matrix driver
tLOW
tSU;DAT
tHD;STA
tBUF
tHD;STA tSU;STA tSU;STO
tHD;DAT
tHIGH
001aai355
start start repeated stop
I2C-bus timing diagram (F/S-mode)
tfDA
trDA
SDAH
tHD;DAT tSU;STA tHD;STA tSU;DAT
tSU;STO
SCLH tfCL trCL1
trCL tHIGH tLOW tLOW tHIGH
trCL1
mgk871
current source pull-up resistor pull-up
Rising edge first SCLH clock pulse after acknowledge bit.
I2C-bus timing diagram (Hs-mode)
PCF8811_4
B.V. 2008. rights reserved.
Product data sheet
Rev. June 2008
Semiconductors
PCF8811
pixels matrix driver
tVHRL
mgw761
Reset timing
Application information
Semiconductors light sensitive. Exposure light sources cause malfunction. this application must protect from light. protection done sides i.e. front, rear edges. pinning PCF8811 optimum design single plane wiring e.g. chip-on-glass display modules. Display size: pixels. further application information refer Semiconductors Application Note AN10170 Design guidelines modules with Philips monochrome drivers.
DISPLAY pixels
PCF8811
VDD3 VDD2 VDD1 VSS1 VSS2
CVDD
CVLCD
VLCDSENSE VLCDOUT VLCDIN
mgw762
Application diagram: internal charge pump single supply
PCF8811_4
B.V. 2008. rights reserved.
Product data sheet
Rev. June 2008
Semiconductors
PCF8811
pixels matrix driver
DISPLAY pixels
PCF8811
VDD3 VDD2 VDD1 VSS1 VSS2
CVDD1 CVDD2
VDD1 VDD2
CVLCD
VLCDSENSE VLCDOUT VLCDIN
mgw763
Application diagram: internal charge pump separate supplies (VDD1 VDD2)
DISPLAY pixels
PCF8811
VDD3 VDD2 VDD1 VSS1 VSS2
CVDD
VLCDSENSE VLCDOUT VLCDIN VLCDIN
mgw764
Application diagram: external high voltage
required minimum value external capacitors application with PCF8811 are: CVLCD depending application. CVDD, CVDD1, CVDD2 these capacitors, higher values used.
PCF8811_4
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Product data sheet
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Semiconductors
PCF8811
pixels matrix driver
Support information
18.1 Module maker programming
Time Programmable (OTP) technology implemented PCF8811. enables module maker program some extended features PCF8811 after been assembled module. Programming made under control interfaces special pad. This must made available module glass need accessed maker. PCF8811 features parameters programmable module maker:
VLCD calibration Temperature coefficient selection Seal
18.1.1 VLCD calibration
first feature included ability adjust VLCD voltage with 5-bit code (MMVOPCAL). This code implemented two's complement notation giving rise positive negative offset register. This same manner on-glass calibration pads VOS. theory, both used together recommended that pads tied when calibration being used. This sets them default offset zero. both used then addition 5-bit numbers must exceed 5-bit result, otherwise resultant value undefined. final adder circuit underflow overflow protection. event overflow, output will clamped 255; during underflow output will clamped final control high voltage multiplier, VOP, calibration registers pads. VLCD Equation Equation given Section 12.10.1 Section 12.10.2 must extended include calibration, follows:
[4:0] MMVOPCAL[4:0] [7:0]
possible values MMVOPCAL[4:0] VOS[4:0] values given Table
Table Binary 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001
PCF8811_4
VOS/MMVOPCAL values two's complement notation Decimal Binary 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 Decimal
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Product data sheet
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Semiconductors
PCF8811
pixels matrix driver
VOS/MMVOPCAL values two's complement notation .continued Decimal Binary 0101 0100 0011 0010 0001 0000 Decimal
Table Binary 1010 1011 1100 1101 1110 1111
VLCD calibration: 5-bit offset MMVOPCAL[4:0] laser trim pins: 5-bit offset VOS[4:0]
range
range
VOP[7:0] range: +255 high voltage generator
range +255 usable range +255 register: 8-bit value VPR[7:0]
mgu287
VLCD calibration
18.1.2 Temperature coefficient selection
second feature factory default setting temperature coefficient selection (MMTC) basic command set. This 3-bit value will loaded from after leaving Power-save mode Refresh command. idea this feature provide, basic command set, complete temperature coefficients without additional command. extended command temperature coefficient programmed given Table Table
18.1.3 Seal
module maker programming performed special mode: calibration mode (CALMM). This mode entered special interface command, CALMM. prevent unwanted programming, seal been implemented which prevents device from entering calibration mode. This seal bit, once programmed, cannot reversed further changes programmed values possible. Applying programming voltages when CALMM mode effect programmed values.
Table Seal Seal definition Action possible enter calibration mode calibration mode disabled
PCF8811_4
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Semiconductors
PCF8811
pixels matrix driver
18.1.4 architecture
circuitry PCF8811 contains bits data: VLCD calibration (MMVOPCAL), temperature coefficient default setting basic command MMTC seal bit. circuitry 1-bit called slice. Each slice consists main parts: cell non-volatile memory cell) shift register cell flip-flop). cells only accessible through their shift register cells: hand both reading from writing cells performed with shift register cells, other hand only shift register cells visible rest circuit. basic architecture shown Figure This architecture allows following operations: Reading data from cells content non-volatile cells transferred shift register where upon affect PCF8811 operation. Writing data cells data bits shifted into shift register interface. content shift register then transferred cells. There some limitations related storing data these cells; Section 18.1.7. Checking calibration without writing cells Shifting data into shift register allows effects VLCD voltage observed. reading data from cells initiated either:
Exit from Power-save mode `Refresh' command (power control)
Remark: Note that both cases reading operation needs complete. shifting data into shift register performed special mode CALMM. PCF8811 CALMM mode entered CALMM command. Once CALMM mode data shifted into shift register interface rate 1-bit command. After transmitting last (9th) exiting CALMM mode, serial interface will return normal mode other commands sent. Care should taken that bits data multiple always transferred before exiting CALMM mode, otherwise bits will wrong positions. shift register value seal like others, always zero reset. ensure that security feature (seal bit) works correctly, CALMM command disabled until refresh been performed. Once refresh completed, seal value shift register will valid permission enter CALMM mode thus determined. bits shifted into shift register predefined order: first bits MMVOPCAL[4:0], bits MMTC[2:0] lastly seal bit. always first, thus first shifted MMVOPCAL[4] last bits MMTC[0] seal bit.
PCF8811_4
B.V. 2008. rights reserved.
Product data sheet
Rev. June 2008
Semiconductors
PCF8811
pixels matrix driver
DATA CIRCUIT CONFIGURATION CALIBRATION slice
SHIFT REGISTER FLIP-FLOP
SHIFT REGISTER DATA INPUT
SHIFT REGISTER
read data from cell
write data cell
CELLS
mgu289
CELL
Basic architecture
18.1.5 Interface commands
These instructions addition those indicated Table
Table Additional interface commands CALMM Power control (`refresh') X[1] X[1] R/W/WR Command byte enter CALMM mode switch HVgen on/off force refresh shift register Description
Instruction
value without meaning.
18.1.5.1
CALMM This instruction puts device calibration mode. This mode enables shift register loading allows programming non-volatile cells take place. seal then this mode cannot accessed instruction will ignored. Once calibration mode commands interpreted shift register data. mode only exited sending data with logic Reset will also clear this mode. Each shift register data byte preceded only significant bits, thus remaining bits ignored. continuation (DB7 remain CALMM mode, exit CALMM mode). data value shifted into shift register falling edge SCLK).
18.1.5.2
Refresh action `Refresh' instruction force shift register re-load from non-volatile cells. This instruction takes complete. During this time other instructions sent. PCF8811 `Refresh' instruction associated with `Power control' instruction that shift register automatically refreshed every time high voltage multiplier enabled disabled. Note that this instruction sent while Power-save mode, PC[1:0] bits updated refreshing ignored.
PCF8811_4
B.V. 2008. rights reserved.
Product data sheet
Rev. June 2008
Semiconductors
PCF8811
pixels matrix driver
18.1.6 Example sequence filling shift register
example sequence commands data shown Table this example shift register filled with following data: MMVOPCAL 1100b), MMTC (010b) seal logic assumed that PCF8811 just been reset. After transmitting last PCF8811 either exit remain CALMM mode; Table Step should noted that while CALMM mode interface does recognize commands normal sense. After this sequence been applied possible observe impact data shifted described sequence however, useful programming because number bits with value logic greater than that allowed programming; Section 18.1.7. shift register after this action shown Figure
Table Step
Sequence filling shift register; example 1[1] Command byte R/W/WR exit power-down wait refresh take effect enter CALMM mode shift data; MMVOPCAL[4] first MMVOPCAL[3] MMVOPCAL[2] MMVOPCAL[1] MMVOPCAL[0] MMTC[2] MMTC[1] MMTC[0] seal bit; exit CALMM mode seal bit; remain CALMM mode Action
alternative ending could stay CALMM mode
value without meaning. data bits correct shift register position until bits have been sent.
SHIFT REGISTER shifting direction SEAL MMTC[2:0] MMVOPCAL[4:0]
mgw765
Shift register contents after example sequence; Table
18.1.7 Programming flow
Programming achieved whilst CALMM mode with application programming voltages. mentioned previously, data programming cell contained corresponding shift register cell. shift register cell must loaded
PCF8811_4 B.V. 2008. rights reserved.
Product data sheet
Rev. June 2008
Semiconductors
PCF8811
pixels matrix driver
with logic order program corresponding cell. shift register cell contains logic then action will take place when programming voltages applied. Once programmed, cell cannot de-programmed. already programmed cell, i.e. cell containing logic must re-programmed. During programming, substantial current flows VLCDIN pad. this reason recommended program only cell time. This achieved filling shift register cells with logic should noted that programming specification refers voltages chip pads, contact resistance must therefore considered user. example sequence commands data programming given Table assumed that PCF8811 just been reset. order programming cells significant. However, Semiconductors recommends that seal programmed last. Once this been programmed CALMM mode exited, possible re-enter CALMM mode.
Table Step Sequence filling shift register; example 2[1] Command byte Action exit power-save wait refresh take effect re-enter power-down (DON enter CALMM mode shift data; MMVOPCAL[4] first MMVOPCAL[3] MMVOPCAL[2] MMVOPCAL[1] MMVOPCAL[0] MMTC[2] MMTC[1] MMTC[0] seal apply programming voltage pads VOTPPROG VLCDIN; Section 18.1.8 apply external reset
R/W/WR
Repeat steps each which must programmed exit CALMM mode
value without meaning.
PCF8811_4
B.V. 2008. rights reserved.
Product data sheet
Rev. June 2008
Semiconductors
PCF8811
pixels matrix driver
18.1.8 Programming specification
Table Programming specification Figure Symbol VOTPPROG VLCDIN ILCDIN IVOTPPROG Tamb(PROG) tSU;SCLK tHD;SCLK Parameter voltage applied VOTPPROG relative VSS1 voltage applied VLCDIN relative VSS1 current drawn VLCDIN during programming current drawn VOTPPROG during programming ambient temperature during programming set-up time internal data after last clock hold time internal data before next clock Conditions programming active programming inactive programming active programming inactive when programming single logic
[1][2] [1][2]
11.5
1000
Unit
VDD2 VDD2
tSU;VOTPPROG set-up time VOTPPROG prior programming tHD;VOTPPROG hold time VOTPPROG after programming pulse width programming voltage
voltage drop across track zebra connector must taken into account guarantee sufficiently high voltage chip pads. Power-down mode (DON CALMM mode must active while VLCDIN being driven.
tSU;SCLK
tHD;SCLK
SCLK
VVOTPPROG
VLCDIN
tSU;VOTPROG
tHD;VOTPPROG
mgw766
Programming waveforms
Package outline
applicable.
PCF8811_4 B.V. 2008. rights reserved.
Product data sheet
Rev. June 2008
Semiconductors
PCF8811
pixels matrix driver
Handling information
Inputs outputs protected against electrostatic discharge normal handling. However, completely safe must take normal precautions appropriate handling devices; JESD625-A and/or IEC61340-5.
Packing information
Table Tray dimensions Figure Symbol Description pocket pitch direction pocket pitch direction pocket width direction pocket width direction tray width direction tray width direction number pockets, direction number pockets, direction Value 13.77 4.45 12.55 2.41 50.8 50.8
mgs488
Tray details
PCF8811_4
B.V. 2008. rights reserved.
Product data sheet
Rev. June 2008
Semiconductors
PCF8811
pixels matrix driver
PCF8811
mgw771
Tray alignment
orientation pocket indicated position type name surface with respect chamfer upper left corner tray. Refer bonding location diagram (Figure orientation position type name surface.
Abbreviations
Table Acronym CMOS DDRAM Abbreviations Description Charged Device Model Complementary Metal Oxide Semiconductor Chip-On-Glass Double Data Random Access Memory ElectroStatic Discharge Human Body Model High Voltage Integrated Circuit Indium Oxide Liquid Crystal Display Least Significant Machine Model Multiple Addressing Most Significant MicroProcessing Unit Time Programmable Read Access Memory Serial Peripheral Interface Temperature Coefficient Tape Carrier Packages
PCF8811_4
B.V. 2008. rights reserved.
Product data sheet
Rev. June 2008
Semiconductors
PCF8811
pixels matrix driver
Revision history
Table Revision history Release date 20080627 Data sheet status Product data sheet Change notice Supersedes PCF8811_3 Document PCF8811_4 Modifications:
format this data sheet been redesigned comply with identity guidelines Semiconductors. Legal texts have been adapted company name where appropriate. Amendments text Added look-up Table Changed values Table Table Changed Figure Figure Figure Figure Figure Moved Figure Section "Pinning information" Moved Table Table Section "Pinning information" Added details adjusted dimensions Table Product specification Product specification Product specification PCF8811_2 PCF8811_1
PCF8811_3 (9397 13144) PCF8811_2 (9397 10285) PCF8811_1 (9397 09148)
20040517 20021204 20020814
PCF8811_4
B.V. 2008. rights reserved.
Product data sheet
Rev. June 2008
Semiconductors
PCF8811
pixels matrix driver
Legal information
24.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
Product status[3] Development Qualification Production
Definition This document contains data from objective specification product development. This document contains data from preliminary specification. This document contains product specification.
Please consult most recently issued document before initiating completing design. term `short data sheet' explained section "Definitions". product status device(s) described this document have changed since this document published differ case multiple devices. latest product status information available Internet http://www.nxp.com.
24.2 Definitions
Draft document draft version only. content still under internal review subject formal approval, which result modifications additions. Semiconductors does give representations warranties accuracy completeness information included herein shall have liability consequences such information. Short data sheet short data sheet extract from full data sheet with same product type number(s) title. short data sheet intended quick reference only should relied upon contain detailed full information. detailed full information relevant full data sheet, which available request local Semiconductors sales office. case inconsistency conflict with short data sheet, full data sheet shall prevail.
result personal injury, death severe property environmental damage. Semiconductors accepts liability inclusion and/or Semiconductors products such equipment applications therefore such inclusion and/or customer's risk. Applications Applications that described herein these products illustrative purposes only. Semiconductors makes representation warranty that such applications will suitable specified without further testing modification. Limiting values Stress above more limiting values defined Absolute Maximum Ratings System 60134) cause permanent damage device. Limiting values stress ratings only operation device these other conditions above those given Characteristics sections this document implied. Exposure limiting values extended periods affect device reliability. Terms conditions sale Semiconductors products sold subject general terms conditions commercial sale, published including those pertaining warranty, intellectual property rights infringement limitation liability, unless explicitly otherwise agreed writing Semiconductors. case inconsistency conflict between information this document such terms conditions, latter will prevail. offer sell license Nothing this document interpreted construed offer sell products that open acceptance grant, conveyance implication license under copyrights, patents other industrial intellectual property rights.
24.3 Disclaimers
General Information this document believed accurate reliable. However, Semiconductors does give representations warranties, expressed implied, accuracy completeness such information shall have liability consequences such information. Right make changes Semiconductors reserves right make changes information published this document, including without limitation specifications product descriptions, time without notice. This document supersedes replaces information supplied prior publication hereof. Suitability Semiconductors products designed, authorized warranted suitable medical, military, aircraft, space life support equipment, applications where failure malfunction Semiconductors product reasonably expected
24.4 Trademarks
Notice: referenced brands, product names, service names trademarks property their respective owners. I2C-bus logo trademark B.V.
Contact information
more information, please visit: http://www.nxp.com sales office addresses, please send email salesaddresses@nxp.com
PCF8811_4
B.V. 2008. rights reserved.
Product data sheet
Rev. June 2008
Semiconductors
PCF8811
pixels matrix driver
Contents
General description Features Applications Ordering information Block diagram Pinning information Pinning description Functional description functions R79: driver outputs C127: column driver signals VSS1 VSS2: negative power supply rails VDD1 VDD3: positive power supply rails VOTPPROG: power supply. VLCDOUT, VLCDIN, VLCDSENSE: power supply 7.1.7 test pads 7.1.8 7.1.9 DS0. 7.1.10 VOS4 VOS0 7.1.11 EXT: extended command 7.1.12 PS0, 7.1.13 7.1.14 R/W/WR 7.1.15 E/RD 7.1.16 SCLH/SCE 7.1.17 SDAH 7.1.18 SDAHOUT 7.1.19 DB0. 7.1.19.1 (parallel interface) 7.1.19.2 DB7, (serial interface) 7.1.19.3 (I2C-bus interface) 7.1.20 OSC: oscillator 7.1.21 RES: reset Block diagram functions 7.2.1 Oscillator. 7.2.2 Address counter 7.2.3 Display data 7.2.4 Timing generator. 7.2.5 Display address counter 7.2.6 column drivers Addressing Display data structure 8.1.1 Basic command 8.1.2 Extended command 7.1.1 7.1.2 7.1.3 7.1.4 7.1.5 7.1.6 8.1.2.1 8.1.2.2 8.1.2.3 10.1 10.1.1 10.1.2 10.2 10.2.1 10.2.2 11.1 11.1.1 11.1.2 11.1.3 11.1.4 11.2 11.3 12.1 12.1.1 12.1.2 12.1.3 12.2 12.3 12.3.1 12.3.2 12.4 12.5 12.5.1 12.5.2 12.6 12.7 12.8 12.9 12.10 12.10.1 12.10.2 12.11 Horizontal/vertical addressing Data order Features available both command sets Parallel interface 6800 series parallel interface Serial interfacing (SPI serial interface) Serial peripheral interface lines Write mode. Read mode (only extended command set) Serial interface (3-line) Write mode. Read mode (only extended command set) I2C-bus interface Characteristics I2C-bus (Hs-mode) System configuration transfer Start stop conditions Acknowledge I2C-bus Hs-mode protocol Command decoder. Instructions Instruction commands Common instructions basic extended command Specific commands basic command Specific commands extended command Initialization Reset function Basic command Extended command Power-save mode. Display control address address display start line Bias levels value Basic command Extended command Temperature control Internal circuitry Limiting values Static characteristics
continued
PCF8811_4
B.V. 2008. rights reserved.
Product data sheet
Rev. June 2008
Semiconductors
PCF8811
pixels matrix driver
Dynamic characteristics 16.1 Parallel interface timing characteristics. 16.2 Serial interface timing characteristics 16.3 I2C-bus interface timing characteristics Application information. Support information 18.1 Module maker programming 18.1.1 VLCD calibration. 18.1.2 Temperature coefficient selection 18.1.3 Seal 18.1.4 architecture. 18.1.5 Interface commands 18.1.5.1 CALMM. 18.1.5.2 Refresh 18.1.6 Example sequence filling shift register 18.1.7 Programming flow 18.1.8 Programming specification Package outline Handling information. Packing information. Abbreviations Revision history Legal information. 24.1 Data sheet status 24.2 Definitions 24.3 Disclaimers 24.4 Trademarks Contact information. Contents
Please aware that important notices concerning this document product(s) described herein, have been included section `Legal information'.
B.V. 2008.
rights reserved.
more information, please visit: http://www.nxp.com sales office addresses, please send email salesaddresses@nxp.com Date release: June 2008 Document identifier: PCF8811_4
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