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ARM9 microcontroller with Rev. June 2009 Preliminary data sheet


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LPC2917/2919/01
ARM9 microcontroller with
Rev. June 2009 Preliminary data sheet
LPC2917/2919/01 combine ARM968E-S core with integrated blocks operating frequencies MHz, LIN, SRAM, flash memory, external memory interface, 10-bit ADCs, multiple serial parallel interfaces single chip targeted consumer, industrial, medical, communication markets. optimize system power consumption, LPC2917/2919/01 very flexible Clock Generation Unit (CGU) that provides dynamic clock gating scaling.
Features
ARM968E-S processor running frequencies maximum. Multi-layer system with three separate layers. On-chip memory: Tightly Coupled Memories (TCM), Instruction (ITCM), Data (DTCM). separate internal Static (SRAM) instances; SRAM SRAM. SRAM also available code execution data. high-speed flash-program memory. true EEPROM, byte-erasable programmable. Dual-master, eight-channel GPDMA controller multi-layer matrix which used with interfaces UARTs, well memory-to-memory transfers including memories. External Static Memory Controller (SMC) with eight memory banks; 32-bit data bus; 24-bit address bus. Serial interfaces: Two-channel controller supporting FullCAN extensive message filtering master controllers with full hardware support communication. interface configured UART provide additional UART interfaces. UARTs with 16-byte FIFO depths, support, RS485/EIA-485 bit) support. Three full-duplex Q-SPIs with four slave-select lines; bits wide; locations deep; FIFO FIFO. I2C-bus interfaces.
Semiconductors
LPC2917/01; LPC2919/01
ARM9 microcontroller with
Other peripherals: 10-bit ADCs, channels each, with measurement range conversion times 2.44 channel. Each channel provides compare function minimize interrupts. Multiple trigger-start option ADCs: timer, PWM, other ADC, external signal input. Four 32-bit timers each containing four capture-and-compare registers linked I/Os. Four six-channel PWMs (Pulse-Width Modulators) with capture trap functionality. dedicated 32-bit timers schedule synchronize ADC. Quadrature encoder interface that monitor external quadrature encoder. 32-bit watchdog with timer change protection, running safe clock. general-purpose pins with programmable pull-up, pull-down, keeper. Vectored Interrupt Controller (VIC) with priority levels. level-sensitive external interrupt pins, including wake-up features. Configurable clock-out driving external system clocks. Processor wake-up from power-down external interrupt pins; activity. Flexible Reset Generator Unit (RGU) able control resets individual modules. Flexible Clock-Generation Unit (CGU0) able control clock frequency individual modules: On-chip very low-power ring oscillator; fixed frequency MHz; always provide Safe_Clock source system monitoring. On-chip crystal oscillator with recommended operating range from MHz. input range MHz. On-chip allows operation maximum rate MHz. Generation base clocks. Seven fractional dividers. Second (CGU1) with generates configurable clock output. Highly configurable system Power Management Unit (PMU): clock control individual modules. allows minimization system operating power consumption configuration. Standard test debug interface with real-time in-circuit emulator. Boundary-scan test supported. ETM/ETB debug functions with dedicated SRAM also accessible application code data storage. Dual power supply: operating voltage: operating voltage: inputs tolerant 144-pin LQFP package. ambient operating temperature range.
LPC2917_19_01_2
B.V. 2009. rights reserved.
Preliminary data sheet
Rev. June 2009
Semiconductors
LPC2917/01; LPC2919/01
ARM9 microcontroller with
Ordering information
Table Ordering information Package Name LPC2917FBD144/01 LPC2919FBD144/01 Description Version SOT486-1 SOT486-1 LQFP144 plastic profile quad flat package; leads; body LQFP144 plastic profile quad flat package; leads; body Type number
Ordering options
Table Part options Flash memory SRAM 32-bit 32-bit Package LQFP144 LQFP144 Type number LPC2917FBD144/01 LPC2919FBD144/01
LPC2917_19_01_2
B.V. 2009. rights reserved.
Preliminary data sheet
Rev. June 2009
Semiconductors
LPC2917/01; LPC2919/01
ARM9 microcontroller with
Block diagram
JTAG interface
LPC2917/01 LPC2919/01
ITCM
TEST/DEBUG INTERFACE SRAM DTCM
ARM968E-S
master slave VECTORED INTERRUPT CONTROLLER CLOCK GENERATION UNIT CGU0/1 RESET GENERATION UNIT POWER MANAGEMENT UNIT BRIDGE slave master slave BRIDGE slave slave GPDMA REGISTERS GPDMA CONTROLLER
master
EXTERNAL STATIC MEMORY CONTROLLER EMBEDDED SRAM
slave slave EMBEDDED SRAM slave slave MULTI LAYER MATRIX EMBEDDED FLASH 512/768 slave BRIDGE SYSTEM CONTROL EVENT ROUTER EEPROM
TIMER0/1 MTMR PWM0/1/2/3 ADC1/2
BRIDGE
slave QUADRATURE ENCODER BRIDGE slave BRIDGE
CHIP FEATURE
GENERAL PURPOSE PORTS 0/1/2/3 TIMER 0/1/2/3
CAN0/1 GLOBAL ACCEPTANCE FILTER LIN0/1 I2C0/1
SPI0/1/2 RS485 UART0/1
002aad959
Grey-shaded blocks represent peripherals memory regions accessible GPDMA.
LPC2917/2919/01 block diagram
LPC2917_19_01_2
B.V. 2009. rights reserved.
Preliminary data sheet
Rev. June 2009
Semiconductors
LPC2917/01; LPC2919/01
ARM9 microcontroller with
Pinning information
Pinning
002aae265
LPC2917FBD144/01 LPC2919FBD144/01
configuration SOT486-1 (LQFP144)
description
5.2.1 General description
LPC2917/2919/01 four ports: pins each, pins pins. which each function assigned controlled SFSP registers SCU. functions combined each port shown description tables this section.
5.2.2 LQFP144 assignment
Table name P2[21]/SDI2/ PCAP2[1]/D19 LQFP144 assignment 1[1] 2[1] Description Default function IEEE 1149.1 test data GPIO GPIO SPI2 UART1 PWM2 CAP1 CAN1 EXTBUS SPI2 SCS0 Function Function Function
P0[24]/TXD1/ 3[1] TXDC1/SCS2[0 P0[25]/RXD1/ RXDC1/SDO2 P0[26]/TXD1/ SDI2 P0[27]/RXD1/ SCK2 4[1] 5[1] 6[1]
GPIO GPIO GPIO GPIO GPIO power supply
UART1
CAN1 UART1 UART1 TIMER0 CAP0 TIMER0 CAP1
SPI2 SPI2 SPI2 TIMER0 MAT0 TIMER0 MAT1
P0[28]/CAP0[0]/ 7[1] MAT0[0] P0[29]/CAP0[1]/ 8[1] MAT0[1] VDD(IO)
LPC2917_19_01_2
B.V. 2009. rights reserved.
Preliminary data sheet
Rev. June 2009
Semiconductors
LPC2917/01; LPC2919/01
ARM9 microcontroller with
Table name
LQFP144 assignment .continued 10[1] Description Default function Function SPI2 SPI1 SCS0 SPI0 SCS3 Function PWM2 CAP2 PWM3 CAP0 PWM1 MAT0 Function EXTBUS EXTBUS LIN1/UART GPIO GPIO GPIO
P2[22]/SCK2/ PCAP2[2]/D20
P2[23]/SCS1[0]/ 11[1] PCAP3[0]/D21 P3[6]/SCS0[3]/ PMAT1[0]/ TXDL1 P3[7]/SCS2[1]/ PMAT1[1]/ RXDL1 12[1]
13[1]
GPIO
SPI2 SCS1
PWM1 MAT1
LIN1/UART
P0[30]/CAP0[2]/ 14[1] MAT0[2] P0[31]/CAP0[3]/ 15[1] MAT0[3] P2[24]/SCS1[1]/ 16[1] PCAP3[1]/D22 P2[25]/SCS1[2]/ 17[1] PCAP3[2]/D23 VDD(CORE) VSS(CORE) P1[31]/CAP0[1]/ MAT0[1]/EI5 VSS(IO) 20[1]
GPIO GPIO GPIO GPIO
SPI1 SCS1 SPI1 SCS2
TIMER0 CAP2 TIMER0 CAP3 PWM3 CAP1 PWM3 CAP2
TIMER0 MAT2 TIMER0 MAT3 EXTBUS EXTBUS
power supply digital core ground digital core GPIO ground GPIO GPIO GPIO GPIO TIMER0 CAP0 SPI2 SCS0 SPI2 TIMER1 CAP0 TIMER0 MAT0 PWM1 MAT2 PWM1 MAT3 TRAP0 EXTINT4 PWM3 MAT5 TIMER0 CAP1 TIMER0 MAT1 EXTINT5
P1[30]/CAP0[0]/ 22[1] MAT0[0]/EI4 P3[8]/SCS2[0]/ PMAT1[2] 23[1]
P3[9]/SDO2/PM 24[1] AT1[3] P1[29]/CAP1[0]/ 25[1] TRAP0/ PMAT3[5] P1[28]/CAP1[1]/ 26[1] TRAP1/ PMAT3[4] P2[26]/CAP0[2]/ 27[1] MAT0[2]/EI6 P2[27]/CAP0[3]/ 28[1] MAT0[3]/EI7 P1[27]/CAP1[2]/ 29[1] TRAP2/ PMAT3[3] P1[26]/ PMAT2[0]/ TRAP3/ PMAT3[2] 30[1]
GPIO
TIMER1 CAP1, ADC1 START TIMER0 CAP2 TIMER0 CAP3 TIMER1 CAP2, ADC2 START PWM2 MAT0
TRAP1
PWM3 MAT4
GPIO GPIO GPIO
TIMER0 MAT2 TIMER0 MAT3 TRAP2
EXTINT6 EXTINT7 PWM3 MAT3
GPIO
TRAP3
PWM3 MAT2
LPC2917_19_01_2
B.V. 2009. rights reserved.
Preliminary data sheet
Rev. June 2009
Semiconductors
LPC2917/01; LPC2919/01
ARM9 microcontroller with
Table name VDD(IO) P1[25]/ PMAT1[0]/ PMAT3[1] P1[24]/ PMAT0[0]/ PMAT3[0] P1[23]/ RXD0/CS5
LQFP144 assignment .continued 32[1] Description Default function power supply GPIO PWM1 MAT0 PWM3 MAT1 Function Function Function
33[1]
GPIO
PWM0 MAT0
PWM3 MAT0
34[1] 35[1] 36[1] 37[1] 38[1]
GPIO GPIO
UART0 UART0
EXTBUS EXTBUS
P1[22]/TXD0/ P1[21]/CAP3[3]/ CAP1[3]/D7
IEEE 1149.1 test mode select, pulled internally IEEE 1149.1 test clock GPIO GPIO GPIO GPIO GPIO ground GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO power supply GPIO TIMER2 MAT2 TRAP1 EXTBUS TIMER2 CAP2 TIMER2 MAT0 TIMER2 MAT1 SPI2 SPI2 TIMER2 CAP1 TIMER2 CAP0 EXTINT3 EXTINT2 SPI0 TRAP3 TRAP2 PWM1 MAT4 PWM1 MAT5 SPI0 SCS0 SPI0 SCS3 I2C1 I2C1 EXTBUS EXTBUS EXTBUS EXTBUS EXTBUS EXTBUS EXTBUS TIMER3 CAP3 TIMER3 CAP2 TIMER3 CAP1 TIMER3 CAP0 TIMER2 CAP3 TIMER1 CAP3, MSCSS PAUSE SPI0 SCS1 SPI0 SCS2 SPI0 SPI0 EXTBUS EXTBUS EXTBUS EXTBUS EXTBUS
P1[20]/CAP3[2]/ 39[1] SCS0[1]/D6 P1[19]/CAP3[1]/ 40[1] SCS0[2]/D5 P1[18]/CAP3[0]/ 41[1] SDO0/D4 P1[17]/CAP2[3]/ 42[1] SDI0/D3 VSS(IO) P1[16]/CAP2[2]/ SCK0/D2 P2[0]/MAT2[0]/ TRAP3/D8 P2[1]/MAT2[1]/ TRAP2/D9 P3[10]/SDI2/ PMAT1[4] P3[11]/SCK2/ PMAT1[5] 44[1] 45[1] 46[1] 47[1] 48[1]
P1[15]/CAP2[1]/ 49[1] SCS0[0]/D1 P1[14]/CAP2[0]/ 50[1] SCS0[3]/D0 P1[13]/SCL1/ EI3/WE P1[12]/SDA1/ EI2/OE VDD(IO) P2[2]/MAT2[2]/ TRAP1/D10 51[1] 52[1] 54[1]
LPC2917_19_01_2
B.V. 2009. rights reserved.
Preliminary data sheet
Rev. June 2009
Semiconductors
LPC2917/01; LPC2919/01
ARM9 microcontroller with
Table name
LQFP144 assignment .continued 55[1] 56[1] 57[1] Description Default function Function TIMER2 MAT3 SPI1 SPI1 SPI1 SCS0 Function TRAP0 I2C0 I2C0 EXTINT4 Function EXTBUS EXTBUS EXTBUS GPIO GPIO GPIO GPIO ground digital core power supply digital core GPIO GPIO GPIO GPIO ground GPIO GPIO GPIO GPIO GPIO GPIO SPI1 SCS0 SPI1 SCS3 SPI1 SCS2 TIMER1 MAT2 SPI1 SCS1 SPI2 SCS2 LIN1/UART UART1 UART1 EXTINT2 PWM3 MAT5 PWM3 MAT4 EXTBUS EXTBUS EXTBUS EXTBUS EXTBUS EXTBUS SPI1 TIMER1 MAT0 TIMER1 MAT1 SPI1 EXTINT5 EXTINT0 EXTINT1 LIN1/UART QEI0 EXTBUS EXTBUS EXTBUS
P2[3]/MAT2[3]/ TRAP0/D11 P1[11]/SCK1/ SCL0/CS3 P1[10]/SDI1/ SDA0/CS2
P3[12]/SCS1[0]/ 58[1] VSS(CORE) VDD(CORE) P3[13]/SDO1/ EI5/IDX0 P2[4]/MAT1[0]/ EI0/D12 P2[5]/MAT1[1]/ EI1/D13 P1[9]/SDO1/ RXDL1/CS1 VSS(IO) P1[8]/SCS1[0]/ TXDL1/CS0 P1[7]/SCS1[3]/ RXD1/A7 P1[6]/SCS1[2]/ TXD1/A6 P2[6]/MAT1[2]/ EI2/D14 P1[5]/SCS1[1]/ PMAT3[5]/A5 P1[4]/SCS2[2]/ PMAT3[4]/A4 TRST VSS(OSC) XOUT_OSC XIN_OSC VDD(OSC) VSS(PLL) P2[7]/MAT1[3]/ EI3/D15 P3[14]/SDI1/ EI6/TXDC0 P3[15]/SCK1/ EI7/RXDC0
LPC2917_19_01_2
61[1] 62[1] 63[1] 64[1] 66[1] 67[1] 68[1] 69[1] 70[1] 71[1] 72[1] 73[1] 75[2] 76[2] 79[1] 80[1] 81[1]
IEEE 1149.1 test reset NOT; active LOW; pulled internally asynchronous device reset; active LOW; pulled internally ground oscillator crystal oscillator crystal oscillator supply oscillator ground GPIO GPIO GPIO TIMER1 MAT3 SPI1 SPI1 EXTINT3 EXTINT6 EXTINT7 EXTBUS CAN0 CAN0
B.V. 2009. rights reserved.
Preliminary data sheet
Rev. June 2009
Semiconductors
LPC2917/01; LPC2919/01
ARM9 microcontroller with
Table name VDD(IO) P2[8]/ CLK_OUT/ PMAT0[0]/ SCS0[2]
LQFP144 assignment .continued 83[1] Description Default function power supply GPIO CLK_OUT PWM0 MAT0 SPI0 SCS2 Function Function Function
P2[9]/PMAT0[1]/ 84[1] SCS0[1] P1[3]/SCS2[1]/ PMAT3[3]/A3 P1[2]/SCS2[3]/ PMAT3[2]/A2 P1[1]/EI1/ PMAT3[1]/A1 VSS(CORE) VDD(CORE) P1[0]/EI0/ PMAT3[0]/A0 P2[10]/ PMAT0[2]/ SCS0[0] 85[1] 86[1] 87[1] 90[1] 91[1]
GPIO GPIO GPIO GPIO ground digital core
SPI2 SCS1 SPI2 SCS3 EXTINT1
PWM0 MAT1 PWM3 MAT3 PWM3 MAT2 PWM3 MAT1
SPI0 SCS1 EXTBUS EXTBUS EXTBUS
power supply digital core GPIO GPIO EXTINT0 PWM3 MAT0 PWM0 MAT2 EXTBUS SPI0 SCS0
P2[11]/ 92[1] PMAT0[3]/SCK0 P0[0]/PHB0/ TXDC0/D24 VSS(IO) P0[1]/PHA0/ RXDC0/D25 P0[2]/ CLK_OUT/ PMAT0[0]/D26 93[1] 95[1] 96[1]
GPIO GPIO ground GPIO GPIO
QEI0
PWM0 MAT3 CAN0
SPI0 EXTBUS
CLK_OUT
CAN0 PWM0 MAT0
EXTBUS EXTBUS
P0[3]/PMAT0[1]/ 97[1] P3[0]/PMAT2[0]/ 98[1] P3[1]/PMAT2[1]/ 99[1] P2[12]/ PMAT0[4]/SDI0 P2[13]/ PMAT0[5]/ SDO0 100[1] 101[1]
GPIO GPIO GPIO GPIO GPIO
PWM0 MAT1 PWM2 MAT0 PWM2 MAT1 PWM0 MAT4 PWM0 MAT5
EXTBUS EXTBUS EXTBUS SPI0 SPI0
P0[4]/PMAT0[2]/ 102[1] P0[5]/PMAT0[3]/ 103[1] VDD(IO)
LPC2917_19_01_2
GPIO GPIO power supply
PWM0 MAT2 PWM0 MAT3
EXTBUS EXTBUS
B.V. 2009. rights reserved.
Preliminary data sheet
Rev. June 2009
Semiconductors
LPC2917/01; LPC2919/01
ARM9 microcontroller with
Table name
LQFP144 assignment .continued 105[1] 106[1] 108[1] 110[2] 111[2] 112[3] 113[3] 114[3] 115[3] Description Default function Function Function PWM0 MAT4 PWM0 MAT5 Function EXTBUS EXTBUS GPIO GPIO
P0[6]/ PMAT0[4]/D30 P0[7]/ PMAT0[5]/D31 VDDA(ADC3V3) JTAGSEL n.c. VREFP VREFN P0[8]/IN1[0]/TX DL0/A20 P0[9]/IN1[1]/ RXDL0/A21 P0[10]/IN1[2]/ PMAT1[0]/A8 P0[11]/IN1[3]/ PMAT1[1]/A9
power supply controller select input; LOW-level selects debug mode; HIGH-level selects boundary scan; pulled internally. connected function, must tied power supply VDDA(ADC3V3). HIGH reference reference GPIO GPIO GPIO GPIO GPIO GPIO GPIO ground GPIO GPIO GPIO GPIO GPIO GPIO GPIO TIMER3 MAT1 ADC1 ADC1 ADC1 ADC1 ADC2 ADC2 PWM2 MAT3 PWM1 MAT2 PWM1 MAT3 PWM1 MAT4 PWM1 MAT5 UART0 UART0 EXTBUS EXTBUS EXTBUS EXTBUS EXTBUS EXTBUS ADC1 ADC1 ADC1 ADC1 I2C1 I2C1 TIMER3 MAT0 LIN0/UART LIN0/UART PWM1 MAT0 PWM1 MAT1 PWM0 CAP0 PWM0 CAP1 PWM2 MAT2 EXTBUS EXTBUS EXTBUS EXTBUS EXTBUS BLS0 EXTBUS BLS1
P2[14]/SDA1/ 116[1] PCAP0[0]/BLS0 P2[15]/SCL1/ 117[1] PCAP0[1]/BLS1 P3[2]/MAT3[0]/ PMAT2[2] VSS(IO) P3[3]/MAT3[1]/ PMAT2[3] P0[12]/IN1[4]/ PMAT1[2]/A10 P0[13]/IN1[5]/ PMAT1[3]/A11 P0[14]/IN1[6]/ PMAT1[4]/A12 P0[15]/IN1[7]/ PMAT1[5]/A13 P0[16]IN2[0]/ TXD0/A22 P0[17]/IN2[1]/ RXD0/A23 VDD(CORE) VSS(CORE) P2[16]/TXD1/ PCAP0[2]/BLS2 118[1] 120[1] 121[3] 122[3] 123[3] 124[3] 125[3] 126[3] 129[1]
power supply digital core ground digital core GPIO GPIO UART1 UART1 PWM0 CAP2 PWM1 CAP0 EXTBUS BLS2 EXTBUS BLS3
P2[17]/RXD1/ 130[1] PCAP1[0]/BLS3
LPC2917_19_01_2
B.V. 2009. rights reserved.
Preliminary data sheet
Rev. June 2009
Semiconductors
LPC2917/01; LPC2919/01
ARM9 microcontroller with
Table name VDD(IO)
LQFP144 assignment .continued 132[3] 133[3] 134[1] Description Default function power supply GPIO GPIO GPIO ADC2 ADC2 TIMER3 MAT2 PWM2 MAT0 PWM2 MAT1 PWM2 MAT4 EXTBUS EXTBUS CAN1 Function Function Function
P0[18]/IN2[2]/ PMAT2[0]/A14 P0[19]/IN2[3]/ PMAT2[1]/A15 P3[4]/MAT3[2]/ PMAT2[4]/ TXDC1 P3[5]/MAT3[3]/ PMAT2[5]/ RXDC1
135[1]
GPIO
TIMER3 MAT3
PWM2 MAT5
CAN1
P2[18]/SCS2[1]/ 136[1] PCAP1[1]/D16 P2[19]/SCS2[0]/ 137[1] PCAP1[2]/D17 P0[20]/IN2[4]/ PMAT2[2]/A16 P0[21]/IN2[5]/ PMAT2[3]/A17 P0[22]/IN2[6]/ PMAT2[4]/A18 VSS(IO) P0[23]/IN2[7]/ PMAT2[5]/A19 P2[20]/ PCAP2[0]/D18
GPIO GPIO GPIO GPIO GPIO ground GPIO GPIO
SPI2 SCS1 SPI2 SCS0 ADC2 ADC2 ADC2
PWM1 CAP1 PWM1 CAP2 PWM2 MAT2 PWM2 MAT3 PWM2 MAT4
EXTBUS EXTBUS EXTBUS EXTBUS EXTBUS
138[3] 139[3] 140[3] 142[3] 143[1] 144[1]
ADC2 SPI2
PWM2 MAT5 PWM2 CAP0
EXTBUS EXTBUS
IEEE 1149.1 data pulled internally
Bidirectional pad; analog port; plain input; 3-state output; slew rate control; tolerant; with hysteresis; programmable pull-up pull-down repeater. Analog pad; analog Analog pad.
Functional description
Architectural overview
LPC2917/2919/01 consists
ARM968E-S processor with real-time emulation support AMBA multi-layer Advanced High-performance (AHB) interfacing
on-chip memory controllers
buses universal interface) interfacing interrupt controller
Power, Clock Reset Control cluster (also called subsystem).
LPC2917_19_01_2
B.V. 2009. rights reserved.
Preliminary data sheet
Rev. June 2009
Semiconductors
LPC2917/01; LPC2919/01
ARM9 microcontroller with
Three Peripheral Buses (APB compatible superset ARM's AMBA
advanced peripheral bus) connection on-chip peripherals clustered subsystems.
Peripheral event router system control.
LPC2917/2919/01 configures ARM968E-S processor little-endian byte order. peripherals their clock frequency optimize total system power consumption. AHB2APB bridge used subsystems contains write-ahead buffer transaction deep. This implies that when ARM968E-S issues buffered write action register located side bridge, continues even though actual write have taken place. Completion second write same subsystem will executed until first write finished.
ARM968E-S processor
ARM968E-S general purpose 32-bit RISC processor, which offers high performance very power consumption. architecture based Reduced Instruction Computer (RISC) principles, instruction related decode mechanism much simpler than those microprogrammed Complex Instruction Computers (CISC). This simplicity results high instruction throughput impressive real-time interrupt response from small cost-effective controller core. Amongst most compelling features ARM968E-S are:
Separate directly connected instruction data Tightly Coupled Memory (TCM)
interfaces
Write buffers buses Enhanced multiplier capable single-cycle operations 16-bit fixedpoint instructions accelerate signal-processing algorithms applications. Pipeline techniques employed that parts processing memory systems operate continuously. ARM968E-S based ARMv5TE five-stage pipeline architecture. Typically, three-stage pipeline architecture, while instruction being executed successor being decoded third instruction being fetched from memory. five-stage pipeline additional stages added memory access write-back cycles. ARM968E-S processor also employs unique architectural strategy known THUMB, which makes ideally suited high-volume applications with memory restrictions applications where code density issue. idea behind THUMB that super-reduced instruction set. Essentially, ARM968E-S processor instruction sets:
Standard 32-bit ARMv5TE 16-bit THUMB
THUMB set's 16-bit instruction length allows approach twice density standard code while retaining most ARM's performance advantage over traditional 16-bit controller using 16-bit registers. This possible because THUMB code operates same 32-bit register code.
LPC2917_19_01_2 B.V. 2009. rights reserved.
Preliminary data sheet
Rev. June 2009
Semiconductors
LPC2917/01; LPC2919/01
ARM9 microcontroller with
THUMB code provide code size ARM, performance equivalent controller connected 16-bit memory system. ARM968E-S processor described detail ARM968E-S data sheet Ref.
On-chip flash memory system
LPC2917/2919/01 includes flash memory system. This memory used both code data storage. Programming flash memory accomplished flash memory controller JTAG. flash controller also supports byte-accessible on-chip EEPROM integrated LPC2917/2919/01.
On-chip static
addition TCMs LPC2917/2919/01 includes static memories: Both used code and/or data storage. addition, SRAM used static memory code data storage. However, access this memory region supported.
LPC2917_19_01_2
B.V. 2009. rights reserved.
Preliminary data sheet
Rev. June 2009
xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxx xxxxx
Preliminary data sheet Rev. June 2009
B.V. 2009. rights reserved. LPC2917_19_01_2
Semiconductors
0xFFFF FFFF 0xFFFF F000 0xFFFF C000 0xFFFF B000 0xFFFF A000 0xFFFF 9000 0xFFFF 8000 0xE00E 0000 0xE00C A000 0xE00C 9000 0xE00C 8000 0xE00C 7000 0xE00C 6000 0xE00C 5000 0xE00C 4000 0xE00C 3000 0xE00C 2000 0xE00C 1000 0xE00C 0000 reserved quadrature encoder PWM3 PWM2 PWM1 PWM0 ADC2 ADC1 reserved MSCSS timer1 MSCSS timer0 remappable shadow area 0x2020 4000 0x2020 0000 flash controller reserved 0x200C 0000 0x2008 0000 0x2000 0000 0x2000 0000 0x0080 0000 0x0040 4000 0x0040 0000 0x0000 4000 0x0000 0000 ITCM physical memory reserved DTCM reserved ITCM/DTCM memory on-chip flash on-chip flash flash memory peripherals MSCSS subsystem reserved CGU1 CGU0 PCR/VIC subsystem
LPC2917/2919/01
PCR/VIC control reserved interface reserved control SRAM controller reserved reserved peripheral subsystem
0xFFFF FFFF 0xFFFF 8000 0xF080 0000 0xF000 0000 0xE018 3000 0xE018 2000 0xE018 0000 0xE014 0000 0xE010 0000 0xE00E 0000 0xE00C 0000 peripherals networking subsystem
0xE00A 0000 reserved LIN1 LIN0 common regs regs reserved I2C1 I2C0 CAN1 CAN0 0xE008 B000 0xE008 A000 0xE008 9000
Memory
0xE008 8000 0xE008 7000 0xE008 6000 0xE008 4000 0xE008 3000 0xE008 2000 0xE008 1000 0xE008 0000 0xE006 0000
reserved 0xE00A 0000 peripheral subsystem reserved peripheral subsystem reserved peripheral subsystem reserved 0x8000 C000 SRAM SRAM reserved 0x6000 4000 controller external static memory banks 0x4300 0000 external static memory bank reserved external static memory bank reserved on-chip flash 0x2000 0000 shadow area ITCM/DTCM 0x0000 0000 0x4200 0000 0x4100 0000 0x4000 0000 0x2020 4000 peripherals general subsystem 0x6000 0000 0x8000 8000 0x8000 0000 0xE008 0000 0xE006 0000 0xE004 0000 0xE002 0000 0xE000 0000 peripherals peripheral subsystem
reserved GPIO3 GPIO2 GPIO1 GPIO0 SPI2 SPI1 SPI0 UART1 UART0 TIMER3 TIMER2 TIMER1 TIMER0
0xE004 E000 0xE004 D000 0xE004 C000 0xE004 B000 0xE004 A000 0xE004 9000
LPC2917/01; LPC2919/01
0xE004 8000 0xE004 7000 0xE004 6000 0xE004 5000 0xE004 4000 0xE004 3000 0xE004 2000 0xE004 1000 0xE004 0000 0xE002 0000
ARM9 microcontroller with
reserved event router CFID
0xE000 2000 0xE000 2000 0xE000 1000 0xE000 0000
002aad963
LPC2917/2919/01 memory
Semiconductors
LPC2917/01; LPC2919/01
ARM9 microcontroller with
Reset, debug, test, power description
6.6.1 Reset power-up behavior
LPC2917/2919/01 contains external reset input internal power-up reset circuits. This ensures that reset extended internally until oscillators flash have reached stable state. Section trip levels internal power-up reset circuit1. Section characteristics several start-up initialization times. Table shows reset pin.
Table Symbol Reset Direction Description external reset input, active LOW; pulled internally
activation JTAGSEL sensed logic LOW. this case LPC2917/2919/01 assumed connected debug hardware, internal circuits re-program source BASE_SYS_CLK crystal oscillator instead Low-Power Ring Oscillator (LP_OSC). This required because clock rate when running LP_OSC speed external debugging environment.
6.6.2 Reset strategy
LPC2917/2919/01 contains central module, Reset Generator Unit (RGU) Power, Clock Reset Subsystem (PCRSS), which controls internal reset signals towards peripheral modules. provides individual reset control well monitoring functions needed tracing reset back source.
6.6.3 IEEE 1149.1 interface pins (JTAG boundary-scan test)
LPC2917/2919/01 contains boundary-scan test logic according IEEE 1149.1, also referred this document Joint Test Action Group (JTAG). boundary-scan test pins used connect debugger probe embedded processor. JTAGSEL selects between boundary-scan mode debug mode. Table shows boundary- scan test pins.
Table Symbol JTAGSEL TRST IEEE 1149.1 boundary-scan test debug interface Description controller select input. level selects debug mode HIGH level selects boundary scan flash programming; pulled internally test reset input; pulled internally (active LOW) test mode select input; pulled internally test data input, pulled internally test data output test clock input
Only power sources
B.V. 2009. rights reserved.
LPC2917_19_01_2
Preliminary data sheet
Rev. June 2009
Semiconductors
LPC2917/01; LPC2919/01
ARM9 microcontroller with
6.6.3.1
ETM/ETB Eprovides real-time trace capability deeply embedded processor cores. outputs information about processor execution trace buffer. software debugger allows configuration Eusing JTAG interface displays trace information that been captured format that user easily understand. stores trace data produced ETM. ETM/ETB module following features:
Closely tracks instructions that core executing. On-chip trace data storage (ETB). registers programmed through JTAG interface. Does consume power when trace being used. THUMB/Java instruction support.
6.6.4 Power supply pins
Table shows power supply pins.
Table Symbol VDD(CORE) VSS(CORE) VDD(IO) VSS(IO) VDD(OSC) VSS(OSC) VDDA(ADC3V3) VSS(PLL) Power supply pins Description digital core supply digital core ground (digital core, ADC1/2) pins supply pins ground oscillator supply oscillator ground ADC1 ADC2 supply ground
Clocking strategy
6.7.1 Clock architecture
LPC2917/2919/01 contains several different internal clock areas. Peripherals like Timers, SPI, UART, have their individual clock sources called base clocks. base clocks generated Clock Generator Unit (CGU0). They unrelated frequency phase have different clock sources within CGU. system clock infrastructure base clock. This means most peripherals clocked independently from system clock. Figure overview clock areas within device. Within each clock area there multiple branch clocks, which offers very flexible control power-management purposes. branch clocks outputs Power Management Unit (PMU) controlled independently. Branch clocks derived from same base clock synchronous frequency phase. Section 6.15 more details clock power control within device.
LPC2917_19_01_2
B.V. 2009. rights reserved.
Preliminary data sheet
Rev. June 2009
Semiconductors
LPC2917/01; LPC2919/01
ARM9 microcontroller with
base clocks generated CGU0 used input into second, dedicated (CGU1). CGU1 uses fractional divider generate base clock independent clock output.
BASE_SYS_CLK
SE_ICLK0_CLK BASE_OUT_CLK BASE_ICLK1_CLK branch clock CGU1 CLOCK
MULTILAYER MATRIX BRIDGES BASE_IVNSS_CLK
networking subsystem GPDMA FLASH/SRAM/SMC branch clocks CAN0/1 GLOBAL ACCEPTANCE FILTER LIN0/1 I2C0/1 BASE_PCR_CLK power control subsystem GPIO0/1/2/3 branch clock RESET/CLOCK GENERATION POWER MANAGEMENT
general subsytem SYSTEM CONTROL EVENT ROUTER CFID peripheral subsystem
branch clocks
BASE_TMR_CLK
BASE_MSCSS_CLK TIMER 0/1/2/3
BASE_SPI_CLK
SPI0/1/2
modulation sampling control subsystem TIMER0/1 MTMR
BASE_UART_CLK
UART0/1
BASE_SAFE_CLK
branch clocks PWM0/1/2/3
BASE_ADC_CLK
branch clocks
ADC1/2
CGU0
002aad962
LPC2917/2919/01 block diagram, overview clock areas
LPC2917_19_01_2
B.V. 2009. rights reserved.
Preliminary data sheet
Rev. June 2009
Semiconductors
LPC2917/01; LPC2919/01
ARM9 microcontroller with
6.7.2 Base clock branch clock relationship
Table Table contain overview base blocks LPC2917/2919/01 their derived branch clocks. relevant cases more detailed information found specific subsystem description. Some branch clocks have special protection since they clock vital system parts device should (for example) switched off. Section 6.15.5 more details control individual branch clocks.
Table CGU0 generated base clock branch clock overview Branch clock name CLK_SAFE CLK_SYS_CPU CLK_SYS_SYS CLK_SYS_PCRSS CLK_SYS_FMC CLK_SYS_RAM0 CLK_SYS_RAM1 CLK_SYS_SMC CLK_SYS_GESS CLK_SYS_VIC CLK_SYS_PESS CLK_SYS_GPIO0 CLK_SYS_GPIO1 CLK_SYS_GPIO2 CLK_SYS_GPIO3 CLK_SYS_IVNSS_A CLK_SYS_MSCSS_A CLK_SYS_DMA BASE_PCR_CLK BASE_IVNSS_CLK CLK_PCR_SLOW CLK_IVNSS_APB CLK_IVNSS_CANCA CLK_IVNSS_CANC0 CLK_IVNSS_CANC1 CLK_IVNSS_I2C0 CLK_IVNSS_I2C1 CLK_IVNSS_LIN0 CLK_IVNSS_LIN1 Parts device clocked this branch clock watchdog timer ARM968E-S TCMs infrastructure side bridge PCRSS Flash-Memory Controller Embedded SRAM Controller Embedded SRAM Controller External Static-Memory Controller General Subsystem Vectored Interrupt Controller Peripheral Subsystem GPIO bank GPIO bank GPIO bank GPIO bank side bridge IVNSS side bridge MSCSS GPDMA PCRSS, CGU, logic clock side IVNSS controller Acceptance Filter channel channel I2C0 I2C1 channel channel
[1],
Base clock BASE_SAFE_CLK BASE_SYS_CLK
Remark
LPC2917_19_01_2
B.V. 2009. rights reserved.
Preliminary data sheet
Rev. June 2009
Semiconductors
LPC2917/01; LPC2919/01
ARM9 microcontroller with
CGU0 generated base clock branch clock overview .continued Branch clock name CLK_MSCSS_APB CLK_MSCSS_MTMR0 CLK_MSCSS_MTMR1 CLK_MSCSS_PWM0 CLK_MSCSS_PWM1 CLK_MSCSS_PWM2 CLK_MSCSS_PWM3 Parts device clocked this branch clock side MSCSS Timer MSCSS Timer MSCSS Remark
Table
Base clock BASE_MSCSS_CLK
CLK_MSCSS_ADC1_APB side CLK_MSCSS_ADC2_APB side CLK_MSCSS_QEI BASE_UART_CLK BASE_ICLK0_CLK BASE_SPI_CLK CLK_UART0 CLK_UART1 CLK_SPI0 CLK_SPI1 CLK_SPI2 BASE_TMR_CLK CLK_TMR0 CLK_TMR1 CLK_TMR2 CLK_TMR3 BASE_ADC_CLK CLK_ADC1 CLK_ADC2 reserved BASE_ICLK1_CLK
Quadrature encoder UART interface clock UART interface clock CGU1 input clock interface clock interface clock interface clock Timer clock counter part Timer clock counter part Timer clock counter part Timer clock counter part Control capture sample result Control capture sample result CGU1 input clock
This clock always (cannot switched system safety reasons) peripheral subsystem parts Timers, watchdog timer, UART have their clock source. Section 6.12 details. Power Clock Reset Control subsystem parts CGU, RGU, have their clock source. Section 6.15 details. clock should remain activated when system wake-up timer UART required.
Table
CGU1 base clock branch clock overview Branch clock name CLK_OUT_CLK Parts device clocked this branch clock clockout
Base clock BASE_OUT_CLK
LPC2917_19_01_2
B.V. 2009. rights reserved.
Preliminary data sheet
Rev. June 2009
Semiconductors
LPC2917/01; LPC2919/01
ARM9 microcontroller with
Flash memory controller
flash memory 128-bit wide data interface flash controller offers 128-bit buffer lines improve system performance. flash programmed initially JTAG. In-system programming must supported bootloader. In-application programming possible. Flash memory contents protected disabling JTAG access. Suspension burning erasing supported. Flash Memory Controller (FMC) interfaces embedded flash memory tasks:
Memory data transfer Memory configuration triggering, programming, erasing
features are:
Programming Programming external programmer JTAG JTAG access protection Burn-finished erase-finished interrupt
6.8.1 Functional description
After reset, flash initialization started, which takes tinit time (see Section During this initialization, flash access possible transfers flash stalled, blocking bus. During flash initialization, index sector read identify status JTAG access protection sector security. JTAG access protection active, flash accessible JTAG. this case, debug facilities disabled flash-memory contents cannot read. sector security active, only unsecured sections read. Flash read synchronously asynchronously system clock. synchronous operation, flash goes into standby after returning read data. Started reads cannot stopped, speculative reading dual buffering therefore supported. With asynchronous reading, transfer address flash read data from flash done asynchronously, giving fastest possible response time. Started reads stopped, speculative reading dual buffering supported. Buffering offered because flash 128-bit wide data interface while interface only bits. With buffering buffer line holds complete 128-bit flash word, from which four words read. Without buffering every data port read starts flash read. flash read slow process compared minimum cycle time, with buffering average read time reduced. This improve system performance. With single buffering, most recently read flash word remains available until next flash read. When data-port read transfer requires data from same flash word previous read transfer, flash read done read data given without wait cycles.
LPC2917_19_01_2
B.V. 2009. rights reserved.
Preliminary data sheet
Rev. June 2009
Semiconductors
LPC2917/01; LPC2919/01
ARM9 microcontroller with
When data port read transfer requires data from different flash word that involved previous read transfer, flash read done wait states given until read data available. With dual buffering, secondary buffer line used, output flash being considered primary buffer. primary buffer, data copied secondary buffer line, which allows flash start speculative read next flash word. Both buffer lines invalidated after:
Initialization Configuration-register access Data-latch reading Index-sector reading
modes operation listed Table
Table Flash read modes single (non-linear) reads; flash-word read word read default mode operation; most recently read flash word kept until another flash word required flash-word read word read most recently read flash word kept until another flash word required buffer miss flash read done, followed most speculative read; optimized execution code with small loops (less than eight words) from flash most recently used flash word copied into second buffer line; next flash-word read started; highest performance linear reads
Synchronous timing buffer line Single buffer line Asynchronous timing buffer line Single buffer line Dual buffer line, single speculative Dual buffer line, always speculative
6.8.2 description
flash memory controller external pins. However, flash programmed JTAG pins, Section 6.6.3.
6.8.3 Clock description
flash memory controller clocked CLK_SYS_FMC, Section 6.7.2.
6.8.4 Flash layout
processor program flash (In-System Programming) (InApplication Programming). Note that flash always programmed `flash words' bits (four 32-bit words, hence bytes). flash memory organized into eight `small' sectors each `large' sectors each. number large sectors depends device type. sector must erased before data written flash memory also sector-wise protection. Writing occurs page which consists 4096 bits flash words). small sector contains pages; large sector contains pages.
LPC2917_19_01_2 B.V. 2009. rights reserved.
Preliminary data sheet
Rev. June 2009
Semiconductors
LPC2917/01; LPC2919/01
ARM9 microcontroller with
Table gives overview flash-sector base addresses.
Table 7[1] 8[1] 9[1] 10[1]
Flash sector overview Sector size (kB) Sector base address 0x2000 0000 0x2000 2000 0x2000 4000 0x2000 6000 0x2000 8000 0x2000 A000 0x2000 C000 0x2000 E000 0x2001 0000 0x2002 0000 0x2003 0000 0x2004 0000 0x2005 0000 0x2006 0000 0x2007 0000 0x2008 0000 0x2009 0000 0x200A 0000 0x200B 0000
Sector number
Availability sector sector depends device type, Section "Ordering information".
index sector special sector which JTAG access protection sector security located. address space becomes visible setting FS_ISS overlaps regular flash sector's address space. Note that index sector cannot erased, that access performed code outside flash.
6.8.5 Flash bridge wait-states
eliminate delay associated with synchronizing flash-read data, predefined number wait-states must programmed. These depend flash-memory response time system clock period. minimum wait-states value calculated with following formulas: Synchronous reading:
tclk
Asynchronous reading: addr tclk
LPC2917_19_01_2
B.V. 2009. rights reserved.
Preliminary data sheet
Rev. June 2009
Semiconductors
LPC2917/01; LPC2919/01
ARM9 microcontroller with
Remark: programmed number wait-states more than three, flash-data reading cannot performed full speed (i.e. with zero wait-states bus) speculative reading active.
6.8.6 EEPROM
EEPROM non-volatile memory mostly used storing relatively small amounts data, example storing settings. contains memory block byte-programmable byte-erasable. EEPROM accessed only through flash controller.
External static memory controller
LPC2917/2919/01 contains external Static Memory Controller (SMC) which provides interface external (off-chip) memory devices. features are:
Supports static memory-mapped devices including RAM, ROM, flash, burst
external devices.
Asynchronous page-mode read operation non-clocked memory subsystems. Asynchronous burst-mode read access burst-mode devices. Independent configuration eight banks, each Programmable bus-turnaround (idle) cycles (one 16). Programmable read write wait states 32), static devices. Programmable initial subsequent burst-read wait state burst-ROM devices. Programmable write protection. Programmable burst-mode operation. Programmable external data width: bits, bits bits. Programmable read-byte lane enable control.
6.9.1 Description
simultaneously supports eight independently configurable memory banks. Each memory bank bits, bits bits wide capable supporting SRAM, ROM, burst-ROM memory, external devices. separate chip select output available each bank. chip select lines configurable active HIGH LOW. Memory-bank selection controlled memory addressing. Table shows 32-bit system address mapped external memory base addresses, chip selects, bank internal addresses.
LPC2917_19_01_2
B.V. 2009. rights reserved.
Preliminary data sheet
Rev. June 2009
Semiconductors
LPC2917/01; LPC2919/01
ARM9 microcontroller with
External memory-bank address description Symbol Description
Table
32-bit system address field
BA[2:0]
external static-memory base address (three most significant bits); base address found memory map; Ref. This field contains `010' when addressing external memory bank. chip select address space eight memory banks; Ref. always `00'; other values `mirrors' bank address. memory banks address space
Table CS[2:0]
CS[2:0] A[23:0]
External static-memory controller banks Bank bank bank bank bank bank bank bank bank
6.9.2 description
external static-memory controller module LPC2917/2919/01 following pins, which combined with other functions port pins LPC2917/2919/01. Table shows external memory controller pins.
Table Symbol EXTBUS EXTBUS BLSy EXTBUS EXTBUS External memory controller pins Direction Description memory-bank select, runs from byte-lane select input runs from write enable (active LOW) output enable (active LOW) address data
EXTBUS A[23:0] EXTBUS D[31:0] IN/OUT
6.9.3 Clock description
External Static-Memory Controller clocked CLK_SYS_SMC, Section 6.7.2.
6.9.4 External memory timing diagrams
timing diagram reading from external memory shown Figure relationship between wait-state settings indicated with arrows.
LPC2917_19_01_2
B.V. 2009. rights reserved.
Preliminary data sheet
Rev. June 2009
Semiconductors
LPC2917/01; LPC2919/01
ARM9 microcontroller with
CLK(SYS)
WST1 WSTOEN
002aae704
WSTOEN WST1
Reading from external memory
timing diagram writing external memory shown Figure relationship between wait-state settings indicated with arrows.
CLK(SYS)
WE/BLS(1)
WST2 WSTWEN
002aae705
WSTWEN WST2 same timing configurations that byte lane enable signals connect write enable devices).
LPC2917_19_01_2
Writing external memory
B.V. 2009. rights reserved.
Preliminary data sheet
Rev. June 2009
Semiconductors
LPC2917/01; LPC2919/01
ARM9 microcontroller with
Usage idle/turn-around time (IDCY) demonstrated Figure Extra wait states added between read write cycle same external memory device.
CLK(SYS)
WST1 IDCY WSTWEN
002aae706
WST2
WSTOEN
WSTOEN WSTWEN WST1 WST2 IDCY
Reading/writing external memory
Address pins device shared with other functions. When connecting external memories, check that programmed correct function. Control these settings handled SCU.
6.10 controller
controller allows peripheral-to memory, memory-to-peripheral, peripheral-to-peripheral, memory-to-memory transactions. Each stream provides unidirectional serial transfers single source destination. example, bidirectional port requires stream transmit receives. source destination areas each either memory region peripheral, accessed through same master area each master. controls eight channels with hardware prioritization. controller interfaces system masters, each with full 32-bit data width. operations 8-bit, 16-bit, 32-bit data widths, either big-endian little-endian. Incrementing non-incrementing addressing source destination supported, well programmable burst size. Scatter gather supported through linked lists. This means that source destination areas have occupy contiguous areas memory.
6.10.1 support peripherals
GPDMA supports following peripherals: SPI0/1/2 UART0/1. GPDMA access both embedded SRAM blocks kB), both TCMs, external static memory, flash memory.
LPC2917_19_01_2 B.V. 2009. rights reserved.
Preliminary data sheet
Rev. June 2009
Semiconductors
LPC2917/01; LPC2919/01
ARM9 microcontroller with
6.10.2 Clock description
controller clocked CLK_SYS_DMA derived from BASE_SYS_CLK, Section 6.7.2.
6.11 General subsystem
6.11.1 General subsystem clock description
general subsystem clocked CLK_SYS_GESS, Section 6.7.2.
6.11.2 Chip feature identification
Chip/Feature (CFID) module contains registers which show control functionality chip. contains identify silicon also registers containing information about features enabled disabled chip. features are:
Identification product Identification features enabled
CFID external pins.
6.11.3 System Control Unit (SCU)
system control unit contains system-related functions.The feature configuration port-pins multiplexer. defines function each LPC2917/2919/01. configuration should consistent with peripheral function usage. external pins.
6.11.4 Event router
event router provides bus-controlled routing input events vectored interrupt controller interrupt wake-up signals. features:
level-sensitive external interrupt pins, including receive pins SPI, CAN,
LIN, UART, well I2C-bus pins plus three internal event sources.
Input events used interrupt source either directly latched
(edge-detected).
Direct events disappear when event becomes inactive. Latched events remain active until they explicitly cleared. Programmable input level edge polarity. Event detection maskable. Event detection fully asynchronous, clock required.
event router allows event source defined, polarity activation type selected interrupt masked enabled. event router used start clock external event.
LPC2917_19_01_2
B.V. 2009. rights reserved.
Preliminary data sheet
Rev. June 2009
Semiconductors
LPC2917/01; LPC2919/01
ARM9 microcontroller with
vectored interrupt-controller inputs active HIGH. 6.11.4.1 description event router module LPC2917/2919/01 connected pins listed below. pins combined with other functions port pins LPC2917/2919/01. Table shows pins connected event router, also corresponding position event-router registers default polarity.
Table Symbol EXTINT CAN0 CAN1 I2C0_SCL I2C1_SCL LIN0 LIN1 SPI0 SPI1 SPI2 UART0 UART1 Event-router connections Direction Description external interrupt input CAN0 receive data input wake-up CAN1 receive data input wake-up I2C0 clock input I2C1 clock input LIN0 receive data input wake-up LIN1 receive data input wake-up SPI0 receive data input SPI1 receive data input SPI2 receive data input UART0 receive data input UART1 receive data input interrupt (internal) (internal) (internal) Default polarity
6.12 Peripheral subsystem
6.12.1 Peripheral subsystem clock description
peripheral subsystem clocked number different clocks:
CLK_SYS_PESS CLK_UART0/1 CLK_SPI0/1/2 CLK_TMR0/1/2/3 CLK_SAFE Section 6.7.2
6.12.2 Watchdog timer
purpose watchdog timer reset ARM9 processor within reasonable amount time processor enters error state. watchdog generates system reset user program fails trigger correctly within predetermined amount time. features:
Internal chip reset periodically triggered Timer counter register runs always-on safe clock
LPC2917_19_01_2 B.V. 2009. rights reserved.
Preliminary data sheet
Rev. June 2009
Semiconductors
LPC2917/01; LPC2919/01
ARM9 microcontroller with
6.12.2.1
Optional interrupt generation watchdog time-out Debug mode with disabling reset Watchdog control register change-protected with Programmable 32-bit watchdog timer period with programmable 32-bit prescaler.
Functional description watchdog timer consists 32-bit counter with 32-bit prescaler. watchdog should programmed with time-out value then periodically restarted. When watchdog times out, generates reset through RGU. generate watchdog interrupts watchdog debug mode interrupt enabled interrupt enable register. watchdog-overflow interrupt cleared writing clear-interrupt register. Another prevent resets during debug mode Pause feature watchdog timer. watchdog stalled when ARM9 debug mode PAUSE_ENABLE watchdog timer control register set. Watchdog Reset output Reset Generator Unit (RGU). contains reset source register identify reset source when device gone through reset. Section 6.15.4.
6.12.2.2
Clock description watchdog timer clocked different clocks; CLK_SYS_PESS CLK_SAFE, Section 6.7.2. register interface towards system clocked CLK_SYS_PESS. timer prescale counters clocked CLK_SAFE which always
6.12.3 Timer
LPC2917/2919/01 contains identical timers: four peripheral subsystem Modulation Sampling Control SubSystem (MSCSS) located different peripheral base addresses. This section describes four timers peripheral subsystem. Each timer four capture inputs and/or match outputs. Connection device pins depends configuration programmed into port function-select registers. timers located MSCSS have external capture match pins, memory identical, Section 6.14.6. these timers external input pause function. features are:
32-bit timer/counter with programmable 32-bit prescaler four 32-bit capture channels timer. These take snapshot timer value
when external signal connected TIMERx CAPn input changes state. capture event also optionally generate interrupt
Four 32-bit match registers timer that allow:
Continuous operation with optional interrupt generation match Stop timer match with optional interrupt generation Reset timer match with optional interrupt generation
LPC2917_19_01_2 B.V. 2009. rights reserved.
Preliminary data sheet
Rev. June 2009
Semiconductors
LPC2917/01; LPC2919/01
ARM9 microcontroller with
four external outputs timer corresponding match registers, with
following capabilities: match HIGH match Toggle match nothing match
Pause input (MSCSS timers only)
timers designed count cycles clock optionally generate interrupts perform other actions specified timer values, based four match registers. They also include capture inputs trap timer value when input signal changes state, optionally generating interrupt. core function timers consists prescale counter triggering timer counter. Both counters clock CLK_TMRx runs from time references related period this clock. Note that each timer individual clock source within Peripheral SubSystem. Modulation Sampling SubSystem each timer also individual clock source. section Section 6.15.5 information generation these clocks. 6.12.3.1 description four timers peripheral subsystem LPC2917/2919/01 have pins described below. timers modulation sampling subsystem have external pins except pause MSCSS timer Section 6.14.6 description these timers their associated pins. timer pins combined with other functions port pins LPC2917/2919/01, Section 6.11.3. Table Table shows timer pins runs from
Table Symbol TIMERx CAP[0] TIMERx CAP[1] TIMERx CAP[2] TIMERx CAP[3] TIMERx MAT[0] TIMERx MAT[1] TIMERx MAT[2] TIMERx MAT[3] Timer pins name CAPx[0] CAPx[1] CAPx[2] CAPx[3] MATx[0] MATx[1] MATx[2] MATx[3] Direction Description TIMER capture input TIMER capture input TIMER capture input TIMER capture input TIMER match output TIMER match output TIMER match output TIMER match output
6.12.3.2
Clock description timer modules clocked different clocks; CLK_SYS_PESS CLK_TMRx 0-3), Section 6.7.2. Note that each timer CLK_TMRx branch clock power management. frequency these clocks identical they derived from same base clock BASE_CLK_TMR. register interface towards system clocked CLK_SYS_PESS. timer prescale counters clocked CLK_TMRx.
LPC2917_19_01_2
B.V. 2009. rights reserved.
Preliminary data sheet
Rev. June 2009
Semiconductors
LPC2917/01; LPC2919/01
ARM9 microcontroller with
6.12.4 UARTs
LPC2917/2919/01 contains identical UARTs located different peripheral base addresses. features are:
16-byte receive transmit FIFOs. Register locations conform industry standard. Receiver FIFO trigger points byte, bytes, bytes bytes. Built-in baud rate generator. Support RS-485/9-bit mode allows both software address detection automatic address detection using 9-bit mode.
UART commonly used implement serial interface such RS232. LPC2917/2919/01 contains industry-standard UARTs with 16-byte transmit receive FIFOs, they also into mode without FIFOs. 6.12.4.1 description UART pins combined with other functions port pins LPC2917/2919/01. Table shows UART pins runs from
Table Symbol UARTx UARTx UART pins name TXDx RXDx Direction Description UART channel transmit data output UART channel receive data input
6.12.4.2
Clock description UART modules clocked different clocks; CLK_SYS_PESS CLK_UARTx 0-1), Section 6.7.2. Note that each UART CLK_UARTx branch clock power management. frequency CLK_UARTx clocks identical since they derived from same base clock BASE_CLK_UART. register interface towards system clocked CLK_SYS_PESS. baud generator clocked CLK_UARTx.
6.12.5 Serial peripheral interface (SPI)
LPC2917/2919/01 contains three Serial Peripheral Interface modules (SPIs) allow synchronous serial communication with slave master peripherals. features are:
Master slave operation Each supports four slaves sequential multi-slave operation Supports timer-triggered operation Programmable clock rate prescale based source clock (BASE_SPI_CLK), independent system clock
Separate transmit receive FIFO memory buffers; bits wide, locations deep Programmable choice interface operation: Motorola Texas Instruments
Synchronous Serial Interfaces
Programmable data-frame size from bits
LPC2917_19_01_2 B.V. 2009. rights reserved.
Preliminary data sheet
Rev. June 2009
Semiconductors
LPC2917/01; LPC2919/01
ARM9 microcontroller with
Independent masking transmit FIFO, receive FIFO receive overrun interrupts Serial clock-rate master mode: fserial_clk fclk(SPI)/2 Serial clock-rate slave mode: fserial_clk fclk(SPI)/4 Internal loopback test mode
module operate
Master mode:
Normal transmission mode Sequential slave mode
Slave mode
6.12.5.1 Functional description module master slave interface synchronous serial communication with peripheral devices that have either Motorola Texas Instruments Synchronous Serial Interfaces. module performs serial-to-parallel conversion data received from peripheral device. transmit receive paths buffered with FIFO memories bits wide words deep). Serial data transmitted pins SDOx received pins SDIx. module includes programmable bit-rate clock divider prescaler generate serial clock from input clock CLK_SPIx. module's operating mode, frame format, word size programmed through SLVn_SETTINGS registers. single combined interrupt request SPI_INTREQ output asserted interrupts asserted unmasked. Depending operating mode selected, outputs operate active-HIGH frame synchronization output Texas Instruments synchronous serial frame format active chip select SPI. Each data frame between four bits long, depending size words programmed, transmitted starting with MSB. 6.12.5.2 description pins combined with other functions port pins LPC2917/2919/01, Section 6.11.3. Table shows pins runs from runs from
Table Symbol SPIx SCSy SPIx SPIx SPIx
LPC2917_19_01_2
pins name SCSx[y] SCKx SDIx SDOx Direction IN/OUT IN/OUT Description SPIx chip select[1][2] SPIx clock[1] SPIx data input SPIx data output
Direction SPIx SPIx pins depends master slave mode. These pins output master mode, input slave mode. slave mode there only chip select input pin, SPIx SCS0. other chip selects have function slave mode.
B.V. 2009. rights reserved.
Preliminary data sheet
Rev. June 2009
Semiconductors
LPC2917/01; LPC2919/01
ARM9 microcontroller with
6.12.5.3
Clock description modules clocked different clocks; CLK_SYS_PESS CLK_SPIx Section 6.7.2. Note that each CLK_SPIx branch clock power management. frequency clocks CLK_SPIx identical they derived from same base clock BASE_CLK_SPI. register interface towards system clocked CLK_SYS_PESS. serial-clock rate divisor clocked CLK_SPIx. clock frequency controlled CGU. master mode clock frequency (CLK_SPIx) must least twice serial clock rate interface. slave mode CLK_SPIx must four times serial clock rate interface.
6.12.6 General-purpose
LPC2917/2919/01 contains four general-purpose ports located different peripheral base addresses. pins bidirectional, direction programmed individually. behavior depends configuration programmed port function-select registers. features are:
6.12.6.1
General-purpose parallel inputs outputs Direction control individual bits Synchronized input sampling stable input-data values defaults input reset avoid possible conflicts
Functional description general-purpose provides individual control over each bidirectional port pin. There registers control direction output level. inputs synchronized achieve stable read-levels. generate open-drain output, output register desired value. direction register control signal. When output, output driver actively drives value output: when input signal floats pulled internally externally.
6.12.6.2
description five GPIO ports LPC2917/2919/01 have pins listed below. GPIO pins combined with other functions port pins LPC2917/2919/01. Table shows GPIO pins.
Table Symbol GPIO0 pin[31:0] GPIO1 pin[31:0] GPIO2 pin[27:0] GPIO3 pin[15:0] GPIO pins name P0[31:0] P1[31:0] P2[27:0] P3[15:0] Direction IN/OUT IN/OUT IN/OUT IN/OUT Description GPIO port pins GPIO port pins GPIO port pins GPIO port pins
LPC2917_19_01_2
B.V. 2009. rights reserved.
Preliminary data sheet
Rev. June 2009
Semiconductors
LPC2917/01; LPC2919/01
ARM9 microcontroller with
6.12.6.3
Clock description GPIO modules clocked several clocks, which derived from BASE_SYS_CLK; CLK_SYS_PESS CLK_SYS_GPIOx Section 6.7.2. Note that each GPIO CLK_SYS_GPIOx branch clock power management. frequency clocks CLK_SYS_GPIOx identical CLK_SYS_PESS since they derived from same base clock BASE_SYS_CLK.
6.13 Networking subsystem
6.13.1 gateway
Controller Area Network (CAN) definition high-performance communication protocol serial data communication. controllers LPC2917/2919/01 provide full implementation protocol according specification version 2.0B. gateway concept fully scalable with number controllers, always operates together with separate powerful flexible hardware acceptance filter. features are:
6.13.1.1
Supports 11-bit well 29-bit identifiers Double receive buffer triple transmit buffer Programmable error-warning limit error counters with read/write access Arbitration-lost capture error-code capture with detailed position Single-shot transmission (i.e. re-transmission) Listen-only mode acknowledge; active error flags) Reception `own' messages (self-reception request) FullCAN mode message reception
Global acceptance filter global acceptance filter provides look-up received identifiers called acceptance filtering terminology controllers. includes look-up table memory, which software maintains five sections identifiers. look-up table memory large (512 words, each bits). contain 1024 standard frame identifiers extended frame identifiers mixture both types. also possible define identifier groups standard extended message formats.
6.13.1.2
description controllers LPC2917/2919/01 have pins listed below. pins combined with other functions port pins LPC2917/2919/01. Table shows pins runs from
Table Symbol CANx CANx pins name TXDC0/1 RXDC0/1 Direction Description channel transmit data output channel receive data input
LPC2917_19_01_2
B.V. 2009. rights reserved.
Preliminary data sheet
Rev. June 2009
Semiconductors
LPC2917/01; LPC2919/01
ARM9 microcontroller with
6.13.2
LPC2917/2919/01 contain master controllers. These used dedicated master controllers with additional support sync break generation with hardware implementation protocol according spec 2.0. Remark: Both channels also configured UART channels. features are:
6.13.2.1
Complete message handling transfer interrupt message Slave response time-out detection Programmable sync-break length Automatic sync-field sync-break generation Programmable inter-byte space Hardware software parity generation Automatic checksum generation Fault confinement Fractional baud rate generator
description master controllers LPC2917/2919/01 have pins listed below. pins combined with other functions port pins LPC2917/2919/01. Table shows pins. more information Ref. subsection 3.43, master controller.
Table Symbol LIN0/1 LIN0/1 controller pins name TXDL0/1 RXDL0/1 Direction Description channel transmit data output channel receive data input
6.13.3 I2C-bus serial controllers
LPC2917/2919/01 each contain I2C-bus controllers. I2C-bus bidirectional inter-IC control using only wires: serial clock line (SCL) serial data line (SDA). Each device recognized unique address operate either receiver-only device (e.g., driver) transmitter with capability both receive send information (such memory). Transmitters and/or receivers operate either master slave mode, depending whether chip initiate data transfer only addressed. multi-master bus, controlled more than master connected main features I2C-bus interfaces are:
I2C0 I2C1 standard pins with rates kbit/s (Fast I2C-bus)
support powering individual devices connected same lines.
Easy configure master, slave, master/slave.
LPC2917_19_01_2 B.V. 2009. rights reserved.
Preliminary data sheet
Rev. June 2009
Semiconductors
LPC2917/01; LPC2919/01
ARM9 microcontroller with
Programmable clocks allow versatile rate control. Bidirectional data transfer between masters slaves. Multi-master central master). Arbitration between simultaneously transmitting masters without corruption serial data bus. serial bus.
Serial clock synchronization allows devices with different rates communicate Serial clock synchronization used handshake mechanism suspend
resume serial transfer.
I2C-bus used test diagnostic purposes. I2C-bus controllers support multiple address recognition monitor mode.
6.13.3.1 description
Table Symbol SCL0/1 SDA0/1
I2C-bus pins[1] name SCL0/1 SDA0/1 Direction Description clock input/output data input/output
Note that pins I2C-bus compliant open-drain pins.
6.14 Modulation sampling control subsystem
Modulation Sampling Control Subsystem (MSCSS) LPC2917/2919/01 includes four Pulse-Width Modulators (PWMs), 10-bit successive approximation Analog-to-Digital Converters (ADCs) timers. features MSCSS are:
10-bit, ksamples/s, 8-channel ADCs with inputs various triggerstart options
Four 6-channel PWMs (Pulse-Width Modulators) with capture trap functionality dedicated timers schedule synchronize PWMs ADCs Quadrature encoder interface
6.14.1 Functional description
MSCSS contains Pulse-Width Modulators (PWMs), Analog-to-Digital Converters (ADCs) timers. Figure provides overview MSCSS. AHB-to-APB bridge takes care communication with system bus. internal timers dedicated this subsystem. MSCSS timer used generate start pulses ADCs first PWM. second timer (MSCSS timer used generate `carrier' signals PWMs. These carrier patterns used, example, applications requiring current control. Several other trigger possibilities provided ADCs (external, cascaded following PWM). capture inputs both timers also used capture start pulse ADCs.
LPC2917_19_01_2
B.V. 2009. rights reserved.
Preliminary data sheet
Rev. June 2009
Semiconductors
LPC2917/01; LPC2919/01
ARM9 microcontroller with
PWMs used generate waveforms which frequency, duty cycle rising falling edges controlled very precisely. Capture inputs provided measure event phases compared main counter. Depending applications, these inputs connected digital sensor motor outputs digital external signals. Interrupt signals generated several events closely interact with CPU. ADCs used application needing accurate digitized data from analog sources. support applications like motor control, mechanism synchronize several PWMs ADCs available (sync_in sync_out). Note that PWMs clock ADCs clock, Section 6.15.2.
LPC2917_19_01_2
B.V. 2009. rights reserved.
Preliminary data sheet
Rev. June 2009
Semiconductors
LPC2917/01; LPC2919/01
ARM9 microcontroller with
AHB-TO-APB BRIDGE
MSCSS
IDX0 PHA0 PHB0
capture
ADC1 START start MSCSS TIMER0 ADC1 ADC1 IN[7:0]
start ADC2
ADC2 START ADC2 IN[7:0]
start PWM0 capture carrier synch carrier PAUSE MSCSS TIMER1 carrier PWM1 synch PWM2 carrier synch PWM3 PWM3 MAT[5:0] PWM2 MAT[5:0] PWM1 MAT[5:0] PWM0 MAT[5:0]
PWM0 TRAP PWM0 CAP[2:0] PWM1 TRAP PWM1 CAP[2:0] PWM2 TRAP PWM2 CAP[2:0] PWM3 TRAP PWM3 CAP[2:0]
002aad961
Modulation Sampling Control Subsystem (MSCSS) block diagram
LPC2917_19_01_2
B.V. 2009. rights reserved.
Preliminary data sheet
Rev. June 2009
Semiconductors
LPC2917/01; LPC2919/01
ARM9 microcontroller with
6.14.2 description
pins LPC2917/2919/01 MSCSS associated with modules described Section 6.14.4.2. Pins connected four modules described Section 6.14.5.4, pins directly connected MSCSS timer module described Section 6.14.6.1, pins connected quadrature encoder interface described Section 6.14.7.1.
6.14.3 Clock description
MSCSS clocked from number different sources:
CLK_SYS_MSCSS_A clocks side AHB-to-APB bridge CLK_MSCSS_APB clocks subsystem CLK_MSCSS_MTMR0/1 clocks timers CLK_MSCSS_PWM0.3 clocks PWMs.
Each clock areas; part clocked CLK_MSCSS_ADCx_APB control part analog section clocked CLK_ADCx Section 6.7.2. clocks derived from BASE_MSCSS_CLK, except CLK_SYS_MSCSS_A which derived form BASE_SYS_CLK, CLK_ADCx clocks which derived from BASE_CLK_ADC. specific modules used their corresponding clocks switched off.
6.14.4 Analog-to-digital converter
MSCSS LPC2917/2919/01 includes 10-bit successive-approximation analog-to-digital converters. features interface module are:
ADC1 ADC2: Eight analog inputs; time-multiplexed; measurement range
External reference-level inputs ksamples second 10-bit resolution 1500 ksamples second
2-bit resolution
Programmable resolution from 2-bit 10-bit Single analog-to-digital conversion scan mode continuous analog-to-digital
conversion scan mode
Optional conversion transition external start input, timer capture/match signal,
PWM_sync `previous'
Converted digital values stored register each channel Optional compare condition generate `less than' `equal greater than'
compare-value indication each channel
Power-down mode
LPC2917_19_01_2
B.V. 2009. rights reserved.
Preliminary data sheet
Rev. June 2009
Semiconductors
LPC2917/01; LPC2919/01
ARM9 microcontroller with
6.14.4.1
Functional description block diagram, Figure shows basic architecture each ADC. functionality divided into major parts; part running MSCSS Subsystem clock, other clock. This split into clock domains affects behavior from system-level perspective. actual analog-to-digital conversions take place clock domain, system control takes place system clock domain. mechanism provided modify configuration control moment which updated configuration transferred domain. clock limited maximum frequency should always lower than equal system clock frequency. meet this constraint select desired lower sampling frequency, clock generation unit provides programmable fractional system-clock divider dedicated clock. Conversion rate determined clock frequency divided number resolution bits plus one. Accessing registers requires enabled clock, which controllable clock generation unit, Section 6.15.2. Each four start inputs. Note that start start captured system clock domain while start start captured domain. start inputs connected MSCSS level, Figure details.
clock (BASE_MSCSS_CLK)
clock MHz) (BASE_ADC_CLK)
SYSTEM DOMAIN
DOMAIN
update system scan compare REGISTERS conversion data configuration data CONTROL
ADC1
ANALOG ANALOG
ADC1 IN[7:0]
ADC2
ADC2 IN[7:0]
start
start
start
start
sync_out
002aad960
block diagram
6.14.4.2
description modules MSCSS have pins described below. ADCx input pins combined with other functions port pins LPC2917/2919/01. VREFN VREFP pins common both ADCs. Table shows pins.
LPC2917_19_01_2
B.V. 2009. rights reserved.
Preliminary data sheet
Rev. June 2009
Semiconductors
LPC2917/01; LPC2919/01
ARM9 microcontroller with
Analog digital converter pins name IN1/2[7:0] Direction Description analog input ADC1/2, channel channel external start-trigger input reference level HIGH reference level
Table Symbol
ADC1/2 IN[7:0]
ADCn_EXT_START CAP1[n] VREFN VREFP VREFN VREFP
Remark: Note that ADC1 ADC2 accept input voltage (see Table ADC1/2 pins. used, pins tolerant. 6.14.4.3 Clock description modules clocked from different sources; CLK_MSCSS_ADCx_APB CLK_ADCx Section 6.7.2. Note that each CLK_ADCx CLK_MSCSS_ADCx_APB branch clocks power management. unused both CLK_MSCSS_ADCx_APB CLK_ADCx switched off. frequency CLK_MSCSS_ADCx_APB clocks identical CLK_MSCSS_APB since they derived from same base clock BASE_MSCSS_CLK. Likewise frequency CLK_ADCx clocks identical since they derived from same base clock BASE_ADC_CLK. register interface towards system clocked CLK_MSCSS_ADCx_APB. Control logic analog section clocked CLK_ADCx, also Figure
6.14.5 Pulse Width Modulator (PWM)
MSCSS LPC2917/2919/01 includes four modules with following features.
pulse-width modulated output signals Double edge features (rising falling edges programmed individually) Optional interrupt generation match (each edge) Different operation modes: continuous run-once 16-bit counter 16-bit prescale counter allow large range periods protective mode (TRAP) holding output software-controllable state with optional interrupt generation trap event capture event
Three capture registers capture trigger pins with optional interrupt generation Interrupt generation match event, capture event, counter overflow trap
event
burst mode mixing external carrier signal with internally generated Programmable sync-delay output trigger other modules (master/slave
behavior)
LPC2917_19_01_2
B.V. 2009. rights reserved.
Preliminary data sheet
Rev. June 2009
Semiconductors
LPC2917/01; LPC2919/01
ARM9 microcontroller with
6.14.5.1
Functional description ability provide flexible waveforms allows blocks used multiple applications; e.g. dimmer/lamp control control. Pulse-width modulation preferred method regulating power since additional heat generated, energy-efficient when compared with linear-regulating voltage control networks. delivers waveforms/pulses desired duty cycles cycle periods. very basic application these pulses controlling amount power transferred load. Since duty cycle pulses controlled, desired amount power transferred controlled duration. examples such applications are:
Dimmer controller: flexibility providing waves desired duty cycle cycle
period allows control amount power transferred load. functions dimmer controller this application
Motor controller: provides multi-phase outputs, these outputs
controlled have certain pattern sequence. this force/torque motor adjusted desired. This makes function motor drive.
sync_in transfer_enable_in
DOMAIN update system CONTROL REGISTERS capture data
DOMAIN
match outputs PWM, COUNTER, PRESCALE COUNTER SHADOW REGISTERS capture inputs
counter value
capt_match
config data IRQs
trap input carrier inputs
transfer_enable_out sync_out
002aad837
block diagram
block diagram Figure shows basic architecture each PWM. functionality split into major parts, domain domain, both which clocks derived from BASE_MSCSS_CLK. This split into domains affects behavior from system-level perspective. actual prescale counters located domain system control takes place domain.
LPC2917_19_01_2
B.V. 2009. rights reserved.
Preliminary data sheet
Rev. June 2009
Semiconductors
LPC2917/01; LPC2919/01
ARM9 microcontroller with
actual consists counters; 16-bit prescale counter 16-bit counter. position rising falling edges outputs programmed individually. prescale counter allows high system frequencies scaled down lower periods. Registers available capture counter values external events. Note that Modulation Sampling SubSystem, each individual clock source CLK_MSCSS_PWMx runs from Both prescale timer counters within each this clock CLK_MSCSS_PWMx, time references related period this clock. Section 6.15 information generation these clocks. 6.14.5.2 Synchronizing counters mechanism included synchronize period other PWMs providing sync input sync output with programmable delay. Several PWMs synchronized using sync_in/sync_out ports. Figure details connections modules within MSCSS LPC2917/2919/01. master over master over etc. 6.14.5.3 Master slave mode module provide synchronization signals other modules (also called Master mode). signal sync_out pulse clock cycle generated when internal counter (re)starts. signal trans_enable_out pulse synchronous sync_out, generated transfer from system registers shadow registers occurred when counter restarted. delay inserted between counter start generation trans_enable_out sync_out. module input signals trans_enable_in sync_in synchronize internal counter transfer shadow registers (Slave mode). 6.14.5.4 description Each four modules MSCSS following pins. These combined with other functions port pins LPC2917/2919/01. Table shows PWM0 PWM3 pins.
Table Symbol PWMn CAP[0] PWMn CAP[1] PWMn CAP[2] PWMn MAT[0] PWMn MAT[1] PWMn MAT[2] PWMn MAT[3] PWMn MAT[4] PWMn MAT[5] PWMn TRAP pins name PCAPn[0] PCAPn[1] PCAPn[2] PMATn[0] PMATn[1] PMATn[2] PMATn[3] PMATn[4] PMATn[5] TRAPn Direction Description capture input capture input capture input match output match output match output match output match output match output trap input
LPC2917_19_01_2
B.V. 2009. rights reserved.
Preliminary data sheet
Rev. June 2009
Semiconductors
LPC2917/01; LPC2919/01
ARM9 microcontroller with
6.14.5.5
Clock description modules clocked CLK_MSCSS_PWMx Section 6.7.2. Note that each CLK_MSCSS_PWMx branch clock power management. frequency these clocks identical CLK_MSCSS_APB since they derived from same base clock BASE_MSCSS_CLK. Also note that unlike timer modules Peripheral SubSystem, actual timer counter registers modules same clock system interface CLK_MSCSS_APB. This clock independent system clock. module used CLK_MSCSS_PWMx branch clock switched off.
6.14.6 Timers MSCSS
timers MSCSS functionally identical timers peripheral subsystem, Section 6.12.3. features timers MSCSS same timers peripheral subsystem, capture inputs match outputs available device pins. These signals instead connected modules outlined description MSCSS, Section 6.14.1. section Section 6.12.3 functional description timers. 6.14.6.1 description MSCSS timer external pins. MSCSS timer PAUSE available external pin. PAUSE combined with other functions port pins LPC2917/2919/01. Table shows MSCSS timer external pin.
Table Symbol MSCSS PAUSE MSCSS timer Direction Description pause MSCSS timer
6.14.6.2
Clock description Timer modules MSCSS clocked CLK_MSCSS_MTMRx Section 6.7.2. Note that each timer CLK_MSCSS_MTMRx branch clock power management. frequency these clocks identical CLK_MSCSS_APB since they derived from same base clock BASE_MSCSS_CLK. Note that, unlike timer modules Peripheral SubSystem, actual timer counter registers same clock system interface CLK_MSCSS_APB. This clock independent system clock. timer module used CLK_MSCSS_MTMRx branch clock switched off.
6.14.7 Quadrature Encoder Interface (QEI)
quadrature encoder, also known 2-channel incremental encoder, converts angular displacement into pulse signals. monitoring both number pulses relative phase signals, user track position, direction rotation, velocity. addition, third channel, index signal, used reset position counter. quadrature encoder interface decodes digital pulses from quadrature encoder wheel integrate position over time determine direction rotation. addition, capture velocity encoder wheel.
LPC2917_19_01_2 B.V. 2009. rights reserved.
Preliminary data sheet
Rev. June 2009
Semiconductors
LPC2917/01; LPC2919/01
ARM9 microcontroller with
following features:
Tracks encoder position. Increments/ decrements depending direction. Programmable position counting. Velocity capture using built-in timer. Velocity compare function with less than interrupt. Uses 32-bit registers position velocity. Three position compare registers with interrupts. Index counter revolution counting. Index compare register with interrupts. combine index position interrupts produce interrupt whole partial revolution displacement.
Digital filter with programmable delays encoder input signals. accept decoded signal inputs (clk direction). Connected APB.
6.14.7.1 description module MSCSS following pins. These combined with other functions port pins LPC2917/2919/01. Table shows pins.
Table Symbol QEI0 QEI0 pins name IDX0 PHA0 Direction Description Index signal. used reset position. Sensor signal. Corresponds quadrature mode direction clock/direction mode. Sensor signal. Corresponds quadrature mode clock signal clock/direction mode.
QEI0
PHB0
6.14.7.2
Clock description module clocked CLK_MSCSS_QEI, Section 6.7.2. frequency this clock identical CLK_MSCSS_APB since they derived from same base clock BASE_MSCSS_CLK. used CLK_MSCSS_QEI branch clock switched off.
6.15 Power, clock reset control subsystem
Power, Clock, Reset Control Subsystem (PCRSS) LPC2917/2919/01 includes Clock Generator Units (CGU0 CGU1), Reset Generator Unit (RGU) Power Management Unit (PMU). Figure provides overview PCRSS. AHB-to-DTL bridge provides communication with system bus.
LPC2917_19_01_2
B.V. 2009. rights reserved.
Preliminary data sheet
Rev. June 2009
Semiconductors
LPC2917/01; LPC2919/01
ARM9 microcontroller with
CGU0 EXTERNAL OSCILLATOR OUT6 OUT11
CGU1
POWER RING OSCILLATOR FDIV[6:0] OUT0 OUT1 FDIV CLOCK GATES branch clocks
OUT5 OUT7 master disable: grant request
CGU0/1 REGISTERS
OUT9 CLOCK ENABLE CONTROL
AHB2DTL BRIDGE
REGISTERS
wakeup_a
AHB_RST REGISTERS SCU_RST RESET OUTPUT DELAY LOGIC WARM_RST COLD_RST PCR_RST RGU_RST POR_RST
INPUT DEGLITCH/ SYNC
(device pin) reset from watchdog counter
002aae355
Power, Clock, Reset control System (PCRSS) block diagram
6.15.1 Clock description
PCRSS clocked number different clocks. CLK_SYS_PCRSS clocks side bridge CLK_PCR_SLOW clocks CGU, internal logic, Section 6.7.2. CLK_SYS_PCRSS derived from BASE_SYS_CLK, which switched low-power modes. CLK_PCR_SLOW derived from BASE_PCR_CLK always order able wake from low-power modes.
LPC2917_19_01_2 B.V. 2009. rights reserved.
Preliminary data sheet
Rev. June 2009
Semiconductors
LPC2917/01; LPC2919/01
ARM9 microcontroller with
6.15.2 Clock Generation Unit (CGU0)
features are:
Generation base clocks, selectable from several embedded clock sources. Crystal oscillator with power-down. Control with power-down. Very low-power ring oscillator, always provide `safe clock'. Seven fractional clock dividers with division. Individual source selector each base clock, with glitch-free switching. Autonomous clock-activity detection every clock source. Protection against switching invalid inactive clock sources. Embedded frequency counter. Register write-protection mechanism prevent unintentional alteration clocks.
Remark: clock-frequency adjustment direct impact timing on-board peripherals. 6.15.2.1 Functional description clock generation unit provides internal clock sources described Table
Table Numbe
CGU0 base clocks Name BASE_SAFE_CLK BASE_SYS_CLK BASE_PCR_CLK BASE_IVNSS_CLK BASE_MSCSS_CLK BASE_UART_CLK BASE_ICLK0_CLK BASE_SPI_CLK BASE_TMR_CLK BASE_ADC_CLK reserved BASE_ICLK1_CLK Frequency (MHz) Description base safe clock (always base system clock base subsystem clock base IVNSS subsystem clock base MSCSS subsystem clock base UART clock base internal clock CGU1 base clock base timers clock base ADCs clock base internal clock CGU1
Maximum frequency that guarantees stable operation LPC2917/2919/01. Fixed low-power oscillator.
LPC2917_19_01_2
B.V. 2009. rights reserved.
Preliminary data sheet
Rev. June 2009
Semiconductors
LPC2917/01; LPC2919/01
ARM9 microcontroller with
CLOCK GENERATION UNIT (CGU0)
BASE_SAFE_CLK
FDIV0 LP_OSC clkout clkout120 clkout240 BASE_SYS_CLK
EXTERNAL OSCILLATOR
FDIV1 BASE_PCR_CLK
BASE_IVNSS_CLK
FDIV6
BASE_ICLK1_CLK
FREQUENCY MONITOR
CLOCK DETECTION
BRIDGE
002aae147
Block diagram CGU0
generation these base clocks, consists primary secondary clock generators output generator each base clock. There primary clock generators: low-power ring oscillator (LP_OSC) crystal oscillator. Figure LP_OSC source BASE_PCR_CLK that clocks CGU0 itself BASE_SAFE_CLK that clocks minimum other logic device (like watchdog timer). prevent device from losing clock source LP_OSC cannot into power-down. crystal oscillator used source high-frequency clocks external clock input crystal connected. Secondary clock generators seven fractional dividers (FDIV0.6). three clock outputs: normal, 120° phase-shifted 240° phase-shifted.
LPC2917_19_01_2 B.V. 2009. rights reserved.
Preliminary data sheet
Rev. June 2009
Semiconductors
LPC2917/01; LPC2919/01
ARM9 microcontroller with
Configuration CGU0: every output generator generating base clocks choice made from primary secondary clock generators according Figure
LP_OSC FDIV0:6 EXTERNAL OSCILLATOR clkout clkout120 clkout240
OUTPUT CONTROL clock outputs
002aad834
Structure clock generation scheme
output generator (except BASE_SAFE_CLK BASE_PCR_CLK) connected either fractional divider (FDIV0.6) outputs LP_OSC/crystal oscillator directly. BASE_SAFE_CLK BASE_PCR_CLK only LP_OSC source. fractional dividers connected outputs directly LP_OSC/crystal Oscillator. connected crystal oscillator. this every output generating base clocks configured required clock. Multiple output generators connected same primary secondary clock source, multiple secondary clock sources connected same output primary clock source. Invalid selections/programming connecting FDIV outputs itself example will blocked hardware. control register will written, previous value will kept, although other fields will written with data. This prevents clocks being blocked incorrect programming. Default Clock Sources: Every secondary clock generator output generator connected LP_OSC reset. this device runs frequency after reset. recommended switch BASE_SYS_CLK high-frequency clock generator first steps boot code after verifying that high-frequency clock generator running. Clock Activity Detection: Clocks that inactive automatically regarded invalid, values `CLK_SEL' that would select those clocks masked written control registers. This accomplished adding clock detector every clock
LPC2917_19_01_2 B.V. 2009. rights reserved.
Preliminary data sheet
Rev. June 2009
Semiconductors
LPC2917/01; LPC2919/01
ARM9 microcontroller with
generator. RDET register keeps track which clocks active inactive, appropriate `CLK_SEL' values masked unmasked accordingly. Each clock detector also generate interrupts clock activation deactivation that system notified change internal clock status. Clock detection done using counter running BASE_PCR_CLK frequency. positive clock edge occurs before counter cycles BASE_PCR_CLK clock assumed inactive. BASE_PCR_CLK slower than clocks detected, normally only BASE_PCR_CLK cycle needed detect activity. After reset clocks assumed `non-present', RDET status register will correct only after BASE_PCR_CLK cycles. Note that this mechanism cannot protect against currently-selected clock going from active inactive state. Therefore inactive clock still sent system under special circumstances, although interrupt still generated notify system. Glitch-Free Switching: Provisions included allow clocks switched glitch-free, both output generator stage also secondary source generators. case clock will stopped held long enough allow stabilize lock before being re-enabled. non-PLL Generators switch will occur quickly possible, although there will always period when clock held synchronization requirements. current clock high does within cycles BASE_PCR_CLK assumed inactive asynchronously forced low. This prevents deadlocks interface. 6.15.2.2 functional description block diagram shown Figure input clock directly analog section. This block compares phase frequency inputs generates main clock2. These clocks either divided programmable post divider create output clock, sent directly output. main output clock then divided programmable feedback divider generate feedback clock. output signal analog section also monitored lock detector signal when locked onto input clock.
PSEL bits P23EN 2PDIV clkout120 clkout240 clkout
input clock
bypass direct MDIV clkout
002aad833
MSEL bits
block diagram
Generation main clock restricted frequency range clock input. Table Dynamic characteristics.
B.V. 2009. rights reserved.
LPC2917_19_01_2
Preliminary data sheet
Rev. June 2009
Semiconductors
LPC2917/01; LPC2919/01
ARM9 microcontroller with
Triple output phases: applications that require multiple clock phases additional clock outputs enabled setting register P23EN logic thus giving three clocks with 120° phase difference. this mode three clocks generated analog section sent output dividers. When achieved lock second third phase output dividers unsynchronized, which means that phase relation output clocks unknown. When LOCK register second third phase output dividers synchronized main output clock CLKOUT PLL, thus giving three clocks with 120° phase difference. Direct output mode: normal operating mode (with DIRECT logic clock divided depending value PSEL[1:0] input, giving output clock with duty cycle. higher output frequency needed clock sent directly output setting DIRECT logic Since does directly generate duty cycle clock, output clock duty cycle this mode deviate from Power-down control: Power-down mode been incorporated reduce power consumption when clock needed. This enabled setting control register bit. this mode analog section turned off, oscillator phase-frequency detector stopped dividers enter reset state. While Power-down mode LOCK output low, indicating that lock. When Power-down mode terminated clearing control-register resumes normal operation, makes LOCK signal high once regained lock input clock. 6.15.2.3 description CGU0 module LPC2917/2919/01 pins listed Table below.
Table Symbol XOUT_OSC XIN_OSC CGU0 pins Direction Description Oscillator crystal output Oscillator crystal input external clock input
6.15.3 Clock generation CLK_OUT (CGU1)
CGU1 block functionally identical CGU0 block generates dedicated output clock. CGU1 block uses fractional divider. PLLs used CGU0 CGU1 identical (see Section 6.15.2.2). clock input CGU1 provided base clocks generated CGU0: BASE_ICLK0_CLK BASE_ICLK1_CLK. base clock used configured drive output clock directly.
LPC2917_19_01_2
B.V. 2009. rights reserved.
Preliminary data sheet
Rev. June 2009
Semiconductors
LPC2917/01; LPC2919/01
ARM9 microcontroller with
CLOCK GENERATION UNIT (CGU1)
BASE_ICLK0_CLK BASE_ICLK1_CLK clkout clkout120 clkout240
BASE_OUT_CLK
FDIV0
BRIDGE
002aae266
Block diagram CGU1
6.15.3.1
description CGU1 module LPC2917/2919/01 pins listed Table below.
Table Symbol CLK_OUT CGU1 pins Direction Description clock output
6.15.4 Reset Generation Unit (RGU)
controls internal resets. features Reset Generation Unit (RGU) are:
6.15.4.1
Reset controlled individually subsystem Automatic reset stretching release Monitor function trace resets back source Register write-protection mechanism prevent unintentional resets
Functional description Each reset output defined combination reset input sources including external reset input pins internal power-on reset, Table first five resets listed this table form sort cascade provide multiple levels impact that reset have. combined input sources logically OR-ed together that activating listed reset sources causes output active.
LPC2917_19_01_2
B.V. 2009. rights reserved.
Preliminary data sheet
Rev. June 2009
Semiconductors
LPC2917/01; LPC2919/01
ARM9 microcontroller with
Reset output configuration Reset source power-on reset module POR_RST, RGU_RST, WATCHDOG PCR_RST COLD_RST COLD_RST COLD_RST COLD_RST COLD_RST COLD_RST WARM_RST WARM_RST WARM_RST WARM_RST WARM_RST WARM_RST WARM_RST WARM_RST WARM_RST WARM_RST WARM_RST WARM_RST WARM_RST WARM_RST WARM_RST WARM_RST WARM_RST WARM_RST Parts device reset when activated LP_OSC; source RGU_RST internal; source PCR_RST internal; source COLD_RST parts with COLD_RST reset source below parts with WARM_RST reset source below CFID embedded Flash-Memory Controller (FMC) embedded SRAM-Memory Controller external Static-Memory Controller (SMC) GeSS AHB-to-APB bridge PeSS AHB-to-APB bridge GPIO modules UART modules Timer modules PeSS modules IVNSS AHB-to-APB bridge modules including Acceptance filter modules MSCSS bridge modules modules Timer modules MSCSS modules Quadrature encoder GPDMA controller Vectored Interrupt Controller (VIC) infrastructure
Table POR_RST RGU_RST PCR_RST
Reset output
COLD_RST WARM_RST SCU_RST CFID_RST FMC_RST EMC_RST SMC_RST GESS_A2A_RST PESS_A2A_RST GPIO_RST UART_RST TMR_RST SPI_RST IVNSS_A2A_RST IVNSS_CAN_RST IVNSS_LIN_RST MSCSS_A2A_RST MSCSS_PWM_RST MSCSS_ADC_RST MSCSS_TMR_RST I2C_RST QEI_RST DMA_RST VIC_RST AHB_RST
6.15.4.2
description module LPC2917/2919/01 following pins. Table shows pins.
Table Symbol pins Direction Description external reset input, Active LOW; pulled internally
6.15.5 Power Management Unit (PMU)
This module enables software actively control system's power consumption disabling clocks required particular operating mode.
LPC2917_19_01_2
B.V. 2009. rights reserved.
Preliminary data sheet
Rev. June 2009
Semiconductors
LPC2917/01; LPC2919/01
ARM9 microcontroller with
Using base clocks from input, generates branch clocks rest LPC2917/2919/01. Output clocks branched from same base clock phase- frequency-related. These branch clocks individually controlled software programming. features are:
6.15.5.1
Individual clock control LPC2917/2919/01 sub-modules Activates sleeping clocks when wake-up event detected Clocks individually disabled software Supports master-disable protocol when AUTO mode Disables wake-up enabled clocks when Power-down mode Activates wake-up enabled clocks when wake-up event received Status register available indicate input base clock safely switched (i.e. branch clocks disabled)
Functional description controls internal clocks coming CGU0 power-mode management. With some exceptions, each branch clock switched individually under control software register bits located individual configuration register. Some branch clocks controlling vital parts device operate fixed mode. Table shows which mode- control bits supported each branch clock. programming configuration register user control which clocks switched off, which clocks switched when entering Power-down mode. Note that standby-wait-for-interrupt instructions ARM968E-S processor (putting into low-power state) supported. Instead putting into power-down should controlled disabling branch clock CPU. Remark: disabled branch clocks re-activated their corresponding base clocks must running (controlled CGU0). Table shows relation between branch base clocks, also Section 6.7.1. Every branch clock related particular base clock: possible switch source branch clock PMU.
Table Branch clock overview Legend: Indicates that related register tied logic HIGH, writes ignored Indicates that related register tied logic LOW, writes ignored Indicates that related register readable writable Branch clock name Base clock Implemented switch on/off mechanism WAKE-UP CLK_SAFE CLK_SYS_CPU CLK_SYS CLK_SYS_PCR CLK_SYS_FMC BASE_SAFE_CLK BASE_SYS_CLK BASE_SYS_CLK BASE_SYS_CLK BASE_SYS_CLK AUTO
B.V. 2009. rights reserved.
LPC2917_19_01_2
Preliminary data sheet
Rev. June 2009
Semiconductors
LPC2917/01; LPC2919/01
ARM9 microcontroller with
Table Branch clock overview .continued Legend: Indicates that related register tied logic HIGH, writes ignored Indicates that related register tied logic LOW, writes ignored Indicates that related register readable writable Branch clock name Base clock Implemented switch on/off mechanism WAKE-UP CLK_SYS_RAM0 CLK_SYS_RAM1 CLK_SYS_SMC CLK_SYS_GESS CLK_SYS_VIC CLK_SYS_PESS CLK_SYS_GPIO0 CLK_SYS_GPIO1 CLK_SYS_GPIO2 CLK_SYS_GPIO3 CLK_SYS_IVNSS_A CLK_SYS_MSCSS_A CLK_SYS_DMA CLK_PCR_SLOW CLK_IVNSS_APB CLK_IVNSS_CANC0 CLK_IVNSS_CANC1 CLK_IVNSS_I2C0 CLK_IVNSS_I2C1 CLK_IVNSS_LIN0 CLK_IVNSS_LIN1 CLK_MSCSS_APB CLK_MSCSS_MTMR0 CLK_MSCSS_MTMR1 CLK_MSCSS_PWM0 CLK_MSCSS_PWM1 CLK_MSCSS_PWM2 CLK_MSCSS_PWM3 BASE_SYS_CLK BASE_SYS_CLK BASE_SYS_CLK BASE_SYS_CLK BASE_SYS_CLK BASE_SYS_CLK BASE_SYS_CLK BASE_SYS_CLK BASE_SYS_CLK BASE_SYS_CLK BASE_SYS_CLK BASE_SYS_CLK BASE_SYS_CLK BASE_PCR_CLK BASE_IVNSS_CLK BASE_IVNSS_CLK BASE_IVNSS_CLK BASE_IVNSS_CLK BASE_IVNSS_CLK BASE_IVNSS_CLK BASE_IVNSS_CLK BASE_MSCSS_CLK BASE_MSCSS_CLK BASE_MSCSS_CLK BASE_MSCSS_CLK BASE_MSCSS_CLK BASE_MSCSS_CLK BASE_MSCSS_CLK AUTO
B.V. 2009. rights reserved.
CLK_MSCSS_ADC1_APB BASE_MSCSS_CLK CLK_MSCSS_ADC2_APB BASE_MSCSS_CLK CLK_MSCSS_QEI CLK_OUT_CLK CLK_UART0 CLK_UART1 CLK_SPI0 CLK_SPI1
LPC2917_19_01_2
BASE_MSCSS_CLK BASE_OUT_CLK BASE_UART_CLK BASE_UART_CLK BASE_SPI_CLK BASE_SPI_CLK
Preliminary data sheet
Rev. June 2009
Semiconductors
LPC2917/01; LPC2919/01
ARM9 microcontroller with
Table Branch clock overview .continued Legend: Indicates that related register tied logic HIGH, writes ignored Indicates that related register tied logic LOW, writes ignored Indicates that related register readable writable Branch clock name Base clock Implemented switch on/off mechanism WAKE-UP CLK_SPI2 CLK_TMR0 CLK_TMR1 CLK_TMR2 CLK_TMR3 CLK_ADC1 CLK_ADC2 BASE_SPI_CLK BASE_TMR_CLK BASE_TMR_CLK BASE_TMR_CLK BASE_TMR_CLK BASE_ADC_CLK BASE_ADC_CLK AUTO
6.16 Vectored Interrupt Controller (VIC)
LPC2917/2919/01 contains very flexible powerful Vectored Interrupt Controller interrupt processor request. features are:
Level-active interrupt request with programmable polarity. interrupt-request inputs. Software-interrupt request capability associated with each request input. Interrupt request state observed before masking. Software-programmable priority assignments interrupt requests levels. Software-programmable routing interrupt requests towards ARM-processor inputs FIQ.
Fast identification interrupt requests through vector. Support nesting interrupt service routines.
6.16.1 Functional description
Vectored Interrupt Controller routes incoming interrupt requests processor. interrupt target configured each interrupt request input VIC. targets defined follows:
Target processor (fast interrupt service). Target processor (standard interrupt service).
Interrupt-request masking performed individually interrupt target comparing priority level assigned specific interrupt request with target-specific priority threshold. priority levels defined follows:
Priority level corresponds `masked' (i.e. interrupt requests with priority never
lead interrupt).
Priority corresponds lowest priority.
LPC2917_19_01_2 B.V. 2009. rights reserved.
Preliminary data sheet
Rev. June 2009
Semiconductors
LPC2917/01; LPC2919/01
ARM9 microcontroller with
Priority corresponds highest priority.
Software interrupt support provided supplied for:
Testing RTOS (Real-Time Operating System) interrupt handling without using
device-specific interrupt service routines.
Software emulation interrupt-requesting device, including interrupts.
6.16.2 Clock description
clocked CLK_SYS_VIC, Section 6.7.2.
LPC2917_19_01_2
B.V. 2009. rights reserved.
Preliminary data sheet
Rev. June 2009
Semiconductors
LPC2917/01; LPC2919/01
ARM9 microcontroller with
Limiting values
Table Limiting values accordance with Absolute Maximum Rating System (IEC 60134). Symbol Supply pins Ptot VDD(CORE) VDD(OSC_PLL) VDDA(ADC3V3) VDD(IO) total power dissipation core supply voltage oscillator supply voltage analog supply voltage input/output supply voltage supply current ground current average value supply average value ground
Parameter
Conditions
-0.5 -0.5 -0.5 -0.5
+2.0 +2.0 +4.6 +4.6
Unit
Input pins pins VXIN_OSC VI(IO) VI(ADC) VVREFP VVREFN II(ADC) IOHS IOLS General Tstg Tamb storage temperature ambient temperature +150 voltage XIN_OSC input voltage input voltage voltage VREFP voltage VREFN input current HIGH-level short-circuit output current LOW-level short-circuit output current average value input drive HIGH, output shorted VSS(IO) drive LOW, output shorted VDD(IO)
[3][4][5]
-0.5 -0.5 -0.5 -0.5 -0.5 ADC1/2: port
[4][5]
+2.0 VDD(IO) VDDA(ADC3V3) +3.6 +3.6
Output pins pins configured output
LPC2917_19_01_2
B.V. 2009. rights reserved.
Preliminary data sheet
Rev. June 2009
Semiconductors
LPC2917/01; LPC2919/01
ARM9 microcontroller with
Table Limiting values .continued accordance with Absolute Maximum Rating System (IEC 60134). Symbol VESD electrostatic discharge voltage pins human body model charged device model corner pins charged device model
Based package heat transfer, device power consumption. Peak current must limited times average current. Port maximum input voltage defined VI(ADC). Only when VDD(IO) present. Note that pull-up should off. With pull-up exceed VDD(IO) VSS(IO) should exceeded. Human-body model: discharging capacitor series resistor.
Parameter
Conditions
Unit
-2000 -500 -750
+2000 +500 +750
LPC2917_19_01_2
B.V. 2009. rights reserved.
Preliminary data sheet
Rev. June 2009
Semiconductors
LPC2917/01; LPC2919/01
ARM9 microcontroller with
Static characteristics
Table Static characteristics VDD(CORE) VDD(OSC_PLL) VDD(IO) VDDA(ADC3V3) voltages measured with respect ground; positive currents flow into unless otherwise specified.[1] Symbol Supplies Core supply VDD(CORE) IDD(CORE) core supply voltage core supply current Device state after reset; system clock MHz; Tamb executing code while(1){} from flash. clocks supply VDD(IO) IDD(IO) VDD(OSC_PLL) IDD(OSC_PLL) input/output supply voltage supply current oscillator supply voltage oscillator supply current normal mode Power-down mode Power-down mode 1.71 normal mode Power-down mode port pins VDD(IO) applied; Section port pins when ADC1/2 used port pins VDD(IO) applied other pins, RST, TRST, TDI, JTAGSEL, TMS, HIGH-level input voltage port pins, RST, TRST, TDI, JTAGSEL, TMS, TCK; Figure port pins, RST, TRST, TDI, JTAGSEL, TMS, TCK; Figure
[3][4]
Parameter
Conditions
Unit
1.71
1.80
1.89
1.80
3.25 1.89
Oscillator supply
Analog-to-digital converter supply VDDA(ADC3V3) IDDA(ADC3V3) analog supply voltage analog supply current
-0.5
Input pins pins configured input input voltage
VVREFP -0.5 -0.5 +3.6 VDD(IO)
LOW-level input voltage
LPC2917_19_01_2
B.V. 2009. rights reserved.
Preliminary data sheet
Rev. June 2009
Semiconductors
LPC2917/01; LPC2919/01
ARM9 microcontroller with
Table Static characteristics .continued VDD(CORE) VDD(OSC_PLL) VDD(IO) VDDA(ADC3V3) voltages measured with respect ground; positive currents flow into unless otherwise specified.[1] Symbol Vhys ILIH ILIL II(pd) II(pu) Parameter hysteresis voltage HIGH-level input leakage current LOW-level input leakage current pull-down input current pull-up input current port pins, Figure port pins, RST, TRST, TDI, JTAGSEL, TMS: allowed; Figure
Conditions
-115
Unit
Oscillator VXIN_OSC Rs(xtal)
input capacitance output voltage HIGH-level output voltage LOW-level output voltage load capacitance voltage XIN_OSC crystal series resistance fosc Cxtal Cext Cxtal Cext fosc Cxtal Cext
VDD(IO)
VDD(IO)
Output pins pins configured output
Vtrip(high) Vtrip(low) Vtrip(dif)
input capacitance high trip level voltage trip level voltage difference between high trip level voltage
XIN_OSC
Power-up reset
parameters guaranteed over virtual junction temperature range design. Pre-testing performed Tamb wafer level. Cased products tested Tamb (final testing). Both pre-testing final testing correlated test conditions cover specified temperature power-supply voltage range. Leakage current exponential temperature; worst-case value Tvj. clocks off. Analog modules FLASH powered down. V-tolerant when pull-up Port maximum input voltage defined VI(ADC). Port maximum input capacitance ADC. Port maximum input capacitance ADC. Cxtal crystal load capacitance Cext external load capacitors.
B.V. 2009. rights reserved.
LPC2917_19_01_2
Preliminary data sheet
Rev. June 2009
Semiconductors
LPC2917/01; LPC2919/01
ARM9 microcontroller with
This parameter part production testing final testing, hence only typical value stated. Maximum minimum values based simulation results. power-up reset time filter: VDD(CORE) must above Vtrip(high) before reset de-asserted; VDD(CORE) must below Vtrip(low) before internal reset asserted.
Table static characteristics VDDA(ADC3V3) Tamb unless otherwise specified; frequency MHz. Symbol VVREFN VVREFP EL(adj) Rvsi Parameter voltage VREFN voltage VREFP input impedance analog input voltage analog input capacitance differential linearity error integral non-linearity offset error gain error absolute error voltage source interface resistance
Conditions: VSS(IO) VDDA(ADC3V3) monotonic, there missing codes. differential linearity error (ED) difference between actual step width ideal step width. Figure integral non-linearity (EL(adj)) peak difference between center steps actual ideal transfer curve after appropriate adjustment gain offset errors. Figure offset error (EO) absolute difference between straight line which fits actual curve straight line which fits ideal curve. Figure gain error (EG) relative difference percent between straight line fitting actual transfer curve after removing offset error, straight line which fits ideal transfer curve. Figure absolute error (ET) maximum difference between center steps actual transfer curve non-calibrated ideal transfer curve. Figure Figure
[1][2][3] [1][4] [1][5] [1][6] [1][7]
Conditions
VVREFP VDDA(ADC3V3) VVREFP
Unit
VVREFN between VVREFN VVREFP VVREFN
±0.5
LPC2XXX
IN[y]SAMPLE
IN[y]
Rvsi
VEXT
VSS(IO), VSS(CORE)
002aae280
Suggested interface LPC2917/2919/01 ADC1/2 IN[y]
LPC2917_19_01_2
B.V. 2009. rights reserved.
Preliminary data sheet
Rev. June 2009
Semiconductors
LPC2917/01; LPC2919/01
ARM9 microcontroller with
offset error 1023
gain error
1022
1021
1020
1019
1018
code
(ideal) 1018 1019 1020 1021 1022 1023 1024
offset error (LSBideal)
002aae703
Example actual transfer curve. ideal transfer curve. Differential linearity error (ED). Integral non-linearity (EL(adj)). Center step actual transfer curve.
characteristics
LPC2917_19_01_2
B.V. 2009. rights reserved.
Preliminary data sheet
Rev. June 2009
Semiconductors
LPC2917/01; LPC2919/01
ARM9 microcontroller with
Power consumption
IDD(CORE) (mA)
002aae241
core frequency (MHz)
Conditions: Tamb active mode entered executing code from flash; core voltage peripherals enabled configured run.
IDD(CORE) different core frequencies (active mode)
IDD(CORE) (mA)
002aae240
core voltage
Conditions: Tamb active mode entered executing code from flash; peripherals enabled configured run.
IDD(CORE) different core voltages VDD(CORE) (active mode)
LPC2917_19_01_2
B.V. 2009. rights reserved.
Preliminary data sheet
Rev. June 2009
Semiconductors
LPC2917/01; LPC2919/01
ARM9 microcontroller with
IDD(CORE) (mA)
002aae239
temperature (°C)
Conditions: active mode entered executing code from flash; core voltage peripherals enabled configured run.
IDD(CORE) different temperatures (active mode)
LPC2917_19_01_2
B.V. 2009. rights reserved.
Preliminary data sheet
Rev. June 2009
Semiconductors
LPC2917/01; LPC2919/01
ARM9 microcontroller with
Electrical characteristics
(mV)
002aae689
IOL(mA)
VDD(IO)
Typical LOW-level output voltage versus LOW-level output current
002aae690
(mA)
VDD(IO)
Typical HIGH-level output voltage versus HIGH-level output current
LPC2917_19_01_2
B.V. 2009. rights reserved.
Preliminary data sheet
Rev. June 2009
Semiconductors
LPC2917/01; LPC2919/01
ARM9 microcontroller with
II(pd) (µA)
002aae691
VDD(IO)
temperature (°C)
Typical pull-down current versus temperature
II(pu) (µA)
002aae692
VDD(IO)
-100
temperature (°C)
Typical pull-up current versus temperature
LPC2917_19_01_2
B.V. 2009. rights reserved.
Preliminary data sheet
Rev. June 2009
Semiconductors
LPC2917/01; LPC2919/01
ARM9 microcontroller with
Dynamic characteristics
Dynamic characteristics: pins, internal clock, oscillators, PLL,
Table Dynamic characteristics VDD(CORE) VDD(OSC_PLL); VDD(IO) VDDA(ADC3V3) voltages measured with respect ground; positive currents flow into unless otherwise specified.[1] Symbol pins tTHL tTLH CLKOUT fclk Internal clock fclk(sys) Tclk(sys) fref(RO) tstartup Oscillator fi(osc) oscillator input frequency maximum frequency clock input external clock source applied XIN_OSC maximum frequency
Parameter
Conditions
13.8 13.8
Unit
HIGH transition time HIGH transition time clock frequency system clock frequency system clock period reference frequency start-up time maximum frequency
CLKOUT
0.36
0.42
Low-power ring oscillator
tstartup fi(PLL) fo(PLL) ta(clk) ta(A)
start-up time
input frequency output frequency CCO; direct mode clock access time address access time
63.4 60.3
LPC2917_19_01_2
B.V. 2009. rights reserved.
Preliminary data sheet
Rev. June 2009
Semiconductors
LPC2917/01; LPC2919/01
ARM9 microcontroller with
Table Dynamic characteristics .continued VDD(CORE) VDD(OSC_PLL); VDD(IO) VDDA(ADC3V3) voltages measured with respect ground; positive currents flow into unless otherwise specified.[1] Symbol tjit(cc)(p-p) Parameter cycle cycle jitter (peak-to-peak value) Conditions TXDC
Unit
Jitter specification
parameters guaranteed over virtual junction temperature range design. Pre-testing performed Tamb ambient temperature wafer level. Cased products tested Tamb (final testing). Both pre-testing final testing correlated test conditions cover specified temperature power supply voltage range. Table This parameter part production testing final testing, hence only typical value stated. Oscillator start-up time depends quality crystal. most crystals takes about 1000 clock pulses until clock fully stable.
fref(RO) (kHz)
002aae373
temperature (°C)
Low-power ring oscillator thermal characteristics
LPC2917_19_01_2
B.V. 2009. rights reserved.
Preliminary data sheet
Rev. June 2009
Semiconductors
LPC2917/01; LPC2919/01
ARM9 microcontroller with
Dynamic characteristics: I2C-bus interface
Table Dynamic characteristic: I2C-bus pins VDD(CORE) VDD(OSC_PLL); VDD(IO) VDDA(ADC3V3) voltages measured with respect ground; positive currents flow into unless otherwise specified[1] Symbol tf(o)
Parameter output fall time
Conditions
Cb[3]
Typ[2]
Unit
parameters guaranteed over virtual junction temperature range design. Pre-testing performed Tamb ambient temperature wafer level. Cased products tested Tamb (final testing). Both pre-testing final testing correlated test conditions cover specified temperature power supply voltage range. Typical ratings guaranteed. values listed room temperature °C), nominal supply voltages. capacitance from
Dynamic characteristics:
Table Dynamic characteristics pins VDD(CORE) VDD(OSC_PLL) VDD(IO) VDDA(ADC3V3) VDDA(ADC5V0) voltages measured with respect ground; positive currents flow into unless otherwise specified.[1] Symbol fSPI tsu(SPI_MISO) Parameter operating frequency SPI_MISO set-up time Conditions master operation slave operation Tamb measured Master mode; Figure
65024fclk(SPI) 65024fclk(SPI)
2fclk(SPI) 4fclk(SPI)
Unit
parameters guaranteed over virtual junction temperature range design. Pre-testing performed Tamb ambient temperature wafer level. Cased products tested Tamb (final testing). Both pre-testing final testing correlated test conditions cover specified temperature power supply voltage range.
shifting edges
SCKn
sampling edges
SDOn
SDIn
tsu(SPI_MISO)
002aae695
data input set-up time Master mode
LPC2917_19_01_2
B.V. 2009. rights reserved.
Preliminary data sheet
Rev. June 2009
Semiconductors
LPC2917/01; LPC2919/01
ARM9 microcontroller with
Dynamic characteristics: flash memory EEPROM
Table Flash characteristics Tamb VDD(CORE) VDD(OSC_PLL); VDD(IO) VDDA(ADC3V3) voltages measured with respect ground. Symbol Nendu tret tprog tinit twr(pg) tfl(BIST) ta(clk) ta(A)
Parameter endurance retention time programming time erase time initialization time page write time flash word BIST time clock access time address access time
Conditions
10000 0.95 0.95
1.05 1.05 63.4 60.3
Unit cycles years years
powered unpowered word global sector
Number program/erase cycles.
Table EEPROM characteristics Tamb VDD(CORE) VDD(OSC_PLL); VDD(IO) VDDA(ADC3V3) voltages measured with respect ground. Symbol fclk Nendu tret Parameter clock frequency endurance retention time powered Conditions 100000 500000 Unit cycles years
LPC2917_19_01_2
B.V. 2009. rights reserved.
Preliminary data sheet
Rev. June 2009
Semiconductors
LPC2917/01; LPC2919/01
ARM9 microcontroller with
Dynamic charact

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