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16/32-bit microcontroller with CAN, 10-bit external memory interface


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LPC2290
16/32-bit microcontroller with CAN, 10-bit external memory interface
Rev. November 2006 Product data sheet
LPC2290 microcontroller based 16/32-bit ARM7TDMI-S with real-time emulation embedded trace support. critical code size applications, alternative 16-bit Thumb mode reduces code more than with minimal performance penalty. With 144-pin package, power consumption, various 32-bit timers, 8-channel 10-bit ADC, advanced channels, channels nine external interrupt pins this microcontroller particularly suitable automotive industrial control applications well medical systems fault-tolerant maintenance buses. LPC2290 provides GPIOs depending configuration. With wide range additional serial communications interfaces, also suited communication gateways protocol converters well many other general-purpose applications. Remark: Throughout data sheet, term `LPC2290' will apply devices with without suffix. devices will suffix differentiate from original devices only when necessary.
Features
Enhancements introduced with LPC2290/01 device
clock on-chip static RAM. Fast GPIO ports enable port toggling times faster than original LPC2290. port read time regardless function. Dedicated result registers reduce interrupt overhead. UART0/1 include fractional baud rate generator, auto-bauding capabilities handshake flow-control fully implemented hardware. serial controller supporting SPI, 4-wire SSI, Microwire buses.
features common LPC2290 LPC2290/01
16/32-bit ARM7TDMI-S microcontroller LQFP144 package. 16/64 on-chip static RAM. Serial bootloader using UART0 provides in-system download programming capabilities. EmbeddedICE-RT Embedded Trace interfaces offer real-time debugging with on-chip RealMonitor software well high-speed real-time tracing instruction execution. interconnected interfaces with advanced acceptance filters. Additional serial interfaces include UARTs (16C550), Fast I2C-bus (400 kbit/s) SPIs.
Semiconductors
LPC2290
16/32-bit microcontroller with external memory interface
Eight channel 10-bit with conversion time 2.44 32-bit timers (with four capture four compare channels), unit (six outputs), Real-Time Clock (RTC) watchdog. Vectored Interrupt Controller (VIC) with configurable priorities vector addresses. Configurable external memory interface with four banks, each 8/16/32-bit data width. general purpose pins tolerant). nine edge/level sensitive external interrupt pins available. 60/72 maximum clock available from programmable on-chip with settling time On-chip crystal oscillator with operating range MHz. Power saving modes include Idle Power-down. Processor wake-up from Power-down mode external interrupt. Individual enable/disable peripheral functions power optimization. Dual power supply: operating voltage range 1.65 1.95 (1.8 0.15 power supply range (3.3 with tolerant pads.
Ordering information
Table Ordering information Package Name LPC2290FBD144 LPC2290FBD144/01 LQFP144 LQFP144 Description plastic profile quad flat package; leads; body plastic profile quad flat package; leads; body Version SOT486-1 SOT486-1 Type number
Ordering options
Table Ordering options Enhancements Temperature range channels None channels Higher clock, more on-chip SRAM, Fast I/Os, improved UARTs, added SSP, upgraded Type number LPC2290FBD144
LPC2290FBD144/01
LPC2290_3
B.V. 2006. rights reserved.
Product data sheet
Rev. November 2006
Semiconductors
LPC2290
16/32-bit microcontroller with external memory interface
Block diagram
TMS(1) TDI(1) TRST(1) TCK(1) TDO(1) XTAL2 XTAL1
LPC2290 LPC2290/01
P0[31:0] P1[31:16], P1[1:0]
TEST/DEBUG INTERFACE
EMULATION TRACE MODULE
system clock
SYSTEM FUNCTIONS VECTORED INTERRUPT CONTROLLER
ARM7TDMI-S
FAST GENERAL PURPOSE I/O(3) ARM7 local BRIDGE
AMBA Advanced High-performance Bus(AHB)
INTERNAL SRAM CONTROLLER
DECODER BRIDGE DIVIDER CS0(2) A0(2) BLS3 BLS0(2) WE(2) D0(2) SCK0, SCK1
16/64 SRAM
EXTERNAL MEMORY CONTROLLER
Advanced Peripheral (APB) EINT3 EINT0 EXTERNAL INTERRUPTS I2C-BUS SERIAL INTERFACE
CAP0 CAP1 MAT0 MAT1
CAPTURE/ COMPARE TIMER 0/TIMER
SSP(3) SERIAL INTERFACES
MOSI0, MOSI1 MISO0, MISO1 SSEL0, SSEL1 TXD0, TXD1
AIN3 AIN0 CONVERTER AIN7 AIN4 P0[30:0] P1[31:16], P1[1:0] P2[31:0] P3[31:0] PWM6 PWM1 PWM0 WATCHDOG TIMER SYSTEM CONTROL GENERAL PURPOSE UART0/UART1
RXD0, RXD1 DSR1, CTS1, DCD1, TD2, RD2,
REAL-TIME CLOCK
002aaa796
When test/debug interface used, GPIO/other functions sharing these pins available. Pins shared with GPIO. Available LPC2290/01 only.
Block diagram
LPC2290_3
B.V. 2006. rights reserved.
Product data sheet
Rev. November 2006
Semiconductors
LPC2290
16/32-bit microcontroller with external memory interface
Pinning information
Pinning
LPC2290
002aaa797
LQFP144 pinning
LPC2290_3
B.V. 2006. rights reserved.
Product data sheet
Rev. November 2006
Semiconductors
LPC2290
16/32-bit microcontroller with external memory interface
description
Table Symbol P0.0 P0.31 description Type Description Port Port 32-bit bidirectional port with individual direction controls each bit. operation port pins depends upon function selected Connect Block. Pins port available. P0.0/TXD0/ PWM1 42[1] P0.1/RXD0/ PWM3/EINT0 49[2] P0.2/SCL/ CAP0.0 50[3] P0.3/SDA/ MAT0.0/EINT1 58[3] P0.4/SCK0/ CAP0.1 59[1] P0.5/MISO0/ MAT0.1 61[1] P0.6/MOSI0/ CAP0.2 68[1] P0.7/SSEL0/ PWM2/EINT2 69[2] P0.8/TXD1/ PWM4 75[1] P0.0 General purpose digital input/output pin. TXD0 Transmitter output UART0. PWM1 Pulse Width Modulator output P0.1 General purpose digital input/output pin. RXD0 Receiver input UART0. PWM3 Pulse Width Modulator output EINT0 External interrupt input P0.2 General purpose digital input/output pin. I2C-bus clock input/output. Open-drain output (for I2C-bus compliance). CAP0.0 Capture input Timer channel P0.3 General purpose digital input/output pin. I2C-bus data input/output. Open-drain output (for I2C-bus compliance). MAT0.0 Match output Timer channel EINT1 External interrupt input. P0.4 General purpose digital input/output pin. SCK0 Serial clock SPI0. clock output from master input slave. CAP0.1 Capture input Timer channel P0.5 General purpose digital input/output pin. MISO0 Master Slave SPI0. Data input master data output from slave. MAT0.1 Match output Timer channel P0.6 General purpose digital input/output pin. MOSI0 Master Slave SPI0. Data output from master data input slave. CAP0.2 Capture input Timer channel P0.7 General purpose digital input/output pin. SSEL0 Slave Select SPI0. Selects interface slave. PWM2 Pulse Width Modulator output EINT2 External interrupt input. P0.8 General purpose digital input/output pin. TXD1 Transmitter output UART1. PWM4 Pulse Width Modulator output
LPC2290_3
B.V. 2006. rights reserved.
Product data sheet
Rev. November 2006
Semiconductors
LPC2290
16/32-bit microcontroller with external memory interface
Table Symbol
description .continued 76[2] Type Description P0.9 General purpose digital input/output pin. RXD1 Receiver input UART1. PWM6 Pulse Width Modulator output EINT3 External interrupt input. P0.10 General purpose digital input/output pin. RTS1 Request Send output UART1. CAP1.0 Capture input Timer channel P0.11 General purpose digital input/output pin. CTS1 Clear Send input UART1. CAP1.1 Capture input Timer channel P0.12 General purpose digital input/output pin. DSR1 Data Ready input UART1. MAT1.0 Match output Timer channel P0.13 General purpose digital input/output pin. DTR1 Data Terminal Ready output UART1. MAT1.1 Match output Timer channel P0.14 General purpose digital input/output pin. DCD1 Data Carrier Detect input UART1. EINT1 External interrupt input. Note: this while RESET forces on-chip bootloader take over control part after reset.
P0.9/RXD1/ PWM6/EINT3
P0.10/RTS1/ CAP1.0
78[1]
P0.11/CTS1/ CAP1.1
83[1]
P0.12/DSR1/ MAT1.0
84[1]
P0.13/DTR1/ MAT1.1
85[1]
P0.14/DCD1/ EINT1
92[2]
P0.15/RI1/ EINT2
99[2]
P0.15 General purpose digital input/output pin. Ring Indicator input UART1. EINT2 External interrupt input. P0.16 General purpose digital input/output pin. EINT0 External interrupt input. MAT0.2 Match output Timer channel CAP0.2 Capture input Timer channel P0.17 General purpose digital input/output pin. CAP1.2 Capture input Timer channel SCK1 Serial Clock SPI1/SSP. clock output from master input slave (SSP available LPC2290/01 only). MAT1.2 Match output Timer channel P0.18 General purpose digital input/output pin. CAP1.3 Capture input Timer channel MISO1 Master Slave SPI1/SSP. Data input master data output from slave (SSP available LPC2290/01 only). MAT1.3 Match output Timer channel
P0.16/EINT0/ 100[2] MAT0.2/CAP0.2
P0.17/CAP1.2/ SCK1/MAT1.2
101[1]
P0.18/CAP1.3/ MISO1/MAT1.3
121[1]
LPC2290_3
B.V. 2006. rights reserved.
Product data sheet
Rev. November 2006
Semiconductors
LPC2290
16/32-bit microcontroller with external memory interface
Table Symbol
description .continued 122[1] Type Description P0.19 General purpose digital input/output pin. MAT1.2 Match output Timer channel MOSI1 Master Slave SPI1/SSP. Data output from master data input slave (SSP available LPC2290/01 only). CAP1.2 Capture input Timer channel P0.20 General purpose digital input/output pin. MAT1.3 Match output Timer channel SSEL1 Slave Select SPI1/SSP. Selects interface slave (SSP available LPC2290/01 only). EINT3 External interrupt input. P0.21 General purpose digital input/output pin. PWM5 Pulse Width Modulator output CAP1.3 Capture input Timer channel P0.22 General purpose digital input/output pin. CAP0.0 Capture input Timer channel MAT0.0 Match output Timer channel P0.23 General purpose digital input/output pin. CAN2 receiver input. P0.24 General purpose digital input/output pin. CAN2 transmitter output. P0.25 General purpose digital input/output pin. CAN1 receiver input. P0.27 General purpose digital input/output pin. AIN0 ADC, input This analog input always connected pin. CAP0.1 Capture input Timer channel MAT0.1 Match output Timer channel P0.28 General purpose digital input/output pin. AIN1 ADC, input This analog input always connected pin. CAP0.2 Capture input Timer channel MAT0.2 Match output Timer channel P0.29 General purpose digital input/output pin. AIN2 ADC, input This analog input always connected pin. CAP0.3 Capture input Timer Channel MAT0.3 Match output Timer channel P0.30 General purpose digital input/output pin. AIN3 ADC, input This analog input always connected pin. EINT3 External interrupt input. CAP0.0 Capture input Timer channel Port Port 32-bit bidirectional port with individual direction controls each bit. operation port pins depends upon function selected Connect Block. Pins through port available.
P0.19/MAT1.2/ MOSI1/CAP1.2
P0.20/MAT1.3/ SSEL1/EINT3
123[2]
P0.21/PWM5/ CAP1.3
4[1]
P0.22/CAP0.0/ MAT0.0
5[1]
P0.23/RD2 P0.24/TD2 P0.25 P0.27/AIN0/ CAP0.1/MAT0.1
6[1] 8[1] 21[1] 23[4]
P0.28/AIN1/ CAP0.2/MAT0.2
25[4]
P0.29/AIN2/ CAP0.3/MAT0.3
32[4]
P0.30/AIN3/ EINT3/CAP0.0
33[4]
P1.0 P1.31
LPC2290_3
B.V. 2006. rights reserved.
Product data sheet
Rev. November 2006
Semiconductors
LPC2290
16/32-bit microcontroller with external memory interface
Table Symbol P1.0/CS0
description .continued 91[5] Type Description P1.0 General purpose digital input/output pin. LOW-active Chip Select signal. (Bank addresses range 0x8000 0000 0x80FF FFFF) P1.1 General purpose digital input/output pin. LOW-active Output Enable signal. P1.16 General purpose digital input/output pin. TRACEPKT0 Trace Packet, Standard port with internal pull-up. P1.17 General purpose digital input/output pin. TRACEPKT1 Trace Packet, Standard port with internal pull-up. P1.18 General purpose digital input/output pin. TRACEPKT2 Trace Packet, Standard port with internal pull-up. P1.19 General purpose digital input/output pin. TRACEPKT3 Trace Packet, Standard port with internal pull-up. P1.20 General purpose digital input/output pin. TRACESYNC Trace Synchronization. Standard port with internal pull-up. Note: this while RESET LOW, enables pins P1[25:16] operate Trace port after reset.
P1.1/OE P1.16/ TRACEPKT0 P1.17/ TRACEPKT1 P1.18/ TRACEPKT2 P1.19/ TRACEPKT3 P1.20/ TRACESYNC
90[5] 34[5] 24[5] 15[5] 7[5] 102[5]
P1.21/ PIPESTAT0 P1.22/ PIPESTAT1 P1.23/ PIPESTAT2 P1.24/ TRACECLK P1.25/EXTIN0 P1.26/RTCK
95[5] 86[5] 82[5] 70[5] 60[5] 52[5]
P1.21 General purpose digital input/output pin. PIPESTAT0 Pipeline Status, Standard port with internal pull-up. P1.22 General purpose digital input/output pin. PIPESTAT1 Pipeline Status, Standard port with internal pull-up. P1.23 General purpose digital input/output pin. PIPESTAT2 Pipeline Status, Standard port with internal pull-up. P1.24 General purpose digital input/output pin. TRACECLK Trace Clock. Standard port with internal pull-up. P1.25 General purpose digital input/output pin. EXTIN0 External Trigger Input. Standard with internal pull-up. P1.26 General purpose digital input/output pin. RTCK Returned Test Clock output. Extra signal added JTAG port. Assists debugger synchronization when processor frequency varies. Bidirectional with internal pull-up. Note: this while RESET LOW, enables pins P1[31:26] operate Debug port after reset.
P1.27/TDO P1.28/TDI P1.29/TCK P1.30/TMS
144[5] 140[5] 126[5] 113[5]
P1.27 General purpose digital input/output pin. Test Data JTAG interface. P1.28 General purpose digital input/output pin. Test Data JTAG interface. P1.29 General purpose digital input/output pin. Test Clock JTAG interface. P1.30 General purpose digital input/output pin. Test Mode Select JTAG interface.
B.V. 2006. rights reserved.
LPC2290_3
Product data sheet
Rev. November 2006
Semiconductors
LPC2290
16/32-bit microcontroller with external memory interface
Table Symbol
description .continued 43[5] Type Description P1.31 General purpose digital input/output pin. TRST Test Reset JTAG interface. Port Port 32-bit bidirectional port with individual direction controls each bit. operation port pins depends upon function selected Connect Block. P2.0 General purpose digital input/output pin. External memory data line P2.1 General purpose digital input/output pin. External memory data line P2.2 General purpose digital input/output pin. External memory data line P2.3 General purpose digital input/output pin. External memory data line P2.4 General purpose digital input/output pin. External memory data line P2.5 General purpose digital input/output pin. External memory data line P2.6 General purpose digital input/output pin. External memory data line P2.7 General purpose digital input/output pin. External memory data line P2.8 General purpose digital input/output pin. External memory data line P2.9 General purpose digital input/output pin. External memory data line P2.10 General purpose digital input/output pin. External memory data line P2.11 General purpose digital input/output pin. External memory data line P2.12 General purpose digital input/output pin. External memory data line P2.13 General purpose digital input/output pin. External memory data line P2.14 General purpose digital input/output pin. External memory data line P2.15 General purpose digital input/output pin. External memory data line P2.16 General purpose digital input/output pin. External memory data line P2.17 General purpose digital input/output pin. External memory data line
B.V. 2006. rights reserved.
P1.31/TRST P2.0 P2.31
P2.0/D0 P2.1/D1 P2.2/D2 P2.3/D3 P2.4/D4 P2.5/D5 P2.6/D6 P2.7/D7 P2.8/D8 P2.9/D9 P2.10/D10 P2.11/D11 P2.12/D12 P2.13/D13 P2.14/D14 P2.15/D15 P2.16/D16 P2.17/D17
98[5] 105[5] 106[5] 108[5] 109[5] 114[5] 115[5] 116[5] 117[5] 118[5] 120[5] 124[5] 125[5] 127[5] 129[5] 130[5] 131[5] 132[5]
LPC2290_3
Product data sheet
Rev. November 2006
Semiconductors
LPC2290
16/32-bit microcontroller with external memory interface
Table Symbol P2.18/D18 P2.19/D19 P2.20/D20 P2.21/D21 P2.22/D22 P2.23/D23 P2.24/D24 P2.25/D25 P2.26/D26/ BOOT0
description .continued 133[5] 134[5] 136[5] 137[5] 1[5] 10[5] 11[5] 12[5] 13[5] Type Description P2.18 General purpose digital input/output pin. External memory data line P2.19 General purpose digital input/output pin. External memory data line P2.20 General purpose digital input/output pin. External memory data line P2.21 General purpose digital input/output pin. External memory data line P2.22 General purpose digital input/output pin. External memory data line P2.23 General purpose digital input/output pin. External memory data line P2.24 General purpose digital input/output pin. External memory data line P2.25 General purpose digital input/output pin. External memory data line P2.26 General purpose digital input/output pin. External memory data line BOOT0 While RESET low, together with BOOT1 controls booting internal operation. Internal pull-up ensures high state left unconnected. P2.27 General purpose digital input/output pin. External memory data line BOOT1 While RESET low, together with BOOT0 controls booting internal operation. Internal pull-up ensures high state left unconnected. BOOT1:0 selects 8-bit memory boot. BOOT1:0 selects 16-bit memory boot. BOOT1:0 selects 32-bit memory boot. BOOT1:0 selects internal flash memory.
P2.27/D27/ BOOT1
16[5]
P2.28/D28 P2.29/D29 P2.30/D30/ AIN4
17[5] 18[5] 19[2]
P2.28 General purpose digital input/output pin. External memory data line P2.29 General purpose digital input/output pin. External memory data line P2.30 General purpose digital input/output pin. External memory data line AIN4 ADC, input This analog input always connected pin. P2.31 General purpose digital input/output pin. External memory data line AIN5 ADC, input This analog input always connected pin. Port Port 32-bit bidirectional port with individual direction controls each bit. operation port pins depends upon function selected Connect Block.
B.V. 2006. rights reserved.
P2.31/D31/ AIN5
20[2]
P3.0 P3.31
LPC2290_3
Product data sheet
Rev. November 2006
Semiconductors
LPC2290
16/32-bit microcontroller with external memory interface
Table Symbol P3.0/A0 P3.1/A1 P3.2/A2 P3.3/A3 P3.4/A4 P3.5/A5 P3.6/A6 P3.7/A7 P3.8/A8 P3.9/A9 P3.10/A10 P3.11/A11 P3.12/A12 P3.13/A13 P3.14/A14 P3.15/A15 P3.16/A16 P3.17/A17 P3.18/A18 P3.19/A19
description .continued 89[5] 88[5] 87[5] 81[5] 80[5] 74[5] 73[5] 72[5] 71[5] 66[5] 65[5] 64[5] 63[5] 62[5] 56[5] 55[5] 53[5] 48[5] 47[5] 46[5] Type Description P3.0 General purpose digital input/output pin. External memory address line P3.1 General purpose digital input/output pin. External memory address line P3.2 General purpose digital input/output pin. External memory address line P3.3 General purpose digital input/output pin. External memory address line P3.4 General purpose digital input/output pin. External memory address line P3.5 General purpose digital input/output pin. External memory address line P3.6 General purpose digital input/output pin. External memory address line P3.7 General purpose digital input/output pin. External memory address line P3.8 General purpose digital input/output pin. External memory address line P3.9 General purpose digital input/output pin. External memory address line P3.10 General purpose digital input/output pin. External memory address line P3.11 General purpose digital input/output pin. External memory address line P3.12 General purpose digital input/output pin. External memory address line P3.13 General purpose digital input/output pin. External memory address line P3.14 General purpose digital input/output pin. External memory address line P3.15 General purpose digital input/output pin. External memory address line P3.16 General purpose digital input/output pin. External memory address line P3.17 General purpose digital input/output pin. External memory address line P3.18 General purpose digital input/output pin. External memory address line P3.19 General purpose digital input/output pin. External memory address line
LPC2290_3
B.V. 2006. rights reserved.
Product data sheet
Rev. November 2006
Semiconductors
LPC2290
16/32-bit microcontroller with external memory interface
Table Symbol P3.20/A20 P3.21/A21 P3.22/A22 P3.23/A23/ XCLK
description .continued 45[5] 44[5] 41[5] 40[5] Type 36[5] Description P3.20 General purpose digital input/output pin. External memory address line P3.21 General purpose digital input/output pin. External memory address line P3.22 General purpose digital input/output pin. External memory address line P3.23 General purpose digital input/output pin. External memory address line XCLK Clock output. P3.24 General purpose digital input/output pin. LOW-active Chip Select signal. (Bank addresses range 0x8300 0000 0x83FF FFFF) P3.25 General purpose digital input/output pin. LOW-active Chip Select signal. (Bank addresses range 0x8200 0000 0x82FF FFFF) P3.26 General purpose digital input/output pin. LOW-active Chip Select signal. (Bank addresses range 0x8100 0000 0x81FF FFFF) P3.27 General purpose digital input/output pin. LOW-active Write enable signal. P3.28 General purpose digital input/output pin. BLS3 LOW-active Byte Lane Select signal (Bank AIN7 ADC, input This analog input always connected pin. P3.29 General purpose digital input/output pin. BLS2 LOW-active Byte Lane Select signal (Bank AIN6 ADC, input This analog input always connected pin. P3.30 General purpose digital input/output pin. BLS1 LOW-active Byte Lane Select signal (Bank P3.31 General purpose digital input/output pin. BLS0 LOW-active Byte Lane Select signal (Bank TD1: CAN1 transmitter output. External Reset input: this resets device, causing ports peripherals take their default states, processor execution begin address with hysteresis, tolerant. Input oscillator circuit internal clock generator circuits. Output from oscillator amplifier. Ground: reference.
P3.24/CS3
P3.25/CS2
35[5]
P3.26/CS1
30[5]
P3.27/WE P3.28/BLS3/ AIN7
29[5] 28[2]
P3.29/BLS2/ AIN6
27[4]
P3.30/BLS1 P3.31/BLS0 RESET
97[4] 96[4] 22[5] 135[6]
XTAL1 XTAL2
142[7] 141[7]
103, 107, 111,
VSSA
Analog ground: reference. This should nominally same voltage VSS, should isolated minimize noise error.
LPC2290_3
B.V. 2006. rights reserved.
Product data sheet
Rev. November 2006
Semiconductors
LPC2290
16/32-bit microcontroller with external memory interface
Table Symbol VSSA(PLL) VDD(1V8) VDDA(1V8)
description .continued Type Description analog ground: reference. This should nominally same voltage VSS, should isolated minimize noise error. core power supply: This power supply voltage internal circuitry. Analog core power supply: This power supply voltage internal circuitry. This should nominally same voltage VDD(1V8) should isolated minimize noise error. power supply: This power supply voltage ports.
VDD(3V3)
104, 112,
VDDA(3V3)
Analog power supply: This should nominally same voltage VDD(3V3) should isolated minimize noise error.
tolerant providing digital functions with levels hysteresis slew rate control. tolerant providing digital functions with levels hysteresis slew rate control. configured input function, this utilizes built-in glitch filter that blocks pulses shorter than Open-drain tolerant digital I2C-bus specification compatible pad. requires external pull-up provide output functionality. tolerant providing digital (with levels hysteresis slew rate control) analog input function. configured digital input function, this utilizes built-in glitch filter that blocks pulses shorter than When configured input, digital section disabled. tolerant with built-in pull-up resistor providing digital functions with levels hysteresis slew rate control. pull-up resistor's value ranges from tolerant providing digital input (with levels hysteresis) function only. provides special analog functionality.
LPC2290_3
B.V. 2006. rights reserved.
Product data sheet
Rev. November 2006
Semiconductors
LPC2290
16/32-bit microcontroller with external memory interface
Functional description
Architectural overview
ARM7TDMI-S general purpose 32-bit microprocessor, which offers high performance very power consumption. architecture based RISC principles, instruction related decode mechanism much simpler than those microprogrammed CISC. This simplicity results high instruction throughput impressive real-time interrupt response from small cost-effective processor core. Pipeline techniques employed that parts processing memory systems operate continuously. Typically, while instruction being executed, successor being decoded, third instruction being fetched from memory. ARM7TDMI-S processor also employs unique architectural strategy known Thumb, which makes ideally suited high-volume applications with memory restrictions, applications where code density issue. idea behind Thumb that super-reduced instruction set. Essentially, ARM7TDMI-S processor instruction sets:
standard 32-bit set. 16-bit Thumb set.
Thumb set's 16-bit instruction length allows approach twice density standard code while retaining most ARM's performance advantage over traditional 16-bit processor using 16-bit registers. This possible because Thumb code operates same 32-bit register code. Thumb code able provide code size ARM, performance equivalent processor connected 16-bit memory system.
On-chip SRAM
On-chip SRAM used code and/or data storage. SRAM accessed 8-bit, 16-bit, 32-bit. LPC2290 provides SRAM LPC2290/01 provides SRAM.
Memory
LPC2290 memory maps incorporate several distinct regions, shown Figure addition, interrupt vectors re-mapped allow them reside either on-chip bootloader, external memory BANK0 on-chip static RAM. This described Section 6.18 "System control".
LPC2290_3
B.V. 2006. rights reserved.
Product data sheet
Rev. November 2006
Semiconductors
LPC2290
16/32-bit microcontroller with external memory interface
PERIPHERALS 3.75 PERIPHERALS
0xFFFF FFFF 0xF000 0000 0xEFFF FFFF 0xE000 0000 0xDFFF FFFF RESERVED ADDRESS SPACE
EXTERNAL MEMORY BANK3 EXTERNAL MEMORY BANK2 EXTERNAL MEMORY BANK1 EXTERNAL MEMORY BANK0 BOOT BLOCK (RE-MAPPED FROM ON-CHIP MEMORY RESERVED ADDRESS SPACE KBYTE ON-CHIP STATIC (/01 ONLY)
0x8400 0000 0x83FF FFFF 0x8300 0000 0x82FF FFFF 0x8200 0000 0x81FF FFFF 0x8100 0000 0x80FF FFFF 0x8000 0000 0x7FFF FFFF 0x7FFF E000 0x7FFF DFFF 0x4001 0000 0x4000 FFFF 0x4000 4000 0x4000 3FFF KBYTE ON-CHIP STATIC
0x4000 0000 0x3FFF FFFF
RESERVED ADDRESS SPACE
0x0000 0000
002aaa798
LPC2290 LPC2290/01 memory
Interrupt controller
Vectored Interrupt Controller (VIC) accepts interrupt request inputs categorizes them Fast Interrupt Request (FIQ), vectored Interrupt Request (IRQ), non-vectored defined programmable settings. programmable assignment scheme means that priorities interrupts from various peripherals dynamically assigned adjusted. highest priority. more than request assigned FIQ, combines requests produce signal processor. fastest possible latency achieved when only request classified FIQ, because then service routine simply start dealing with that device. more than request assigned class, service routine read word from that identifies which source(s) (are) requesting interrupt.
LPC2290_3
B.V. 2006. rights reserved.
Product data sheet
Rev. November 2006
Semiconductors
LPC2290
16/32-bit microcontroller with external memory interface
Vectored IRQs have middle priority. Sixteen interrupt requests assigned this category. interrupt requests assigned vectored slots, among which slot highest priority slot lowest. Non-vectored IRQs have lowest priority. combines requests from vectored non-vectored IRQs produce signal processor. service routine start reading register from jumping there. vectored IRQs requesting, provides address highest-priority requesting IRQs service routine, otherwise provides address default routine that shared non-vectored IRQs. default routine read another register what IRQs active.
6.4.1 Interrupt sources
Table lists interrupt sources each peripheral function. Each peripheral device interrupt line connected VIC, have several internal interrupt flags. Individual interrupt flags also represent more than interrupt source.
Table Block Core Core Timer Timer UART0 Interrupt sources Flag(s) Watchdog Interrupt (WDINT) Reserved software interrupts only EmbeddedICE, DbgCommRx EmbeddedICE, DbgCommTx Match (MR0, MR1, MR2, MR3) Capture (CR0, CR1, CR2, CR3) Match (MR0, MR1, MR2, MR3) Capture (CR0, CR1, CR2, CR3) Line Status (RLS) Transmit Holding Register Empty (THRE) Data Available (RDA) Character Time-out Indicator (CTI) Auto-Baud Time-Out (ABTO) (available LPC2290/01 only) Auto-Baud (ABEO) UART1 Line Status (RLS) Transmit Holding Register empty (THRE) Data Available (RDA) Character Time-out Indicator (CTI) Modem Status Interrupt (MSI) Auto-Baud Time-Out (ABTO) (available LPC2290/01 only) Auto-Baud (ABEO) PWM0 I2C-bus SPI0 Match (MR0, MR1, MR2, MR3, MR4, MR5, MR6) (state change) SPIF, MODF channel
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Semiconductors
LPC2290
16/32-bit microcontroller with external memory interface
Interrupt sources .continued Flag(s) Source: SPI1 Interrupt Flag (SPIF), Mode Fault (MODF) Source: (available LPC2290/01 only) FIFO least half empty (TXRIS) FIFO least half full (RXRIS) Receive Timeout condition (RTRIS) Receive Overrun (RORRIS) channel
Table Block SPI1/SSP
System Control
Lock (PLOCK) RTCCIF (Counter Increment), RTCALF (Alarm) External Interrupt (EINT0) External Interrupt (EINT1) External Interrupt (EINT2) External Interrupt (EINT3)
ORed Acceptance Filter CAN1 int, int) CAN2 int, int)
connect block
connect block allows selected pins microcontroller have more than function. Configuration registers control multiplexers allow connection between on-chip peripherals. Peripherals should connected appropriate pins prior being activated, prior related interrupt(s) being enabled. Activity enabled peripheral function that mapped related should considered undefined.
External memory controller
external Static Memory Controller module which provides interface between system external (off-chip) memory devices. provides support four independently configurable memory banks each with byte lane enable control) simultaneously. Each memory bank capable supporting SRAM, ROM, flash EPROM, burst memory, some external devices. Each memory bank 8-bit, 16-bit, 32-bit wide.
General purpose parallel Fast
Device pins that connected specific peripheral function controlled GPIO registers. Pins dynamically configured inputs outputs. Separate registers allow setting clearing number outputs simultaneously. value output register read back, well current state port pins.
6.7.1 Features
Direction control individual bits. Separate control output clear.
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LPC2290
16/32-bit microcontroller with external memory interface
default inputs after reset.
6.7.2 Fast features available LPC2290/01 only
Fast registers located local fastest possible timing. GPIO registers byte addressable. Entire port value written instruction. Mask registers allow single instruction clear number bits port.
10-bit
LPC2290 each contain single 10-bit successive approximation with eight multiplexed channels.
6.8.1 Features
Measurement range Capable performing more than 400000 10-bit samples second. Burst conversion mode single multiple inputs. Optional conversion transition input Timer Match signal.
6.8.2 features available LPC2290/01 only
Every analog input dedicated result register reduce interrupt overhead. Every analog input generate interrupt once conversion completed. controllers acceptance filter
LPC2290 contains controllers. serial communications protocol which efficiently supports distributed real-time control with very high level security. domain application ranges from high-speed networks cost multiplex wiring.
6.9.1 Features
Data rates Mbit/s each bus. 32-bit register access. Compatible with specification 2.0B, 11898-1. Global Acceptance Filter recognizes 11-bit 29-bit identifiers buses. Acceptance Filter provide FullCAN-style automatic reception selected Standard identifiers.
Full messages generate interrupts. 6.10 UARTs
LPC2290 contains UARTs. addition standard transmit receive data lines, UART1 also provides full modem control handshake interface.
6.10.1 Features
Receive Transmit FIFOs.
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LPC2290
16/32-bit microcontroller with external memory interface
Register locations conform 16C550 industry standard. Receiver FIFO trigger points Built-in baud rate generator. Standard modem interface signals included UART1.
6.10.2 UART features available LPC2290/01 only
transmission FIFO control enables implementation software (XON/XOFF) flow
control both UARTs hardware (CTS/RTS) flow control UART1 only.
Fractional baud rate generator enables standard baud rates such 115200
achieved with crystal frequency above MHz.
Auto-bauding. Auto-CTS/RTS flow-control fully implemented hardware. 6.11 I2C-bus serial controller
I2C-bus bidirectional, inter-IC control using only wires: serial clock line (SCL), serial data line (SDA). Each device recognized unique address operate either receiver-only device (e.g., driver transmitter with capability both receive send information (such memory). Transmitters and/or receivers operate either master slave mode, depending whether chip initiate data transfer only addressed. I2C-bus multi-master bus, controlled more than master connected I2C-bus implemented LPC2290 supports rate kbit/s (Fast I2C-bus).
6.11.1 Features
Compliant with standard I2C-bus interface. Easy configure master, slave, master/slave. Programmable clocks allow versatile rate control. Bidirectional data transfer between masters slaves. Multi-master central master). Arbitration between simultaneously transmitting masters without corruption serial data bus. serial bus.
Serial clock synchronization allows devices with different rates communicate Serial clock synchronization used handshake mechanism suspend
resume serial transfer.
I2C-bus used test diagnostic purposes. 6.12 serial controller
LPC2290 contains SPIs. full duplex serial interface, designed able handle multiple masters slaves connected given bus. Only single master single slave communicate interface during given data transfer. During data transfer master always sends byte data slave, slave always sends byte data master.
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LPC2290
16/32-bit microcontroller with external memory interface
6.12.1 Features
Compliant with specification. Synchronous, serial, full duplex, communication. Combined master slave. Maximum data rate eighth input clock rate.
6.13 serial controller (available LPC2290/01 only)
LPC2290/01 contains Serial Synchronous Port controller (SSP). controller capable operation SPI, 4-wire SSI, Microwire bus. interact with multiple masters slaves bus. However, only single master single slave communicate during given data transfer. supports full duplex transfers, with frames bits bits data flowing from master slave from slave master. Often only these data flows carries meaningful data. SPI1 share same pins LPC2290/01. After reset, SPI1 enabled disabled.
6.13.1 Features
Synchronous Serial Communication. 8-frame FIFOs both transmit receive. Compatible with Motorola SPI, 4-wire National Semiconductor Microwire
buses.
Master slave operation. Four bits bits frame. 6.14 General purpose timers
TIMER0 TIMER1 designed count cycles peripheral clock (PCLK) optionally generate interrupts perform other actions specified timer values, based four match registers. also includes four capture inputs trap timer value when input signal transitions, optionally generating interrupt. Multiple pins selected perform single capture match function, providing application with `or' `and', well `broadcast' functions among them.
6.14.1 Features
32-bit Timer/Counter with programmable 32-bit prescaler. Four 32-bit capture channels timer that take snapshot timer value
when input signal transitions. capture event also optionally generate interrupt.
Four 32-bit match registers that allow:
Continuous operation with optional interrupt generation match. Stop timer match with optional interrupt generation. Reset timer match with optional interrupt generation.
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LPC2290
16/32-bit microcontroller with external memory interface
Four external outputs timer corresponding match registers, with following
capabilities: match. HIGH match. Toggle match. nothing match.
6.14.2 Timer features available LPC2290/01 only
Timers count cycles externally supplied clock providing external event
counting functionality
6.15 Watchdog timer
purpose watchdog reset microcontroller within reasonable amount time enters erroneous state. When enabled, watchdog will generate system reset user program fails `feed' reload) watchdog within predetermined amount time.
6.15.1 Features
Internally resets chip periodically reloaded. Debug mode. Enabled software requires hardware reset watchdog reset/interrupt
disabled.
Incorrect/incomplete feed sequence causes reset/interrupt enabled. Flag indicate watchdog reset. Programmable 32-bit timer with internal pre-scaler. Selectable time period from (Tcy(PCLK) (Tcy(PCLK) multiples Tcy(PCLK)
6.16 Real-time clock
Real-Time Clock (RTC) designed provide counters measure time when normal idle operating mode selected. been designed little power, making suitable battery powered systems where running continuously (Idle mode).
6.16.1 Features
Measures passage time maintain calendar clock. Ultra-low power design support battery powered systems. Provides Seconds, Minutes, Hours, Month, Month, Year, Week,
Year.
Programmable Reference Clock Divider allows adjustment match
various crystal frequencies.
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LPC2290
16/32-bit microcontroller with external memory interface
6.17 Pulse width modulator
based standard Timer block inherits features, although only function pinned LPC2290. Timer designed count cycles peripheral clock (PCLK) optionally generate interrupts perform other actions when specified timer values occur, based seven match registers. function also based match register events. ability separately control rising falling edge locations allows used more applications. instance, multi-phase motor control typically requires three non-overlapping outputs with individual control three pulse widths positions. match registers used provide single edge controlled output. match register (MR0) controls cycle rate, resetting count upon match. other match register controls edge position. Additional single edge controlled outputs require only match register each, since repetition rate same outputs. Multiple single edge controlled outputs will have rising edge beginning each cycle, when match occurs. Three match registers used provide output with both edges controlled. Again, match register controls cycle rate. other match registers control edge positions. Additional double edge controlled outputs require only match registers each, since repetition rate same outputs. With double edge controlled outputs, specific match registers control rising falling edge output. This allows both positive going pulses (when rising edge occurs prior falling edge), negative going pulses (when falling edge occurs prior rising edge).
6.17.1 Features
Seven match registers allow single edge controlled three double edge
controlled outputs, both types.
match registers also allow:
Continuous operation with optional interrupt generation match. Stop timer match with optional interrupt generation. Reset timer match with optional interrupt generation.
Supports single edge controlled and/or double edge controlled outputs. Single
edge controlled outputs HIGH beginning each cycle unless output constant LOW. Double edge controlled outputs have either edge occur position within cycle. This allows both positive going negative going pulses.
Pulse period width number timer counts. This allows complete
flexibility trade-off between resolution repetition rate. outputs will occur same repetition rate.
Double edge controlled outputs programmed either positive going
negative going pulses.
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LPC2290
16/32-bit microcontroller with external memory interface
Match register updates synchronized with pulse outputs prevent generation
erroneous pulses. Software must `release' match values before they become effective.
used standard timer mode enabled. 32-bit Timer/Counter with programmable 32-bit prescaler. 6.18 System control
6.18.1 Crystal oscillator
oscillator supports crystals range MHz. oscillator output frequency called fosc processor clock frequency referred CCLK purposes rate equations, etc. fosc CCLK same value unless running connected. Refer Section 6.18.2 "PLL" additional information.
6.18.2
accepts input clock frequency range MHz. input frequency multiplied into range with Current Controlled Oscillator (CCO). multiplier integer value from practice, multiplier value cannot higher than this family microcontrollers upper frequency limit CPU). operates range MHz, there additional divider loop keep within frequency range while providing desired output frequency. output divider divide produce output clock. Since minimum output divider value insured that output duty cycle.The turned bypassed following chip reset enabled software. program must configure activate PLL, wait Lock, then connect clock source. settling time
6.18.3 Reset wake-up timer
Reset sources LPC2290: RESET watchdog reset. RESET Schmitt trigger input with additional glitch filter. Assertion chip reset source starts Wake-up Timer (see Wake-up Timer description below), causing internal chip reset remain asserted until external reset de-asserted, oscillator running, fixed number clocks have passed, on-chip flash controller completed initialization. When internal reset removed, processor begins executing address which reset vector. that point, processor peripheral registers have been initialized predetermined values. Wake-up Timer ensures that oscillator other analog functions required chip operation fully functional before processor allowed execute instructions. This important power-on, types reset, whenever aforementioned functions turned reason. Since oscillator other functions turned during Power-down mode, wake-up processor from Power-down mode makes Wake-up Timer.
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LPC2290
16/32-bit microcontroller with external memory interface
Wake-up Timer monitors crystal oscillator means checking whether safe begin code execution. When power applied chip, some event caused chip exit Power-down mode, some time required oscillator produce signal sufficient amplitude drive clock logic. amount time depends many factors, including rate ramp case power-on), type crystal electrical characteristics quartz crystal used), well other external circuitry (e.g. capacitors), characteristics oscillator itself under existing ambient conditions.
6.18.4 External interrupt inputs
LPC2290 include nine edge level sensitive External Interrupt Inputs selectable functions. When pins combined, external events processed four independent interrupt signals. External Interrupt Inputs optionally used wake processor from Power-down mode.
6.18.5 Memory mapping control
Memory Mapping Control alters mapping interrupt vectors that appear beginning address 0x0000 0000. Vectors mapped bottom on-chip flash memory, on-chip static RAM. This allows code running different memory spaces have control interrupts.
6.18.6 Power control
LPC2290 support reduced power modes: Idle mode Power-down mode. Idle mode, execution instructions suspended until either reset interrupt occurs. Peripheral functions continue operation during Idle mode generate interrupts cause processor resume execution. Idle mode eliminates power used processor itself, memory systems related controllers, internal buses. Power-down mode, oscillator shut down chip receives internal clocks. processor state registers, peripheral registers, internal SRAM values preserved throughout Power-down mode logic levels chip output pins remain static. Power-down mode terminated normal operation resumed either reset certain specific interrupts that able function without clocks. Since dynamic operation chip suspended, Power-down mode reduces chip power consumption nearly zero. Power Control Peripherals feature allows individual peripherals turned they needed application, resulting additional power savings.
6.18.7
divider determines relationship between processor clock (CCLK) clock used peripheral devices (PCLK). divider serves purposes. first provide peripherals with desired PCLK that they operate speed chosen processor. order achieve this, slowed down processor clock rate. Because must work properly power-up (and timing cannot altered does work since divider control registers reside bus), default condition reset processor clock rate. second purpose divider allow power savings when application does require peripherals full processor rate. Because divider connected output, remains active running) during Idle mode.
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LPC2290
16/32-bit microcontroller with external memory interface
6.19 Emulation debugging
LPC2290 support emulation debugging JTAG serial port. trace port allows tracing program execution. Debugging trace functions multiplexed only with GPIOs Port This means that communication, timer interface peripherals residing Port available during development debugging phase they when application embedded system itself.
6.19.1 EmbeddedICE
Standard EmbeddedICE logic provides on-chip debug support. debugging target system requires host computer running debugger software EmbeddedICE protocol convertor. EmbeddedICE protocol convertor converts remote debug protocol commands JTAG data needed access core. core Debug Communication Channel function built-in. debug communication channel allows program running target communicate with host debugger another separate host without stopping program flow even entering debug state. debug communication channel accessed coprocessor program running ARM7TDMI-S core. debug communication channel allows JTAG port used sending receiving data without affecting normal program flow. debug communication channel data control registers mapped addresses EmbeddedICE logic.
6.19.2 Embedded trace
Since LPC2290 significant amounts on-chip memory, possible determine processor core operating simply observing external pins. Embedded Trace Macrocell (ETM) provides real-time trace capability deeply embedded processor cores. outputs information about processor execution trace port. connected directly core main AMBA system bus. compresses trace information exports through narrow trace port. external trace port analyzer must capture trace information under software debugger control. Instruction trace trace) shows flow execution processor provides list instructions that were executed. Instruction trace significantly compressed only broadcasting branch addresses well status signals that indicate pipeline status cycle cycle basis. Trace information generation controlled selecting trigger resource. Trigger resources include address comparators, counters sequencers. Since trace information compressed software debugger requires static image code being executed. Self-modifying code traced because this restriction.
6.19.3 RealMonitor
RealMonitor configurable software module, developed Inc., which enables real-time debug. lightweight debug monitor that runs background while users debug their foreground application. communicates with host using (Debug Communications Channel), which present EmbeddedICE logic. LPC2290 contain specific configuration RealMonitor software programmed into on-chip flash memory.
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LPC2290
16/32-bit microcontroller with external memory interface
Limiting values
Table Limiting values accordance with Absolute Maximum Rating System (IEC 60134).[1] Symbol VDD(1V8) VDD(3V3) VDDA(3V3) Tstg Ptot(pack) Parameter supply voltage (1.8 supply voltage (3.3 analog supply voltage (3.3 analog input voltage input voltage supply current ground current storage temperature total power dissipation (per package) electrostatic discharge voltage based package heat transfer, device power consumption human body model; pins
Conditions internal rail external rail
-0.5 -0.5 -0.5 -0.5
+2.5 +3.6 +4.6 +5.1 +6.0 VDD(3V3) +150
Unit
tolerant pins other pins supply ground
[2][3] [2][4]
-0.5 -0.5
Vesd
-2000
+2000
following applies Table This product includes circuitry specifically designed protection internal devices from damaging effects excessive static charge. Nonetheless, suggested that conventional precautions taken avoid applying greater than rated maximum. Parameters valid over operating temperature range unless otherwise specified. voltages with respect unless otherwise noted. Including voltage outputs 3-state mode. Only valid when VDD(3V3) supply voltage present. exceed peak current limited times corresponding maximum current. Dependent package type. Human body model: equivalent discharging capacitor through series resistor.
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LPC2290
16/32-bit microcontroller with external memory interface
Static characteristics
Table Static characteristics Tamb industrial applications, unless otherwise specified. Symbol VDD(1V8) VDD(3V3) Parameter supply voltage (1.8 supply voltage (3.3 Conditions internal rail external rail 1.65 Typ[1] 1.95 Unit
VDDA(3V3) analog supply voltage (3.3 Standard port pins, RESET, RTCK Ilatch Vhys IOHS IOLS IDD(act) LOW-level input current HIGH-level input current OFF-state output current latch-up current input voltage output voltage HIGH-level input voltage LOW-level input voltage hysteresis voltage HIGH-level output voltage LOW-level output voltage LOW-level output current HIGH-level short-circuit output current LOW-level short-circuit output current pull-down current pull-up current active mode supply current VDD(3V3) VDD(3V3) VDD(1V8) CCLK MHz, Tamb code HIGH-level output current VDD(3V3)
pull-up VDD(3V3); pull-down VDD(3V3); pull-up/down -(0.5VDD(3V3)) (1.5VDD(3V3));
[2][3][4]
VDD(3V3)
output active
VDD(3V3)
while(1){}
executed from flash, active peripherals IDD(pd) Power-down mode supply VDD(1V8) current Tamb VDD(1V8) Tamb VDD(1V8) Tamb 1000
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16/32-bit microcontroller with external memory interface
Table Static characteristics .continued Tamb industrial applications, unless otherwise specified. Symbol I2C-bus Vhys Parameter pins HIGH-level input voltage LOW-level input voltage hysteresis voltage LOW-level output voltage input leakage current IOLS VDD(3V3); Oscillator pins Vi(XTAL1) Vo(XTAL2) input voltage XTAL1 output voltage XTAL2
Conditions
0.7VDD(3V3)
Typ[1]
Unit
0.3VDD(3V3)
0.5VDD(3V3)
Typical ratings guaranteed. values listed room temperature (+25 °C), nominal supply voltages. Including voltage outputs 3-state mode. VDD(3V3) supply voltages must present. 3-state outputs into 3-state mode when VDD(3V3) grounded. Accounts voltage drop supply lines. Only allowed short time period. Minimum condition maximum condition Applies P1[25:16].
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LPC2290
16/32-bit microcontroller with external memory interface
Table static characteristics VDDA Tamb +125 unless otherwise specified. frequency MHz. Symbol EL(adj)
Parameter analog input voltage analog input capacitance differential linearity error integral non-linearity offset error gain error absolute error
Conditions
[1][2][3] [1][4] [1][5] [1][6] [1][7]
VDDA ±0.5
Unit
Conditions: VSSA VDDA monotonic, there missing codes. differential linearity error (ED) difference between actual step width ideal step width. Figure integral non-linearity (EL(adj)) peak difference between center steps actual ideal transfer curve after appropriate adjustment gain offset errors. Figure offset error (EO) absolute difference between straight line which fits actual curve straight line which fits ideal curve. Figure gain error (EG) relative difference percent between straight line fitting actual transfer curve after removing offset error, straight line which fits ideal transfer curve. Figure absolute voltage error (ET) maximum difference between center steps actual transfer curve non-calibrated ideal transfer curve. Figure
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LPC2290
16/32-bit microcontroller with external memory interface
offset error 1023
gain error
1022
1021
1020
1019
1018
code
(ideal) 1018 1019 1020 1021 1022 1023 1024
(LSBideal) offset error
VDDA VSSA 1024
002aaa668
Example actual transfer curve. ideal transfer curve. Differential linearity error (ED). Integral non-linearity (EL(adj)). Center step actual transfer curve.
characteristics
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16/32-bit microcontroller with external memory interface
Dynamic characteristics
Table Dynamic characteristics Tamb +125 VDD(1V8), VDD(3V3) over specified ranges.[1] Symbol External clock fosc oscillator frequency supplied external oscillator (signal generator) external clock frequency supplied external crystal oscillator external clock frequency on-chip used external clock frequency on-chip bootloader used initial code download Tcy(clk) tCHCX tCLCX tCLCH tCHCL
Parameter
Conditions
Unit
clock cycle time clock HIGH time clock time clock rise time clock fall time rise time fall time fall time
Tcy(clk) Tcy(clk)
1000
Port pins (except P0.2 P0.3)
I2C-bus pins (P0.2 P0.3)
Parameters valid over operating temperature range unless otherwise specified. capacitance from
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16/32-bit microcontroller with external memory interface
Table External memory interface dynamic characteristics Tamb Symbol tCHAV tCHCSL tCHCSH tCHANV Parameter XCLK HIGH address valid time XCLK HIGH time XCLK HIGH HIGH time XCLK HIGH address invalid time address valid time address valid time time memory access time memory access time (initial burst-ROM) memory access time (subsequent burst-ROM) data hold time HIGH HIGH time HIGH address invalid time XCLK HIGH time XCLK HIGH HIGH time address valid time data valid time time time data valid time data valid time HIGH time HIGH time HIGH address invalid time HIGH data invalid time HIGH address invalid time
[2][3]
Conditions
Unit
Common read write cycles
Read cycle parameters tCSLAV tOELAV tCSLOEL tam(ibr) tam(sbr) th(D) tCSHOEH tOEHANV tCHOEL tCHOEH (Tcy(CCLK) WST1)) (-20) (Tcy(CCLK) WST1)) (-20) Tcy(CCLK) (-20)
[2][3]
[2][4]
Write cycle parameters tAVCSL tCSLDV tCSLWEL tCSLBLSL tWELDV tCSLDV tWELWEH tBLSLBLSH tWEHANV tWEHDNV tBLSHANV Tcy(CCLK) Tcy(CCLK) WST2) Tcy(CCLK) WST2) Tcy(CCLK) Tcy(CCLK)) Tcy(CCLK) Tcy(CCLK) WST2) Tcy(CCLK) WST2) Tcy(CCLK)
Tcy(CCLK)) Tcy(CCLK)
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Table External memory interface dynamic characteristics .continued Tamb Symbol tBLSHDNV tCHDV tCHWEL tCHBLSL tCHWEH tCHBLSH tCHDNV Parameter HIGH data invalid time XCLK HIGH data valid time XCLK HIGH time XCLK HIGH time XCLK HIGH HIGH time XCLK HIGH HIGH time XCLK HIGH data invalid time Conditions
Tcy(CCLK))
Unit
Tcy(CCLK))
Except initial access, which case address Tcy(CCLK) earlier. Tcy(CCLK) 1/CCLK. Latest address valid, LOW, data valid. Address valid data valid. Earliest HIGH, HIGH, address change data invalid.
Table
Standard read access specifications frequency setting round integer Memory access time requirement
Access cycle
standard read
WRITE INIT
CCLK WRITE CCLK INIT CCLK
CCLK WRITE CCLK INIT CCLK CCLK
standard write
burst read initial
burst read subsequent
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16/32-bit microcontroller with external memory interface
Timing
XCLK tCSLAV tCSHOEH
addr data tCSLOEL tOELAV tCHOEL tCHOEH
002aaa749
th(D)
tOEHANV
External memory read access
XCLK tCSLDV
tAVCSL tWELWEH tBLSLBLSH tWEHANV tCSLBLSL tWELDV tBLSHANV
tCSLWEL BLS/WE
addr tCSLDV data tWEHDNV tBLSHDNV
002aaa750
External memory write access
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16/32-bit microcontroller with external memory interface
0.45
0.2VDD 0.2VDD tCHCL tCLCX Tcy(clk)
002aaa907
tCHCX tCLCH
External clock timing
LPC2290 power consumption measurements
current (mA)
002aab452
frequency (MHz)
Test conditions: code executed from on-chip RAM; peripherals enabled PCONP register; PCLK CCLK/4. core (typical) 1.65 core (typical)
LPC2290 IDD(act) measured different frequencies (CCLK) temperatures
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current (mA)
002aab453
frequency (MHz)
Test conditions: Idle mode entered executing code from on-chip RAM; peripherals enabled PCONP register; PCLK CCLK/4. core (typical) 1.65 core (typical)
LPC2290 idle measured different frequencies (CCLK) temperatures
current (µA)
002aab454
-100
temp (°C)
Test conditions: Power-down mode entered executing code from on-chip RAM; peripherals enabled PCONP register. 1.95 core core 1.65 core
LPC2290 IDD(pd) measured different temperatures
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Package outline
LQFP144: plastic profile quad flat package; leads; body SOT486-1
detail
index
scale
DIMENSIONS original dimensions) UNIT max. 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09 20.1 19.9 20.1 19.9 0.75 0.45 0.08 0.08 D(1) E(1)
22.15 22.15 21.85 21.85
Note Plastic metal protrusions 0.25 maximum side included. OUTLINE VERSION SOT486-1 REFERENCES 136E23 JEDEC MS-026 JEITA EUROPEAN PROJECTION
ISSUE DATE 00-03-14 03-02-20
Package outline SOT486-1 (LQFP144)
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Abbreviations
Table Acronym AMBA CISC FIFO GPIO RISC SRAM UART Abbreviations Description Analog-to-Digital Converter Advanced Microcontroller Architecture AMBA Peripheral Controller Area Network Complex Instruction Computer Central Processing Unit First First General Purpose Input/Output Phase-Locked Loop Pulse Width Modulator Random Access Memory Reduced Instruction Computer Serial Peripheral Interface Static Random Access Memory Synchronous Serial Port Transistor-Transistor Logic Universal Asynchronous Receiver/Transmitter
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16/32-bit microcontroller with external memory interface
Revision history
Table Revision history Release date 20061116 Data sheet status Product data sheet Change notice Supersedes LPC2290-02 Document LPC2290_3 Modifications:
format this data sheet been redesigned comply with identity guidelines Semiconductors. Legal texts have been adapted company name where appropriate. features specific LPC2290/01 have been added throughout. Product data Preliminary data LPC2290-01
LPC2290-02 LPC2290-01
20041223 20040209
LPC2290_3
B.V. 2006. rights reserved.
Product data sheet
Rev. November 2006
Semiconductors
LPC2290
16/32-bit microcontroller with external memory interface
Legal information
13.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
Product status[3] Development Qualification Production
Definition This document contains data from objective specification product development. This document contains data from preliminary specification. This document contains product specification.
Please consult most recently issued document before initiating completing design. term `short data sheet' explained section "Definitions". product status device(s) described this document have changed since this document published differ case multiple devices. latest product status information available Internet http://www.nxp.com.
13.2 Definitions
Draft document draft version only. content still under internal review subject formal approval, which result modifications additions. Semiconductors does give representations warranties accuracy completeness information included herein shall have liability consequences such information. Short data sheet short data sheet extract from full data sheet with same product type number(s) title. short data sheet intended quick reference only should relied upon contain detailed full information. detailed full information relevant full data sheet, which available request local Semiconductors sales office. case inconsistency conflict with short data sheet, full data sheet shall prevail.
result personal injury, death severe property environmental damage. Semiconductors accepts liability inclusion and/or Semiconductors products such equipment applications therefore such inclusion and/or customer's risk. Applications Applications that described herein these products illustrative purposes only. Semiconductors makes representation warranty that such applications will suitable specified without further testing modification. Limiting values Stress above more limiting values defined Absolute Maximum Ratings System 60134) cause permanent damage device. Limiting values stress ratings only operation device these other conditions above those given Characteristics sections this document implied. Exposure limiting values extended periods affect device reliability. Terms conditions sale Semiconductors products sold subject general terms conditions commercial sale, published including those pertaining warranty, intellectual property rights infringement limitation liability, unless explicitly otherwise agreed writing Semiconductors. case inconsistency conflict between information this document such terms conditions, latter will prevail. offer sell license Nothing this document interpreted construed offer sell products that open acceptance grant, conveyance implication license under copyrights, patents other industrial intellectual property rights.
13.3 Disclaimers
General Information this document believed accurate reliable. However, Semiconductors does give representations warranties, expressed implied, accuracy completeness such information shall have liability consequences such information. Right make changes Semiconductors reserves right make changes information published this document, including without limitation specifications product descriptions, time without notice. This document supersedes replaces information supplied prior publication hereof. Suitability Semiconductors products designed, authorized warranted suitable medical, military, aircraft, space life support equipment, applications where failure malfunction Semiconductors product reasonably expected
13.4 Trademarks
Notice: referenced brands, product names, service names trademarks property their respective owners. I2C-bus logo trademark B.V.
Contact information
additional information, please visit: http://www.nxp.com sales office addresses, send email salesaddresses@nxp.com
LPC2290_3
B.V. 2006. rights reserved.
Product data sheet
Rev. November 2006
Semiconductors
LPC2290
16/32-bit microcontroller with external memory interface
Contents
6.4.1 6.7.1 6.7.2 6.8.1 6.8.2 6.9.1 6.10 6.10.1 6.10.2 6.11 6.11.1 6.12 6.12.1 6.13 6.13.1 6.14 6.14.1 6.14.2 6.15 6.15.1 6.16 6.16.1 6.17 General description Features Enhancements introduced with LPC2290/01 device features common LPC2290 LPC2290/01 Ordering information Ordering options Block diagram Pinning information Pinning description Functional description Architectural overview. On-chip SRAM Memory map. Interrupt controller Interrupt sources. connect block External memory controller. General purpose parallel Fast Features Fast features available LPC2290/01 only 10-bit Features features available LPC2290/01 only controllers acceptance filter Features UARTs Features UART features available LPC2290/01 only I2C-bus serial controller Features serial controller. Features serial controller (available LPC2290/01 only) Features General purpose timers Features Timer features available LPC2290/01 only Watchdog timer. Features Real-time clock Features Pulse width modulator 6.17.1 6.18 6.18.1 6.18.2 6.18.3 6.18.4 6.18.5 6.18.6 6.18.7 6.19 6.19.1 6.19.2 6.19.3 13.1 13.2 13.3 13.4 Features System control Crystal oscillator. PLL. Reset wake-up timer External interrupt inputs Memory mapping control Power control Emulation debugging. EmbeddedICE Embedded trace. RealMonitor Limiting values Static characteristics Dynamic characteristics Timing LPC2290 power consumption measurements Package outline Abbreviations Revision history Legal information Data sheet status Definitions Disclaimers. Trademarks Contact information Contents.
Please aware that important notices concerning this document product(s) described herein, have been included section `Legal information'.
B.V. 2006.
rights reserved.
more information, please visit: http://www.nxp.com sales office addresses, please send email salesaddresses@nxp.com Date release: November 2006 Document identifier: LPC2290_3

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