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16/32-bit microcontrollers; flashless, with 10-bit external memory int


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LPC2210/2220
16/32-bit microcontrollers; flashless, with 10-bit external memory interface
Rev. December 2008 Product data sheet
LPC2210/2220 microcontrollers based 16/32-bit ARM7TDMI-S with real-time emulation embedded trace support. critical code size applications, alternative 16-bit Thumb mode reduces code more than with minimal performance penalty. With their 144-pin package, power consumption, various 32-bit timers, 8-channel 10-bit ADC, channels, nine external interrupt pins these microcontrollers particularly suitable industrial control, medical systems, access control point-of-sale. LPC2210/2220 provide GPIOs depending configuration. With wide range serial communications interfaces, also very well suited communication gateways, protocol converters embedded soft modems well many other general-purpose applications. Remark: Throughout data sheet, term LPC2210/2220 will apply devices with without suffix. suffix will used differentiate LPC2210 devices only when necessary.
Features
features
16/32-bit ARM7TDMI-S microcontroller LQFP144 TFBGA144 package. 16/64 on-chip static (LPC2210/2220). Serial bootloader using UART0 provides in-system download programming capabilities. EmbeddedICE-RT Embedded Trace interfaces offer real-time debugging with on-chip RealMonitor software well high-speed real-time tracing instruction execution. Eight channel 10-bit with conversion time 2.44 LPC2210/01 LPC2220 only: Dedicated result registers ADC(s) reduce interrupt overhead. pads tolerant when configured digital function(s). 32-bit timers (LPC2220 LPC2210/01 also external event counters) with four capture four compare channels, unit (six outputs), Real-Time Clock (RTC), watchdog. Multiple serial interfaces including UARTs (16C550), Fast I2C-bus (400 kbit/s) SPIs. LPC2210/01 LPC2220 only: Synchronous Serial Port (SSP) with data buffers variable length transfers selected replace SPI.
Semiconductors
LPC2210/2220
16/32-bit microcontrollers
LPC2210/01 LPC2220 only: UART0/1 include fractional baud rate generator, auto-bauding capabilities, handshake flow-control fully implemented hardware. Vectored Interrupt Controller (VIC) with configurable priorities vector addresses. Configurable external memory interface with four banks, each 8/16/32-bit data width. general purpose pins tolerant) capable. nine edge/level sensitive external interrupt pins available. LPC2210/01 LPC2220 only: Fast GPIO ports enable port toggling times faster than original device. They also allow port read time regardless function. (LPC2210) (LPC2210/01 LPC2220) maximum clock available from programmable on-chip Phase-Locked Loop (PLL) with settling time On-chip integrated oscillator operates with external crystal range with external oscillator MHz. Power saving modes include Idle Power-down. Processor wake-up from Power-down mode external interrupt. Individual enable/disable peripheral functions power optimization. Dual power supply: operating voltage range 1.65 1.95 (1.8 0.15 power supply range (3.3 with tolerant pads. 16/32-bit ARM7TDMI-S processor.
Ordering information
Table Ordering information Package Name LPC2210FBD144 LQFP144 Description plastic profile quad flat package; leads; body plastic profile quad flat package; leads; body plastic profile quad flat package; leads; body plastic thin fine-pitch ball grid array package; balls; body plastic thin fine-pitch ball grid array package; balls; body Version SOT486-1 SOT486-1 SOT486-1 SOT569-2 SOT569-2 Type number
LPC2210FBD144/01 LQFP144 LPC2220FBD144 LPC2220FET144 LPC2220FET144/G LQFP144 TFBGA144 TFBGA144
LPC2210_2220_6
B.V. 2008. rights reserved.
Product data sheet
Rev. December 2008
Semiconductors
LPC2210/2220
16/32-bit microcontrollers
Ordering options
Table Ordering options Fast GPIO/ Temperature range SSP/ Enhanced UART, ADC, Timer Type number
LPC2210FBD144 LPC2210FBD144/01 LPC2220FBD144 LPC2220FET144 LPC2220FET144/G
LPC2210_2220_6
B.V. 2008. rights reserved.
Product data sheet
Rev. December 2008
Semiconductors
LPC2210/2220
16/32-bit microcontrollers
Block diagram
TMS(1) TDI(1) TRST(1) TCK(1) TDO(1)
XTAL2 XTAL1 RESET
LPC2210 LPC2210/01 LPC2220
FAST GENERAL PURPOSE I/O(3)
TEST/DEBUG INTERFACE
EMULATION TRACE MODULE
system clock
SYSTEM FUNCTIONS VECTORED INTERRUPT CONTROLLER
ARM7TDMI-S
BRIDGE
ARM7 local
AMBA (Advanced High-performance Bus)
INTERNAL SRAM CONTROLLER
DECODER BRIDGE (Advanced Peripheral Bus) DIVIDER CS[3:0](2) A[23:0](2) BLS[3:0](2) WE(2) D[31:0](2) SCK0, SCK1
16/64 SRAM
EXTERNAL MEMORY CONTROLLER
EINT[3:0]
EXTERNAL INTERRUPTS
SERIAL INTERFACE
CAP0 CAP1 MAT0 MAT1
CAPTURE/ COMPARE TIMER 0/TIMER
SSP(3) SERIAL INTERFACES
MOSI0, MOSI1 MISO0, MISO1 SSEL0, SSEL1 TXD0, TXD1
AIN[7:0]
CONVERTER
UART0/UART1
WATCHDOG TIMER GENERAL PURPOSE REAL-TIME CLOCK
RXD0, RXD1 DSR1, CTS1, RTS1, DTR1 DCD1,
PWM[6:1]
PWM0
SYSTEM CONTROL
002aaa793
When test/debug interface used, GPIO/other functions sharing these pins available. Shared with GPIO. LPC2210/01 LPC2220 only.
Block diagram
LPC2210_2220_6 B.V. 2008. rights reserved.
Product data sheet
Rev. December 2008
Semiconductors
LPC2210/2220
16/32-bit microcontrollers
Pinning information
Pinning
002aaa794
LPC2210FBD144 LPC2210FBD144/01 LPC2220FBD144
configuration LQFP144
ball index area
LPC2220FET144
002aab245
Transparent view
Ball configuration diagram TFBGA144
LPC2210_2220_6
B.V. 2008. rights reserved.
Product data sheet
Rev. December 2008
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx
Table P2.22/ VDD(3V3) Ball allocation VDDA(1V8) P1.27/ P1.28/ XTAL2 P2.21/ VSSA(PLL) P2.18/ P2.19/ P2.14/ P2.15/ P1.29/ P2.12/ P2.11/ P0.20/ MAT1.3/ SSEL1/ EINT3 P0.19/ MAT1.2/ MOSI1/ CAP1.2 P0.18/ CAP1.3/ MISO1/ MAT1.3 P2.10/ VDD(3V3) P2.7/D7 P2.6/D6 VDD(3V3) VDD(1V8) P2.3/D3 P2.4/D4
Product data sheet Rev. December 2008
B.V. 2008. rights reserved. LPC2210_2220_6
Semiconductors
Column
P0.21/ PWM5/ CAP1.3 P0.24
XTAL1
VSSA
RESET
P2.16/
P2.13/
P2.9/D9
P2.5/D5
P2.2/D2
P2.1/D1
VDD(3V3)
P1.19/ TRACEP P2.24/
P0.23
P0.22/ CAP0.0/ MAT0.0
P2.20/
P2.17/
P2.8/D8
P1.30/
P1.20/ TRACES P2.0/D0
P0.17/ CAP1.2/ SCK1/ MAT1.2 P3.30/ BLS1
P2.25/
P2.23/
P0.16/ EINT0/ MAT0.2/ CAP0.2 P3.31/ BLS0 P0.14/ DCD1/ EINT1 P0.13/ DTR1/ MAT1.1 P3.3/A3
P0.15/ RI1/ EINT2
P2.27/ D27/ BOOT1 P2.29/ P0.25
P1.18/ TRACEP P2.28/ n.c.
VDDA(3V3)
P2.26/ D26/ BOOT0
P1.21/ VDD(3V3) PIPESTAT P1.0/CS0 P3.0/A0
P2.30/ P2.31/ D30/AIN4 D31/AIN5 P0.27/ AIN0/ CAP0.1/ MAT0.1 P3.29/ BLS2/ AIN6 VDD(3V3) P1.17/ TRACEP P3.28/ BLS3/ AIN7 P3.22/ P3.20/ P0.1/ RXD0/ PWM3/ EINT0 P3.14/ P1.25/ EXTIN0 P3.11/
P1.1/OE
P1.22/ P3.2/A2 PIPESTAT P1.23/ P0.11/ PIPESTAT CTS1/ CAP1.1 P0.10/ RTS1/ CAP1.0
P3.1/A1
16/32-bit microcontrollers
LPC2210/2220
P0.28/ AIN1/ CAP0.2/ MAT0.2
P0.12/ DSR1/ MAT1.0 P3.4/A4
P3.27/WE P3.26/
VDD(3V3)
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx
Table P0.29/ AIN2/ CAP0.3/ MAT0.3 P3.25/ Ball allocation .continued P0.30/ AIN3/ EINT3/ CAP0.0 P3.24/ P1.16/ TRACEP VDD(3V3) P0.0/ TXD0/ PWM1 P1.31/ TRST P3.19/ P0.2/ SCL/ CAP0.0 VDD(3V3) P3.15/ P0.4/ SCK0/ CAP0.1 P0.3/ SDA/ MAT0.0/ EINT1 VDD(3V3) P3.12/ P1.24/ TRACEC P0.7/ SSEL0/ PWM2/ EINT2 P0.6/ MOSI0/ CAP0.2 P0.8/ TXD1/ PWM4 P3.7/A7 P0.9/ RXD1/ PWM6/ EINT3 P3.5/A5
Product data sheet Rev. December 2008
LPC2210_2220_6 B.V. 2008. rights reserved.
Semiconductors
Column
P3.18/
P3.16/
P3.13/
P3.9/A9
VDD(1V8)
P3.23/ A23/ XCLK
P3.21/
P3.17/
P1.26/ RTCK
P0.5/ MISO0/ MAT0.1
P3.10/
P3.8/A8
P3.6/A6
16/32-bit microcontrollers
LPC2210/2220
Semiconductors
LPC2210/2220
16/32-bit microcontrollers
description
Table Symbol P0.0 P0.31 description (LQFP) (TFBGA) Type Description Port Port 32-bit bidirectional port with individual direction controls each bit. operation port pins depends upon function selected Connect Block. Pins port available. P0.0/TXD0/ PWM1 P0.1/RXD0/ PWM3/EINT0 42[1] 49[2] L4[1] K6[2] P0.2/SCL/ CAP0.0 P0.3/SDA/ MAT0.0/EINT1 50[3] L6[3] 58[3] M8[3] P0.4/SCK0/ CAP0.1 P0.5/MISO0/ MAT0.1 P0.6/MOSI0/ CAP0.2 P0.7/SSEL0/ PWM2/EINT2 59[1] L8[1] 61[1] N9[1] 68[1] N11[1] 69[2] M11[2] P0.8/TXD1/ PWM4 P0.9/RXD1/ PWM6/EINT3 75[1] 76[2] L12[1] L13[2] P0.10/RTS1/ CAP1.0 P0.11/CTS1/ CAP1.1 P0.12/DSR1/ MAT1.0 78[1] 83[1] 84[1] K11[1] J12[1] J13[1] TXD0 Transmitter output UART0. PWM1 Pulse Width Modulator output RXD0 Receiver input UART0. PWM3 Pulse Width Modulator output EINT0 External interrupt input I2C-bus clock input/output. Open-drain output (for I2C-bus compliance). CAP0.0 Capture input Timer channel I2C-bus data input/output. Open-drain output (for I2C-bus compliance). MAT0.0 Match output Timer channel EINT1 External interrupt input. SCK0 Serial clock SPI0. clock output from master input slave. CAP0.1 Capture input Timer channel MISO0 Master Slave SPI0. Data input master data output from slave. MAT0.1 Match output Timer channel MOSI0 Master Slave SPI0. Data output from master data input slave. CAP0.2 Capture input Timer channel SSEL0 Slave Select SPI0. Selects interface slave. PWM2 Pulse Width Modulator output EINT2 External interrupt input. TXD1 Transmitter output UART1. PWM4 Pulse Width Modulator output RXD1 Receiver input UART1. PWM6 Pulse Width Modulator output EINT3 External interrupt input. RTS1 Request Send output UART1. CAP1.0 Capture input Timer channel CTS1 Clear Send input UART1. CAP1.1 Capture input Timer channel DSR1 Data Ready input UART1. MAT1.0 Match output Timer channel
LPC2210_2220_6
B.V. 2008. rights reserved.
Product data sheet
Rev. December 2008
Semiconductors
LPC2210/2220
16/32-bit microcontrollers
Table Symbol
description .continued (LQFP) 85[1] 92[2] (TFBGA) Type H10[1] G10[2] Description DTR1 Data Terminal Ready output UART1. MAT1.1 Match output Timer channel DCD1 Data Carrier Detect input UART1. EINT1 External interrupt input. Note: this while RESET forces on-chip bootloader take over control part after reset.
P0.13/DTR1/ MAT1.1 P0.14/DCD1/ EINT1
P0.15/RI1/ EINT2
99[2]
E11[2] E10[2]
Ring Indicator input UART1. EINT2 External interrupt input. EINT0 External interrupt input. MAT0.2 Match output Timer channel CAP0.2 Capture input Timer channel CAP1.2 Capture input Timer channel SCK1 Serial Clock SPI1/SSI/Microwire. SPI/SSI/Microwire clock output from master input slave. MAT1.2 Match output Timer channel CAP1.3 Capture input Timer channel MISO1 Master Slave SPI1. Data input master data output from slave. MAT1.3 Match output Timer channel MAT1.2 Match output Timer channel MOSI1 Master Slave SPI1. Data output from master data input slave.
P0.16/EINT0/ 100[2] MAT0.2/CAP0.2
P0.17/CAP1.2/ SCK1/MAT1.2
101[1]
D13[1]
P0.18/CAP1.3/ MISO1/MAT1.3
121[1]
D8[1]
P0.19/MAT1.2/ MOSI1/CAP1.2
122[1]
C8[1]
P0.20/MAT1.3/ SSEL1/ EINT3 123[2] B8[2]
interface: MOSI line. SSI: DX/RX line (SPI1 master/slave). Microwire: SO/SI line (SPI1 master/slave).
CAP1.2 Capture input Timer channel MAT1.3 Match output Timer channel SSEL1 Slave Select SPI1/Microwire. Used select Microwire interface slave. Frame synchronization case 4-wire SSI. EINT3 External interrupt input. PWM5 Pulse Width Modulator output CAP1.3 Capture input Timer channel CAP0.0 Capture input Timer channel MAT0.0 Match output Timer channel General purpose bidirectional digital port only. General purpose bidirectional digital port only. General purpose bidirectional digital port only. AIN0 ADC, input This analog input always connected pin. CAP0.1 Capture input Timer channel MAT0.1 Match output Timer channel
P0.21/PWM5/ CAP1.3 P0.22/CAP0.0/ MAT0.0 P0.23 P0.24 P0.25 P0.27/AIN0/ CAP0.1/MAT0.1 4[1] 5[1] 6[1] 8[1] 21[1] 23[4] C1[1] D4[1] D3[1] D1[1] H1[1] H3[4]
LPC2210_2220_6
B.V. 2008. rights reserved.
Product data sheet
Rev. December 2008
Semiconductors
LPC2210/2220
16/32-bit microcontrollers
Table Symbol
description .continued (LQFP) (TFBGA) Type J1[4] Description AIN1 ADC, input This analog input always connected pin. CAP0.2 Capture input Timer channel MAT0.2 Match output Timer channel AIN2 ADC, input This analog input always connected pin. CAP0.3 Capture input Timer Channel MAT0.3 Match output Timer channel AIN3 ADC, input This analog input always connected pin. EINT3 External interrupt input. CAP0.0 Capture input Timer channel Port Port 32-bit bidirectional port with individual direction controls each bit. operation port pins depends upon function selected Connect Block. Pins through port available. LOW-active Chip Select signal. (Bank addresses range 0x8000 0000 0x80FF FFFF) LOW-active Output Enable signal. TRACEPKT0 Trace Packet, Standard port with internal pull-up. TRACEPKT1 Trace Packet, Standard port with internal pull-up. TRACEPKT2 Trace Packet, Standard port with internal pull-up. TRACEPKT3 Trace Packet, Standard port with internal pull-up. TRACESYNC Trace Synchronization. Standard port with internal pull-up. Note: this while RESET LOW, enables pins P1[25:16] operate Trace port after reset.
P0.28/AIN1/ 25[4] CAP0.2/MAT0.2
P0.29/AIN2/ 32[4] CAP0.3/MAT0.3
L1[4]
P0.30/AIN3/ EINT3/CAP0.0
33[4]
L2[4]
P1.0 P1.31
P1.0/CS0 P1.1/OE P1.16/ TRACEPKT0 P1.17/ TRACEPKT1 P1.18/ TRACEPKT2 P1.19/ TRACEPKT3 P1.20/ TRACESYNC
91[5] 90[5] 34[5] 24[5] 15[5] 7[5] 102[5]
G11[5] G13[5] L3[5] H4[5] F2[5] D2[5] D12[5]
P1.21/ PIPESTAT0 P1.22/ PIPESTAT1 P1.23/ PIPESTAT2 P1.24/ TRACECLK P1.25/EXTIN0
95[5] 86[5] 82[5] 70[5] 60[5]
F11[5] H11[5] J11[5] L11[5] K8[5]
PIPESTAT0 Pipeline Status, Standard port with internal pull-up. PIPESTAT1 Pipeline Status, Standard port with internal pull-up. PIPESTAT2 Pipeline Status, Standard port with internal pull-up. TRACECLK Trace Clock. Standard port with internal pull-up. EXTIN0 External Trigger Input. Standard with internal pull-up.
LPC2210_2220_6
B.V. 2008. rights reserved.
Product data sheet
Rev. December 2008
Semiconductors
LPC2210/2220
16/32-bit microcontrollers
Table Symbol
description .continued (LQFP) 52[5] (TFBGA) Type N6[5] Description RTCK Returned Test Clock output. Extra signal added JTAG port. Assists debugger synchronization when processor frequency varies. Bidirectional with internal pull-up. Note: this while RESET LOW, enables pins P1[31:26] operate Debug port after reset.
P1.26/RTCK
P1.27/TDO P1.28/TDI P1.29/TCK
144[5] 140[5] 126[5]
B2[5] A3[5] A7[5]
Test Data JTAG interface. Test Data JTAG interface. Test Clock JTAG interface. This clock must slower than clock (CCLK) JTAG interface operate. Test Mode Select JTAG interface. TRST Test Reset JTAG interface. Port Port 32-bit bidirectional port with individual direction controls each bit. operation port pins depends upon function selected Connect Block. External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line
B.V. 2008. rights reserved.
P1.30/TMS P1.31/TRST P2.0 P2.31
113[5] 43[5]
D10[5] M4[5]
P2.0/D0 P2.1/D1 P2.2/D2 P2.3/D3 P2.4/D4 P2.5/D5 P2.6/D6 P2.7/D7 P2.8/D8 P2.9/D9 P2.10/D10 P2.11/D11 P2.12/D12 P2.13/D13 P2.14/D14 P2.15/D15 P2.16/D16 P2.17/D17 P2.18/D18 P2.19/D19 P2.20/D20 P2.21/D21 P2.22/D22 P2.23/D23 P2.24/D24 P2.25/D25
LPC2210_2220_6
98[5] 105[5] 106[5] 108[5] 109[5] 114[5] 115[5] 116[5] 117[5] 118[5] 120[5] 124[5] 125[5] 127[5] 129[5] 130[5] 131[5] 132[5] 133[5] 134[5] 136[5] 137[5] 1[5] 10[5] 11[5] 12[5]
E12[5] C12[5] C11[5] B12[5] A13[5] C10[5] B10[5] A10[5] D9[5] C9[5] A9[5] A8[5] B7[5] C7[5] A6[5] B6[5] C6[5] D6[5] A5[5] B5[5] D5[5] A4[5] A1[5] E3[5] E2[5] E1[5]
Product data sheet
Rev. December 2008
Semiconductors
LPC2210/2220
16/32-bit microcontrollers
Table Symbol P2.26/D26/ BOOT0
description .continued (LQFP) 13[5] (TFBGA) Type F4[5] Description External memory data line BOOT0 While RESET LOW, together with BOOT1 controls booting internal operation. Internal pull-up ensures HIGH state left unconnected. External memory data line BOOT1 While RESET LOW, together with BOOT0 controls booting internal operation. Internal pull-up ensures HIGH state left unconnected. BOOT1:0 selects 8-bit memory boot. BOOT1:0 selects 16-bit memory boot. BOOT1:0 selects 32-bit memory boot. BOOT1:0 selects 16-bit memory boot.
P2.27/D27/ BOOT1
16[5]
F1[5]
P2.28/D28 P2.29/D29 P2.30/D30/ AIN4 P2.31/D31/ AIN5 P3.0 P3.31
17[5] 18[5] 19[2]
G2[5] G1[5] G3[2]
External memory data line External memory data line External memory data line AIN4 ADC, input This analog input always connected pin. External memory data line AIN5 ADC, input This analog input always connected pin. Port Port 32-bit bidirectional port with individual direction controls each bit. operation port pins depends upon function selected Connect Block. External memory address line External memory address line External memory address line External memory address line External memory address line External memory address line External memory address line External memory address line External memory address line External memory address line External memory address line External memory address line External memory address line External memory address line External memory address line External memory address line External memory address line External memory address line External memory address line
20[2]
G4[2]
P3.0/A0 P3.1/A1 P3.2/A2 P3.3/A3 P3.4/A4 P3.5/A5 P3.6/A6 P3.7/A7 P3.8/A8 P3.9/A9 P3.10/A10 P3.11/A11 P3.12/A12 P3.13/A13 P3.14/A14 P3.15/A15 P3.16/A16 P3.17/A17 P3.18/A18
89[5] 88[5] 87[5] 81[5] 80[5] 74[5] 73[5] 72[5] 71[5] 66[5] 65[5] 64[5] 63[5] 62[5] 56[5] 55[5] 53[5] 48[5] 47[5]
G12[5] H13[5] H12[5] J10[5] K13[5] M13[5] N13[5] M12[5] N12[5] M10[5] N10[5] K9[5] L9[5] M9[5] K7[5] L7[5] M7[5] N5[5] M5[5]
LPC2210_2220_6
B.V. 2008. rights reserved.
Product data sheet
Rev. December 2008
Semiconductors
LPC2210/2220
16/32-bit microcontrollers
Table Symbol P3.19/A19 P3.20/A20 P3.21/A21 P3.22/A22 P3.23/A23/ XCLK P3.24/CS3 P3.25/CS2 P3.26/CS1 P3.27/WE
description .continued (LQFP) 46[5] 45[5] 44[5] 41[5] 40[5] 36[5] 35[5] 30[5] 29[5] 28[2] (TFBGA) Type L5[5] K5[5] N4[5] K4[5] N3[5] M2[5] M1[5] K2[5] K1[5] J4[2] 27[4] J3[4] 97[4] 96[4] 22[5] 135[6] E13[4] F10[4] H2[5] C5[6] Description External memory address line External memory address line External memory address line External memory address line External memory address line XCLK Clock output. LOW-active Chip Select signal. (Bank addresses range 0x8300 0000 0x83FF FFFF) LOW-active Chip Select signal. (Bank addresses range 0x8200 0000 0x82FF FFFF) LOW-active Chip Select signal. (Bank addresses range 0x8100 0000 0x81FF FFFF) LOW-active Write enable signal. BLS3 LOW-active Byte Lane Select signal (Bank AIN7 ADC, input This analog input always connected pin. BLS2 LOW-active Byte Lane Select signal (Bank AIN6 ADC, input This analog input always connected pin. BLS1 LOW-active Byte Lane Select signal (Bank BLS0 LOW-active Byte Lane Select signal (Bank connected. This MUST pulled device might operate properly. External reset input: this resets device, causing ports peripherals take their default states, processor execution begin address with hysteresis, tolerant. Input oscillator circuit internal clock generator circuits. Output from oscillator amplifier. Ground: reference.
P3.28/BLS3/ AIN7 P3.29/BLS2/ AIN6 P3.30/BLS1 P3.31/BLS0 n.c. RESET
XTAL1 XTAL2
142[7] 141[7] 103, 107, 111,
C3[7] B3[7] L10, K12, F13, D11, B13, B11,
VSSA
Analog ground: reference. This should nominally same voltage VSS, should isolated minimize noise error. analog ground: reference. This should nominally same voltage VSS, should isolated minimize noise error. core power supply: This power supply voltage internal circuitry.
VSSA(PLL)
VDD(1V8)
LPC2210_2220_6
B.V. 2008. rights reserved.
Product data sheet
Rev. December 2008
Semiconductors
LPC2210/2220
16/32-bit microcontrollers
Table Symbol VDDA(1V8)
description .continued (LQFP) (TFBGA) Type Description Analog core power supply: This power supply voltage internal circuitry. This should nominally same voltage VDD(1V8) should isolated minimize noise error. power supply: This power supply voltage ports.
VDD(3V3)
K10, 104, 112, F12, C13, A11,
VDDA(3V3)
Analog power supply: This should nominally same voltage VDD(3V3) should isolated minimize noise error.
tolerant providing digital functions with levels hysteresis slew rate control. tolerant providing digital functions with levels hysteresis slew rate control. configured input function, this utilizes built-in glitch filter that blocks pulses shorter than Open drain tolerant digital I2C-bus specification compatible pad. requires external pull-up provide output functionality. tolerant providing digital (with levels hysteresis slew rate control) analog input function. configured digital input function, this utilizes built-in glitch filter that blocks pulses shorter than When configured input, digital section disabled. tolerant with built-in pull-up resistor providing digital functions with levels hysteresis slew rate control. pull-up resistor's value ranges from tolerant providing digital input (with levels hysteresis) function only. provides special analog functionality.
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Functional description
Architectural overview
ARM7TDMI-S general purpose 32-bit microprocessor, which offers high performance very power consumption. architecture based RISC principles, instruction related decode mechanism much simpler than those microprogrammed CISC. This simplicity results high instruction throughput impressive real-time interrupt response from small cost-effective processor core. Pipeline techniques employed that parts processing memory systems operate continuously. Typically, while instruction being executed, successor being decoded, third instruction being fetched from memory. ARM7TDMI-S processor also employs unique architectural strategy known Thumb, which makes ideally suited high-volume applications with memory restrictions, applications where code density issue. idea behind Thumb that super-reduced instruction set. Essentially, ARM7TDMI-S processor instruction sets:
standard 32-bit set. 16-bit Thumb set.
Thumb set's 16-bit instruction length allows approach twice density standard code while retaining most ARM's performance advantage over traditional 16-bit processor using 16-bit registers. This possible because Thumb code operates same 32-bit register code. Thumb code able provide code size ARM, performance equivalent processor connected 16-bit memory system.
On-chip SRAM
On-chip SRAM used code and/or data storage. SRAM accessed 8-bit, 16-bit, 32-bit. LPC2210 LPC2210/01 provide static RAM, LPC2220 provides static RAM.
Memory
LPC2210/2220 memory maps incorporate several distinct regions, shown Figure addition, interrupt vectors re-mapped allow them reside either on-chip bootloader, external memory BANK0 on-chip static RAM. This described Section 6.20 "System control".
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PERIPHERALS 3.75 PERIPHERALS
0xFFFF FFFF 0xF000 0000 0xEFFF FFFF 0xE000 0000 0xDFFF FFFF RESERVED ADDRESS SPACE
EXTERNAL MEMORY BANK EXTERNAL MEMORY BANK EXTERNAL MEMORY BANK EXTERNAL MEMORY BANK BOOT BLOCK (RE-MAPPED FROM ON-CHIP MEMORY) RESERVED ADDRESS SPACE
0x8400 0000 0x83FF FFFF 0x8300 0000 0x82FF FFFF 0x8200 0000 0x81FF FFFF 0x8100 0000 0x80FF FFFF 0x8000 0000 0x7FFF FFFF 0x7FFF E000 0x7FFF DFFF
ON-CHIP STATIC (LPC2220) ON-CHIP STATIC (LPC2210)
0x4001 0000 0x4000 FFFF 0x4000 4000 0x4000 3FFF 0x4000 0000 0x3FFF FFFF
RESERVED ADDRESS SPACE
0x0000 0000
002aaa795
LPC2210/2220 memory
Interrupt controller
accepts interrupt request inputs categorizes them Fast Interrupt Request (FIQ), vectored Interrupt Request (IRQ), non-vectored defined programmable settings. programmable assignment scheme means that priorities interrupts from various peripherals dynamically assigned adjusted. highest priority. more than request assigned FIQ, combines requests produce signal processor. fastest possible latency achieved when only request classified FIQ, because then service routine simply start dealing with that device. more than request assigned class, service routine read word from that identifies which source(s) (are) requesting interrupt. Vectored IRQs have middle priority. Sixteen interrupt requests assigned this category. interrupt requests assigned vectored slots, among which slot highest priority slot lowest.
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Non-vectored IRQs have lowest priority. combines requests from vectored non-vectored IRQs produce signal processor. service routine start reading register from jumping there. vectored IRQs requesting, provides address highest-priority requesting IRQs service routine, otherwise provides address default routine that shared non-vectored IRQs. default routine read another register what IRQs active.
6.4.1 Interrupt sources
Table lists interrupt sources each peripheral function. Each peripheral device interrupt line connected VIC, have several internal interrupt flags. Individual interrupt flags also represent more than interrupt source.
Table Block Core Core TIMER0 TIMER1 UART0 Interrupt sources Flag(s) Watchdog Interrupt (WDINT) Reserved software interrupts only EmbeddedICE, DbgCommRX EmbeddedICE, DbgCommTX Match (MR0, MR1, MR2, MR3) Match (MR0, MR1, MR2, MR3) Line Status (RLS) Transmit Holding Register Empty (THRE) Data Available (RDA) Character Time-out Indicator (CTI) UART1 Line Status (RLS) Transmit Holding Register empty (THRE) Data Available (RDA) Character Time-out Indicator (CTI) Modem Status Interrupt (MSI) PWM0 SPI0 SPI1 System Control Match (MR0, MR1, MR2, MR3, MR4, MR5, MR6) (state change) SPIF, MODF SPIF, MODF TXRIS, RXRIS, RTRIS, RORRIS Lock (PLOCK) RTCCIF (Counter Increment), RTCALF (Alarm) External Interrupt (EINT0) External Interrupt (EINT1) External Interrupt (EINT2) External Interrupt (EINT3) channel
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connect block
connect block allows selected pins microcontroller have more than function. Configuration registers control multiplexers allow connection between chip peripherals. Peripherals should connected appropriate pins prior being activated, prior related interrupt(s) being enabled. Activity enabled peripheral function that mapped related should considered undefined. control module contains three registers shown Table
Table Address 0xE002 C000 0xE002 C004 0xE002 C014 control module registers Name PINSEL0 PINSEL1 PINSEL2 Description function select register function select register function select register Access read/write read/write read/write
function select register (PINSEL0 0xE002 C000)
PINSEL0 register controls functions pins settings listed Table direction control IODIR register effective only when GPIO function selected pin. other functions, direction controlled automatically. Settings other than those shown Table reserved, should used
Table PINSEL0 function select register (PINSEL0 0xE002 C000) name P0.0 Value P0.1 P0.2 P0.3 P0.4 Function GPIO Port TXD0 (UART0) PWM1 reserved GPIO Port RXD0 (UART0) PWM3 EINT0 GPIO Port (I2C-bus) Capture (Timer reserved GPIO Port (I2C-bus) Match (Timer EINT1 GPIO Port (SPI0) Capture (Timer reserved Value after reset
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function select register (PINSEL0 0xE002 C000) .continued name P0.5 Value Function GPIO Port MISO (SPI0) Match (Timer reserved GPIO Port MOSI (SPI0) Capture (Timer reserved GPIO Port SSEL (SPI0) PWM2 EINT2 GPIO Port TXD1 UART1 PWM4 reserved GPIO Port RXD1 (UART1) PWM6 EINT3 GPIO Port 0.10 RTS1 (UART1) Capture (Timer reserved GPIO Port 0.11 CTS1 (UART1) Capture (Timer reserved GPIO Port 0.12 DSR1 (UART1) Match (Timer reserved GPIO Port 0.13 DTR1 (UART1) Match (Timer reserved GPIO Port 0.14 DCD1 (UART1) EINT1 reserved Value after reset
Table PINSEL0 11:10
13:12
P0.6
15:14
P0.7
17:16
P0.8
19:18
P0.9
21:20
P0.10
23:22
P0.11
25:24
P0.12
27:26
P0.13
29:28
P0.14
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function select register (PINSEL0 0xE002 C000) .continued name P0.15 Value Function GPIO Port 0.15 (UART1) EINT2 reserved Value after reset
Table PINSEL0 31:30
function select register (PINSEL1 0xE002 C004)
PINSEL1 register controls functions pins settings listed Table direction control IODIR register effective only when GPIO function selected pin. other functions direction controlled automatically. Settings other than those shown Table reserved, should used.
Table PINSEL1 function select register (PINSEL1 0xE002 C004) name P0.16 Value P0.17 P0.18 P0.19 P0.20 11:10 P0.21 13:12 P0.22 Function GPIO Port 0.16 EINT0 Match (Timer Capture (Timer GPIO Port 0.17 Capture (Timer (SPI1) Match (Timer GPIO Port 0.18 Capture (Timer MISO (SPI1) Match (Timer GPIO Port 0.19 Match (Timer MOSI (SPI1) Capture (Timer GPIO Port 0.20 Match (Timer SSEL (SPI1) EINT3 GPIO Port 0.21 PWM5 reserved Capture (Timer GPIO Port 0.22 reserved Capture (Timer Match (Timer Value after reset
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function select register (PINSEL1 0xE002 C004) .continued name P0.23 Value Function GPIO Port 0.23 reserved reserved reserved GPIO Port 0.24 reserved reserved reserved GPIO Port 0.25 reserved reserved reserved reserved reserved reserved reserved GPIO Port 0.27 AIN0 (A/D input Capture (Timer Match (Timer GPIO Port 0.28 AIN1 (A/D input Capture (Timer Match (Timer GPIO Port 0.29 AIN2 (A/D input Capture (Timer Match (Timer GPIO Port 0.30 AIN3 (A/D input EINT3 Capture (Timer reserved reserved reserved reserved Value after reset
Table PINSEL1 15:14
17:16
P0.24
19:18
P0.25
21:20
P0.26
23:22
P0.27
25:24
P0.28
27:26
P0.29
29:28
P0.30
31:30
P0.31
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function select register (PINSEL2 0xE002 C014)
PINSEL2 register controls functions pins settings listed Table direction control IODIR register effective only when GPIO function selected pin. other functions direction controlled automatically. Settings other than those shown Table reserved, should used.
Table function select register (PINSEL2 0xE002 C014) Description reserved When pins P1[36:26] used GPIO pins. When P1[31:26] used Debug port. When pins P1[25:16] used GPIO pins. When P1[25:16] used Trace port. Controls data strobe pins: Pins P2[7:0] P1.0 P1.1 P3.31 Pins P2[15:8] P3.30 Pins P2[27:16] Pins P2[29:28] Pins P2[31:30] Pins P3[29:28] 10:9 15:14 17:16 19:18 P2[7:0] P1.0 P1.1 P3.31 P2[15:8] P3.30 P2[27:16] P2[29:28] P2[31:30] AIN5 AIN4 P3[29:28] AIN7 AIN6 BLS0 BLS1 D29, D31, BLS2, BLS3 Reset value P1.26/RTCK P1.20/ TRACESYNC BOOT1:0
PINSEL2 bits
bits controls P3.29: enables P3.29, enables AIN6. bits controls P3.28: enables P3.28, enables AIN7. Controls P3.27: enables P3.27, enables reserved Controls P3.26: enables P3.26, enables CS1. reserved
bits 27:25 111, controls P3.23/A23/XCLK: enables P3.23, enables XCLK. Controls P3.25: enables P3.25, enables CS2, reserved values. Controls P3.24: enables P3.24, enables CS3, reserved values. reserved bits controls P2[29:28]: enables P2[29:28], reserved bits controls P2.30: enables P2.30, enables AIN4. bits controls P2.31: enables P2.31, enables AIN5.
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Table
function select register (PINSEL2 0xE002 C014) .continued Description Controls whether P3.0/A0 port address line (1). Reset value BOOT1:0 RESET otherwise BOOT1 during reset BOOT1:0 reset, otherwise
PINSEL2 bits
27:25
Controls whether P3.1/A1 port address line (1). Controls number pins among P3.23/A23/XCLK P3[22:2]/A2[22:2] that address lines: None address lines. address lines. address lines. address lines. address lines. address lines. address lines.
31:28
reserved
External memory controller
external static memory controller module which provides interface between system external (off-chip) memory devices. provides support four independently configurable memory banks each with byte lane enable control) simultaneously. Each memory bank capable supporting SRAM, ROM, flash EPROM, burst memory, some external devices. Each memory bank 8-bit, 16-bit, 32-bit wide.
6.10 General purpose parallel
Device pins that connected specific peripheral function controlled GPIO registers. Pins dynamically configured inputs outputs. Separate registers allow setting clearing number outputs simultaneously. value output register read back, well current state port pins.
6.10.1 Features
Direction control individual bits. Separate control output clear. default inputs after reset. 6.11 10-bit
LPC2210/2220 each contain single 10-bit successive approximation with eight multiplexed channels.
6.11.1 Features
Measurement range Capable performing more than 400000 10-bit samples second. Burst conversion mode single multiple inputs.
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Optional conversion transition input Timer Match signal.
6.11.2 features available LPC2210/01 LPC2220 only
Every analog input dedicated result register reduce interrupt overhead. Every analog input generate interrupt once conversion completed. pads tolerant when configured digital function(s). 6.12 UARTs
LPC2210/2220 each contain UARTs. UART provides full modem control handshake interface, other provides only transmit receive data lines.
6.12.1 Features
receive transmit FIFOs. Register locations conform 16C550 industry standard. Receiver FIFO trigger points Built-in baud rate generator. Standard modem interface signals included UART1.
6.12.2 UART features available LPC2210/01 LPC2220 only
Compared previous LPC2000 microcontrollers, UARTs LPC2210/01 LPC2220 introduce fractional baud rate generator both UARTs, enabling these microcontrollers achieve standard baud rates such 115200 with crystal frequency above MHz. addition, auto-CTS/RTS flow-control functions fully implemented hardware.
Fractional baud rate generator enables standard baud rates such 115200
achieved with crystal frequency above MHz.
Auto-bauding. Auto-CTS/RTS flow-control fully implemented hardware. 6.13 I2C-bus serial controller
I2C-bus bidirectional inter-IC control using only wires: serial clock line (SCL), serial data line (SDA). Each device recognized unique address operate either receiver-only device (e.g., driver transmitter with capability both receive send information (such memory). Transmitters and/or receivers operate either master slave mode, depending whether chip initiate data transfer only addressed. I2C-bus multi-master bus, controlled more than master connected I2C-bus implemented LPC2210/2220 supports rate kbit/s (fast I2C-bus).
6.13.1 Features
Compliant with standard I2C-bus interface. Easy configure master, slave, master/slave.
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Programmable clocks allow versatile rate control. Bidirectional data transfer between masters slaves. Multi-master central master). Arbitration between simultaneously transmitting masters without corruption serial data bus. serial bus.
Serial clock synchronization allows devices with different rates communicate Serial clock synchronization used handshake mechanism suspend
resume serial transfer.
I2C-bus used test diagnostic purposes. 6.14 serial controller
LPC2210/2220 each contain SPIs. full duplex serial interface, designed able handle multiple masters slaves connected given bus. Only single master single slave communicate interface during given data transfer. During data transfer master always sends byte data slave, slave always sends byte data master.
6.14.1 Features
Compliant with specification. Synchronous, serial, full duplex, communication. Combined master slave. Maximum data rate eighth input clock rate.
6.15 controller
This peripheral available LPC2210/01 LPC2220 only.
6.15.1 Features
Compatible with Motorola's SPI, Texas Instrument's 4-wire SSI, National
Semiconductor's Microwire buses.
Synchronous serial communication. Master slave operation. 8-frame FIFOs both transmit receive. bits bits frame.
6.15.2 Description
controller capable operation SPI, 4-wire SSI, Microwire bus. interact with multiple masters slaves bus. Only single master single slave communicate during given data transfer. Data transfers principle full duplex, with frames bits bits data flowing from master slave from slave master.
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While SPI1 peripherals share same physical pins, possible have both these peripherals active same time. Application switch from SPI1 back.
6.16 General purpose timers
timer/counter designed count cycles peripheral clock (PCLK) externally supplied clock optionally generate interrupts perform other actions specified timer values, based four match registers. also includes four capture inputs trap timer value when input signal transitions, optionally generating interrupt. Multiple pins selected perform single capture match function, providing application with `or' `and', well `broadcast' functions among them.
6.16.1 Features
32-bit timer/counter with programmable 32-bit prescaler. Timer operation (LPC2210/2220) external event counter (LPC2210/01
LPC2220 only).
Four 32-bit capture channels timer/counter that take snapshot timer
value when input signal transitions. capture event also optionally generate interrupt.
Four 32-bit match registers that allow:
Continuous operation with optional interrupt generation match. Stop timer match with optional interrupt generation. Reset timer match with optional interrupt generation.
Four external outputs timer/counter corresponding match registers, with
following capabilities: match. HIGH match. Toggle match. nothing match.
6.16.2 Features available LPC2210/01 LPC2220 only
LPC2210/01 LPC2220 count external events capture inputs external pulse lasts least half period PCLK. this configuration, unused capture lines selected regular timer capture inputs used external interrupts.
Timer count cycles either peripheral clock (PCLK) externally supplied
clock.
When counting cycles externally supplied clock, only timer's capture
inputs selected timer's clock. rate such clock limited PCLK Duration high/low levels selected capture input cannot shorter than (2PCLK).
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6.17 Watchdog timer
purpose watchdog reset microcontroller within reasonable amount time enters erroneous state. When enabled, watchdog will generate system reset user program fails `feed' reload) watchdog within predetermined amount time.
6.17.1 Features
Internally resets chip periodically reloaded. Debug mode. Enabled software requires hardware reset watchdog reset/interrupt
disabled.
Incorrect/incomplete feed sequence causes reset/interrupt enabled. Flag indicate watchdog reset. Programmable 32-bit timer with internal prescaler. Selectable time period from (Tcy(PCLK) (Tcy(PCLK) multiples Tcy(PCLK)
6.18 Real-time clock
Real-Time Clock (RTC) designed provide counters measure time when normal idle operating mode selected. been designed little power, making suitable battery powered systems where running continuously (Idle mode).
6.18.1 Features
Measures passage time maintain calendar clock. Ultra-low power design support battery powered systems. Provides Seconds, Minutes, Hours, Month, Month, Year, Week,
Year.
Programmable reference clock divider allows adjustment match various
crystal frequencies.
6.19 Pulse width modulator
based standard timer block inherits features, although only function pinned LPC2210/2220. timer designed count cycles peripheral clock (PCLK) optionally generate interrupts perform other actions when specified timer values occur, based seven match registers. function also based match register events. ability separately control rising falling edge locations allows used more applications. instance, multi-phase motor control typically requires three non-overlapping outputs with individual control three pulse widths positions. match registers used provide single edge controlled output. match register (MR0) controls cycle rate, resetting count upon match. other match register controls edge position. Additional single edge
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controlled outputs require only match register each, since repetition rate same outputs. Multiple single edge controlled outputs will have rising edge beginning each cycle, when match occurs. Three match registers used provide output with both edges controlled. Again, match register controls cycle rate. other match registers control edge positions. Additional double edge controlled outputs require only match registers each, since repetition rate same outputs. With double edge controlled outputs, specific match registers control rising falling edge output. This allows both positive going pulses (when rising edge occurs prior falling edge), negative going pulses (when falling edge occurs prior rising edge).
6.19.1 Features
Seven match registers allow single edge controlled three double edge
controlled outputs, both types.
match registers also allow:
Continuous operation with optional interrupt generation match. Stop timer match with optional interrupt generation. Reset timer match with optional interrupt generation.
Supports single edge controlled and/or double edge controlled outputs. Single
edge controlled outputs HIGH beginning each cycle unless output constant LOW. Double edge controlled outputs have either edge occur position within cycle. This allows both positive going negative going pulses.
Pulse period width number timer counts. This allows complete
flexibility trade-off between resolution repetition rate. outputs will occur same repetition rate.
Double edge controlled outputs programmed either positive going
negative going pulses.
Match register updates synchronized with pulse outputs prevent generation
erroneous pulses. Software must `release' match values before they become effective.
used standard timer mode enabled. 32-bit timer/counter with programmable 32-bit prescaler. 6.20 System control
6.20.1 Crystal oscillator
oscillator supports crystals range with external oscillator. oscillator output frequency called fosc processor clock frequency referred CCLK purposes rate equations, etc. fosc CCLK same value unless running connected. Refer Section 6.20.2 "PLL" additional information.
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6.20.2
accepts input clock frequency range MHz. input frequency multiplied into range (LPC2210) (LPC2210/01 LPC2220) with Current Controlled Oscillator (CCO). multiplier integer value from practice, multiplier value cannot higher than this family microcontrollers upper frequency limit CPU). operates range MHz, there additional divider loop keep within frequency range while providing desired output frequency. output divider divide produce output clock. Since minimum output divider value insured that output duty cycle. turned bypassed following chip reset enabled software. program must configure activate PLL, wait Lock, then connect clock source. settling time
6.20.3 Reset wake-up timer
Reset sources LPC2210/2220: RESET watchdog reset. RESET Schmitt trigger input with additional glitch filter. Assertion chip reset source starts wake-up timer (see wake-up timer description below), causing internal chip reset remain asserted until external reset de-asserted, oscillator running, fixed number clocks have passed, on-chip circuitry completed initialization. When internal reset removed, processor begins executing address which reset vector. that point, processor peripheral registers have been initialized predetermined values. wake-up timer ensures that oscillator other analog functions required chip operation fully functional before processor allowed execute instructions. This important power-on, types reset, whenever aforementioned functions turned reason. Since oscillator other functions turned during Power-down mode, wake-up processor from Power-down mode makes wake-up timer. wake-up timer monitors crystal oscillator means checking whether safe begin code execution. When power applied chip, some event caused chip exit Power-down mode, some time required oscillator produce signal sufficient amplitude drive clock logic. amount time depends many factors, including rate ramp case power on), type crystal electrical characteristics quartz crystal used), well other external circuitry (e.g. capacitors), characteristics oscillator itself under existing ambient conditions.
6.20.4 External interrupt inputs
LPC2210/2220 include nine edge level sensitive external interrupt inputs selectable functions. When pins combined, external events processed four independent interrupt signals. external interrupt inputs optionally used wake processor from Power-down mode.
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6.20.5 Memory mapping control
memory mapping control alters mapping interrupt vectors that appear beginning address 0x0000 0000. Vectors mapped bottom BANK0 external memory, on-chip static RAM. This allows code running different memory spaces have control interrupts.
6.20.6 Power control
LPC2210/2220 support reduced power modes: Idle mode Power-down mode. Idle mode, execution instructions suspended until either reset interrupt occurs. Peripheral functions continue operation during Idle mode generate interrupts cause processor resume execution. Idle mode eliminates power used processor itself, memory systems related controllers, internal buses. Power-down mode, oscillator shut down, chip receives internal clocks. processor state registers, peripheral registers, internal SRAM values preserved throughout Power-down mode, logic levels chip output pins remain static. Power-down mode terminated normal operation resumed either reset certain specific interrupts that able function without clocks. Since dynamic operation chip suspended, Power-down mode reduces chip power consumption nearly zero. power control peripherals feature allows individual peripherals turned they needed application, resulting additional power savings.
6.20.7
divider determines relationship between processor clock (CCLK) clock used peripheral devices (PCLK). divider serves purposes. first provide peripherals with desired PCLK that they operate speed chosen processor. order achieve this, slowed down processor clock rate. Because must work properly power-up (and timing cannot altered does work since divider control registers reside APB), default condition reset processor clock rate. second purpose divider allow power savings when application does require peripherals full processor rate. Because divider connected output, remains active running) during Idle mode.
6.21 Emulation debugging
LPC2210/2220 support emulation debugging JTAG serial port. trace port allows tracing program execution. Debugging trace functions multiplexed only with GPIOs Port This means that communication, timer interface peripherals residing Port available during development debugging phase they when application embedded system itself.
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6.21.1 EmbeddedICE
Standard EmbeddedICE logic provides on-chip debug support. debugging target system requires host computer running debugger software EmbeddedICE protocol converter. EmbeddedICE protocol converter converts remote debug protocol commands JTAG data needed access core. core Debug Communication Channel (DCC) function built-in. debug communication channel allows program running target communicate with host debugger another separate host without stopping program flow even entering debug state. debug communication channel accessed co-processor program running ARM7TDMI-S core. debug communication channel allows JTAG port used sending receiving data without affecting normal program flow. debug communication channel data control registers mapped addresses EmbeddedICE logic. JTAG clock (TCK) must slower than clock (CCLK) JTAG interface operate.
6.21.2 Embedded trace
Since LPC2210/2220 have significant amounts on-chip memory, possible determine processor core operating simply observing external pins. Embedded Trace Macrocell (ETM) provides real-time trace capability deeply embedded processor cores. outputs information about processor execution trace port. connected directly core main AMBA system bus. compresses trace information exports through narrow trace port. external trace port analyzer must capture trace information under software debugger control. Instruction trace trace) shows flow execution processor provides list instructions that were executed. Instruction trace significantly compressed only broadcasting branch addresses well status signals that indicate pipeline status cycle cycle basis. Trace information generation controlled selecting trigger resource. Trigger resources include address comparators, counters sequencers. Since trace information compressed software debugger requires static image code being executed. Self-modifying code cannot traced because this restriction.
6.21.3 RealMonitor
RealMonitor configurable software module, developed Inc., which enables real-time debug. lightweight debug monitor that runs background while users debug their foreground application. communicates with host using debug communication channel, which present EmbeddedICE logic. LPC2210/2220 contain specific configuration RealMonitor software programmed into on-chip flash memory.
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Limiting values
Table Limiting values reset accordance with Absolute Maximum Rating System (IEC 60134).[1] Symbol VDD(1V8) VDD(3V3) VDDA(3V3) Tstg Ptot(pack) Parameter supply voltage (1.8 supply voltage (3.3 analog supply voltage (3.3 analog input voltage input voltage supply current ground current storage temperature total power dissipation (per package) electrostatic discharge voltage based package heat transfer, device power consumption human body model pins
[11]
Conditions
-0.5 -0.5 -0.5 -0.5
+2.5 +3.6 +4.6 +5.1 +6.0 VDD(3V3) +150
Unit
tolerant pins other pins
[4][5] [4][6] [7][8] [8][9] [10]
-0.5 -0.5
Vesd
-2000
+2000
following applies Table This product includes circuitry specifically designed protection internal devices from damaging effects excessive static charge. Nonetheless, suggested that conventional precautions taken avoid applying greater than rated maximum. Parameters valid over operating temperature range unless otherwise specified. voltages with respect unless otherwise noted. Internal rail. External rail. Including voltage outputs 3-state mode. Only valid when VDD(3V3) supply voltage present. exceed supply pin. peak current limited times corresponding maximum current. ground pin.
[10] Dependent package type. [11] Human body model: equivalent discharging capacitor through series resistor.
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Static characteristics
Table Static characteristics Tamb commercial applications, unless otherwise specified. Symbol VDD(1V8) VDD(3V3) Parameter supply voltage (1.8 supply voltage (3.3 Conditions
1.65
Typ[1]
1.95
Unit
VDDA(3V3) analog supply voltage (3.3 Standard port pins, RESET, RTCK Ilatch Vhys IOHS IOLS IDD(act) LOW-level input current HIGH-level input current OFF-state output current latch-up current input voltage output voltage HIGH-level input voltage LOW-level input voltage hysteresis voltage HIGH-level output voltage LOW-level output voltage HIGH-level output current LOW-level output current HIGH-level short circuit output current LOW-level short circuit output current pull-down current pull-up current active mode supply current VDD(3V3) VDD(3V3) VDD(3V3) VDD(1V8) Tamb code
pull-up VDD(3V3); pull-down VDD(3V3); pull-up/down -(0.5VDD(3V3)) (1.5VDD(3V3));
[4][5][6]
VDD(3V3)
VDD(3V3)
output active
[10]
while(1){}
executed from on-chip RAM; active peripherals CCLK (LPC2210) CCLK (LPC2210/01; LPC2220)
LPC2210_2220_6
B.V. 2008. rights reserved.
Product data sheet
Rev. December 2008
Semiconductors
LPC2210/2220
16/32-bit microcontrollers
Table Static characteristics .continued Tamb commercial applications, unless otherwise specified. Symbol IDD(pd) Parameter Power-down mode supply current Conditions VDD(1V8) Tamb VDD(1V8) Tamb I2C-bus pins Vhys HIGH-level input voltage LOW-level input voltage hysteresis voltage LOW-level output voltage input leakage current IOLS VDD(3V3) Oscillator pins Vi(XTAL1) Vo(XTAL2)
[11]
Typ[1]
Unit
0.7VDD(3V3)
0.3VDD(3V3)
0.5VDD(3V3)
input voltage XTAL1 output voltage XTAL2
Typical ratings guaranteed. values listed room temperature (+25 °C), nominal supply voltages. Internal rail. External rail. Including voltage outputs 3-state mode. VDD(3V3) supply voltages must present. 3-state outputs into 3-state mode when VDD(3V3) grounded. Accounts voltage drop supply lines. Allowed long current limit does exceed maximum current allowed device. Minimum condition maximum condition
[10] Applies P1[25:16]. [11] VSS.
LPC2210_2220_6
B.V. 2008. rights reserved.
Product data sheet
Rev. December 2008
Semiconductors
LPC2210/2220
16/32-bit microcontrollers
Table static characteristics VDDA(3V3) Tamb unless otherwise specified. frequency MHz. Symbol EL(adj)
Parameter analog input voltage analog input capacitance differential linearity error integral non-linearity offset error gain error absolute error
Conditions
[1][2][3] [1][4] [1][5] [1][6] [1][7]
VDDA(3V3) ±0.5
Unit
Conditions: VSSA VDDA(3V3) monotonic, there missing codes. differential linearity error (ED) difference between actual step width ideal step width. Figure integral non-linearity (EL(adj)) peak difference between center steps actual ideal transfer curve after appropriate adjustment gain offset errors. Figure offset error (EO) absolute difference between straight line which fits actual curve straight line which fits ideal curve. Figure gain error (EG) relative difference percent between straight line fitting actual transfer curve after removing offset error, straight line which fits ideal transfer curve. Figure absolute voltage error (ET) maximum difference between center steps actual transfer curve non-calibrated ideal transfer curve. Figure
LPC2210_2220_6
B.V. 2008. rights reserved.
Product data sheet
Rev. December 2008
Semiconductors
LPC2210/2220
16/32-bit microcontrollers
offset error 1023
gain error
1022
1021
1020
1019
1018
code
(ideal) 1018 1019 1020 1021 1022 1023 1024
(LSBideal) offset error
VDDA VSSA 1024
002aaa668
Example actual transfer curve. ideal transfer curve. Differential linearity error (ED). Integral non-linearity (EL(adj)). Center step actual transfer curve.
characteristics
LPC2210_2220_6
B.V. 2008. rights reserved.
Product data sheet
Rev. December 2008
Semiconductors
LPC2210/2220
16/32-bit microcontrollers
Dynamic characteristics
Table Dynamic characteristics Tamb commercial applications, industrial applications, VDD(1V8), VDD(3V3) over specified ranges.[1] Symbol External clock fosc oscillator frequency supplied external oscillator (signal generator) external clock frequency supplied external crystal oscillator external clock frequency on-chip used external clock frequency on-chip bootloader used initial code download Tcy(clk) tCHCX tCLCX tCLCH tCHCL I2C-bus
Parameter
Conditions
Unit
clock cycle time clock HIGH time clock time clock rise time clock fall time rise time fall time pins (P0.2 P0.3) fall time
Tcy(clk) Tcy(clk)
1000
Port pins (except P0.2 P0.3)
Parameters valid over operating temperature range unless otherwise specified. capacitance from
LPC2210_2220_6
B.V. 2008. rights reserved.
Product data sheet
Rev. December 2008
Semiconductors
LPC2210/2220
16/32-bit microcontrollers
Table External memory interface dynamic characteristics Tamb Symbol tCHAV tCHCSL tCHCSH tCHANV Parameter XCLK HIGH address valid time XCLK HIGH time XCLK HIGH HIGH time XCLK HIGH address invalid time address valid time address valid time time memory access time memory access time (initial burst-ROM) memory access time (subsequent burst-ROM) data hold time HIGH HIGH time HIGH address invalid time XCLK HIGH time XCLK HIGH HIGH time address valid time data valid time time time data valid time data valid time HIGH time HIGH time HIGH address invalid time HIGH data invalid time HIGH address invalid time
[2][4] [2][3]
Conditions
Unit
Common read write cycles
Read cycle parameters tCSLAV tOELAV tCSLOEL tam(ibr) tam(sbr) th(D) tCSHOEH tOEHANV tCHOEL tCHOEH (Tcy(CCLK) WST1)) (-20) (Tcy(CCLK) WST1)) (-20) Tcy(CCLK) (-20)
[2][3] [2][5]
Write cycle parameters tAVCSL tCSLDV tCSLWEL tCSLBLSL tWELDV tCSLDV tWELWEH tBLSLBLSH tWEHANV tWEHDNV tBLSHANV Tcy(CCLK) Tcy(CCLK) WST2) Tcy(CCLK) WST2) Tcy(CCLK) Tcy(CCLK)) Tcy(CCLK) Tcy(CCLK) WST2) Tcy(CCLK) WST2) Tcy(CCLK)
[2][4]
Tcy(CCLK)) Tcy(CCLK)
LPC2210_2220_6
B.V. 2008. rights reserved.
Product data sheet
Rev. December 2008
Semiconductors
LPC2210/2220
16/32-bit microcontrollers
Table External memory interface dynamic characteristics .continued Tamb Symbol tBLSHDNV tCHDV tCHWEL tCHBLSL tCHWEH tCHBLSH tCHDNV Parameter HIGH data invalid time XCLK HIGH data valid time XCLK HIGH time XCLK HIGH time XCLK HIGH HIGH time XCLK HIGH HIGH time XCLK HIGH data invalid time Conditions
Tcy(CCLK))
Unit
Tcy(CCLK))
Except initial access, which case address Tcy(CCLK) earlier. Tcy(CCLK) 1/CCLK. Latest address valid, LOW, data valid. LPC2210/20 user manual UM10114_1 description WSTn bits. Address valid data valid. Earliest HIGH, HIGH, address change data invalid.
Table
Standard read access specifications frequency setting round integer Memory access time requirement
Access cycle
standard read
WRITE INIT
CCLK WRITE CCLK INIT CCLK
CCLK WRITE CCLK INIT CCLK CCLK
standard write
burst read initial
burst read subsequent
LPC2210_2220_6
B.V. 2008. rights reserved.
Product data sheet
Rev. December 2008
Semiconductors
LPC2210/2220
16/32-bit microcontrollers
Timing
XCLK tCSLAV tCSHOEH
addr data tCSLOEL tOELAV tCHOEL tCHOEH
002aaa749
th(D)
tOEHANV
External memory read access
XCLK tCSLDV
tAVCSL tWELWEH tBLSLBLSH tWEHANV tCSLBLSL tWELDV tBLSHANV
tCSLWEL BLS/WE
addr tCSLDV data tWEHDNV tBLSHDNV
002aaa750
External memory write access
LPC2210_2220_6
B.V. 2008. rights reserved.
Product data sheet
Rev. December 2008
Semiconductors
LPC2210/2220
16/32-bit microcontrollers
tCHCL
tCLCX Tcy(clk)
tCHCX tCLCH
002aaa907
External clock timing (with amplitude least Vi(RMS)
LPC2210 power consumption measurements
current (mA)
002aab452
frequency (MHz)
Test conditions: code executed from on-chip RAM; peripherals enabled PCONP register; PCLK CCLK/4. core (typical) 1.65 core (typical)
LPC2210 Active mode measured different frequencies (CCLK) temperatures
LPC2210_2220_6
B.V. 2008. rights reserved.
Product data sheet
Rev. December 2008
Semiconductors
LPC2210/2220
16/32-bit microcontrollers
current (mA)
002aab453
frequency (MHz)
Test conditions: Idle mode entered executing code from on-chip RAM; peripherals enabled PCONP register; PCLK CCLK/4. core (typical) 1.65 core (typical)
LPC2210 Idle mode measured different frequencies (CCLK) temperatures
current (µA)
002aab454
-100
temp (°C)
Test conditions: Power-down mode entered executing code from on-chip RAM; peripherals enabled PCONP register. 1.95 core core 1.65 core
LPC2210 Power-down mode measured different temperatures
LPC2210_2220_6
B.V. 2008. rights reserved.
Product data sheet
Rev. December 2008
Semiconductors
LPC2210/2220
16/32-bit microcontrollers
LPC2220 LPC2210/01 power consumption measurements
002aad390
(mA)
(1),
frequency (MHz)
Test conditions: code executed from on-chip RAM; peripherals enabled PCONP register; PCLK CCLK/4. core (typical) core (typical) 1.65 core (typical)
LPC2220 LPC2210/01 Active mode measured different frequencies (CCLK) temperatures
(mA)
002aad391
frequency (MHz)
Test conditions: Idle mode entered executing code from on-chip RAM; peripherals enabled PCONP register; PCLK CCLK/4. core (typical) core (typical) 1.65 core (typical)
LPC2220 LPC2210/01 Idle mode measured different frequencies (CCLK) temperatures
LPC2210_2220_6
B.V. 2008. rights reserved.
Product data sheet
Rev. December 2008
Semiconductors
LPC2210/2220
16/32-bit microcontrollers
IDD(pd) (µA)
002aad389
1.65
temperature (°C)
Test conditions: Power-down mode entered executing code from on-chip RAM; peripherals enabled PCONP register.
LPC2220 LPC2210/01 Power-down mode measured different temperatures
LPC2210_2220_6
B.V. 2008. rights reserved.
Product data sheet
Rev. December 2008
Semiconductors
LPC2210/2220
16/32-bit microcontrollers
Package outline
LQFP144: plastic profile quad flat package; leads; body SOT486-1
detail
index
scale
DIMENSIONS original dimensions) UNIT max. 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09 20.1 19.9 20.1 19.9 0.75 0.45 0.08 0.08 D(1) E(1)
22.15 22.15 21.85 21.85
Note Plastic metal protrusions 0.25 maximum side included. OUTLINE VERSION SOT486-1 REFERENCES 136E23 JEDEC MS-026 JEITA EUROPEAN PROJECTION
ISSUE DATE 00-03-14 03-02-20
Package outline SOT486-1 (LQFP144)
LPC2210_2220_6 B.V. 2008. rights reserved.
Product data sheet
Rev. December 2008
Semiconductors
LPC2210/2220
16/32-bit microcontrollers
TFBGA144: plastic thin fine-pitch ball grid array package; balls
SOT569-2
ball index area
detail
ball index area
scale
DIMENSIONS original dimensions) UNIT 1.20 1.05 0.95 0.40 0.35 0.30 0.80 0.70 0.65 0.50 0.45 0.40 12.1 12.0 11.9 12.1 12.0 11.9 0.15 0.05 0.08
OUTLINE VERSION SOT569-2
REFERENCES JEDEC JEITA
EUROPEAN PROJECTION
ISSUE DATE 08-01-29 08-03-14
Package outline SOT569-2 (TFBGA144)
LPC2210_2220_6 B.V. 2008. rights reserved.
Product data sheet
Rev. December 2008
Semiconductors
LPC2210/2220
16/32-bit microcontrollers
Abbreviations
Table Acronym AMBA CISC FIFO GPIO JTAG RISC SRAM UART Acronym list Description Analog-to-Digital Converter Advanced Microcontroller Architecture Advanced Peripheral Complex Instruction Computer First First General Purpose Input/Output Input/Output Joint Test Action Group Pulse Width Modulator Reduced Instruction Computer Serial Peripheral Interface Serial Synchronous Interface Static Random Access Memory Transistor-Transistor Logic Universal Asynchronous Receiver/Transmitter
LPC2210_2220_6
B.V. 2008. rights reserved.
Product data sheet
Rev. December 2008
Semiconductors
LPC2210/2220
16/32-bit microcontrollers
Revision history
Table Revision history Release date 20081211 Data sheet status Product data sheet Change notice Supersedes LPC2210_2220_5 Document LPC2210_2220_6 Modifications:
Figure "External clock timing (with amplitude least Vi(RMS) mV)": removed figure note "VDD updated graphic figure title. Table "Static characteristics": Vhys, moved from column. Table "Static characteristics": modified Table note Maximum frequency fosc external oscillator external crystal updated. Changed SOT569-1 SOT569-2. Added overbar indicate LOW-active BLSn, CSn, Product data sheet LPC2210_2220_4 LPC2210FBD144/01 added. power consumption measurements LPC2220 LPC2210/01 included. Product data sheet Product data sheet Product data sheet Preliminary data LPC2210_2220_3 LPC2210_2220_2 LPC2210-01
LPC2210_2220_5 Modifications: LPC2210_2220_4 LPC2210_2220_3 LPC2210_2220_2 LPC2210-01
20071220
20071002 20070213 20050530 20040209
LPC2210_2220_6
B.V. 2008. rights reserved.
Product data sheet
Rev. December 2008
Semiconductors
LPC2210/2220
16/32-bit microcontrollers
Legal information
13.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
Product status[3] Development Qualification Production
Definition This document contains data from objective specification product development. This document contains data from preliminary specification. This document contains product specification.
Please consult most recently issued document before initiating completing design. term `short data sheet' explained section "Definitions". product status device(s) described this document have changed since this document published differ case multiple devices. latest product status information available Internet http://www.nxp.com.
13.2 Definitions
Draft document draft version only. content still under internal review subject formal approval, which result modifications additions. Semiconductors does give representations warranties accuracy completeness information included herein shall have liability consequences such information. Short data sheet short data sheet extract from full data sheet with same product type number(s) title. short data sheet intended quick reference only should relied upon contain detailed full information. detailed full information relevant full data sheet, which available request local Semiconductors sales office. case inconsistency conflict with short data sheet, full data sheet shall prevail.
result personal injury, death severe property environmental damage. Semiconductors accepts liability inclusion and/or Semiconductors products such equipment applications therefore such inclusion and/or customer's risk. Applications Applications that described herein these products illustrative purposes only. Semiconductors makes representation warranty that such applications will suitable specified without further testing modification. Limiting values Stress above more limiting values defined Absolute Maximum Ratings System 60134) cause permanent damage device. Limiting values stress ratings only operation device these other conditions above those given Characteristics sections this document implied. Exposure limiting values extended periods affect device reliability. Terms conditions sale Semiconductors products sold subject general terms conditions commercial sale, published including those pertaining warranty, intellectual property rights infringement limitation liability, unless explicitly otherwise agreed writing Semiconductors. case inconsistency conflict between information this document such terms conditions, latter will prevail. offer sell license Nothing this document interpreted construed offer sell products that open acceptance grant, conveyance implication license under copyrights, patents other industrial intellectual property rights.
13.3 Disclaimers
General Information this document believed accurate reliable. However, Semiconductors does give representations warranties, expressed implied, accuracy completeness such information shall have liability consequences such information. Right make changes Semiconductors reserves right make changes information published this document, including without limitation specifications product descriptions, time without notice. This document supersedes replaces information supplied prior publication hereof. Suitability Semiconductors products designed, authorized warranted suitable medical, military, aircraft, space life support equipment, applications where failure malfunction Semiconductors product reasonably expected
13.4 Trademarks
Notice: referenced brands, product names, service names trademarks property their respective owners. I2C-bus logo trademark B.V.
Contact information
more information, please visit: http://www.nxp.com sales office addresses, please send email salesaddresses@nxp.com
LPC2210_2220_6
B.V. 2008. rights reserved.
Product data sheet
Rev. December 2008
Semiconductors
LPC2210/2220
16/32-bit microcontrollers
Contents
6.4.1 6.10 6.10.1 6.11 6.11.1 6.11.2 6.12 6.12.1 6.12.2 6.13 6.13.1 6.14 6.14.1 6.15 6.15.1 6.15.2 6.16 6.16.1 6.16.2 6.17 6.17.1 6.18 General description Features features Ordering information Ordering options Block diagram Pinning information Pinning description Functional description Architectural overview. On-chip SRAM Memory map. Interrupt controller Interrupt sources. connect block function select register (PINSEL0 0xE002 C000) function select register (PINSEL1 0xE002 C004) function select register (PINSEL2 0xE002 C014) External memory controller. General purpose parallel I/O. Features 10-bit Features features available LPC2210/01 LPC2220 only UARTs Features UART features available LPC2210/01 LPC2220 only I2C-bus serial controller Features serial controller. Features controller. Features Description General purpose timers Features Features available LPC2210/01 LPC2220 only Watchdog timer. Features Real-time clock 6.18.1 Features 6.19 Pulse width modulator 6.19.1 Features 6.20 System control 6.20.1 Crystal oscillator. 6.20.2 PLL. 6.20.3 Reset wake-up timer 6.20.4 External interrupt inputs 6.20.5 Memory mapping control 6.20.6 Power control 6.20.7 6.21 Emulation debugging. 6.21.1 EmbeddedICE 6.21.2 Embedded trace. 6.21.3 RealMonitor Limiting values Static characteristics Dynamic characteristics Timing LPC2210 power consumption measurements LPC2220 LPC2210/01 power consumption measurements Package outline Abbreviations Revision history Legal information 13.1 Data sheet status 13.2 Definitions 13.3 Disclaimers. 13.4 Trademarks Contact information Contents.
Please aware that important notices concerning this document product(s) described herein, have been included section `Legal information'.
B.V. 2008.
rights reserved.
more information, please visit: http://www.nxp.com sales office addresses, please send email salesaddresses@nxp.com Date release: December 2008 Document identifier: LPC2210_2220_6

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