Single-chip 16/32-bit microcontrollers; 128/256 ISP/IAP flash with 10-

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Single-chip 16/32-bit microcontrollers; 128/256 ISP/IAP flash with 10-

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LPC2114/2124
Single-chip 16/32-bit microcontrollers; 128/256 ISP/IAP flash with 10-bit
Rev. December 2007 Product data sheet
LPC2114/2124 based 16/32-bit ARM7TDMI-S with real-time emulation embedded trace support, together with 128/256 embedded high-speed flash memory. 128-bit wide memory interface unique accelerator architecture enable 32-bit code execution maximum clock rate. critical code size applications, alternative 16-bit Thumb mode reduces code more than with minimal performance penalty. With their compact 64-pin package, power consumption, various 32-bit timers, 4-channel 10-bit ADC, channels fast GPIO lines with nine external interrupt pins these microcontrollers particularly suitable industrial control, medical systems, access control point-of-sale. With wide range serial communications interfaces, they also very well suited communication gateways, protocol converters embedded soft modems well many other general-purpose applications. Remark: Throughout data sheet, term LPC2114/2124 will apply devices with without suffixes. suffix will used differentiate from other devices only when necessary.
Features
features brought LPC2114/2124/01 devices
Fast GPIO ports enable port toggling times faster than original device. They also allow port read time regardless function. Dedicated result registers ADC(s) reduce interrupt overhead. pads tolerant when configured digital function(s). UART0/1 include fractional baud rate generator, auto-bauding capabilities handshake flow-control fully implemented hardware. Buffered serial controller supporting SPI, 4-wire SSI, Microwire formats. programmable data length master mode enhancement. Diversified Code Read Protection (CRP) enables different security levels implemented. This feature available LPC2114/2124/00 devices well. General purpose timers operate external event counters.
features common devices
16/32-bit ARM7TDMI-S microcontroller tiny LQFP64 package. on-chip static RAM.
Semiconductors
LPC2114/2124
Single-chip 16/32-bit microcontrollers
128/256 on-chip flash program memory. 128-bit wide interface/accelerator enables high speed operation. In-System Programming (ISP) In-Application Programming (IAP) on-chip bootloader software. Flash programming takes line. Single sector full chip erase takes EmbeddedICE-RT interface enables breakpoints watch points. Interrupt service routines continue execute whilst foreground task debugged with on-chip RealMonitor software. Embedded Trace Macrocell (ETM) enables non-intrusive high speed real-time tracing instruction execution. Four-channel 10-bit with conversion time 2.44 32-bit timers (with four capture four compare channels), unit (six outputs), Real-Time Clock (RTC) watchdog. Multiple serial interfaces including UARTs (16C550), Fast I2C-bus (400 kbit/s) SPIs. maximum clock available from programmable on-chip Phase-Locked Loop with settling time Vectored Interrupt Controller with configurable priorities vector addresses. forty-six tolerant general purpose pins. nine edge level sensitive external interrupt pins available. On-chip crystal oscillator with operating range MHz. power modes, Idle Power-down. Processor wake-up from Power-down mode external interrupt. Individual enable/disable peripheral functions power optimization. Dual power supply: operating voltage range 1.65 1.95 (1.8 0.15 power supply range (3.3 with tolerant pads. 16/32-bit ARM7TDMI-S processor.
Ordering information
Table Ordering information Package Name LPC2114FBD64 LPC2114FBD64/00 LPC2114FBD64/01 LPC2124FBD64 LPC2124FBD64/00 LPC2124FBD64/01 LQFP64 LQFP64 LQFP64 LQFP64 LQFP64 LQFP64 Description plastic profile quad flat package; leads; body plastic profile quad flat package; leads; body plastic profile quad flat package; leads; body plastic profile quad flat package; leads; body plastic profile quad flat package; leads; body plastic profile quad flat package; leads; body Version SOT314-2 SOT314-2 SOT314-2 SOT314-2 SOT314-2 SOT314-2 Type number
LPC2114_2124_6
B.V. 2007. rights reserved.
Product data sheet
Rev. December 2007
Semiconductors
LPC2114/2124
Single-chip 16/32-bit microcontrollers
Ordering options
Table Ordering options Flash memory Fast GPIO/SSP/ Enhanced UART, ADC, Timer Temperature range Type number
LPC2114FBD64 LPC2114FBD64/00 LPC2114FBD64/01 LPC2124FBD64 LPC2124FBD64/00 LPC2124FBD64/01
LPC2114_2124_6
B.V. 2007. rights reserved.
Product data sheet
Rev. December 2007
Semiconductors
LPC2114/2124
Single-chip 16/32-bit microcontrollers
Block diagram
TMS(2) TDI(2) RTCK(2) TRST(2) TCK(2) TDO(2) XTAL2 XTAL1 RESET
EMULATION TRACE MODULE
LPC2114 LPC2124
P0[30:27], P0[25:0] P1[31:16] HIGH-SPEED GPIO(3) PINS TOTAL
TEST/DEBUG INTERFACE
system clock
SYSTEM FUNCTIONS VECTORED INTERRUPT CONTROLLER
ARM7TDMI-S
BRIDGE
ARM7 LOCAL
AMBA Advanced High-performance (AHB)
INTERNAL SRAM CONTROLLER
MEMORY ACCELERATOR
DECODER BRIDGE DIVIDER
SRAM
128/256 FLASH
EINT[3:0](1)
EXTERNAL INTERRUPTS
I2C-BUS SERIAL INTERFACE
SCL(1) SDA(1) SCK0(1)
CAP0(1) CAP1(1) MAT0(1) MAT1(1) AIN[3:0](1)
CAPTURE/ COMPARE TIMER 0/TIMER
SPI0 SERIAL INTERFACE
MOSI0(1) MISO0(1) SSEL0(1) SCK1(1)
CONVERTER
SPI1/SSP(3) SERIAL INTERFACE
MOSI1(1) MISO1(1) SSEL1(1)
P0[30:27], P0[25:0] P1[31:16]
GENERAL PURPOSE
UART0/UART1
TXD[1:0](1) RXD[1:0](1)
DSR1(1), CTS1(1), RTS1(1), DTR1(1), DCD1(1), RI1(1)
PWM0 WATCHDOG TIMER
PWM[6:1](1)
REAL-TIME CLOCK
SYSTEM CONTROL
002aad175
Shared with GPIO. When test/debug interface used, GPIO/other functions sharing these pins available. interface high-speed GPIO available LPC2114/01 LPC2124/01 only.
Block diagram
LPC2114_2124_6
B.V. 2007. rights reserved.
Product data sheet
Rev. December 2007
Semiconductors
LPC2114/2124
Single-chip 16/32-bit microcontrollers
Pinning information
Pinning
P0[19]/MAT1[2]/MOSI1/CAP1[2] P0[18]/CAP1[3]/MISO1/MAT1[3]
P0[20]/MAT1[3]/SSEL1/EINT3
P1[30]/TMS
P1[27]/TDO
P1[29]/TCK
P1[28]/TDI
VDDA(1V8) XTAL1
VSSA(PLL) RESET
VDD(3V3)
P0[21]/PWM5/CAP1[3] P0[22]/CAP0[0]/MAT0[0] P0[23] P1[19]/TRACEPKT3 P0[24] VDDA(3V3) P1[18]/TRACEPKT2 P0[25]
VDD(1V8) P1[20]/TRACESYNC P0[17]/CAP1[2]/SCK1/MAT1[2] P0[16]/EINT0/MAT0[2]/CAP0[2] P0[15]/RI1/EINT2 P1[21]/PIPESTAT0 VDD(3V3) P0[14]/DCD1/EINT1 P1[22]/PIPESTAT1 P0[13]/DTR1/MAT1[1] P0[12]/DSR1/MAT1[0] P0[11]/CTS1/CAP1[1] P1[23]/PIPESTAT2 P0[10]/RTS1/CAP1[0] P0[9]/RXD1/PWM6/EINT3 P0[8]/TXD1/PWM4 P1[24]/TRACECLK
002aad176
XTAL2
VSSA P0[2]/SCL/CAP0[0]
LPC2114 LPC2124(1)
n.c. P0[27]/AIN0/CAP0[1]/MAT0[1] P1[17]/TRACEPKT1 P0[28]/AIN1/CAP0[2]/MAT0[2] P0[29]/AIN2/CAP0[3]/MAT0[3] P0[30]/AIN3/EINT3/CAP0[0] P1[16]/TRACEPKT0
VDD(1V8)
P0[0]/TXD0/PWM1
P1[31]/TRST
P0[1]/RXD0/PWM3/EINT0
VDD(3V3)
P1[26]/RTCK
P0[3]/SDA/MAT0[0]/EINT1
P0[4]/SCK0/CAP0[1]
P1[25]/EXTIN0
P0[5]/MISO0/MAT0[1]
P0[6]/MOSI0/CAP0[2]
configuration identical devices with without suffixes.
configuration
LPC2114_2124_6
P0[7]/SSEL0/PWM2/EINT2
B.V. 2007. rights reserved.
Product data sheet
Rev. December 2007
Semiconductors
LPC2114/2124
Single-chip 16/32-bit microcontrollers
description
Table Symbol P0[0] P0[31] description Type Description Port 32-bit bidirectional port with individual direction controls each bit. operation port pins depends upon function selected Connect Block. Pins port available. TXD0 Transmitter output UART0. PWM1 Pulse Width Modulator output RXD0 Receiver input UART0. PWM3 Pulse Width Modulator output EINT0 External interrupt input I2C-bus clock input/output. Open-drain output (for I2C-bus compliance). CAP0[0] Capture input Timer channel I2C-bus data input/output. Open-drain output (for I2C-bus compliance). MAT0[0] Match output Timer channel EINT1 External interrupt input. SCK0 Serial clock SPI0. clock output from master input slave. CAP0[1] Capture input Timer channel MISO0 Master Slave SPI0. Data input master data output from slave. MAT0[1] Match output Timer channel MOSI0 Master Slave SPI0. Data output from master data input slave. CAP0[2] Capture input Timer channel SSEL0 Slave Select SPI0. Selects interface slave. PWM2 Pulse Width Modulator output EINT2 External interrupt input. TXD1 Transmitter output UART1. PWM4 Pulse Width Modulator output RXD1 Receiver input UART1. PWM6 Pulse Width Modulator output EINT3 External interrupt input. RTS1 Request Send output UART1. CAP1[0] Capture input Timer channel CTS1 Clear Send input UART1. CAP1[1] Capture input Timer channel DSR1 Data Ready input UART1. MAT1[0] Match output Timer channel DTR1 Data Terminal Ready output UART1. MAT1[1] Match output Timer channel DCD1 Data Carrier Detect input UART1. EINT1 External interrupt input. Note: this while RESET forces on-chip bootloader take control part after reset.
LPC2114_2124_6 B.V. 2007. rights reserved.
P0[0]/TXD0/ PWM1 P0[1]/RXD0/ PWM3/EINT0
P0[2]/SCL/ CAP0[0] P0[3]/SDA/ MAT0[0]/EINT1
P0[4]/SCK0/ CAP0[1] P0[5]/MISO0/ MAT0[1] P0[6]/MOSI0/ CAP0[2] P0[7]/SSEL0/ PWM2/EINT2
P0[8]/TXD1/ PWM4 P0[9]/RXD1/ PWM6/EINT3
P0[10]/RTS1/ CAP1[0] P0[11]/CTS1/ CAP1[1] P0[12]/DSR1/ MAT1[0] P0[13]/DTR1/ MAT1[1] P0[14]/DCD1/ EINT1
Product data sheet
Rev. December 2007
Semiconductors
LPC2114/2124
Single-chip 16/32-bit microcontrollers
Table Symbol
description .continued Type Description Ring Indicator input UART1. EINT2 External interrupt input. EINT0 External interrupt input. MAT0[2] Match output Timer channel CAP0[2] Capture input Timer channel CAP1[2] Capture input Timer channel SCK1 Serial Clock SPI1/SSP[1]. clock output from master input slave. MAT1[2] Match output Timer channel CAP1[3] Capture input Timer channel MISO1 Master Slave SPI1/SSP[1]. Data input master data output from slave. MAT1[3] Match output Timer channel MAT1[2] Match output Timer channel MOSI1 Master Slave SPI1/SSP[1]. Data output from master data input slave. CAP1[2] Capture input Timer channel MAT1[3] Match output Timer channel SSEL1 Slave Select SPI1/SSP[1]. Selects interface slave. EINT3 External interrupt input. PWM5 Pulse Width Modulator output CAP1[3] Capture input Timer channel CAP0[0] Capture input Timer channel MAT0[0] Match output Timer channel general purpose bidirectional digital port only general purpose bidirectional digital port only general purpose bidirectional digital port only AIN0 ADC, input This analog input always connected pin. CAP0[1] Capture input Timer channel MAT0[1] Match output Timer channel AIN1 ADC, input This analog input always connected pin. CAP0[2] Capture input Timer channel MAT0[2] Match output Timer channel AIN2 ADC, input This analog input always connected pin. CAP0[3] Capture input Timer Channel MAT0[3] Match output Timer channel AIN3 ADC, input This analog input always connected pin. EINT3 External interrupt input. CAP0[0] Capture input Timer channel Port 32-bit bidirectional port with individual direction controls each bit. operation port pins depends upon function selected Connect Block. Pins through port available.
B.V. 2007. rights reserved.
P0[15]/RI1/EINT2 P0[16]/EINT0/ MAT0[2]/CAP0[2]
P0[17]/CAP1[2]/ SCK1/MAT1[2]
P0[18]/CAP1[3]/ MISO1/MAT1[3]
P0[19]/MAT1[2]/ MOSI1/CAP1[2]
P0[20]/MAT1[3]/ SSEL1/EINT3
P0[21]/PWM5/ CAP1[3] P0[22]/CAP0[0]/ MAT0[0] P0[23] P0[24] P0[25] P0[27]/AIN0/ CAP0[1]/MAT0[1]
P0[28]/AIN1/ CAP0[2]/MAT0[2]
P0[29]/AIN2/ CAP0[3]/MAT0[3]
P0[30]/AIN3/ EINT3/CAP0[0]
P1[0] P1[31]
LPC2114_2124_6
Product data sheet
Rev. December 2007
Semiconductors
LPC2114/2124
Single-chip 16/32-bit microcontrollers
Table Symbol
description .continued Type Description Trace Packet, Standard port with internal pull-up. Trace Packet, Standard port with internal pull-up. Trace Packet, Standard port with internal pull-up. Trace Packet, Standard port with internal pull-up. Trace Synchronization. Standard port with internal pull-up. Note: this while RESET LOW, enables pins P1[25:16] operate Trace port after reset. Pipeline Status, Standard port with internal pull-up. Pipeline Status, Standard port with internal pull-up. Pipeline Status, Standard port with internal pull-up. Trace Clock. Standard port with internal pull-up. External Trigger Input. Standard with internal pull-up. Returned Test Clock output. Extra signal added JTAG port. Assists debugger synchronization when processor frequency varies. Bidirectional with internal pull-up. Note: this while RESET LOW, enables pins P1[31:26] operate Debug port after reset.
P1[16]/ TRACEPKT0 P1[17]/ TRACEPKT1 P1[18]/ TRACEPKT2 P1[19]/ TRACEPKT3 P1[20]/ TRACESYNC P1[21]/ PIPESTAT0 P1[22]/ PIPESTAT1 P1[23]/ PIPESTAT2 P1[24]/ TRACECLK P1[25]/EXTIN0 P1[26]/RTCK
P1[27]/TDO P1[28]/TDI P1[29]/TCK P1[30]/TMS P1[31]/TRST n.c. RESET
Test Data JTAG interface. Test Data JTAG interface. Test Clock JTAG interface. This clock must slower than clock (CCLK) JTAG interface operate. Test Mode Select JTAG interface. Test Reset JTAG interface. connected. external reset input; this resets device, causing ports peripherals take their default states, processor execution begin address with hysteresis, tolerant. input oscillator circuit internal clock generator circuits. output from oscillator amplifier. ground: reference. analog ground; reference. This should nominally same voltage VSS, should isolated minimize noise error. analog ground; reference. This should nominally same voltage VSS, should isolated minimize noise error. core power supply; this power supply voltage internal circuitry.
XTAL1 XTAL2 VSSA VSSA(PLL) VDD(1V8)
LPC2114_2124_6
B.V. 2007. rights reserved.
Product data sheet
Rev. December 2007
Semiconductors
LPC2114/2124
Single-chip 16/32-bit microcontrollers
Table Symbol VDDA(1V8)
description .continued Type Description analog core power supply; this power supply voltage internal circuitry. This should nominally same voltage VDD(1V8) should isolated minimize noise error. power supply; this power supply voltage ports analog power supply; this should nominally same voltage VDD(3V3) should isolated minimize noise error
VDD(3V3) VDDA(3V3)
interface available LPC2114/01 LPC2124/01 only.
LPC2114_2124_6
B.V. 2007. rights reserved.
Product data sheet
Rev. December 2007
Semiconductors
LPC2114/2124
Single-chip 16/32-bit microcontrollers
Functional description
Details LPC2114/2124 systems peripheral functions described following sections.
Architectural overview
ARM7TDMI-S general purpose 32-bit microprocessor, which offers high performance very power consumption. architecture based Reduced Instruction Computer (RISC) principles, instruction related decode mechanism much simpler than those microprogrammed Complex Instruction Computers. This simplicity results high instruction throughput impressive real-time interrupt response from small cost-effective processor core. Pipeline techniques employed that parts processing memory systems operate continuously. Typically, while instruction being executed, successor being decoded, third instruction being fetched from memory. ARM7TDMI-S processor also employs unique architectural strategy known Thumb, which makes ideally suited high-volume applications with memory restrictions, applications where code density issue. idea behind Thumb that super-reduced instruction set. Essentially, ARM7TDMI-S processor instruction sets:
standard 32-bit set. 16-bit Thumb set.
Thumb set's 16-bit instruction length allows approach twice density standard code while retaining most ARM's performance advantage over traditional 16-bit processor using 16-bit registers. This possible because Thumb code operates same 32-bit register code. Thumb code able provide code size ARM, performance equivalent processor connected 16-bit memory system.
On-chip flash program memory
LPC2114/2124 incorporate flash memory system respectively. This memory used both code data storage. Programming flash memory accomplished several ways. programmed System serial port. application program also erase and/or program flash while application running, allowing great degree flexibility data storage field firmware upgrades, etc. When on-chip bootloader used, flash memory available user code. LPC2114/2124 flash memory provides minimum 100000 erase/write cycles years data retention. On-chip bootloader revision 1.60) provides Code Read Protection (CRP) LPC2114/2124 on-chip flash memory. When enabled, JTAG debug port commands accessing either on-chip flash memory disabled.
LPC2114_2124_6
B.V. 2007. rights reserved.
Product data sheet
Rev. December 2007
Semiconductors
LPC2114/2124
Single-chip 16/32-bit microcontrollers
However, flash erase command executed time matter whether off). Removal achieved erasure full on-chip user flash. With off, full access chip JTAG and/or restored.
On-chip static
On-chip static used code and/or data storage. SRAM accessed bit, bit, bit. LPC2114/2124 provide static RAM.
Memory
LPC2114/2124 memory maps incorporate several distinct regions, shown Figure addition, interrupt vectors re-mapped allow them reside either flash memory (the default) on-chip static RAM. This described Section 6.17 "System control".
LPC2114_2124_6
B.V. 2007. rights reserved.
Product data sheet
Rev. December 2007
Semiconductors
LPC2114/2124
Single-chip 16/32-bit microcontrollers
PERIPHERALS 3.75 PERIPHERALS
0xFFFF FFFF 0xF000 0000 0xEFFF FFFF 0xE000 0000 0xDFFF FFFF
RESERVED ADDRESS SPACE
0xC000 0000
BOOT BLOCK (RE-MAPPED FROM ON-CHIP FLASH MEMORY)
0x8000 0000 0x7FFF FFFF 0x7FFF E000 0x7FFF DFFF
RESERVED ADDRESS SPACE 0x4000 4000 0x4000 3FFF ON-CHIP STATIC 0x4000 0000 0x3FFF FFFF
RESERVED ADDRESS SPACE
0x0004 0000 0x0003 FFFF ON-CHIP FLASH MEMORY (LPC2124) ON-CHIP FLASH MEMORY (LPC2114) 0x0000 0000
002aad177
0x0002 0000 0x0001 FFFF
LPC2114/2124 memory
Interrupt controller
Vectored Interrupt Controller (VIC) accepts interrupt request inputs categorizes them Fast Interrupt Request (FIQ), vectored Interrupt Request (IRQ), non-vectored defined programmable settings. programmable assignment scheme means that priorities interrupts from various peripherals dynamically assigned adjusted. Fast Interrupt reQuest (FIQ) highest priority. more than request assigned FIQ, combines requests produce signal processor. fastest possible latency achieved when only request classified FIQ, because then service routine simply start dealing with that device. more than request assigned class, service routine read word from that identifies which source(s) (are) requesting interrupt.
LPC2114_2124_6 B.V. 2007. rights reserved.
Product data sheet
Rev. December 2007
Semiconductors
LPC2114/2124
Single-chip 16/32-bit microcontrollers
Vectored IRQs have middle priority. Sixteen interrupt requests assigned this category. interrupt requests assigned vectored slots, among which slot highest priority slot lowest. Non-vectored IRQs have lowest priority. combines requests from vectored non-vectored IRQs produce signal processor. service routine start reading register from jumping there. vectored IRQs requesting, provides address highest-priority requesting IRQs service routine, otherwise provides address default routine that shared non-vectored IRQs. default routine read another register what IRQs active.
6.5.1 Interrupt sources
Table lists interrupt sources each peripheral function. Each peripheral device interrupt line connected Vectored Interrupt Controller, have several internal interrupt flags. Individual interrupt flags also represent more than interrupt source.
Table Block Core Core Timer Timer UART0 Interrupt sources Flag(s) Watchdog Interrupt (WDINT) Reserved software interrupts only EmbeddedICE, DbgCommRx EmbeddedICE, DbgCommTx Match (MR0, MR1, MR2, MR3) Capture (CR0, CR1, CR2, CR3) Match (MR0, MR1, MR2, MR3) Capture (CR0, CR1, CR2, CR3) Line Status (RLS) Transmit Holding Register empty (THRE) Data Available (RDA) Character Time-out Indicator (CTI) UART1 Line Status (RLS) Transmit Holding Register empty (THRE) Data Available (RDA) Character Time-out Indicator (CTI) Modem Status Interrupt (MSI) PWM0 I2C-bus SPI0 SPI1 SSP[1] Match (MR0, MR1, MR2, MR3, MR4, MR5, MR6) (state change) SPIF, MODF SPIF, MODF TXRIS, RXRIS, RTRIS, RORRIS Lock (PLOCK) RTCCIF (Counter Increment), RTCALF (Alarm) channel
LPC2114_2124_6
B.V. 2007. rights reserved.
Product data sheet
Rev. December 2007
Semiconductors
LPC2114/2124
Single-chip 16/32-bit microcontrollers
Interrupt sources .continued Flag(s) External Interrupt (EINT0) External Interrupt (EINT1) External Interrupt (EINT2) External Interrupt (EINT3) channel
Table Block
System Control
interface available LPC2114/01 LPC2124/01 only.
connect block
connect block allows selected pins microcontroller have more than function. Configuration registers control multiplexers allow connection between chip peripherals. Peripherals should connected appropriate pins prior being activated, prior related interrupt(s) being enabled. Activity enabled peripheral function that mapped related should considered undefined.
General purpose parallel (GPIO) Fast
Device pins that connected specific peripheral function controlled parallel registers. Pins dynamically configured inputs outputs. Separate registers allow setting clearing number outputs simultaneously. value output register read back, well current state port pins.
6.7.1 Features
Bit-level clear registers allow single instruction clear number
bits port.
Direction control individual bits. Separate control output clear. default inputs after reset.
6.7.2 Features added with Fast GPIO registers available LPC2114/2124/01 only
Fast GPIO registers relocated local fastest possible
timing, enabling port toggling times faster than earlier LPC2000 devices.
Mask registers allow treating sets port bits group, leaving other bits
unchanged.
Fast GPIO registers byte addressable. Entire port value written instruction. Ports accessible either legacy group registers (GPIOs) group
registers providing accelerated port access (Fast GPIOs).
10-bit
LPC2114/2124 each contain single 10-bit successive approximation analog digital converter with four multiplexed channels.
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Product data sheet
Rev. December 2007
Semiconductors
LPC2114/2124
Single-chip 16/32-bit microcontrollers
6.8.1 Features
Measurement range Capable performing more than 400000 10-bit samples second. Burst conversion mode single multiple inputs. Optional conversion transition input Timer Match signal. Every analog input dedicated result register reduce interrupt overhead. Every analog input generate interrupt once conversion completed.
6.8.2 features available LPC2114/2124/01 only
Every analog input dedicated result register reduce interrupt overhead. Every analog input generate interrupt once conversion completed. pads tolerant when configured digital function(s). UARTs
LPC2114/2124 each contain UARTs. addition standard transmit receive data lines, UART1 also provides full modem control handshake interface.
6.9.1 Features
Receive Transmit FIFOs. Register locations conform 16C550 industry standard. Receiver FIFO trigger points Built-in fractional baud rate generator covering wide range baud rates without need external crystals particular values. control both UARTs.
Transmission FIFO control enables implementation software (XON/XOFF) flow UART1 equipped with standard modem interface signals. This module also
provides full support hardware flow control (auto-CTS/RTS).
6.9.2 UART features available LPC2114/2124/01 only
Compared previous LPC2000 microcontrollers, UARTs LPC2114/2124/01 introduce fractional baud rate generator both UARTs, enabling these microcontrollers achieve standard baud rates such 115200 with crystal frequency above MHz. addition, auto-CTS/RTS flow-control functions fully implemented hardware.
Fractional baud rate generator enables standard baud rates such 115200
achieved with crystal frequency above MHz.
Auto-bauding. Auto-CTS/RTS flow-control fully implemented hardware. 6.10 I2C-bus serial controller
I2C-bus bidirectional inter-IC control using only wires: serial clock line (SCL), serial data line (SDA). Each device recognized unique address operate either receiver-only device (e.g. driver transmitter with
LPC2114_2124_6 B.V. 2007. rights reserved.
Product data sheet
Rev. December 2007
Semiconductors
LPC2114/2124
Single-chip 16/32-bit microcontrollers
capability both receive send information (such memory). Transmitters and/or receivers operate either master slave mode, depending whether chip initiate data transfer only addressed. I2C-bus multi-master bus; controlled more than master connected I2C-bus implemented LPC2114/2124 supports rate kbit/s (Fast I2C-bus).
6.10.1 Features
Standard I2C-bus compliant interface. Easy configure Master, Slave, Master/Slave. Programmable clocks allow versatile rate control. Bidirectional data transfer between masters slaves. Multi-master central master). Arbitration between simultaneously transmitting masters without corruption serial
data bus.
Serial clock synchronization allows devices with different rates communicate
serial bus.
Serial clock synchronization used handshake mechanism suspend
resume serial transfer.
I2C-bus used test diagnostic purposes. 6.11 serial controller
LPC2114/2124 each contain SPIs. full duplex serial interface, designed able handle multiple masters slaves connected given bus. Only single master single slave communicate interface during given data transfer. During data transfer master always sends byte data slave, slave always sends byte data master.
6.11.1 Features
Compliant with Serial Peripheral Interface (SPI) specification. Synchronous, Serial, Full Duplex communication. Combined master slave. Maximum data rate input clock rate.
6.11.2 Features available LPC2114/2124/01 only
Eight bits frame. When interface used Master mode, SSELn needed (can
used different function).
LPC2114_2124_6
B.V. 2007. rights reserved.
Product data sheet
Rev. December 2007
Semiconductors
LPC2114/2124
Single-chip 16/32-bit microcontrollers
6.12 controller (LPC2114/2124/01 only)
Remark: This peripheral available LPC2114/2124/01 only. controller capable operation SPI, 4-wire SSI, Microwire bus. interact with multiple masters slaves bus. Only single master single slave communicate during given data transfer. Data transfers principle full duplex, with frames four bits data flowing from master slave from slave master. While SPI1 peripherals share same physical pins, possible have both these peripherals active same time. application switch from SPI1 back.
6.12.1 Features
Compatible with Motorola's SPI, Texas Instrument's 4-wire SSI, National
Semiconductor's Microwire buses.
Synchronous serial communication. Master slave operation. 8-frame FIFOs both transmit receive. Four bits frame.
6.13 General purpose timers
Timer designed count cycles peripheral clock (PCLK) optionally generate interrupts perform other actions specified timer values, based four match registers. also includes four capture inputs trap timer value when input signal transitions, optionally generating interrupt. Multiple pins selected perform single capture match function, providing application with `or' `and', well `broadcast' functions among them.
6.13.1 Features
32-bit Timer/Counter with programmable 32-bit Prescaler. Four 32-bit capture channels timer that take snapshot timer value
when input signal transitions. capture event also optionally generate interrupt.
Four 32-bit match registers that allow:
Continuous operation with optional interrupt generation match. Stop timer match with optional interrupt generation. Reset timer match with optional interrupt generation.
Four external outputs timer corresponding match registers, with following
capabilities: match. HIGH match. Toggle match. nothing match.
LPC2114_2124_6
B.V. 2007. rights reserved.
Product data sheet
Rev. December 2007
Semiconductors
LPC2114/2124
Single-chip 16/32-bit microcontrollers
6.13.2 Features available LPC2114/2124/01 only
Timer count cycles either peripheral clock (PCLK) externally supplied
clock.
When counting cycles externally supplied clock only timer's capture
inputs selected timer's clock. rate such clock limited PCLK Duration HIGH/LOW levels selected input shorter than (2PCLK).
6.14 Watchdog timer
purpose watchdog reset microcontroller within reasonable amount time enters erroneous state. When enabled, watchdog will generate system reset user program fails `feed' reload) watchdog within predetermined amount time.
6.14.1 Features
Internally resets chip periodically reloaded. Debug mode. Enabled software requires hardware reset watchdog reset/interrupt
disabled.
Incorrect/incomplete feed sequence causes reset/interrupt enabled. Flag indicate watchdog reset. Programmable 32-bit timer with internal pre-scaler. Selectable time period from (Tcy(PCLK) (Tcy(PCLK) multiples
Tcy(PCLK)
6.15 Real-time clock
designed provide counters measure time when normal idle operating mode selected. been designed little power, making suitable battery powered systems where running continuously (Idle mode).
6.15.1 Features
Measures passage time maintain calendar clock. Ultra power design support battery powered systems. Provides Seconds, Minutes, Hours, Month, Month, Year, Week,
Year.
Programmable reference clock divider allows adjustment match various
crystal frequencies.
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Semiconductors
LPC2114/2124
Single-chip 16/32-bit microcontrollers
6.16 Pulse width modulator
based standard Timer block inherits features, although only function pinned LPC2114/2124. Timer designed count cycles peripheral clock (PCLK) optionally generate interrupts perform other actions when specified timer values occur, based seven match registers. function also based match register events. ability separately control rising falling edge locations allows used more applications. instance, multi-phase motor control typically requires three non-overlapping outputs with individual control three pulse widths positions. match registers used provide single edge controlled output. match register (MR0) controls cycle rate, resetting count upon match. other match register controls edge position. Additional single edge controlled outputs require only match register each, since repetition rate same outputs. Multiple single edge controlled outputs will have rising edge beginning each cycle, when match occurs. Three match registers used provide output with both edges controlled. Again, match register controls cycle rate. other match registers control edge positions. Additional double edge controlled outputs require only match registers each, since repetition rate same outputs. With double edge controlled outputs, specific match registers control rising falling edge output. This allows both positive going pulses (when rising edge occurs prior falling edge), negative going pulses (when falling edge occurs prior rising edge).
6.16.1 Features
Seven match registers allow single edge controlled three double edge
controlled outputs, both types.
match registers also allow:
Continuous operation with optional interrupt generation match. Stop timer match with optional interrupt generation. Reset timer match with optional interrupt generation.
Supports single edge controlled and/or double edge controlled outputs. Single
edge controlled outputs HIGH beginning each cycle unless output constant LOW. Double edge controlled outputs have either edge occur position within cycle. This allows both positive going negative going pulses.
Pulse period width number timer counts. This allows complete
flexibility trade-off between resolution repetition rate. outputs will occur same repetition rate.
Double edge controlled outputs programmed either positive going
negative going pulses.
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Product data sheet
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Semiconductors
LPC2114/2124
Single-chip 16/32-bit microcontrollers
Match register updates synchronized with pulse outputs prevent generation
erroneous pulses. Software must `release' match values before they become effective.
used standard timer mode enabled. 32-bit Timer/Counter with programmable 32-bit Prescaler. 6.17 System control
6.17.1 Crystal oscillator
oscillator supports crystals range MHz. oscillator output frequency called fosc processor clock frequency referred CCLK purposes rate equations, etc. fosc CCLK same value unless running connected. Refer Section 6.17.2 "PLL" additional information.
6.17.2
accepts input clock frequency range MHz. input frequency multiplied into range with Current Controlled Oscillator (CCO). multiplier integer value from practice, multiplier value cannot higher than this family microcontrollers upper frequency limit CPU). operates range MHz, there additional divider loop keep within frequency range while providing desired output frequency. output divider divide produce output clock. Since minimum output divider value insured that output duty cycle. turned bypassed following chip Reset enabled software. program must configure activate PLL, wait Lock, then connect clock source. settling time
6.17.3 Reset wake-up timer
Reset sources LPC2114/2124: RESET Watchdog Reset. RESET Schmitt trigger input with additional glitch filter. Assertion chip Reset source starts Wake-up Timer (see Wake-up Timer description below), causing internal chip reset remain asserted until external Reset de-asserted, oscillator running, fixed number clocks have passed, on-chip flash controller completed initialization. When internal Reset removed, processor begins executing address which Reset vector. that point, processor peripheral registers have been initialized predetermined values. wake-up timer ensures that oscillator other analog functions required chip operation fully functional before processor allowed execute instructions. This important power types Reset, whenever aforementioned functions turned reason. Since oscillator other functions turned during Power-down mode, wake-up processor from Power-down mode makes Wake-up Timer.
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Semiconductors
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Single-chip 16/32-bit microcontrollers
Wake-up Timer monitors crystal oscillator means checking whether safe begin code execution. When power applied chip, some event caused chip exit Power-down mode, some time required oscillator produce signal sufficient amplitude drive clock logic. amount time depends many factors, including rate ramp case power on), type crystal electrical characteristics quartz crystal used), well other external circuitry (e.g. capacitors), characteristics oscillator itself under existing ambient conditions.
6.17.4 Code security (Code Read Protection CRP)
This feature LPC2114/2124/01 allows user enable different levels security system that access on-chip flash JTAG restricted. When needed, invoked programming specific pattern into dedicated flash location. commands affected CRP. There three levels Code Read Protection. CRP1 disables access chip JTAG allows partial flash update (excluding flash sector using limited commands. This mode useful when required flash field updates needed sectors erased. CRP2 disables access chip JTAG only allows full flash erase update using reduced commands. Running application with level CRP3 selected fully disables access chip JTAG pins ISP. This mode effectively disables override using P0[14] pin, too. user's application provide needed) flash update mechanism using calls call reinvoke command enable flash update UART0.
CAUTION level three Code Read Protection (CRP3) selected, future factory testing performed device.
Remark: Devices without suffix have only security level equivalent CRP2 available.
6.17.5 External interrupt inputs
LPC2114/2124 include nine edge level sensitive External Interrupt Inputs selectable functions. When pins combined, external events processed four independent interrupt signals. External Interrupt Inputs optionally used wake processor from Power-down mode.
6.17.6 Memory mapping control
Memory Mapping Control alters mapping interrupt vectors that appear beginning address 0x0000 0000. Vectors mapped bottom on-chip flash memory, on-chip static RAM. This allows code running different memory spaces have control interrupts.
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6.17.7 Power control
LPC2114/2124 support reduced power modes: Idle mode Power-down mode. Idle mode, execution instructions suspended until either Reset interrupt occurs. Peripheral functions continue operation during Idle mode generate interrupts cause processor resume execution. Idle mode eliminates power used processor itself, memory systems related controllers, internal buses. Power-down mode, oscillator shut down chip receives internal clocks. processor state registers, peripheral registers, internal SRAM values preserved throughout Power-down mode logic levels chip output pins remain static. Power-down mode terminated normal operation resumed either Reset certain specific interrupts that able function without clocks. Since dynamic operation chip suspended, Power-down mode reduces chip power consumption nearly zero. Power Control Peripherals feature allows individual peripherals turned they needed application, resulting additional power savings.
6.17.8
divider determines relationship between processor clock (CCLK) clock used peripheral devices (PCLK). divider serves purposes. first provide peripherals with desired PCLK that they operate speed chosen processor. order achieve this, slowed down processor clock rate. Because must work properly power-up (and timing cannot altered does work since divider control registers reside bus), default condition reset processor clock rate. second purpose divider allow power savings when application does require peripherals full processor rate. Because divider connected output, remains active running) during Idle mode.
6.18 Emulation debugging
LPC2114/2124 support emulation debugging JTAG serial port. trace port allows tracing program execution. Debugging trace functions multiplexed only with GPIOs Port This means that communication, timer interface peripherals residing Port available during development debugging phase they when application embedded system itself.
6.18.1 EmbeddedICE
Standard EmbeddedICE logic provides on-chip debug support. debugging target system requires host computer running debugger software EmbeddedICE protocol convertor. EmbeddedICE protocol convertor converts Remote Debug Protocol commands JTAG data needed access core. core Debug Communication Channel function built-in. debug communication channel allows program running target communicate with host debugger another separate host without stopping program flow even entering debug state. debug communication channel accessed co-processor program running ARM7TDMI-S core. debug
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communication channel allows JTAG port used sending receiving data without affecting normal program flow. debug communication channel data control registers mapped addresses EmbeddedICE logic. JTAG clock (TCK) must slower than clock (CCLK) JTAG interface operate.
6.18.2 Embedded trace
Since LPC2114/2124 have significant amounts on-chip memory, possible determine processor core operating simply observing external pins. Eprovides real-time trace capability deeply embedded processor cores. outputs information about processor execution trace port. connected directly core main AMBA system bus. compresses trace information exports through narrow trace port. external trace port analyzer must capture trace information under software debugger control. Instruction trace trace) shows flow execution processor provides list instructions that were executed. Instruction trace significantly compressed only broadcasting branch addresses well status signals that indicate pipeline status cycle cycle basis. Trace information generation controlled selecting trigger resource. Trigger resources include address comparators, counters sequencers. Since trace information compressed software debugger requires static image code being executed. Self-modifying code traced because this restriction.
6.18.3 RealMonitor
RealMonitor configurable software module, developed Inc., which enables real time debug. lightweight debug monitor that runs background while users debug their foreground application. communicates with host using (Debug Communications Channel), which present EmbeddedICE logic. LPC2114/2124 contain specific configuration RealMonitor software programmed into on-chip flash memory.
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B.V. 2007. rights reserved.
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Semiconductors
LPC2114/2124
Single-chip 16/32-bit microcontrollers
Limiting values
Table Limiting values accordance with Absolute Maximum Rating System (IEC 60134).[1] Symbol VDD(1V8) VDD(3V3) VDDA(3V3) Tstg Ptot(pack) Parameter supply voltage (1.8 supply voltage (3.3 analog supply voltage (3.3 analog input voltage input voltage supply current ground current junction temperature storage temperature total power dissipation (per package) electrostatic discharge voltage based package heat transfer, device power consumption human body model pins machine model pins
[12] [11] [10]
Conditions
-0.5 -0.5 -0.5 -0.5
+2.5 +3.6 +4.6 +5.1 +6.0 VDD(3V3) +150
Unit
tolerant pins other pins
[4][5] [4][6] [7][8] [8][9]
-0.5 -0.5
Vesd
-2000 -200
+2000 +200
following applies Table This product includes circuitry specifically designed protection internal devices from damaging effects excessive static charge. Nonetheless, suggested that conventional precautions taken avoid applying greater than rated maximum. Parameters valid over operating temperature range unless otherwise specified. voltages with respect unless otherwise noted. Internal rail. External rail. Including voltage outputs 3-state mode. Only valid when VDD(3V3) supply voltage present. exceed supply pin. peak current limited times corresponding maximum current. ground pin.
[10] Dependent package type. [11] Human body model: equivalent discharging capacitor through series resistor. [12] Machine model: equivalent discharging capacitor through 0.75 coil series resistor.
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Semiconductors
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Static characteristics
Table Static characteristics Tamb industrial applications, unless otherwise specified. Symbol VDD(1V8) VDD(3V3) Parameter supply voltage (1.8 supply voltage (3.3 Conditions
1.65
Typ[1]
1.95
Unit
VDDA(3V3) analog supply voltage (3.3 Standard port pins, RESET, RTCK Ilatch Vhys IOHS IOLS LOW-state input current HIGH-state input current OFF-state output current latch-up current input voltage output voltage HIGH-state input voltage LOW-state input voltage hysteresis voltage HIGH-state output voltage LOW-state output voltage HIGH-state output current LOW-state output current HIGH-state short-circuit output current LOW-state short-circuit output current pull-down current pull-up current VDD(3V3) VDD(3V3) VDD(3V3) Power consumption LPC2114, LPC2114/00, LPC2124, LPC2124/00 IDD(act) active mode supply current VDD(1V8) CCLK MHz; Tamb code
pull-up VDD(3V3); pull-down VDD(3V3); pull-up/down -(0.5VDD(3V3)) (1.5VDD(3V3));
[4][5][6]
VDD(3V3)
output active
VDD(3V3)
[10]
while(1){}
executed from flash; peripherals enabled PCONP[11] register configured IDD(pd) Power-down mode supply current VDD(1V8) Tamb VDD(1V8) Tamb
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Semiconductors
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Single-chip 16/32-bit microcontrollers
Table Static characteristics .continued Tamb industrial applications, unless otherwise specified. Symbol IDD(act) Parameter active mode supply current Conditions VDD(1V8) CCLK MHz; Tamb code Typ[1] Unit Power consumption LPC2114/01 LPC2124/01
while(1){}
executed from flash; peripherals enabled PCONP[11] register configured IDD(idle) Idle mode supply current VDD(1V8) CCLK MHz; Tamb executed from flash; peripherals enabled PCONP[11] register configured IDD(pd) Power-down mode supply current VDD(1V8) Tamb VDD(1V8) Tamb I2C-bus pins Vhys HIGH-state input voltage LOW-state input voltage hysteresis voltage LOW-state output voltage input leakage current IOLS VDD(3V3) Oscillator pins Vi(XTAL1) Vo(XTAL2) input voltage XTAL1 output voltage XTAL2
[12]
0.7VDD(3V3)
0.3VDD(3V3)
0.5VDD(3V3)
Typical ratings guaranteed. values listed room temperature °C), nominal supply voltages. Internal rail. External rail. Including voltage outputs 3-state mode. VDD(3V3) supply voltages must present. 3-state outputs into 3-state mode when VDD(3V3) grounded. Accounts voltage drop supply lines. Only allowed short time period. Minimum condition maximum condition
[10] Applies P1[25:16]. [11] LPC2114/2124/2212/2214 User Manual. [12] VSS.
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B.V. 2007. rights reserved.
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Semiconductors
LPC2114/2124
Single-chip 16/32-bit microcontrollers
Table static characteristics VDDA unless otherwise specified; Tamb unless otherwise specified. frequency MHz. Symbol EL(adj)
Parameter analog input voltage analog input capacitance differential linearity error integral non-linearity offset error gain error absolute error
Conditions
[1][2][3]
VDDA ±0.5
Unit
[1][4] [1][5] [1][6] [1][7]
Conditions: VSSA VDDA monotonic, there missing codes. differential linearity error (ED) difference between actual step width ideal step width. Figure integral non-linearity (EL(adj)) peak difference between center steps actual ideal transfer curve after appropriate adjustment gain offset errors. Figure offset error (EO) absolute difference between straight line which fits actual curve straight line which fits ideal curve. Figure gain error (EG) relative difference percent between straight line fitting actual transfer curve after removing offset error, straight line which fits ideal transfer curve. Figure absolute voltage error (ET) maximum difference between center steps actual transfer curve non-calibrated ideal transfer curve. Figure
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Semiconductors
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Single-chip 16/32-bit microcontrollers
offset error 1023
gain error
1022
1021
1020
1019
1018
code
(ideal) 1018 1019 1020 1021 1022 1023 1024
(LSBideal) offset error
VDDA VSSA 1024
002aaa668
Example actual transfer curve. ideal transfer curve. Differential linearity error (ED). Integral non-linearity (EL(adj)). Center step actual transfer curve.
characteristics
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Semiconductors
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Single-chip 16/32-bit microcontrollers
Power consumption measurements LPC2114/01 LPC2124/01
power consumption measurements represent typical values given conditions. peripherals were enabled through PCONP register, these measurements, peripherals were configured run. Peripherals were disabled through PCONP register. description PCONP register refer LPC2114/2124/2212/2214 User Manual.
IDD(act) (mA) peripherals enabled
002aad149
peripherals disabled
frequency (MHz)
Test conditions: Active mode entered executing code from on-chip flash; PCLK CCLK/4; Tamb core voltage
Typical LPC2114/01 LPC2124/01 IDD(act) measured different frequencies
IDD(act) (mA)
002aad150
1.65 1.80 voltage 1.95
Test conditions: Active mode entered executing code from on-chip flash; PCLK CCLK/4; Temp core voltage peripherals disabled.
Typical LPC2114/01 LPC2124/01 IDD(act) measured different voltages
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IDD(act) (mA)
002aad151
1.65 1.80 voltage 1.95
Test conditions: Active mode entered executing code from on-chip flash; PCLK CCLK/4; Tamb core voltage peripherals enabled.
Typical LPC2114/01 LPC2124/01 IDD(act) measured different voltages
IDD(idle) (mA)
002aad152
peripherals enabled peripherals disabled
frequency (MHz)
Test conditions: Idle mode entered executing code from on-chip flash; PCLK CCLK/4; Tamb core voltage
Typical LPC2114/01 LPC2124/01 IDD(idle) measured different frequencies
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IDD(idle) (mA)
002aad154
1.65 1.80 voltage 1.95
Test conditions: Idle mode entered executing code from on-chip flash; PCLK CCLK/4; Tamb core voltage peripherals enabled.
Typical LPC2114/01 LPC2124/01 IDD(idle) measured different voltages
IDD(idle) (mA)
002aad153
1.65 1.80 voltage 1.95
Test conditions: Idle mode entered executing code from on-chip flash; PCLK CCLK/4; Temp core voltage peripherals disabled.
Typical LPC2114/01 LPC2124/01 IDD(idle) measured different voltages
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IDD(act) (mA)
002aad155
temperature (°C)
Test conditions: Active mode entered executing code from on-chip flash; PCLK CCLK/4; core voltage peripherals disabled.
Typical LPC2114/01 LPC2124/01 IDD(act) measured different temperatures
IDD(idle) (mA)
002aad156
temperature (°C)
Test conditions: Idle mode entered executing code from on-chip flash; PCLK CCLK/4; core voltage peripherals disabled.
Typical LPC2114/01 LPC2124/01 IDD(idle) measured different temperatures
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IDD(pd) (µA)
002aad157
1.95 1.65
temperature (°C)
Test conditions: Power-down mode entered executing code from on-chip flash.
Typical LPC2114/01 LPC2124/01 core power-down current IDD(pd) measured different temperatures Typical LPC2114/01 LPC2124/01 peripheral power consumption active mode Core voltage Tamb measurements PCLK CCLK/4. Peripheral Timer0 Timer1 UART0 UART1 PWM0 I2C-bus SPI0/1 CCLK CCLK CCLK Table
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Dynamic characteristics
Table Dynamic characteristics Tamb industrial applications; VDD(1V8), VDD(3V3) over specified ranges.[1] Symbol External clock fosc oscillator frequency supplied external oscillator (signal generator) external clock frequency supplied external crystal oscillator external clock frequency on-chip used external clock frequency on-chip bootloader used initial code download Tcy(clk) tCHCX tCLCX tCLCH tCHCL
Parameter
Conditions
Unit
clock cycle time clock HIGH time clock time clock rise time clock fall time rise time fall time fall time
Tcy(clk) Tcy(clk)
1000
Port pins (except P0[2] P0[3])
I2C-bus pins (P0[2] P0[3])
Parameters valid over operating temperature range unless otherwise specified. capacitance from
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Timing
0.45
0.2VDD 0.2VDD tCHCL tCLCX Tcy(clk)
002aaa907
tCHCX tCLCH
External clock timing
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Package outline
LQFP64: plastic profile quad flat package; leads; body SOT314-2
index detail
scale
DIMENSIONS original dimensions) UNIT max. 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 10.1 10.1 0.75 0.45 0.12 1.45 1.05 1.45 1.05
12.15 12.15 11.85 11.85
Note Plastic metal protrusions 0.25 maximum side included. OUTLINE VERSION SOT314-2 REFERENCES 136E10 JEDEC MS-026 JEITA EUROPEAN PROJECTION
ISSUE DATE 00-01-19 03-02-25
Package outline SOT314-2 (LQFP64)
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Abbreviations
Table Acronym AMBA FIFO GPIO JTAG SRAM UART Abbreviations Description Analog-to-Digital Converter Advanced Microcontroller Architecture Advanced Peripheral Central Processing Unit Digital-to-Analog Converter Debug Communications Channel First First General Purpose Input/Output Input/Output Joint Test Action Group Phase-Locked Loop Pulse Width Modulator Random Access Memory Serial Peripheral Interface Static Random Access Memory Synchronous Serial Interface Synchronous Serial Port Transistor-Transistor Logic Universal Asynchronous Receiver/Transmitter
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Revision history
Table Revision history Release date 20071210 Data sheet status Product data sheet Change notice Supersedes LPC2114_2124_5 Document LPC2114_2124_6 Modifications:
format this data sheet been redesigned comply with identity guidelines Semiconductors. Legal texts have been adapted company name where appropriate. Type number LPC2114FBD64/01 been added. Type number LPC2124FBD64/01 been added. Details introduced with devices peripherals/features (Fast Ports, SSP, CRP) enhancements existing ones (UART0/1, Timers, ADC, SPI) added. Power consumption measurements LPC2114/2124/01 devices added. Product data sheet Product data sheet Product data Preliminary data Preliminary data LPC2114_2124_4 LPC2114_2124-03 LPC2114_2124-02 LPC2114_2124-01
LPC2114_2124_5 LPC2114_2124_4 LPC2114_2124-03 LPC2114_2124-02 LPC2114_2124-01
20060629 20060621 20041222 20040202 20031118
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Legal information
13.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
Product status[3] Development Qualification Production
Definition This document contains data from objective specification product development. This document contains data from preliminary specification. This document contains product specification.
Please consult most recently issued document before initiating completing design. term `short data sheet' explained section "Definitions". product status device(s) described this document have changed since this document published differ case multiple devices. latest product status information available Internet http://www.nxp.com.
13.2 Definitions
Draft document draft version only. content still under internal review subject formal approval, which result modifications additions. Semiconductors does give representations warranties accuracy completeness information included herein shall have liability consequences such information. Short data sheet short data sheet extract from full data sheet with same product type number(s) title. short data sheet intended quick reference only should relied upon contain detailed full information. detailed full information relevant full data sheet, which available request local Semiconductors sales office. case inconsistency conflict with short data sheet, full data sheet shall prevail.
result personal injury, death severe property environmental damage. Semiconductors accepts liability inclusion and/or Semiconductors products such equipment applications therefore such inclusion and/or customer's risk. Applications Applications that described herein these products illustrative purposes only. Semiconductors makes representation warranty that such applications will suitable specified without further testing modification. Limiting values Stress above more limiting values defined Absolute Maximum Ratings System 60134) cause permanent damage device. Limiting values stress ratings only operation device these other conditions above those given Characteristics sections this document implied. Exposure limiting values extended periods affect device reliability. Terms conditions sale Semiconductors products sold subject general terms conditions commercial sale, published including those pertaining warranty, intellectual property rights infringement limitation liability, unless explicitly otherwise agreed writing Semiconductors. case inconsistency conflict between information this document such terms conditions, latter will prevail. offer sell license Nothing this document interpreted construed offer sell products that open acceptance grant, conveyance implication license under copyrights, patents other industrial intellectual property rights.
13.3 Disclaimers
General Information this document believed accurate reliable. However, Semiconductors does give representations warranties, expressed implied, accuracy completeness such information shall have liability consequences such information. Right make changes Semiconductors reserves right make changes information published this document, including without limitation specifications product descriptions, time without notice. This document supersedes replaces information supplied prior publication hereof. Suitability Semiconductors products designed, authorized warranted suitable medical, military, aircraft, space life support equipment, applications where failure malfunction Semiconductors product reasonably expected
13.4 Trademarks
Notice: referenced brands, product names, service names trademarks property their respective owners. I2C-bus logo trademark B.V.
Contact information
additional information, please visit: http://www.nxp.com sales office addresses, send email salesaddresses@nxp.com
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Contents
6.5.1 6.7.1 6.7.2 6.8.1 6.8.2 6.9.1 6.9.2 6.10 6.10.1 6.11 6.11.1 6.11.2 6.12 6.12.1 6.13 6.13.1 6.13.2 6.14 6.14.1 6.15 6.15.1 6.16 General description Features features brought LPC2114/2124/01 devices features common devices Ordering information Ordering options Block diagram Pinning information Pinning description Functional description Architectural overview. On-chip flash program memory On-chip static RAM. Memory map. Interrupt controller Interrupt sources. connect block General purpose parallel (GPIO) Fast Features Features added with Fast GPIO registers available LPC2114/2124/01 only 10-bit Features features available LPC2114/2124/01 only UARTs Features UART features available LPC2114/2124/01 only I2C-bus serial controller Features serial controller. Features Features available LPC2114/2124/01 only controller (LPC2114/2124/01 only). Features General purpose timers Features Features available LPC2114/2124/01 only Watchdog timer. Features Real-time clock Features Pulse width modulator 6.16.1 Features 6.17 System control 6.17.1 Crystal oscillator. 6.17.2 PLL. 6.17.3 Reset wake-up timer 6.17.4 Code security (Code Read Protection CRP) 6.17.5 External interrupt inputs 6.17.6 Memory mapping control 6.17.7 Power control 6.17.8 6.18 Emulation debugging. 6.18.1 EmbeddedICE 6.18.2 Embedded trace. 6.18.3 RealMonitor Limiting values Static characteristics Power consumption measurements LPC2114/01 LPC2124/01 Dynamic characteristics Timing Package outline Abbreviations Revision history Legal information 13.1 Data sheet status 13.2 Definitions 13.3 Disclaimers. 13.4 Trademarks Contact information Contents.
Please aware that important notices concerning this document product(s) described herein, have been included section `Legal information'.
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