Single-chip 32-bit microcontrollers; ISP/IAP flash with 16/32/64

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Single-chip 32-bit microcontrollers; ISP/IAP flash with 16/32/64

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LPC2104/2105/2106
Single-chip 32-bit microcontrollers; ISP/IAP flash with 16/32/64
Rev. June 2008 Product data sheet
UART based 16/32-bit ARM7TDMI-S with real-time emulation embedded trace support, together with embedded high speed flash memory. 128-bit wide memory interface unique accelerator architecture enable 32-bit code execution maximum clock rate. critical code size applications, alternative 16-bit Thumb mode reduces code more than with minimal performance penalty. their tiny size power consumption, these microcontrollers ideal applications where miniaturization requirement, such access control point-of-sale. With wide range serial communications interfaces on-chip SRAM options they very well suited communication gateways protocol converters, soft modems, voice recognition imaging, providing both large buffer size high processing power. Various 32-bit timers, channels, GPIO lines make these microcontrollers particularly suitable industrial control medical systems. Remark: Throughout data sheet, term LPC2104/2105/2106 will apply devices with without suffixes. Suffixes will used differentiate devices whenever they include features.
Features
features implemented LPC2104/2105/2106/01 devices
Fast GPIO port enables port toggling times faster than original device also allows port read time regardless function. UART include fractional baud rate generator, autobauding capabilities, handshake flow-control fully implemented hardware. Buffered serial controller supporting SPI, 4-wire SSI, Microwire formats. programmable data length master mode enhancement. Diversified Code Read Protection (CRP) enables different security levels implemented. General purpose timers operate external event counters.
common features
16/32-bit ARM7TDMI-S processor. 16/32/64 on-chip static RAM. on-chip flash program memory. 128-bit-wide interface/accelerator enables high speed operation.
Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
In-System Programming (ISP) In-Application Programming (IAP) on-chip bootloader software. Flash programming takes line. Single sector full chip erase takes Vectored Interrupt Controller with configurable priorities vector addresses. EmbeddedICE-RT interface enables breakpoints watch points. Interrupt service routines continue execute whilst foreground task debugged with on-chip RealMonitor software. Embedded Trace Macrocell enables non-intrusive high speed real-time tracing instruction execution. Multiple serial interfaces including UARTs (16C550), Fast I2C-bus (400 kbit/s), SPI. 32-bit timers capture/compare channels), unit outputs), Real Time Clock Watchdog. thirty-two tolerant general purpose pins tiny LQFP48 package. maximum clock available from programmable on-chip Phase-Locked Loop with settling time on-chip crystal oscillator should have operating range MHz. power modes, Idle Power-down. Processor wake-up from Power-down mode external interrupt. Individual enable/disable peripheral functions power optimization. Dual power supply: operating voltage range 1.65 1.95 (1.8 power supply range (3.3 with tolerant pads.
Ordering information
Table Ordering information Package Name LPC2104BBD48 LPC2104FBD48/00 LPC2104FBD48/01 LPC2105BBD48 LPC2105FBD48/00 LPC2105FBD48/01 LPC2106BBD48 LPC2106FBD48 LQFP48 LQFP48 LQFP48 LQFP48 LQFP48 LQFP48 LQFP48 LQFP48 Description plastic profile quad flat package; leads; body plastic profile quad flat package; leads; body plastic profile quad flat package; leads; body plastic profile quad flat package; leads; body plastic profile quad flat package; leads; body plastic profile quad flat package; leads; body plastic profile quad flat package; leads; body plastic profile quad flat package; leads; body Version SOT313-2 SOT313-2 SOT313-2 SOT313-2 SOT313-2 SOT313-2 SOT313-2 SOT313-2 Type number
LPC2104_2105_2106_7
B.V. 2008. rights reserved.
Product data sheet
Rev. June 2008
Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
Ordering information .continued Package Name Description plastic profile quad flat package; leads; body plastic profile quad flat package; leads; body Version SOT313-2 SOT313-2 SOT619-1 LQFP48 LQFP48
Table
Type number LPC2106FBD48/00 LPC2106FBD48/01 LPC2106FHN48
HVQFN48 plastic thermal enhanced very thin quad flat package; leads; terminals; body 0.85 HVQFN48 plastic thermal enhanced very thin quad flat package; leads; terminals; body 0.85 HVQFN48 plastic thermal enhanced very thin quad flat package; leads; terminals; body 0.85
LPC2106FHN48/00
SOT619-1
LPC2106FHN48/01
SOT619-1
Ordering options
Table Ordering options Flash memory Temperature range Type number LPC2104BBD48 LPC2104FBD48/00 LPC2104FBD48/01 LPC2105BBD48 LPC2105FBD48/00 LPC2105FBD48/01 LPC2106BBD48 LPC2106FBD48 LPC2106FBD48/00 LPC2106FBD48/01 LPC2106FHN48 LPC2106FHN48/00 LPC2106FHN48/01
LPC2104_2105_2106_7
B.V. 2008. rights reserved.
Product data sheet
Rev. June 2008
Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
Block diagram
TMS(2) TDI(2) RTCK TRST(2) TCK(2) TDO(2) XTAL2 XTAL1 RESET
EMULATION TRACE MODULE
LPC2104/2105/2106
TEST/DEBUG INTERFACE
system clock
SYSTEM FUNCTIONS VECTORED INTERRUPT CONTROLLER
ARM7TDMI-S
VDD(3V3) VDD(1V8)
HIGH-SPEED GPIO(3) PINS TOTAL
BRIDGE
ARM7 LOCAL
AMBA Advanced High-performance (AHB)
INTERNAL SRAM CONTROLLER
INTERNAL FLASH CONTROLLER
DECODER BRIDGE DIVIDER
16/32/64 SRAM
FLASH
Advanced Peripheral (APB) EINT[2:0](1) EXTERNAL INTERRUPTS I2C-BUS SERIAL INTERFACE SCL(1) SDA(1) SCK(1) CAPTURE/ COMPARE TIMER 0/TIMER SPI/SSP(3) SERIAL INTERFACE MOSI(1) MISO(1) SSEL(1) TXD[1:0](1) RXD[1:0](1)
CAP0[2:0](1) CAP1[3:0](1) MAT0[2:0](1) MAT1[3:0](1)
P0[31:0]
GENERAL PURPOSE
UART0/UART1
PWM[6:1](1)
PWM0
WATCHDOG TIMER
DSR1(1), CTS1(1), RTS1(1), DTR1(1), DCD1(1), RI1(1)
REAL-TIME CLOCK
SYSTEM CONTROL
002aaa412
Shared with GPIO. When test/debug interface used, GPIO/other functions sharing these pins available. Available LPC2104/2105/2106/01 only.
Block diagram
LPC2104_2105_2106_7
B.V. 2008. rights reserved.
Product data sheet
Rev. June 2008
Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
Pinning information
Pinning
P0.16/EINT0/MAT0.2 P0.12/DSR1/MAT1.0 P0.11/CTS1/CAP1.1 P0.10/RTS1/CAP1.0 P0.24/PIPESTAT1 P0.23/PIPESTAT0 P0.22/TRACECLK P0.9/RXD1/PWM6 P0.8/TXD1/PWM4 P0.7/SSEL/PWM2 DBGSEL RTCK n.c. P0.0/TXD0/PWM1 P0.1/RXD0/PWM3 P0.30/TRACEPKT3/TDI P0.31/EXTIN0/TDO VDD(3V3) P0.2/SCL/CAP0.0 n.c. P0.3/SDA/MAT0.0 P0.4/SCK/CAP0.1 P0.5/MISO/MAT0.1 P0.6/MOSI/CAP0.2
002aaa411
P0.13/DTR1/MAT1.1
P0.17/CAP1.2/TRST
P0.26/TRACESYNC
P0.18/CAP1.3/TMS
P0.14/DCD1/EINT1
P0.19/MAT1.2/TCK P0.20/MAT1.3/TDI P0.21/PWM5/TDO n.c. VDD(1V8) RESET P0.27/TRACEPKT0/TRST P0.28/TRACEPKT1/TMS
LPC2104/2105/2106
P0.29/TRACEPKT2/TCK XTAL1 XTAL2
configuration identical LQFP48 packages.
configuration (LQFP48)
LPC2104_2105_2106_7
P0.25/PIPESTAT2
P0.15/RI1/EINT2
VDD(3V3)
n.c.
B.V. 2008. rights reserved.
Product data sheet
Rev. June 2008
Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
P0.16/EINT0/MAT0.2
terminal index area P0.19/MAT1.2/TCK P0.20/MAT1.3/TDI P0.21/PWM5/TDO n.c. VDD(1V8) RESET P0.27/TRACEPKT0/TRST P0.28/TRACEPKT1/TMS
P0.12/DSR1/MAT1.0 P0.11/CTS1/CAP1.1 P0.10/RTS1/CAP1.0 P0.24/PIPESTAT1 P0.23/PIPESTAT0 P0.22/TRACECLK P0.9/RXD1/PWM6 P0.8/TXD1/PWM4 P0.7/SSEL/PWM2 DBGSEL RTCK n.c. P0.6/MOSI/CAP0.2
002aac440
P0.13/DTR1/MAT1.1
P0.17/CAP1.2/TRST
VDD(3V3) P0.26/TRACESYNC P0.3/SDA/MAT0.0 P0.4/SCK/CAP0.1
P0.18/CAP1.3/TMS
P0.14/DCD1/EINT1
LPC2104/2105/2106
P0.29/TRACEPKT2/TCK XTAL1 XTAL2 P0.0/TXD0/PWM1 P0.1/RXD0/PWM3 P0.30/TRACEPKT3/TDI P0.31/EXTIN0/TDO VDD(3V3) P0.2/SCL/CAP0.0 n.c. P0.5/MISO/MAT0.1
Transparent view
configuration identical LPC2106FHN48, LPC2106FHN48/00, LPC2106FHN48/01.
configuration (HVQFN48)
LPC2104_2105_2106_7
P0.25/PIPESTAT2
P0.15/RI1/EINT2
n.c.
B.V. 2008. rights reserved.
Product data sheet
Rev. June 2008
Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
description
Table Symbol P0.0 P0.31 description Type Description Port Port 32-bit bidirectional port with individual direction controls each bit. operation port pins depends upon function selected Connect Block. P0.0 Port TXD0 Transmitter output UART PWM1 Pulse Width Modulator output P0.1 Port RXD0 Receiver input UART PWM3 Pulse Width Modulator output P0.2 Port output open-drain. I2C-bus clock input/output. Open-drain output (for I2C-bus compliance). CAP0.0 Capture input Timer channel P0.3 Port output open-drain. I2C-bus data input/output. Open-drain output (for I2C-bus compliance). MAT0.0 Match output Timer channel output open-drain. P0.4 Port Serial clock SPI/SSP[3]. Clock output from master input slave. CAP0.1 Capture input Timer channel P0.5 Port MISO Master Slave SPI/SSP[3]. Data input SPI/SSP master data output from SPI/SSP slave. MAT0.1 Match output Timer channel P0.6 Port MOSI Master Slave SPI/SSP[3]. Data output from SPI/SSP master data input SPI/SSP slave. CAP0.2 Capture input Timer channel P0.7 Port SSEL Slave Select SPI/SSP[3]. Selects SPI/SSP interface slave. PWM2 Pulse Width Modulator output P0.8 Port TXD1 Transmitter output UART PWM4 Pulse Width Modulator output P0.9 Port RXD1 Receiver input UART PWM6 Pulse Width Modulator output P0.10 Port RTS1 Request Send output UART CAP1.0 Capture input Timer channel
P0.0/TXD0/PWM1
13[1]
P0.1/RXD0/PWM3
14[1]
P0.2/SCL/CAP0.0
18[2]
P0.3/SDA/MAT0.0
21[2]
P0.4/SCK/CAP0.1
22[1]
P0.5/MISO/MAT0.1
23[1]
P0.6/MOSI/CAP0.2
24[1]
P0.7/SSEL/PWM2
28[1]
P0.8/TXD1/PWM4
29[1]
P0.9/RXD1/PWM6
30[1]
P0.10/RTS1/CAP1.0
35[1]
LPC2104_2105_2106_7
B.V. 2008. rights reserved.
Product data sheet
Rev. June 2008
Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
Table Symbol
description .continued 36[1] Type Description P0.11 Port CTS1 Clear Send input UART CAP1.1 Capture input Timer channel P0.12 Port DSR1 Data Ready input UART MAT1.0 Match output Timer channel P0.13 Port DTR1 Data Terminal Ready output UART MAT1.1 Match output Timer channel P0.14 Port DCD1 Data Carrier Detect input UART EINT1 External interrupt input. P0.15 Port Ring Indicator input UART EINT2 External interrupt input. P0.16 Port EINT0 External interrupt input. MAT0.2 Match output Timer channel P0.17 Port CAP1.2 Capture input Timer channel TRST Test Reset JTAG interface, primary JTAG group. P0.18 Port CAP1.3 Capture input Timer channel Test Mode Select JTAG interface, primary JTAG group. P0.19 Port MAT1.2 Match output Timer channel Test Clock JTAG interface, primary JTAG group. P0.20 Port MAT1.3 Match output Timer channel Test Data JTAG interface, primary JTAG group. P0.21 Port PWM5 Pulse Width Modulator output Test Data JTAG interface, primary JTAG group. P0.22 Port TRACECLK Trace Clock. Standard port with internal pull-up. P0.23 Port PIPESTAT0 Pipeline Status, Standard port with internal pull-up. P0.24 Port PIPESTAT1 Pipeline Status, Standard port with internal pull-up. P0.25 Port PIPESTAT2 Pipeline Status, Standard port with internal pull-up.
B.V. 2008. rights reserved.
P0.11/CTS1/CAP1.1
P0.12/DSR1/MAT1.0
37[1]
P0.13/DTR1/MAT1.1
41[1]
P0.14/DCD1/EINT1
44[1]
P0.15/RI1/EINT2
45[1]
P0.16/EINT0/MAT0.2
46[1]
P0.17/CAP1.2/TRST
47[1]
P0.18/CAP1.3/TMS
48[1]
P0.19/MAT1.2/TCK
1[1]
P0.20/MAT1.3/TDI
2[1]
P0.21/PWM5/TDO
3[1]
P0.22/TRACECLK P0.23/PIPESTAT0 P0.24/PIPESTAT1 P0.25/PIPESTAT2
32[4] 33[4] 34[4] 38[4]
LPC2104_2105_2106_7
Product data sheet
Rev. June 2008
Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
Table Symbol
description .continued 39[4] 8[4] Type 9[4] 10[4] Description P0.26 Port TRACESYNC Trace Synchronization Standard port with internal pull-up. P0.27 Port TRACEPKT0 Trace Packet, Standard port with internal pull-up. TRST Test Reset JTAG interface, secondary JTAG group. P0.28 Port TRACEPKT1 Trace Packet, Standard port with internal pull-up. Test Mode Select JTAG interface, secondary JTAG group. P0.29 Port TRACEPKT2 Trace Packet, Standard port with internal pull-up. Test Clock JTAG interface, secondary JTAG group. This clock must slower than clock (CCLK) JTAG interface operate. P0.30 Port TRACEPKT3 Trace Packet, Standard port with internal pull-up. Test Data JTAG interface, secondary JTAG group. P0.31 Port EXTIN0 External Trigger Input. Standard port with internal pull-up. Test Data JTAG interface, secondary JTAG group. Returned Test Clock output: Extra signal added JTAG port. Assists debugger synchronization when processor frequency varies. Also used during debug mode entry select primary secondary JTAG pins with 48-pin package. Bidirectional with internal pull-up. Debug Select: When LOW, part operates normally. When HIGH, debug mode entered. Input with internal pull-down. external reset input; this resets device, causing ports peripherals take their default states, processor execution begin address with hysteresis, tolerant. input oscillator circuit internal clock generator circuits. output from oscillator amplifier. ground: reference. core power supply; this power supply voltage internal circuitry. power supply; this power supply voltage ports. connected; these pins connected 48-pin package.
P0.26/TRACESYNC P0.27/TRACEPKT0/ TRST
P0.28/TRACEPKT1/
P0.29/TRACEPKT2/
P0.30/TRACEPKT3/
15[4]
P0.31/EXTIN0/TDO
16[4]
RTCK
26[4]
DBGSEL RESET
6[5]
XTAL1 XTAL2 VDD(1V8) VDD(3V3) n.c.
tolerant providing digital functions with levels hysteresis slew rate control. Open-drain tolerant digital pad, compatible with I2C-bus specification. requires external pull-up provide output functionality. Open-drain configuration applies functions this pin. interface available LPC2104/2105/2106/01 only. tolerant with built-in pull-up resistor providing digital functions with levels hysteresis slew rate control. pull-up resistor's value ranges from tolerant providing digital input (with levels hysteresis) function only.
LPC2104_2105_2106_7
B.V. 2008. rights reserved.
Product data sheet
Rev. June 2008
Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
Functional description
Architectural overview
ARM7TDMI-S general purpose 32-bit microprocessor, which offers high performance very power consumption. architecture based Reduced Instruction Computer (RISC) principles, instruction related decode mechanism much simpler than those microprogrammed Complex Instruction Computers. This simplicity results high instruction throughput impressive real-time interrupt response from small cost-effective processor core. Pipeline techniques employed that parts processing memory systems operate continuously. Typically, while instruction being executed, successor being decoded, third instruction being fetched from memory. ARM7TDMI-S processor also employs unique architectural strategy known Thumb, which makes ideally suited high-volume applications with memory restrictions, applications where code density issue. idea behind Thumb that super-reduced instruction set. Essentially, ARM7TDMI-S processor instruction sets:
standard 32-bit set. 16-bit Thumb set.
Thumb set's 16-bit instruction length allows approach twice density standard code while retaining most ARM's performance advantage over traditional 16-bit processor using 16-bit registers. This possible because Thumb code operates same 32-bit register code. Thumb code able provide code size ARM, performance equivalent processor connected 16-bit memory system.
On-chip flash program memory
LPC2104/2105/2106 incorporate flash memory system. This memory used both code data storage. Programming flash memory accomplished several ways. programmed System serial port. application program also erase and/or program flash while application running, allowing great degree flexibility data storage field firmware upgrades, etc. When on-chip bootloader used, flash memory available user code. LPC2104/2105/2106 flash memory provides minimum 100000 erase/write cycles years data retention.
On-chip static
On-chip static used code and/or data storage. SRAM accessed bit, bit, bit. LPC2104/2105/2106 provide 16/32/64 static RAM, respectively.
LPC2104_2105_2106_7
B.V. 2008. rights reserved.
Product data sheet
Rev. June 2008
Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
Memory
LPC2104/2105/2106 memory maps incorporate several distinct regions, shown following figures. addition, interrupt vectors re-mapped allow them reside either flash memory (the default) on-chip static RAM. This described Section 6.18 "System control".
PERIPHERALS 3.75 PERIPHERALS
0xFFFF FFFF 0xF000 0000 0xEFFF FFFF 0xE000 0000 0xDFFF FFFF
RESERVED ADDRESS SPACE
0xC000 0000
BOOT BLOCK (RE-MAPPED FROM ON-CHIP FLASH MEMORY)
0x8000 0000 0x7FFF FFFF 0x7FFF E000 0x7FFF DFFF
RESERVED ADDRESS SPACE 0x4001 0000 0x4000 FFFF ON-CHIP STATIC (LPC2106) 0x4000 8000 0x4000 7FFF ON-CHIP STATIC (LPC2105) ON-CHIP STATIC (LPC2104) FAST GPIO REGISTERS(1) 0x4000 0000 0x3FFF FFFF 0x3FFF C000 0x4000 4000 0x4000 3FFF
RESERVED ADDRESS SPACE
0x0002 0000 0x0001 FFFF ON-CHIP FLASH MEMORY 0x0000 0000
002aad666
LPC2104/2105/2106/01 only.
LPC2104/2105/2106 memory
LPC2104_2105_2106_7
B.V. 2008. rights reserved.
Product data sheet
Rev. June 2008
Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
Interrupt controller
Vectored Interrupt Controller (VIC) accepts Interrupt Request (IRQ) inputs categorizes, them FIQ, vectored IRQ, non-vectored defined programmable settings. programmable assignment scheme means that priorities interrupts from various peripherals dynamically assigned adjusted. Fast Interrupt reQuest (FIQ) highest priority. more than request assigned FIQ, combines requests produce signal processor. fastest possible latency achieved when only request classified FIQ, because then service routine simply start dealing with that device. more than request assigned class, service routine read word from that identifies which source(s) (are) requesting interrupt. Vectored IRQs have middle priority. Sixteen interrupt requests assigned this category. interrupt requests assigned vectored slots, among which slot highest priority slot lowest. Non-vectored IRQs have lowest priority. combines requests from vectored non-vectored IRQs produce signal processor. service routine start reading register from jumping there. vectored IRQs requesting, provides address highest-priority requesting IRQs service routine, otherwise provides address default routine that shared non-vectored IRQs. default routine read another register what IRQs active.
6.5.1 Interrupt sources
Table lists interrupt sources each peripheral function. Each peripheral device interrupt line connected Vectored Interrupt Controller, have several internal interrupt flags. Individual interrupt flags also represent more than interrupt source.
Table Block Core Core Timer Timer UART Interrupt sources Flag(s) Watchdog Interrupt (WDINT) Reserved software interrupts only EmbeddedICE, DbgCommRx EmbeddedICE, DbgCommTx Match (MR0, MR1, MR2, MR3) Capture (CR0, CR1, CR2) Match (MR0, MR1, MR2, MR3) Capture (CR0, CR1, CR2, CR3) Line Status (RLS) Transmit Holding Register empty (THRE) Data Available (RDA) Character Time-out Indicator (CTI) Auto-Baud Time-Out (ABTO)[1] Auto-Baud (ABEO)[1] channel
LPC2104_2105_2106_7
B.V. 2008. rights reserved.
Product data sheet
Rev. June 2008
Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
Interrupt sources .continued Flag(s) Line Status (RLS) Transmit Holding Register empty (THRE) Data Available (RDA) Character Time-out Indicator (CTI) Modem Status Interrupt (MSI) Auto-Baud Time-Out (ABTO)[1] Auto-Baud (ABEO)[1] channel
Table Block UART
PWM0 I2C-bus System Control System Control System Control
Match (MR0, MR1, MR2, MR3, MR4, MR5, MR6) (state change) SSP[1] SPIF, MODF (SPI) TXRIS, RXRIS, RTRIS, RORRIS (SSP)[1] reserved Lock (PLOCK) RTCCIF (Counter Increment), RTCALF (Alarm) External Interrupt (EINT0) External Interrupt (EINT1) External Interrupt (EINT2)
Available LPC2104/2105/2106/01 only.
connect block
connect block allows selected pins microcontroller have more than function. Configuration registers control multiplexers allow connection between chip peripherals. Peripherals should connected appropriate pins prior being activated, prior related interrupt(s) being enabled. Activity enabled peripheral function that mapped related should considered undefined. Control Module contains registers shown Table
Table Address 0xE002 C000 0xE002 C004 control module registers Name PINSEL0 PINSEL1 Description function select register function select register Access Read/Write Read/Write
function select register (PINSEL0 0xE002 C000)
PINSEL0 register controls functions pins settings listed Table direction control IODIR register effective only when GPIO function selected pin. other functions, direction controlled automatically. Settings other than those shown Table reserved, should used
LPC2104_2105_2106_7
B.V. 2008. rights reserved.
Product data sheet
Rev. June 2008
Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
function select register (PINSEL0 0xE002 C000) name P0.0 Value Function GPIO Port (UART PWM1 GPIO Port (UART PWM3 GPIO Port (I2C-bus) Capture (Timer GPIO Port (I2C-bus) Match (Timer GPIO Port (SPI/SSP) Capture (Timer GPIO Port MISO (SPI/SSP) Match (Timer GPIO Port MOSI (SPI/SSP) Capture (Timer GPIO Port SSEL (SPI/SSP) PWM2 GPIO Port (UART PWM4 GPIO Port (UART PWM6 GPIO Port 0.10 (UART Capture (Timer GPIO Port 0.11 (UART Capture (Timer GPIO Port 0.12 (UART Match (Timer Value after reset
Table PINSEL0
P0.1
P0.2
P0.3
P0.4
11:10
P0.5
13:12
P0.6
15:14
P0.7
17:16
P0.8
19:18
P0.9
21:20
P0.10
23:22
P0.11
25:24
P0.12
LPC2104_2105_2106_7
B.V. 2008. rights reserved.
Product data sheet
Rev. June 2008
Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
function select register (PINSEL0 0xE002 C000) .continued name P0.13 Value Function GPIO Port 0.13 (UART Match (Timer GPIO Port 0.14 (UART EINT1 GPIO Port 0.15 (UART EINT2 Value after reset
Table PINSEL0 27:26
29:28
P0.14
31:30
P0.15
function select register (PINSEL1 0xE002 C004)
PINSEL1 register controls functions pins settings listed Table direction control IODIR register effective only when GPIO function selected pin. other functions direction controlled automatically. Remark: primary JTAG port trace port selected only through DBGSEL reset (Debug mode). Function control pins P0[31:17] effective only when DBGSEL input pulled during reset.
Table PINSEL1 function select register (PINSEL1 0xE002 C004) name P0.16 Value 11:10 13:12 15:14 17:16 19:18 21:20 23:22 P0.17 P0.18 P0.19 P0.20 P0.21 P0.22 P0.23 P0.24 P0.25 P0.26 P0.27 Function GPIO Port 0.16 EINT0 Match (Timer GPIO Port 0.17 Capture (Timer GPIO Port 0.18 Capture (Timer GPIO Port 0.19 Match (Timer GPIO Port 0.20 Match (Timer GPIO Port 0.21 PWM5 GPIO Port 0.22 GPIO Port 0.23 GPIO Port 0.24 GPIO Port 0.25 GPIO Port 0.26 GPIO Port 0.27 TRST Value after reset
LPC2104_2105_2106_7
B.V. 2008. rights reserved.
Product data sheet
Rev. June 2008
Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
function select register (PINSEL1 0xE002 C004) .continued name P0.28 P0.29 P0.30 P0.31 Value Function GPIO Port 0.28 GPIO Port 0.29 GPIO Port 0.30 GPIO Port 0.31 Value after reset
Table PINSEL1 25:24 27:26 29:28 31:30
General purpose parallel
Device pins that connected specific peripheral function controlled GPIO registers. Pins dynamically configured inputs outputs. Separate registers allow setting clearing number outputs simultaneously. value output register read back, well current state port pins.
6.9.1 Features
Direction control individual bits. Separate control output clear. default inputs after reset.
6.9.2 Features added with Fast GPIO registers available LPC2104/2105/2106/01 only
Fast GPIO registers relocated local fastest possible
timing, enabling port toggling times faster than earlier LPC2000 devices.
Mask registers allow treating sets port bits group, leaving other bits
unchanged.
Fast GPIO registers byte addressable. Entire port value written instruction. Ports accessible either legacy group registers (GPIOs) group
registers providing accelerated port access (Fast GPIOs).
6.10 UARTs
LPC2104/2105/2106 each contain UARTs. UART provides full modem control handshake interface, other provides only transmit receive data lines.
6.10.1 Features
LPC2104_2105_2106_7
byte Receive Transmit FIFOs Register locations conform 16C550 industry standard Receiver FIFO trigger points Built-in baud rate generator
B.V. 2008. rights reserved.
Product data sheet
Rev. June 2008
Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
Standard modem interface signals included UART
6.10.2 UART features available LPC2104/2105/2106/01 only
Compared previous LPC2000 microcontrollers, UARTs LPC2104/2105/2106/01 introduce fractional baud rate generator both UARTs, enabling these microcontrollers achieve standard baud rates such 115200 with crystal frequency above MHz. addition, auto-CTS/RTS flow-control functions fully implemented hardware.
Fractional baud rate generator enables standard baud rates such 115200
achieved with crystal frequency above MHz.
Autobauding. Auto-CTS/RTS flow-control fully implemented hardware. 6.11 I2C-bus serial controller
bidirectional inter-IC control using only wires: serial clock line (SCL), serial data line (SDA). Each device recognized unique address operate either receiver-only device (e.g. driver transmitter with capability both receive send information (such memory). Transmitters and/or receivers operate either master slave mode, depending whether chip initiate data transfer only addressed. multi-master bus, controlled more than master connected I2C-bus implemented LPC2104/2105/2106 supports rate kbit/s (Fast I2C-bus).
6.11.1 Features
Standard compliant interface. Easy configure Master, Slave Master/Slave. Programmable clocks allow versatile rate control. Bidirectional data transfer between masters slaves. Multi-master central master). Arbitration between simultaneously transmitting masters without corruption serial
data bus.
Serial clock synchronization allows devices with different rates communicate
serial bus.
Serial clock synchronization used handshake mechanism suspend
resume serial transfer.
I2C-bus used test diagnostic purposes.
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6.12 serial controller
full duplex serial interface, designed able handle multiple masters slaves connected given bus. Only single master single slave communicate interface during given data transfer. During data transfer master always sends byte data slave, slave always sends byte data master.
6.12.1 Features
Compliant with Serial Peripheral Interface (SPI) specification. Synchronous, serial, full duplex communication. Combined master slave. Maximum data rate eighth input clock rate.
6.12.2 Features available LPC2104/2105/2106/01 only
Selectable transfer width eight frame. When interface used Master mode, SSEL needed (can
used different function).
6.13 controller (LPC2104/2015/2106/01 only)
controller capable operation SPI, 4-wire SSI, Microwire bus. interact with multiple masters slaves bus. Only single master single slave communicate during given data transfer. Data transfers principle full duplex, with frames four bits data flowing from master slave from slave master. Because peripherals share same physical pins, possible have both these peripherals active same time. Application switch from back.
6.13.1 Features
Compatible with Motorola's SPI, Texas Instrument's 4-wire SSI, National
Semiconductor's Microwire buses.
Synchronous serial communication. Master slave operation. 8-frame FIFOs both transmit receive. Four bits frame.
6.14 General purpose timers
Timer designed count cycles peripheral clock (PCLK) optionally generate interrupts perform other actions specified timer values, based four match registers. also includes four capture inputs trap timer value when input signal transitions, optionally generating interrupt.
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6.14.1 Features
32-bit Timer/Counter with programmable 32-bit Prescaler. four (Timer three (Timer 32-bit capture channels, that take
snapshot timer value when input signal transitions. capture event also optionally generate interrupt.
Four 32-bit match registers that allow:
Continuous operation with optional interrupt generation match. Stop timer match with optional interrupt generation. Reset timer match with optional interrupt generation.
four (Timer three (Timer external outputs corresponding match
registers, with following capabilities: match. HIGH match. Toggle match. nothing match.
6.14.2 Features available LPC2104/2105/2106/01 only
LPC2104/2105/2106/01 count external events capture inputs external pulse lasts least half period PCLK. this configuration, unused capture lines selected regular timer capture inputs used external interrupts.
Timer count cycles either peripheral clock (PCLK) externally supplied
clock.
When counting cycles externally supplied clock, only timer's capture
inputs selected timer's clock. rate such clock limited PCLK/ Duration HIGH/LOW levels selected input cannot shorter than 1/(2PCLK).
6.15 Watchdog timer
purpose Watchdog reset microcontroller within reasonable amount time enters erroneous state. When enabled, Watchdog will generate system reset user program fails `feed' reload) Watchdog within predetermined amount time.
6.15.1 Features
Internally resets chip periodically reloaded. Debug mode. Enabled software requires hardware reset watchdog reset/interrupt
disabled.
Incorrect/Incomplete feed sequence causes reset/interrupt enabled. Flag indicate watchdog reset.
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Programmable 32-bit timer with internal pre-scaler. Selectable time period from (Tcy(PCLK) (Tcy(PCLK) multiples
Tcy(PCLK)
6.16 Real time clock
Real Time Clock (RTC) designed provide counters measure time when normal idle operating mode selected. been designed little power, making suitable battery powered systems where running continuously (Idle mode).
6.16.1 Features
Measures passage time maintain calendar clock. Ultra Power design support battery powered systems. Provides Seconds, Minutes, Hours, Month, Month, Year, Week,
Year.
Programmable Reference Clock Divider allows adjustment match
various crystal frequencies.
6.17 Pulse width modulator
based standard Timer block inherits features, although only function pinned LPC2104/2105/2106. Timer designed count cycles peripheral clock (PCLK) optionally generate interrupts perform other actions when specified timer values occur, based seven match registers. also includes four capture inputs save timer value when input signal transitions, optionally generate interrupt when those events occur. function addition these features, based match register events. ability separately control rising falling edge locations allows used more applications. instance, multi-phase motor control typically requires three non-overlapping outputs with individual control three pulse widths positions. match registers used provide single edge controlled output. match register (MR0) controls cycle rate, resetting count upon match. other match register controls edge position. Additional single edge controlled outputs require only match register each, since repetition rate same outputs. Multiple single edge controlled outputs will have rising edge beginning each cycle, when match occurs. Three match registers used provide output with both edges controlled. Again, match register controls cycle rate. other match registers control edge positions. Additional double edge controlled outputs require only match registers each, since repetition rate same outputs.
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With double edge controlled outputs, specific match registers control rising falling edge output. This allows both positive going pulses (when rising edge occurs prior falling edge), negative going pulses (when falling edge occurs prior rising edge).
6.17.1 Features
Seven match registers allow single edge controlled three double edge
controlled outputs, both types.
match registers also allow:
Continuous operation with optional interrupt generation match. Stop timer match with optional interrupt generation. Reset timer match with optional interrupt generation.
Supports single edge controlled and/or double edge controlled outputs. Single
edge controlled outputs HIGH beginning each cycle unless output constant LOW. Double edge controlled outputs have either edge occur position within cycle. This allows both positive going negative going pulses.
Pulse period width number timer counts. This allows complete
flexibility trade-off between resolution repetition rate. outputs will occur same repetition rate.
Double edge controlled outputs programmed either positive going
negative going pulses.
Match register updates synchronized with pulse outputs prevent generation
erroneous pulses. Software must "release" match values before they become effective.
used standard timer mode enabled. 32-bit Timer/Counter with programmable 32-bit Prescaler. 6.18 System control
6.18.1 Crystal oscillator
oscillator supports crystals range MHz. oscillator output frequency called FOSC processor clock frequency referred CCLK purposes rate equations, etc. FOSC CCLK same value unless running connected. Refer Section 6.18.2 "PLL" additional information.
6.18.2
accepts input clock frequency range MHz. input frequency multiplied into range with Current Controlled Oscillator (CCO). multiplier integer value from practice, multiplier value cannot higher than this family microcontrollers upper frequency limit CPU). operates range MHz, there additional divider loop keep within frequency range while providing desired output frequency. output divider divide
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produce output clock. Since minimum output divider value insured that output duty cycle.The turned bypassed following chip Reset enabled software. program must configure activate PLL, wait Lock, then connect clock source. settling time
6.18.3 Reset wake-up timer
Reset sources LPC2104/2105/2106: RESET Watchdog Reset. RESET Schmitt trigger input with additional glitch filter. Assertion chip Reset source starts wake-up timer (see wake-up timer description below), causing internal chip reset remain asserted until external Reset de-asserted, oscillator running, fixed number clocks have passed, on-chip flash controller completed initialization. When internal Reset removed, processor begins executing address which Reset vector. that point, processor peripheral registers have been initialized predetermined values. wake-up timer ensures that oscillator other analog functions required chip operation fully functional before processor allowed execute instructions. This important power types Reset, whenever aforementioned functions turned reason. Since oscillator other functions turned during Power-down mode, wake-up processor from Power-down mode makes wake-up timer. wake-up timer monitors crystal oscillator means checking whether safe begin code execution. When power applied chip, some event caused chip exit Power-down mode, some time required oscillator produce signal sufficient amplitude drive clock logic. amount time depends many factors, including rate ramp case power on), type crystal electrical characteristics quartz crystal used), well other external circuitry (e.g. capacitors), characteristics oscillator itself under existing ambient conditions.
6.18.4 Code security (Code Read Protection CRP)
This feature LPC2104/2105/2106/01 allows user enable different levels security system that access on-chip flash JTAG restricted. When needed, invoked programming specific pattern into dedicated flash location. commands affected CRP. There three levels Code Read Protection: CRP1 disables access chip JTAG allows partial flash update (excluding flash sector using limited commands. This mode useful when required flash field updates needed sectors erased. CRP2 disables access chip JTAG only allows full flash erase update using reduced commands.
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Running application with level CRP3 selected fully disables access chip JTAG pins ISP. This mode effectively disables override using P0[14] pin, too. user's application provide needed) flash update mechanism using calls call reinvoke command enable flash update UART
CAUTION level three Code Read Protection (CRP3) selected, future factory testing performed device.
6.18.5 External interrupt inputs
LPC2104/2105/2106 include three external interrupt inputs selectable functions. external interrupt inputs optionally used wake processor from Power-down mode.
6.18.6 Memory mapping control
Memory mapping control alters mapping interrupt vectors that appear beginning address 0x0000 0000. Vectors mapped bottom on-chip flash memory, on-chip static RAM. This allows code running different memory spaces have control interrupts.
6.18.7 Power control
LPC2104/2105/2106 support reduced power modes: Idle mode Power-down mode. Idle mode, execution instructions suspended until either Reset interrupt occurs. Peripheral functions continue operation during Idle mode generate interrupts cause processor resume execution. Idle mode eliminates power used processor itself, memory systems related controllers, internal buses. Power-down mode, oscillator shut down chip receives internal clocks. processor state registers, peripheral registers, internal SRAM values preserved throughout Power-down mode logic levels chip output pins remain static. Power-down mode terminated normal operation resumed either Reset certain specific interrupts that able function without clocks. Since dynamic operation chip suspended, Power-down mode reduces chip power consumption nearly zero. power controlled each peripheral individually allowing peripherals turned they needed application resulting additional power savings.
6.18.8
divider determines relationship between processor clock (CCLK) clock used peripheral devices (PCLK). divider serves purposes. first provide peripherals with desired PCLK that they operate speed chosen processor. order achieve this, slowed down processor clock rate. Because must work properly power-up (and timing cannot altered does work since divider control registers reside APB), default condition reset
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processor clock rate. second purpose divider allow power savings when application does require peripherals full processor rate. Because divider connected output, remains active running) during Idle mode.
6.19 Emulation debugging
LPC2104/2105/2106 support emulation debugging JTAG serial port. trace port allows tracing program execution. Each these functions requires trade-off debugging features versus device pins. Because LPC2104/2105/2106 provided small package, there room permanently assigned JTAG Trace pins. alternate JTAG port allows option debug functions assigned pins used primary JTAG port (see Section 6.8).
6.19.1 EmbeddedICE
Standard EmbeddedICE logic provides on-chip debug support. debugging target system requires host computer running debugger software EmbeddedICE protocol convertor. EmbeddedICE protocol convertor converts Remote Debug Protocol commands JTAG data needed access core. core Debug Communication Channel function built-in. debug communication channel allows program running target communicate with host debugger another separate host without stopping program flow even entering debug state. debug communication channel accessed co-processor program running ARM7TDMI-S core. debug communication channel allows JTAG port used sending receiving data without affecting normal program flow. debug communication channel data control registers mapped addresses EmbeddedICE logic. JTAG clock (TCK) must slower than clock (CCLK) JTAG interface operate.
6.19.2 Embedded trace
Since LPC2104/2105/2106 have significant amounts on-chip memory, possible determine processor core operating simply observing external pins. Embedded Trace Macrocell (ETM) provides real-time trace capability deeply embedded processor cores. outputs information about processor execution trace port. connected directly core main AMBA system bus. compresses trace information exports through narrow trace port. external trace port analyzer must capture trace information under software debugger control. Instruction trace trace) shows flow execution processor provides list instructions that were executed. Instruction trace significantly compressed only broadcasting branch addresses well status signals that indicate pipeline status cycle cycle basis. Trace information generation controlled selecting trigger resource. Trigger resources include address comparators, counters sequencers. Since trace information compressed software debugger requires static image code being executed. Self-modifying code cannot traced because this restriction.
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6.19.3 RealMonitor
RealMonitor configurable software module, developed Inc., which enables real time debug. lightweight debug monitor that runs background while users debug their foreground application. communicates with host using (Debug Communications Channel), which present EmbeddedICE logic. LPC2104/2105/2106 contain specific configuration RealMonitor software programmed into on-chip flash memory.
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Limiting values
Table Limiting values accordance with Absolute Maximum Rating System (IEC 60134).[1] Symbol VDD(1V8) VDD(3V3) Tstg Ptot(pack) Parameter supply voltage (1.8 supply voltage (3.3 input voltage supply current ground current storage temperature total power dissipation (per package) electrostatic discharge voltage based package heat transfer, device power consumption human body model pins machine model pins
[12] [11]
Conditions
-0.5 -0.5 -0.5 -0.5
+2.5 +3.6 +6.0 VDD(3V3) +150
Unit
tolerant pins other pins
[4][5] [4][6] [7][8] [8][9] [10]
Vesd
-2000 -200
+2000 +200
following applies Table This product includes circuitry specifically designed protection internal devices from damaging effects excessive static charge. Nonetheless, suggested that conventional precautions taken avoid applying greater than rated maximum. Parameters valid over operating temperature range unless otherwise specified. voltages with respect unless otherwise noted. Internal rail. External rail. Including voltage outputs 3-state mode. Only valid when VDD(3V3) supply voltage present. exceed supply pin. peak current limited times corresponding maximum current. ground pin.
[10] Dependent package type. [11] Human body model: equivalent discharging capacitor through series resistor. [12] Machine model: equivalent discharging capacitor through 0.75 coil series resistor.
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Static characteristics
Table Static characteristics Tamb commercial applications, unless otherwise specified. Symbol VDD(1V8) VDD(3V3) Ilatch Vhys IOHS IOLS Parameter supply voltage (1.8 supply voltage (3.3 LOW-state input current HIGH-state input current OFF-state output current latch-up current input voltage output voltage HIGH-state input voltage LOW-state input voltage hysteresis voltage HIGH-state output voltage LOW-state output voltage HIGH-state output current LOW-state output current HIGH-state short-circuit output current LOW-state short-circuit output current pull-down current pull-up current VDD(3V3) VDD(3V3) applies DBGSEL VDD(3V3) LPC2104/2105/2106/01 pull-up current VDD(3V3)
[10] [9][10]
Conditions
1.65
[4][5]
Typ[1]
1.95 VDD(3V3)
Unit
Standard port pins, RESET, RTCK, DBGSEL pull-up VDD(3V3); pull-down VDD(3V3); pull-up/down -(0.5VDD(3V3)) (1.5VDD(3V3));
output active
VDD(3V3)
LPC2104/2105/2106 LPC2104/2105/2106/00
[10] [9][10]
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Table Static characteristics .continued Tamb commercial applications, unless otherwise specified. Symbol IDD(act) Parameter active mode supply current Conditions VDD(1V8) CCLK MHz; Tamb code Typ[1] Unit LPC2104/2105/2106 LPC2104/2105/2106/00 power consumption
while(1){}
executed from flash; peripherals enabled PCONP register configured IDD(pd) Power-down mode supply current VDD(1V8) Tamb VDD(1V8) Tamb LPC2104/2105/2106/01 power consumption IDD(act) active mode supply current VDD(1V8) CCLK MHz; Tamb code
while(1){}
executed from flash; peripherals enabled PCONP register configured run[11] IDD(idle) Idle mode supply current VDD(1V8) CCLK MHz; Tamb executed from flash; peripherals enabled PCONP register configured run[11] IDD(pd) Power-down mode supply current VDD(1V8) Tamb VDD(1V8) Tamb I2C-bus pins Vhys HIGH-state input voltage LOW-state input voltage hysteresis voltage LOW-state output voltage input leakage current IOLS VDD(3V3)
[12]
0.7VDD(3V3)
0.3VDD(3V3)
0.5VDD(3V3)
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Table Static characteristics .continued Tamb commercial applications, unless otherwise specified. Symbol Vi(XTAL1) Vo(XTAL2) Parameter input voltage XTAL1 output voltage XTAL2 Conditions Typ[1] Unit Oscillator pins
Typical ratings guaranteed. values listed room temperature (+25 °C), nominal supply voltages. Internal rail. External rail. Including voltage outputs 3-state mode. VDD(3V3) supply voltages must present. 3-state outputs into 3-state mode when VDD(3V3) grounded. Accounts voltage drop supply lines. Allowed long current limit does exceed maximum current allowed device. Minimum condition maximum condition
[10] Applies P0[31:22]. [11] enabled disabled PCONP register (see LPC2104/2105/2106 user manual). [12] VSS.
Power consumption measurements LPC2104/2105/2106/01
power consumption measurements represent typical values given conditions. peripherals were enabled through PCONP register, these measurements peripherals were configured run. Power measurements with peripherals enabled were performed with enabled disabled. Peripherals were disabled through PCONP register. Refer LPC2104/2105/2106 User Manual description PCONP register.
IDD(act) (mA) peripherals enabled peripherals disabled
002aad709
frequency (MHz)
Test conditions: Active mode entered executing code from on-chip flash; PCLK CCLK/4; Tamb core voltage
LPC2104_2105_2106_7
Typical LPC2104/2105/2106/01 IDD(act) measured different frequencies
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IDD(act) (mA)
002aad710
1.65
1.70
1.75
1.80
1.85
1.90 1.95 core voltage
Test conditions: Active mode entered executing code from on-chip flash; PCLK CCLK/4; Tamb peripherals enabled.
Typical LPC2104/2105/2106/01 IDD(act) measured different core voltages
15.0 IDD(idle) (mA) 10.0
002aad711
peripherals enabled peripherals disabled
frequency (MHz)
Test conditions: Idle mode entered executing code from on-chip flash; PCLK CCLK/4; Tamb core voltage
Typical LPC2104/2105/2106/01 IDD(idle) measured different frequencies
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15.0 IDD(idle) (mA) 10.0
002aad712
1.65
1.70
1.75
1.80
1.85
1.90 1.95 core voltage
Test conditions: Idle mode entered executing code from on-chip flash; PCLK CCLK/4; Tamb peripherals enabled.
Typical LPC2104/2105/2106/01 IDD(idle) measured different core voltages
IDD(act) (mA)
002aad713
temperature (°C)
Test conditions: Active mode entered executing code from on-chip flash; PCLK CCLK/4; core voltage peripherals disabled.
Typical LPC2104/2105/2106/01 IDD(act) measured different temperatures
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IDD(Idle) (mA)
002aad714
temperature (°C)
Test conditions: Idle mode entered executing code from on-chip flash; PCLK CCLK/4; core voltage peripherals disabled.
Typical LPC2104/2105/2106/01 IDD(idle) measured different temperatures
IDD(pd) (µA) 1.95 1.80 1.65
002aad715
temperature (°C)
Test conditions: Power-down mode entered executing code from on-chip flash.
Typical LPC2104/2105/2106/01 core power-down current IDD(pd) measured different temperatures Table Typical LPC2104/2105/2106/01 peripheral power consumption Idle mode Core voltage Tamb measurements PCLK CCLK/4 Peripheral Timer Timer UART UART CCLK 0.258 0.254 0.494 0.561
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Typical LPC2104/2105/2106/01 peripheral power consumption Idle mode
.continued
Table Peripheral PWM0 I2C-bus
CCLK 0.511 0.078 0.060 0.109 0.377
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Dynamic characteristics
Table Dynamic characteristics Tamb commercial applications, industrial applications; VDD(1V8), VDD(3V3) over specified ranges.[1] Symbol External clock fosc oscillator frequency supplied external oscillator (signal generator) external clock frequency supplied external crystal oscillator external clock frequency on-chip used external clock frequency on-chip bootloader used initial code download Tcy(clk) tCHCX tCLCX tCLCH tCHCL I2C-bus
Parameter
Conditions
Unit
clock cycle time clock HIGH time clock time clock rise time clock fall time rise time fall time pins (P0.2 P0.3) fall time
Tcy(clk) Tcy(clk)
1000
Port pins (except P0.2 P0.3)
Parameters valid over operating temperature range unless otherwise specified. capacitance from
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Timing
tCHCL
tCLCX Tcy(clk)
tCHCX tCLCH
002aaa907
External clock timing (with amplitude least Vi(RMS)
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Package outline
LQFP48: plastic profile quad flat package; leads; body SOT313-2
detail
index
scale
DIMENSIONS original dimensions) UNIT max. 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 9.15 8.85 9.15 8.85 0.75 0.45 0.12 0.95 0.55 0.95 0.55
Note Plastic metal protrusions 0.25 maximum side included. OUTLINE VERSION SOT313-2 REFERENCES 136E05 JEDEC MS-026 JEITA EUROPEAN PROJECTION
ISSUE DATE 00-01-19 03-02-25
Package outline SOT313-2 (LQFP48)
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HVQFN48: plastic thermal enhanced very thin quad flat package; leads; terminals; body 0.85
SOT619-1
terminal index area
detail
terminal index area DIMENSIONS original dimensions) UNIT A(1) max. 0.05 0.00 0.30 0.18 5.25 4.95 5.25 4.95
scale 0.05 0.05
Note Plastic metal protrusions 0.075 maximum side included. OUTLINE VERSION SOT619-1 REFERENCES -JEDEC MO-220 JEITA -EUROPEAN PROJECTION ISSUE DATE 01-08-08 02-10-18
Package outline SOT619-1 (HVQFN48)
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Abbreviations
Table Acronym AMBA FIFO GPIO SRAM UART Abbreviations Description Advanced Microcontroller Architecture Peripheral Central Processing Unit Debug Communications Channel First First General Purpose Input/Output Phase-Locked Loop Pulse Width Modulator Random Access Memory Serial Peripheral Interface Synchronous Serial Interface Synchronous Serial Port Static Random Access Memory Transistor-Transistor Logic Universal Asynchronous Receiver/Transmitter
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Revision history
Table Revision history Release date 20080620 Data sheet status Product data sheet Change notice Supersedes LPC2104_2105_2106_6 Document LPC2104_2105_2106_7 Modifications:
format this data sheet been redesigned comply with identity guidelines Semiconductors. Legal texts have been adapted company name where appropriate. Section "Ordering information"; corrected temperature range LPC2104FBD48/00, LPC2105FBD48/00. Parts LPC2104FBD48/01, LPC2105FBD48/01, LPC2106BBD48, LPC2106FBD48/01, LPC2106FHN48/01 added. Description features added. LPC2104/2105/2106/01 power consumption measurements added. Maximum frequency fosc external oscillator external crystal updated. Figure "External clock timing (with amplitude least Vi(RMS) mV)" updated. Condition IOHS IOLS updated Table "Static characteristics". Product data sheet Product data Product data Product data Product data Product data LPC2104_2105_2106-05 LPC2104_2105_2106-04 LPC2104_2105_2106-03 LPC2104_2105_2106-02 LPC2104_2105_2106-01
LPC2104_2105_2106_6 LPC2104_2105_2106-05 LPC2104_2105_2106-04 LPC2104_2105_2106-03 LPC2104_2105_2106-02 LPC2104_2105_2106-01
20060725 20041222 20040205 20031007 20030611 20030425
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Legal information
13.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
Product status[3] Development Qualification Production
Definition This document contains data from objective specification product development. This document contains data from preliminary specification. This document contains product specification.
Please consult most recently issued document before initiating completing design. term `short data sheet' explained section "Definitions". product status device(s) described this document have changed since this document published differ case multiple devices. latest product status information available Internet http://www.nxp.com.
13.2 Definitions
Draft document draft version only. content still under internal review subject formal approval, which result modifications additions. Semiconductors does give representations warranties accuracy completeness information included herein shall have liability consequences such information. Short data sheet short data sheet extract from full data sheet with same product type number(s) title. short data sheet intended quick reference only should relied upon contain detailed full information. detailed full information relevant full data sheet, which available request local Semiconductors sales office. case inconsistency conflict with short data sheet, full data sheet shall prevail.
result personal injury, death severe property environmental damage. Semiconductors accepts liability inclusion and/or Semiconductors products such equipment applications therefore such inclusion and/or customer's risk. Applications Applications that described herein these products illustrative purposes only. Semiconductors makes representation warranty that such applications will suitable specified without further testing modification. Limiting values Stress above more limiting values defined Absolute Maximum Ratings System 60134) cause permanent damage device. Limiting values stress ratings only operation device these other conditions above those given Characteristics sections this document implied. Exposure limiting values extended periods affect device reliability. Terms conditions sale Semiconductors products sold subject general terms conditions commercial sale, published including those pertaining warranty, intellectual property rights infringement limitation liability, unless explicitly otherwise agreed writing Semiconductors. case inconsistency conflict between information this document such terms conditions, latter will prevail. offer sell license Nothing this document interpreted construed offer sell products that open acceptance grant, conveyance implication license under copyrights, patents other industrial intellectual property rights.
13.3 Disclaimers
General Information this document believed accurate reliable. However, Semiconductors does give representations warranties, expressed implied, accuracy completeness such information shall have liability consequences such information. Right make changes Semiconductors reserves right make changes information published this document, including without limitation specifications product descriptions, time without notice. This document supersedes replaces information supplied prior publication hereof. Suitability Semiconductors products designed, authorized warranted suitable medical, military, aircraft, space life support equipment, applications where failure malfunction Semiconductors product reasonably expected
13.4 Trademarks
Notice: referenced brands, product names, service names trademarks property their respective owners. I2C-bus logo trademark B.V.
Contact information
more information, please visit: http://www.nxp.com sales office addresses, please send email salesaddresses@nxp.com
LPC2104_2105_2106_7
B.V. 2008. rights reserved.
Product data sheet
Rev. June 2008
Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
Contents
6.5.1 6.9.1 6.9.2 General description Features features implemented LPC2104/2105/2106/01 devices. common features Ordering information Ordering options Block diagram Pinning information Pinning description Functional description Architectural overview. On-chip flash program memory On-chip static RAM. Memory map. Interrupt controller Interrupt sources. connect block function select register (PINSEL0 0xE002 C000). function select register (PINSEL1 0xE002 C004). General purpose parallel I/O. Features Features added with Fast GPIO registers available LPC2104/2105/2106/01 only UARTs Features UART features available LPC2104/2105/2106/01 only I2C-bus serial controller Features serial controller. Features Features available LPC2104/2105/2106/01 only controller (LPC2104/2015/2106/01 only) Features General purpose timers Features Features available LPC2104/2105/2106/01 only Watchdog timer. Features Real time clock 6.16.1 Features 6.17 Pulse width modulator 6.17.1 Features 6.18 System control 6.18.1 Crystal oscillator. 6.18.2 PLL. 6.18.3 Reset wake-up timer 6.18.4 Code security (Code Read Protection CRP) 6.18.5 External interrupt inputs 6.18.6 Memory mapping control 6.18.7 Power control 6.18.8 6.19 Emulation debugging. 6.19.1 EmbeddedICE 6.19.2 Embedded trace. 6.19.3 RealMonitor Limiting values Static characteristics Power consumption measurements LPC2104/2105/2106/01 Dynamic characteristics Timing Package outline Abbreviations Revision history Legal information 13.1 Data sheet status 13.2 Definitions 13.3 Disclaimers. 13.4 Trademarks Contact information Contents.
6.10 6.10.1 6.10.2 6.11 6.11.1 6.12 6.12.1 6.12.2 6.13 6.13.1 6.14 6.14.1 6.14.2 6.15 6.15.1 6.16
Please aware that important notices concerning this document product(s) described herein, have been included section `Legal information'.
B.V. 2008.
rights reserved.
more information, please visit: http://www.nxp.com sales office addresses, please send email salesaddresses@nxp.com Date release: June 2008 Document identifier: LPC2104_2105_2106_7

Single-chip 32-bit microcontrollers; ISP/IAP flash with 16/32/64

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