Single-chip 16-bit/32-bit microcontrollers; kB/16 kB/32 flash with ISP

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Single-chip 16-bit/32-bit microcontrollers; kB/16 kB/32 flash with ISP

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LPC2101/02/03
Single-chip 16-bit/32-bit microcontrollers; kB/16 kB/32 flash with ISP/IAP, fast ports 10-bit
Rev. June 2009 Product data sheet
LPC2101/02/03 microcontrollers based 16-bit/32-bit ARM7TDMI-S with real-time emulation that combines microcontroller with embedded high-speed flash memory. 128-bit wide memory interface unique accelerator architecture enable 32-bit code execution maximum clock rate. critical performance interrupt service routines algorithms, this increases performance over Thumb mode. critical code size applications, alternative 16-bit Thumb mode reduces code more than with minimal performance penalty. their tiny size power consumption, LPC2101/02/03 ideal applications where miniaturization requirement. blend serial communications interfaces ranging from multiple UARTs, I2C-buses, combined with on-chip SRAM kB/4 kB/8 make these devices very well suited communication gateways protocol converters. superior performance also makes these devices suitable math coprocessors. Various 32-bit 16-bit timers, improved 10-bit ADC, features through output match timers, fast GPIO lines with nine edge level sensitive external interrupt pins make these microcontrollers particularly suitable industrial control medical systems.
Features
Enhanced features
Enhanced features available parts LPC2101/02/03 labelled Revision higher: Deep power-down mode with option retain SRAM memory and/or RTC. Three levels flash Code Read Protection (CRP) implemented.
features
16-bit/32-bit ARM7TDMI-S microcontroller tiny LQFP48 HVQFN48 packages. kB/4 kB/8 on-chip static kB/16 kB/32 on-chip flash program memory. 128-bit wide interface/accelerator enables high-speed operation. ISP/IAP on-chip bootloader software. Single flash sector full chip erase programming bytes EmbeddedICE-RT offers real-time debugging with on-chip RealMonitor software. 10-bit provides eight analog inputs, with conversion times 2.44 channel dedicated result registers minimize interrupt overhead. 32-bit timers/external event counters with combined seven capture seven compare channels.
Semiconductors
LPC2101/02/03
Single-chip 16-bit/32-bit microcontrollers
16-bit timers/external event counters with combined three capture seven compare channels. power Real-Time Clock (RTC) with independent power dedicated clock input. Multiple serial interfaces including UARTs (16C550), Fast I2C-buses (400 kbit/s), with buffering variable data length capabilities. Vectored interrupt controller with configurable priorities vector addresses. thirty-two, tolerant fast general purpose pins. edge level sensitive external interrupt pins available. maximum clock available from programmable on-chip with possible input frequency settling time On-chip integrated oscillator operates with external crystal range from MHz. Power saving modes include Idle mode, Power-down mode with active, Power-down mode. Individual enable/disable peripheral functions well peripheral clock scaling additional power optimization. Processor wake-up from Power-down Deep power-down (Revision higher) mode external interrupt RTC.
Ordering information
Table Ordering information Package Name LPC2101FBD48 LPC2102FBD48 LPC2103FBD48 LPC2102FHN48 LPC2103FHN48 LQFP48 LQFP48 LQFP48 HVQFN48 HVQFN48 Description plastic profile quad flat package; leads; body plastic profile quad flat package; leads; body plastic profile quad flat package; leads; body plastic thermal enhanced very thin quad flat package; leads; terminals; body 0.85 plastic thermal enhanced very thin quad flat package; leads; terminals; body 0.85 plastic thermal enhanced very thin quad flat package; leads; terminals; body 0.85 Version SOT313-2 SOT313-2 SOT313-2 SOT619-7 SOT619-7 SOT778-3 Type number
LPC2103FHN48H HVQFN48
Ordering options
Table Ordering options Flash memory inputs inputs inputs inputs inputs inputs Temperature range (°C)
B.V. 2009. rights reserved.
Type number LPC2101FBD48 LPC2102FBD48 LPC2103FBD48 LPC2102FHN48 LPC2103FHN48 LPC2103FHN48H
LPC2101_02_03_4
Product data sheet
Rev. June 2009
Semiconductors
LPC2101/02/03
Single-chip 16-bit/32-bit microcontrollers
Block diagram
TRST XTAL2 VDD(3V3) VDD(1V8) XTAL1
LPC2101/2102/2103
HIGH SPEED GENERAL PURPOSE
TEST/DEBUG INTERFACE
P0[31:0]
BOOT
ARM7TDMI-S
BRIDGE
system clock
SYSTEM FUNCTIONS
ARM7 local
VECTORED INTERRUPT CONTROLLER
AMBA (Advanced High-performance Bus) INTERNAL SRAM CONTROLLER MEMORY ACCELERATOR
kB/4 SRAM
kB/16 FLASH
BRIDGE (ARM peripheral bus)
EINT2 EINT0(1) CAP0(1) CAP1(1) CAP2(1) MAT0(1) MAT1(1) MAT2(1) MAT3(1) AD0[7:0]
EXTERNAL INTERRUPTS
I2C-BUS SERIAL INTERFACES
SCL0, SCL1(1) SDA0, SDA1(1) SCK0, SCK1(1)
CAPTURE/COMPARE EXTERNAL COUNTER TIMER 0/TIMER TIMER 2/TIMER
SERIAL INTERFACES
MOSI0, MOSI1(1) MISO0, MISO1(1) SSEL0, SSEL1(1) TXD0, TXD1(1)
UART0/UART1
RXD0, RXD1(1)
DSR1, CTS1, RTS1, DTR1 DCD1,
RTCX1 RTCX2 VBAT
P0[31:0]
GENERAL PURPOSE
REAL-TIME CLOCK
WATCHDOG TIMER
SYSTEM CONTROL
002aab814
Pins shared with GPIO.
Block diagram
LPC2101_02_03_4
B.V. 2009. rights reserved.
Product data sheet
Rev. June 2009
Semiconductors
LPC2101/02/03
Single-chip 16-bit/32-bit microcontrollers
Pinning information
Pinning
P0.12/DSR1/MAT1.0/AD0.5 P0.11/CTS1/CAP1.1/AD0.4 P0.10/RTS1/CAP1.0/AD0.3 P0.24/AD0.2 P0.23/AD0.1 P0.22/AD0.0 VSSA P0.9/RXD1/MAT2.2 P0.8/TXD1/MAT2.1 P0.7/SSEL0/MAT2.0 DBGSEL RTCK RTCX2 P0.0/TXD0/MAT3.1 P0.1/RXD0/MAT3.2 P0.30/TDI/MAT3.3 P0.31/TDO VDD(3V3) P0.2/SCL0/CAP0.0 RTCX1 P0.3/SDA0/MAT0.0 P0.4/SCK0/CAP0.1 P0.5/MISO0/MAT0.1 P0.6/MOSI0/CAP0.2
002aab821
P0.14/DCD1/SCK1/EINT1
P0.16/EINT0/MAT0.2
P0.13/DTR1/MAT1.1
P0.18/CAP1.3/SDA1
P0.17/CAP1.2/SCL1
P0.15/RI1/EINT2
P0.19/MAT1.2/MISO1 P0.20/MAT1.3/MOSI1 P0.21/SSEL1/MAT3.0 VBAT VDD(1V8) P0.27/TRST/CAP2.0 P0.28/TMS/CAP2.1
LPC2101FBD48 LPC2102FBD48 LPC2103FBD48
P0.29/TCK/CAP2.2 XTAL1 XTAL2
configuration (LQFP48)
LPC2101_02_03_4
P0.25/AD0.6
P0.26/AD0.7
VDD(3V3)
VDDA
B.V. 2009. rights reserved.
Product data sheet
Rev. June 2009
Semiconductors
LPC2101/02/03
Single-chip 16-bit/32-bit microcontrollers
terminal index area P0.19/MAT1.2/MISO1 P0.20/MAT1.3/MOSI1 P0.21/SSEL1/MAT3.0 VBAT VDD(1V8) P0.27/TRST/CAP2.0 P0.28/TMS/CAP2.1
P0.12/DSR1/MAT1.0/AD0.5 P0.11/CTS1/CAP1.1/AD0.4 P0.10/RTS1/CAP1.0/AD0.3 P0.24/AD0.2 P0.23/AD0.1 P0.22/AD0.0 VSSA P0.9/RXD1/MAT2.2 P0.8/TXD1/MAT2.1 P0.7/SSEL0/MAT2.0 DBGSEL RTCK RTCX2 P0.6/MOSI0/CAP0.2
002aad918
P0.14/DCD1/SCK1/EINT1
P0.16/EINT0/MAT0.2
P0.13/DTR1/MAT1.1
P0.18/CAP1.3/SDA1
P0.17/CAP1.2/SCL1
P0.15/RI1/EINT2
VDD(3V3) P0.26/AD0.7 P0.3/SDA0/MAT0.0 P0.4/SCK0/CAP0.1
LPC2102FHN48 LPC2103FHN48 LPC2103FHN48H
P0.29/TCK/CAP2.2 XTAL1 XTAL2 P0.0/TXD0/MAT3.1 P0.1/RXD0/MAT3.2 P0.30/TDI/MAT3.3 P0.31/TDO VDD(3V3) P0.2/SCL0/CAP0.0 RTCX1 P0.5/MISO0/MAT0.1
Transparent view
configuration (HVQFN48)
LPC2101_02_03_4
P0.25/AD0.6
VDDA
B.V. 2009. rights reserved.
Product data sheet
Rev. June 2009
Semiconductors
LPC2101/02/03
Single-chip 16-bit/32-bit microcontrollers
description
Table Symbol P0.0 P0.31 description Type Description Port Port 32-bit port with individual direction controls each bit. total pins Port used general purpose bidirectional digital I/Os while P0.31 output only pin. operation port pins depends upon function selected connect block. P0.0 General purpose input/output digital pin. TXD0 Transmitter output UART0. MAT3.1 output Timer P0.1 General purpose input/output digital pin. RXD0 Receiver input UART0. MAT3.2 output Timer P0.2 General purpose input/output digital pin. Output open-drain. SCL0 I2C0 clock Input/output. Open-drain output (for I2C-bus compliance). CAP0.0 Capture input Timer channel P0.3 General purpose input/output digital pin. Output open-drain. SDA0 I2C0 data input/output. Open-drain output (for I2C-bus compliance). MAT0.0 output Timer channel Output open-drain. P0.4 General purpose input/output digital pin. SCK0 Serial clock SPI0. clock output from master input slave. CAP0.1 Capture input Timer channel P0.5 General purpose input/output digital pin. MISO0 Master Slave SPI0. Data input master data output from slave. MAT0.1 output Timer channel P0.6 General purpose input/output digital pin. MOSI0 Master Slave SPI0. Data output from master data input slave. CAP0.2 Capture input Timer channel P0.7 General purpose input/output digital pin. SSEL0 Slave Select SPI0. Selects interface slave. MAT2.0 output Timer channel P0.8 General purpose input/output digital pin. TXD1 Transmitter output UART1. MAT2.1 output Timer channel P0.9 General purpose input/output digital pin. RXD1 Receiver input UART1. MAT2.2 output Timer channel P0.10 General purpose input/output digital pin. RTS1 Request Send output UART1. CAP1.0 Capture input Timer channel AD0.3 input
P0.0/TXD0/ MAT3.1
13[1]
P0.1/RXD0/ MAT3.2
14[1]
P0.2/SCL0/ CAP0.0
18[2]
P0.3/SDA0/ MAT0.0
21[2]
P0.4/SCK0/ CAP0.1
22[1]
P0.5/MISO0/ MAT0.1
23[1]
P0.6/MOSI0/ CAP0.2
24[1]
P0.7/SSEL0/ MAT2.0
28[1]
P0.8/TXD1/ MAT2.1
29[1]
P0.9/RXD1/ MAT2.2
30[1]
P0.10/RTS1/ CAP1.0/AD0.3
35[3]
LPC2101_02_03_4
B.V. 2009. rights reserved.
Product data sheet
Rev. June 2009
Semiconductors
LPC2101/02/03
Single-chip 16-bit/32-bit microcontrollers
Table Symbol
description .continued 36[3] Type Description P0.11 General purpose input/output digital pin. CTS1 Clear Send input UART1. CAP1.1 Capture input Timer channel AD0.4 input P0.12 General purpose input/output digital pin. DSR1 Data Ready input UART1. MAT1.0 output Timer channel AD0.5 input P0.13 General purpose input/output digital pin. DTR1 Data Terminal Ready output UART1. MAT1.1 output Timer channel P0.14 General purpose input/output digital pin. DCD1 Data Carrier Detect input UART1. SCK1 Serial Clock SPI1. clock output from master input slave. EINT1 External interrupt input. P0.15 General purpose input/output digital pin. Ring Indicator input UART1. EINT2 External interrupt input. P0.16 General purpose input/output digital pin. EINT0 External interrupt input. MAT0.2 output Timer channel P0.17 General purpose input/output digital pin. output open-drain. CAP1.2 Capture input Timer channel SCL1 I2C1 clock Input/output. This open-drain output I2C1 function selected connect block. P0.18 General purpose input/output digital pin. output open-drain. CAP1.3 Capture input Timer channel SDA1 I2C1 data Input/output. This open-drain output I2C1 function selected connect block. P0.19 General purpose input/output digital pin. MAT1.2 output Timer channel MISO1 Master Slave SSP. Data input master data output from slave. P0.20 General purpose input/output digital pin. MAT1.3 output Timer channel MOSI1 Master Slave SSP. Data output from master data input slave. P0.21 General purpose input/output digital pin. SSEL1 Slave Select SPI1. Selects interface slave. MAT3.0 output Timer channel
P0.11/CTS1/ CAP1.1/AD0.4
P0.12/DSR1/ MAT1.0/AD0.5
37[3]
P0.13/DTR1/ MAT1.1
41[1]
P0.14/DCD1/ SCK1/EINT1
44[4][5]
P0.15/RI1/ EINT2
45[4]
P0.16/EINT0/ MAT0.2
46[4]
P0.17/CAP1.2/ SCL1
47[6]
P0.18/CAP1.3/ SDA1
48[6]
P0.19/MAT1.2/ MISO1
1[1]
P0.20/MAT1.3/ MOSI1
2[1]
P0.21/SSEL1/ MAT3.0
3[1]
LPC2101_02_03_4
B.V. 2009. rights reserved.
Product data sheet
Rev. June 2009
Semiconductors
LPC2101/02/03
Single-chip 16-bit/32-bit microcontrollers
Table Symbol
description .continued 32[3] 33[3] 34[3] 38[3] 39[3] 8[1] Type Description P0.22 General purpose input/output digital pin. AD0.0 input P0.23 General purpose input/output digital pin. AD0.1 input P0.24 General purpose input/output digital pin. AD0.2 input P0.25 General purpose input/output digital pin. AD0.6 input P0.26 General purpose input/output digital pin. AD0.7 input P0.27 General purpose input/output digital pin. TRST Test Reset JTAG interface. DBGSEL HIGH, this automatically configured with EmbeddedICE (Debug mode). CAP2.0 Capture input Timer channel P0.28 General purpose input/output digital pin. Test Mode Select JTAG interface. DBGSEL HIGH, this automatically configured with EmbeddedICE (Debug mode). CAP2.1 Capture input Timer channel P0.29 General purpose input/output digital pin. Test Clock JTAG interface. This clock must slower than clock (CCLK) JTAG interface operate. DBGSEL HIGH, this automatically configured with EmbeddedICE (Debug mode). CAP2.2 Capture input Timer channel P0.30 General purpose input/output digital pin. Test Data JTAG interface. DBGSEL HIGH, this automatically configured with EmbeddedICE (Debug mode). MAT3.3 output Timer P0.31 General purpose output only digital pin. Test Data JTAG interface. DBGSEL HIGH, this automatically configured with EmbeddedICE (Debug mode). Input oscillator circuit. Input voltage must exceed Output from oscillator circuit. Returned test clock output: Extra signal added JTAG port. Assists debugger synchronization when processor frequency varies. Bidirectional with internal pull-up. Input oscillator circuit internal clock generator circuits. Input voltage must exceed Output from oscillator amplifier. Debug select: When LOW, part operates normally. When externally pulled HIGH reset, P0.27 P0.31 configured JTAG port, part Debug mode[9]. Input with internal pull-down. External reset input: this resets device, causing ports peripherals take their default states processor execution begin address with hysteresis, tolerant.
B.V. 2009. rights reserved.
P0.22/AD0.0 P0.23/AD0.1 P0.24/AD0.2 P0.25/AD0.6 P0.26/AD0.7 P0.27/TRST/ CAP2.0
P0.28/TMS/ CAP2.1
9[1]
P0.29/TCK/ CAP2.2
10[1]
P0.30/TDI/ MAT3.3 15[1] P0.31/TDO 16[1] RTCX1 RTCX2 RTCK 20[7][8] 25[7][8] 26[7]
XTAL1 XTAL2 DBGSEL
LPC2101_02_03_4
Product data sheet
Rev. June 2009
Semiconductors
LPC2101/02/03
Single-chip 16-bit/32-bit microcontrollers
Table Symbol VSSA VDDA
description .continued Type Description Ground: reference. Analog ground: reference. This should nominally same voltage should isolated minimize noise error. Analog power supply: This should nominally same voltage VDD(3V3) should isolated minimize noise error. level this also provides voltage reference level ADC. core power supply: This power supply voltage internal circuitry on-chip PLL. power supply: This power supply voltage ports. power supply: this supplies power RTC.
VDD(1V8) VDD(3V3) VBAT
tolerant VDD(3V3) VDDA providing digital functions with levels hysteresis slew rate control. Open-drain tolerant VDD(3V3) VDDA digital I2C-bus specification compatible pad. requires external pull-up provide output functionality. Open-drain configuration applies functions that pin. tolerant VDD(3V3) VDDA providing digital (with levels hysteresis slew rate control) analog input function. configured input function, this utilizes built-in glitch filter that blocks pulses shorter than When configured input, digital section disabled. tolerant VDD(3V3) VDDA providing digital functions with levels hysteresis slew rate control. configured input function, this utilizes built-in glitch filter that blocks pulses shorter than level during reset P0.14 considered external hardware request start command handler. Open-drain tolerant VDD(3V3) VDDA digital I2C-bus specification compatible pad. requires external pull-up provide output functionality. Open-drain configuration applies only function that pin. provides special analog functionality. lowest power consumption, should left floating when used. LPC2101/02/03 User manual UM10161 details.
LPC2101_02_03_4
B.V. 2009. rights reserved.
Product data sheet
Rev. June 2009
Semiconductors
LPC2101/02/03
Single-chip 16-bit/32-bit microcontrollers
Functional description
Architectural overview
ARM7TDMI-S general purpose 32-bit microprocessor, which offers high performance very power consumption. architecture based Reduced Instruction Computer (RISC) principles, instruction related decode mechanism much simpler than those microprogrammed Complex Instruction Computers (CISC). This simplicity results high instruction throughput impressive real-time interrupt response from small cost-effective processor core. Pipeline techniques employed that parts processing memory systems operate continuously. Typically, while instruction being executed, successor being decoded, third instruction being fetched from memory. ARM7TDMI-S processor also employs unique architectural strategy known Thumb, which makes ideally suited high-volume applications with memory restrictions, applications where code density issue. idea behind Thumb that super-reduced instruction set. Essentially, ARM7TDMI-S processor instruction sets:
standard 32-bit set. 16-bit Thumb set.
Thumb set's 16-bit instruction length allows approach twice density standard code while retaining most ARM's performance advantage over traditional 16-bit processor using 16-bit registers. This possible because Thumb code operates same 32-bit register code. Thumb code able provide code size ARM, performance equivalent processor connected 16-bit memory system. particular flash implementation LPC2101/02/03 allows full speed execution also mode. recommended program performance critical short code sections mode. impact overall code size will minimal speed increased over Thumb mode.
On-chip flash program memory
LPC2101/02/03 incorporate flash memory system respectively. This memory used both code data storage. Programming flash memory accomplished several ways. programmed system serial port. application program also erase and/or program flash while application running, allowing great degree flexibility data storage field firmware upgrades, etc. entire flash memory available user code bootloader resides separate memory. LPC2101/02/03 flash memory provides minimum 100,000 erase/write cycles years data-retention memory.
LPC2101_02_03_4
B.V. 2009. rights reserved.
Product data sheet
Rev. June 2009
Semiconductors
LPC2101/02/03
Single-chip 16-bit/32-bit microcontrollers
On-chip static
On-chip static used code and/or data storage. SRAM accessed 8-bits, 16-bits, 32-bits. LPC2101/02/03 provide static RAM.
Memory
LPC2101/02/03 memory incorporates several distinct regions, shown Figure addition, interrupt vectors re-mapped allow them reside either flash memory (the default) on-chip static RAM. This described Section 6.17 "System control".
PERIPHERALS 3.75 PERIPHERALS
0xFFFF FFFF 0xF000 0000 0xE000 0000
RESERVED ADDRESS SPACE
0xC000 0000
BOOT BLOCK RESERVED ADDRESS SPACE
0x8000 0000 0x7FFF FFFF 0x7FFF E000 0x7FFF DFFF 0x4000 2000 0x4000 1FFF
ON-CHIP STATIC (LPC2103) ON-CHIP STATIC (LPC2102) ON-CHIP STATIC (LPC2101) RESERVED ADDRESS SPACE ON-CHIP NON-VOLATILE MEMORY (LPC2103) ON-CHIP NON-VOLATILE MEMORY (LPC2102) ON-CHIP NON-VOLATILE MEMORY (LPC2101)
0x4000 1000 0x4000 0FFF 0x4000 0800 0x4000 07FF 0x4000 0000 0x0000 8000 0x0000 7FFF 0x0000 4000 0x0000 3FFF 0x0000 2000 0x0000 1FFF 0x0000 0000
002aab822
LPC2101/02/03 memory
LPC2101_02_03_4
B.V. 2009. rights reserved.
Product data sheet
Rev. June 2009
Semiconductors
LPC2101/02/03
Single-chip 16-bit/32-bit microcontrollers
Interrupt controller
accepts interrupt request inputs categorizes them FIQ, vectored IRQ, non-vectored defined programmable settings. programmable assignment scheme means that priorities interrupts from various peripherals dynamically assigned adjusted. highest priority. more than request assigned FIQ, combines requests produce signal processor. fastest possible latency achieved when only request classified FIQ, because then service routine does need branch into interrupt service routine from interrupt vector location. more than request assigned class, service routine will read word from that identifies which source(s) (are) requesting interrupt. Vectored IRQs have middle priority. Sixteen interrupt requests assigned this category. interrupt requests assigned vectored slots, among which slot highest priority slot lowest. Non-vectored IRQs have lowest priority. combines requests from vectored non-vectored IRQs produce signal processor. service routine start reading register from jumping there. vectored IRQs pending, provides address highest-priority requesting IRQs service routine, otherwise provides address default routine that shared non-vectored IRQs. default routine read another register what IRQs active.
6.5.1 Interrupt sources
Each peripheral device interrupt line connected Vectored Interrupt Controller, have several internal interrupt flags. Individual interrupt flags also represent more than interrupt source.
connect block
connect block allows selected pins microcontroller have more than function. Configuration registers control multiplexers allow connection between chip peripherals. Peripherals should connected appropriate pins prior being activated, prior related interrupt(s) being enabled. Activity enabled peripheral function that mapped related should considered undefined. control module with select registers defines functionality microcontroller given hardware environment. After reset pins Port configured input with following exceptions: DBGSEL HIGH (Debug mode enabled), JTAG pins will assume their JTAG functionality with EmbeddedICE cannot configured connect block.
LPC2101_02_03_4
B.V. 2009. rights reserved.
Product data sheet
Rev. June 2009
Semiconductors
LPC2101/02/03
Single-chip 16-bit/32-bit microcontrollers
Fast general purpose parallel
Device pins that connected specific peripheral function controlled GPIO registers. Pins dynamically configured inputs outputs. Separate registers allow setting clearing number outputs simultaneously. value output register read back, well current state port pins. LPC2101/02/03 introduce accelerated GPIO functions over prior LPC2000 devices:
GPIO registers relocated local fastest possible timing. Mask registers allow treating sets port bits group, leaving other bits
unchanged.
GPIO registers byte addressable. Entire port value written instruction.
6.7.1 Features
Bit-level clear registers allow single instruction clear number
bits port.
Direction control individual bits. Separate control output clear. default inputs after reset. 10-bit
LPC2101/02/03 contain ADC. single 10-bit successive approximation with eight channels.
6.8.1 Features
Measurement range Each converter capable performing more than 400,000 10-bit samples second. Burst conversion mode single multiple inputs. Optional conversion transition input Timer Match signal. Every analog input dedicated result register reduce interrupt overhead.
UARTs
LPC2101/02/03 each contain UARTs. addition standard transmit receive data lines, UART1 also provides full modem control handshake interface. Compared previous LPC2000 microcontrollers, UARTs LPC2101/02/03 include fractional baud rate generator both UARTs. Standard baud rates such 115200 achieved with crystal frequency above MHz.
6.9.1 Features
byte Receive Transmit FIFOs. Register locations conform 16C550 industry standard. Receiver FIFO trigger points bytes
LPC2101_02_03_4 B.V. 2009. rights reserved.
Product data sheet
Rev. June 2009
Semiconductors
LPC2101/02/03
Single-chip 16-bit/32-bit microcontrollers
Built-in fractional baud rate generator covering wide range baud rates without
need external crystals particular values.
Transmission FIFO control enables implementation software (XON/XOFF) flow
control both UARTs.
UART1 equipped with standard modem interface signals. This module also
provides full support hardware flow control (auto-CTS/RTS).
6.10 I2C-bus serial controllers
LPC2101/02/03 each contain I2C-bus controllers. I2C-bus bidirectional, inter-IC control using only wires: Serial Clock Line (SCL), Serial Data Line (SDA). Each device recognized unique address operate either receiver-only device (e.g., driver) transmitter with capability both receive send information such serial memory. Transmitters and/or receivers operate either master slave mode, depending whether chip initiate data transfer only addressed. I2C-bus multi-master bus, controlled more than master connected I2C-bus implemented LPC2101/02/03 supports rates kbit/s (Fast I2C-bus).
6.10.1 Features
Compliant with standard I2C-bus interface. Easy configure Master, Slave, Master/Slave. Programmable clocks allow versatile rate control. Bidirectional data transfer between masters slaves. Multi-master central master). Arbitration between simultaneously transmitting masters without corruption serial data bus. serial bus.
Serial clock synchronization allows devices with different rates communicate Serial clock synchronization used handshake mechanism suspend
resume serial transfer.
I2C-bus also used test diagnostic purposes. 6.11 serial controller
LPC2101/02/03 each contain controller. full duplex serial interface, designed handle multiple masters slaves connected given bus. Only single master single slave communicate interface during given data transfer. During data transfer master always sends bits bits data slave, slave always sends bits bits data master.
6.11.1 Features
Compliant with specification. Synchronous, Serial, Full Duplex, Communication.
LPC2101_02_03_4 B.V. 2009. rights reserved.
Product data sheet
Rev. June 2009
Semiconductors
LPC2101/02/03
Single-chip 16-bit/32-bit microcontrollers
Combined master slave. Maximum data rate eighth input clock rate. 6.12 serial controller
LPC2101/02/03 each contain SSP. controller capable operation SPI, 4-wire SSI, Microwire bus. interact with multiple masters slaves bus. However, only single master single slave communicate during given data transfer. supports full duplex transfers, with data frames bits bits flowing from master slave from slave master. Often only these data streams carries meaningful data.
6.12.1 Features
Compatible with Motorola SPI, 4-wire Texas Instruments SSI, National
Semiconductor's Microwire buses
Synchronous serial communication Master slave operation 8-frame FIFOs both transmit receive Four bits bits frame
6.13 General purpose 32-bit timers/external event counters
Timer/Counter designed count cycles Peripheral Clock (PCLK) externally supplied clock optionally generate interrupts perform other actions specified timer values, based four match registers. also includes four capture inputs trap timer value when input signal transitions, optionally generating interrupt. Multiple pins selected perform single capture match function, providing application with `or' `and', well `broadcast' functions among them. LPC2101/02/03 count external events capture inputs minimum external pulse equal longer than period PCLK. this configuration, unused capture lines selected regular timer capture inputs used external interrupts.
6.13.1 Features
32-bit timer/counter with programmable 32-bit prescaler. External event counter timer operation. Four 32-bit capture channels timer/counter that take snapshot timer
value when input signal transitions. capture event also optionally generate interrupt.
Four 32-bit match registers that allow:
Continuous operation with optional interrupt generation match. Stop timer match with optional interrupt generation. Reset timer match with optional interrupt generation.
Four external outputs timer/counter corresponding match registers, with
following capabilities: match.
LPC2101_02_03_4 B.V. 2009. rights reserved.
Product data sheet
Rev. June 2009
Semiconductors
LPC2101/02/03
Single-chip 16-bit/32-bit microcontrollers
HIGH match. Toggle match. nothing match.
6.14 General purpose 16-bit timers/external event counters
Timer/Counter designed count cycles peripheral clock (PCLK) externally supplied clock optionally generate interrupts perform other actions specified timer values, based four match registers. also includes three capture inputs trap timer value when input signal transitions, optionally generating interrupt. Multiple pins selected perform single capture match function, providing application with `or' `and', well `broadcast' functions among them. LPC2101/02/03 count external events capture inputs minimum external pulse equal longer than period PCLK. this configuration, unused capture lines selected regular timer capture inputs used external interrupts.
6.14.1 Features
16-bit timer/counters with programmable 16-bit prescaler. External event counter timer operation. Three 16-bit capture channels that take snapshot timer value when
input signal transitions. capture event also optionally generate interrupt.
Four 16-bit match registers that allow:
Continuous operation with optional interrupt generation match. Stop timer match with optional interrupt generation. Reset timer match with optional interrupt generation.
Four external outputs timer/counter corresponding match registers, with
following capabilities: match. HIGH match. Toggle match. nothing match.
6.15 Watchdog timer
purpose watchdog reset microcontroller within reasonable amount time enters erroneous state. When enabled, watchdog will generate system reset user program fails `feed' reload) watchdog within predetermined amount time.
6.15.1 Features
Internally resets chip periodically reloaded. Debug mode. Enabled software requires hardware reset watchdog reset/interrupt
disabled.
LPC2101_02_03_4 B.V. 2009. rights reserved.
Product data sheet
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Semiconductors
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Single-chip 16-bit/32-bit microcontrollers
Incorrect/Incomplete feed sequence causes reset/interrupt enabled. Flag indicate watchdog reset. Programmable 32-bit timer with internal pre-scaler. Selectable time period from (TPCLK (TPCLK multiples TPCLK
6.16 Real-time clock
Real-Time Clock (RTC) designed provide counters measure time when normal idle operating mode selected. been designed little power, making suitable battery powered systems where running continuously (Idle mode).
6.16.1 Features
Measures passage time maintain calendar clock. Ultra-low power design support battery powered systems. Provides Seconds, Minutes, Hours, Month, Month, Year, Week,
Year.
either dedicated oscillator input clock derived from
external crystal/oscillator input XTAL1. programmable reference clock divider allows fine adjustment RTC.
Dedicated power supply connected battery main 6.17 System control
6.17.1 Crystal oscillator
on-chip integrated oscillator operates with external crystal range MHz. oscillator output frequency called fosc processor clock frequency referred CCLK purposes rate equations, etc. fosc CCLK same value unless running connected. Refer Section 6.17.2 "PLL" Section 10.1 "XTAL1 input" additional information.
6.17.2
accepts input clock frequency range MHz. input frequency multiplied into range with Current Controlled Oscillator (CCO). multiplier integer value from practice, multiplier value cannot higher than this family microcontrollers upper frequency limit CPU). operates range MHz, there additional divider loop keep within frequency range while providing desired output frequency. output divider divide produce output clock. Since minimum output divider value insured that output duty cycle. turned bypassed following chip reset enabled software. program must configure activate PLL, wait lock, then connect clock source. settling time
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Single-chip 16-bit/32-bit microcontrollers
6.17.3 Reset wake-up timer
Reset sources LPC2101/02/03: watchdog reset. Schmitt trigger input with additional glitch filter. Assertion chip reset source starts wake-up timer (see wake-up timer description below), causing internal chip reset remain asserted until external reset de-asserted, oscillator running, fixed number clocks have passed, on-chip flash controller completed initialization. When internal reset removed, processor begins executing address which reset vector. that point, processor peripheral registers have been initialized predetermined reset values. wake-up timer ensures that oscillator other analog functions required chip operation fully functional before processor allowed execute instructions. This important power types reset, whenever aforementioned functions turned reason. Since oscillator other functions turned during Power-down Deep power-down mode, wake-up processor from Power-down modes makes wake-up timer. wake-up timer monitors crystal oscillator means checking whether safe begin code execution. When power applied chip, some event caused chip exit Power-down mode, some time required oscillator produce signal sufficient amplitude drive clock logic. amount time depends many factors, including rate ramp case power on), type crystal electrical characteristics quartz crystal used), well other external circuitry (e.g., capacitors), characteristics oscillator itself under existing ambient conditions.
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Single-chip 16-bit/32-bit microcontrollers
6.17.4 Code security (Code Read Protection CRP)
This feature LPC2101/02/03 allows user enable different levels security system that access on-chip flash JTAG restricted. When needed, invoked programming specific pattern into dedicated flash location. commands affected CRP. Implemented bootloader code version 2.21 three levels Code Read Protection: CRP1 disables access chip JTAG allows partial flash update (excluding flash sector using limited commands. This mode useful when required flash field updates needed sectors cannot erased. CRP2 disables access chip JTAG only allows full flash erase update using reduced commands. Running application with level CRP3 selected fully disables access chip JTAG pins ISP. This mode effectively disables override using P0.14 pin, too. user's application provide needed) flash update mechanism using calls call reinvoke command enable flash update UART0.
CAUTION level three Code Read Protection (CRP3) selected, future factory testing performed device.
Remark: Parts LPC2101/02/03 Revision have CRP2 enabled only (bootloader code version 2.2).
6.17.5 External interrupt inputs
LPC2101/02/03 include three edge level sensitive external interrupt inputs selectable functions. When pins combined, external events processed three independent interrupt signals. external interrupt inputs optionally used wake-up processor from Power-down mode Deep power-down mode. Additionally capture input pins also used external interrupts without option wake device from Power-down mode.
6.17.6 Memory mapping control
memory mapping control alters mapping interrupt vectors that appear beginning address 0x0000 0000. Vectors mapped bottom on-chip flash memory, on-chip static RAM. This allows code running different memory spaces have control interrupts.
6.17.7 Power control
LPC2101/02/03 supports three reduced power modes: Idle mode, Power-down mode, Deep power-down mode.
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Idle mode, execution instructions suspended until either reset interrupt occurs. Peripheral functions continue operation during Idle mode generate interrupts cause processor resume execution. Idle mode eliminates power used processor itself, memory systems related controllers, internal buses. Power-down mode, oscillator shut down chip receives internal clocks. processor state registers, peripheral registers, internal SRAM values preserved throughout Power-down mode logic levels chip output pins remain static. Power-down mode terminated normal operation resumed either reset certain specific interrupts that able function without clocks. Since dynamic operation chip suspended, Power-down mode reduces chip power consumption nearly zero. Selecting external clock instead PCLK clock-source on-chip will enable microcontroller have active during Power-down mode. Power-down current increased with active. However, significantly lower than Idle mode. Deep-power down mode power removed from internal chip logic except module, ports, SRAM, external oscillator. additional power savings, SRAM oscillator powered down individually. Deep power-down mode produces lowest possible power consumption without actually removing power from entire chip. Deep power-down mode, contents registers memory preserved except SRAM, selected, three general purpose registers. Therefore, resume operations, full chip reset process required. power selector module switches power supply from VBAT VDD(1V8) whenever core voltage present VDD(1V8) conserve battery power. power control peripherals feature allows individual peripherals turned they needed application, resulting additional power savings during Active Idle mode.
6.17.8
divider determines relationship between processor clock (CCLK) clock used peripheral devices (PCLK). divider serves purposes. first provide peripherals with desired PCLK that they operate speed chosen processor. order achieve this, slowed down processor clock rate. Because must work properly power-up (and timing cannot altered does work since divider control registers reside APB), default condition reset processor clock rate. second purpose divider allow power savings when application does require peripherals full processor rate. Because divider connected output, remains active running) during Idle mode.
6.18 Emulation debugging
LPC2101/02/03 support emulation debugging JTAG serial port.
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6.18.1 EmbeddedICE
Standard EmbeddedICE logic provides on-chip debug support. debugging target system requires host computer running debugger software EmbeddedICE protocol converter. EmbeddedICE protocol converter converts remote debug protocol commands JTAG data needed access core. core debug communication channel function built-in. debug communication channel allows program running target communicate with host debugger another separate host without stopping program flow even entering debug state. debug communication channel accessed coprocessor program running ARM7TDMI-S core. debug communication channel allows JTAG port used sending receiving data without affecting normal program flow. debug communication channel data control registers mapped addresses EmbeddedICE logic. JTAG clock (TCK) must slower than clock (CCLK) JTAG interface operate.
6.18.2 RealMonitor
RealMonitor configurable software module, developed Inc., which enables real time debug. lightweight debug monitor that runs background while users debug their foreground application. communicates with host using DCC, which present EmbeddedICE logic. LPC2101/02/03 contain specific configuration RealMonitor software programmed into on-chip boot memory.
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Semiconductors
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Single-chip 16-bit/32-bit microcontrollers
Limiting values
Table Limiting values accordance with Absolute Maximum Rating System (IEC 60134).[1] Symbol VDD(1V8) VDD(3V3) VDDA Vi(VBAT) Parameter supply voltage (1.8 supply voltage (3.3 analog supply voltage input voltage VBAT analog input voltage input voltage tolerant pins other pins Tstg Ptot(pack) supply current ground current storage temperature total power dissipation (per package) based package heat transfer, device power consumption Human Body Model (HBM) Machine Model (MM) Charged Device Model (CDM)
Conditions
-0.5 -0.5 -0.5 -0.5
[5][6]
+2.5 +4.6 +4.6 +4.6 +5.1 +6.0
Unit
-0.5 -0.5 -0.5
[10] [11]
0.5[7] 100[9] 100[9] +150
VESD
electrostatic discharge voltage
-4000 -200 -800
+4000 +200 +800
V[12] V[13] V[14]
following applies limiting values: This product includes circuitry specifically designed protection internal devices from damaging effects excessive static charge. Nonetheless, suggested that conventional precautions taken avoid applying greater than rated maximum. Parameters valid over operating temperature range unless otherwise specified. voltages with respect unless otherwise noted. Core internal rail. External rail. related pins. Including voltage outputs 3-state mode. Only valid when VDD(3V3) supply voltage present. exceed supply pin. peak current limited times corresponding maximum current.
[10] ground pin. [11] Dependent package type. [12] Performed AEC-Q100-002. [13] Performed AEC-Q100-003. [14] Performed AEC-Q100-011.
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B.V. 2009. rights reserved.
Product data sheet
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Semiconductors
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Single-chip 16-bit/32-bit microcontrollers
Static characteristics
Table Static characteristics Tamb= commercial applications, unless otherwise specified. Symbol VDD(1V8) VDD(3V3) VDDA Vi(VBAT) Parameter supply voltage (1.8 supply voltage (3.3 analog supply voltage input voltage VBAT LOW-level input current HIGH-level input current OFF-state output current latch-up current input voltage pull-up VDD(3V3); pull-down VDD(3V3); pull-up/down -(0.5VDD(3V3)) (1.5VDD(3V3)); configured provide digital function; VDD(3V3) VDDA configured provide digital function; VDD(3V3) VDDA Vhys IOHS output voltage HIGH-level input voltage LOW-level input voltage hysteresis voltage HIGH-level output voltage LOW-level output voltage HIGH-level output current LOW-level output current HIGH-level short-circuit output current LOW-level short-circuit output current pull-down current VDD(3V3)
[10] [7][8] [7][8]
Conditions
1.65 2.6[4] 2.6[5] 2.0[6]
Typ[1]
1.95
Unit
Standard port pins, RST, RTCK Ilatch VDD(3V3) VDD(3V3)
output active
VDD(3V3)
[10]
[10]
[10]
[11]
IOLS
VDDA
[11]
V[12]
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Table Static characteristics .continued Tamb= commercial applications, unless otherwise specified. Symbol Parameter pull-up current Conditions VDD(3V3) IDD(CORE) core supply current Active mode; code V[12]
[13]
Typ[1]
Unit
while(1){}
executed from flash; peripherals enabled PCONP register configured run; CCLK VDD(1V8) Tamb Power-down mode; VDD(1V8) Tamb VDD(1V8) Tamb Deep power-down mode; off; SRAM off; Tamb Vi(VBAT) VDD(1V8) IBAT battery supply current Active mode; CCLK MHz; PCLK 17.5 MHz; PCLK enabled RTCK; clock (from RTCX pins); Tamb VDD(1V8) Vi(VBAT) Power-down mode; clock (from RTCX pins); Tamb VDD(1V8) Vi(VBAT) VDD(1V8) Vi(VBAT) Deep power-down mode; off; SRAM off; Tamb VDD(1V8) Vi(VBAT) I2C-bus pins Vhys HIGH-level input voltage LOW-level input voltage hysteresis voltage LOW-level output voltage input leakage current IOLS VDD(3V3)
[15] [10]
[14]
0.7VDD(3V3)
0.3VDD(3V3)
0.5VDD(3V3)
Oscillator pins Vi(XTAL1) input voltage XTAL1
LPC2101_02_03_4
B.V. 2009. rights reserved.
Product data sheet
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Semiconductors
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Table Static characteristics .continued Tamb= commercial applications, unless otherwise specified. Symbol Vo(XTAL2) Vi(RTCX1) Parameter output voltage XTAL2 input voltage RTCX1 Conditions Typ[1] Unit
Vo(RTCX2) output voltage RTCX2
Typical ratings guaranteed. values listed room temperature °C), nominal supply voltages. Core internal rail. External rail. VDD(3V3) pins tolerant, input voltage limited VDDA VDDA pins tolerant. typically fails when Vi(VBAT) drops below Including voltage outputs 3-state mode. VDD(3V3) supply voltages must present. 3-state outputs into 3-state mode when VDD(3V3) grounded.
[10] Accounts voltage drop supply lines. [11] Allowed long current limit does exceed maximum current allowed device. [12] Minimum condition maximum condition VDDA VDD(3V3) [13] Applies P0.25:16. [14] Battery supply current VBAT. [15] Input leakage current VSS.
Table static characteristics VDDA Tamb unless otherwise specified. frequency MHz. Symbol EL(adj)
Parameter analog input voltage analog input capacitance differential linearity error integral non-linearity offset error gain error absolute error
Conditions
[1][2][3] [1][4] [1][5] [1][6] [1][7]
VDDA ±0.5
Unit
Conditions: VSSA VDDA VDD(3V3) 10-bit resolution full speed; VDDA VDD(3V3) 8-bit resolution full speed. monotonic, there missing codes. differential linearity error (ED) difference between actual step width ideal step width. Figure integral non-linearity (EL(adj)) peak difference between center steps actual ideal transfer curve after appropriate adjustment gain offset errors. Figure offset error (EO) absolute difference between straight line which fits actual curve straight line which fits ideal curve. Figure gain error (EG) relative difference percent between straight line fitting actual transfer curve after removing offset error, straight line which fits ideal transfer curve. Figure absolute error (ET) maximum difference between center steps actual transfer curve non-calibrated ideal transfer curve. Figure
B.V. 2009. rights reserved.
LPC2101_02_03_4
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Semiconductors
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Single-chip 16-bit/32-bit microcontrollers
offset error 1023
gain error
1022
1021
1020
1019
1018
code
(ideal) 1018 1019 1020 1021 1022 1023 1024
offset error (LSBideal)
VDDA VSSA 1024
002aac046
Example actual transfer curve. ideal transfer curve. Differential linearity error (ED). Integral non-linearity (EL(adj)). Center step actual transfer curve.
conversion characteristics
LPC2101_02_03_4
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Product data sheet
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Semiconductors
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Single-chip 16-bit/32-bit microcontrollers
Power consumption Deep power-down mode
IDD(CORE) (µA) 1.25
002aae680
VDD(1V8) =1.8 0.75 1.65
Temperature (°C)
Test conditions: Deep power-down mode entered; off; SRAM off; Vi(VBAT) VDD(3V3) VDDA
Core supply current IDD(CORE) measured different temperatures supply voltages
IBAT (µA) 12.5
SRAM SRAM
002aae681
off; SRAM off; SRAM
Temperature (°C)
Test conditions: Deep power-down mode entered; Vi(BAT) VDD(1V8) VDD(3V3) VDDA
Battery supply current IBAT measured different temperatures conditions
LPC2101_02_03_4
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Product data sheet
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Single-chip 16-bit/32-bit microcontrollers
0.20 IDD(IO) (µA) 0.15
002aae682
0.10
0.05
Temperature (°C)
Test conditions: Deep power-down mode entered; off; SRAM off; VDD(3V3) VDD(1V8) Vi(BAT) VDDA
supply current IDD(IO) measured different temperatures
LPC2101_02_03_4
B.V. 2009. rights reserved.
Product data sheet
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Single-chip 16-bit/32-bit microcontrollers
Dynamic characteristics
Table Dynamic characteristics Tamb commercial applications, industrial applications, VDD(1V8), VDD(3V3) over specified ranges[1]. Symbol External clock fosc Tcy(clk) tCHCX tCLCX tCLCH tCHCL tr(o) tf(o) I2C-bus tf(o)
Parameter oscillator frequency clock cycle time clock HIGH time clock time clock rise time clock fall time output rise time output fall time pins (P0.2 P0.3) output fall time
Conditions
Tcy(clk) Tcy(clk)
Typ[2]
Unit
Port pins (except P0.2 P0.3)
Cb[3]
Parameters valid over operating temperature range unless otherwise specified. Typical ratings guaranteed. values listed room temperature °C), nominal supply voltages. capacitance from
Application information
10.1 XTAL1 input
input voltage on-chip oscillators limited oscillator driven clock slave mode, recommended that input coupled through capacitor with limit input voltage specified range, choose additional capacitor ground which attenuates input voltage factor Ci/(Ci Cg). slave mode, minimum (RMS) needed. more details LPC2101/02/03 User manual UM10161.
LPC2xxx
XTAL1
002aae718
Slave mode operation on-chip oscillator
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10.2 XTAL Printed Circuit Board (PCB) layout guidelines
crystal should connected close possible oscillator input output pins chip. Take care that load capacitors Cx2, case third overtone crystal usage, have common ground plane. external components must also connected ground plain. Loops must made small possible, order keep noise coupled small possible. Also parasitics should stay small possible. Values should chosen smaller accordingly increase parasitics layout.
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Package outline
LQFP48: plastic profile quad flat package; leads; body SOT313-2
detail
index
scale
DIMENSIONS original dimensions) UNIT max. 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 9.15 8.85 9.15 8.85 0.75 0.45 0.12 0.95 0.55 0.95 0.55
Note Plastic metal protrusions 0.25 maximum side included. OUTLINE VERSION SOT313-2 REFERENCES 136E05 JEDEC MS-026 JEITA EUROPEAN PROJECTION
ISSUE DATE 00-01-19 03-02-25
Package outline SOT313-2 (LQFP48)
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HVQFN48: plastic thermal enhanced very thin quad flat package; leads; terminals; body 0.85
SOT619-7
terminal index area
detail
terminal index area DIMENSIONS original dimensions) UNIT A(1) 0.05 0.00 0.30 0.18 3.45 3.15 3.45 3.15
scale 0.05 0.05
Note Plastic metal protrusions 0.075 maximum side included OUTLINE VERSION SOT619-7 REFERENCES -JEDEC MO-220 JEITA -EUROPEAN PROJECTION ISSUE DATE 05-10-24 05-10-25
Package outline SOT619-7 (HVQFN48)
LPC2101_02_03_4 B.V. 2009. rights reserved.
Product data sheet
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Semiconductors
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Single-chip 16-bit/32-bit microcontrollers
HVQFN48: plastic thermal enhanced very thin quad flat package; leads; terminals; body 0.85
SOT778-3
terminal index area
detail
terminal index area
scale
DIMENSIONS original dimensions) UNIT A(1) 0.05 0.00 0.25 0.15 3.95 3.65 3.95 3.65 0.05 0.05
Note Plastic metal protrusions 0.075 maximum side included OUTLINE VERSION SOT778-3 REFERENCES -JEDEC -JEITA -EUROPEAN PROJECTION ISSUE DATE 04-06-16 04-06-23
Package outline SOT778-3 (HVQFN48)
LPC2101_02_03_4 B.V. 2009. rights reserved.
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Abbreviations
Table Acronym AMBA FIFO GPIO SRAM UART Acronym list Description Analog-to-Digital Converter Advanced Microcontroller Architecture Advanced Peripheral Debug Communications Channel Digital Signal Processor First First Fast Interrupt reQuest General Purpose Input/Output In-Application Programming Interrupt Request In-System Programming Phase-Locked Loop Pulse Width Modulator Serial Peripheral Interface Static Random Access Memory Synchronous Serial Interface Synchronous Serial Port Transistor-Transistor Logic Universal Asynchronous Receiver/Transmitter Vectored Interrupt Controller
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B.V. 2009. rights reserved.
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Single-chip 16-bit/32-bit microcontrollers
Revision history
Table Revision history Release date 20090602 Data sheet status Product data sheet Change notice Supersedes LPC2101_02_03_3 Document LPC2101_02_03_4 Modifications:
Section 6.17.4 "Code security (Code Read Protection CRP)": added description three levels (applicable Revision higher). Section 6.17.7 "Power control": added description Deep power-down mode (applicable Revision higher). Section 10.1 "XTAL1 input" added. Section 10.2 "XTAL Printed Circuit Board (PCB) layout guidelines" added. Figure Figure Figure added power consumption data Deep power-down mode (applicable Revision higher). Table added table note Table modified description P0.14, RTCX1, RTCX2, XTAL1, XTAL2, JTAG, DBGSEL pins. Table modified value VDD(3V3). Table added modified values Vhys. Table Voltage range pins VDD(3V3) VDDA extended Product data sheet LPC2101_02_03_2 Updated data sheet status Product data sheet. Table Table added LPC2102FHN48 LPC2103FHN48. Table Table Table related figures: removed LPC2103FA44. Table updated descriptions. Table updated description SCL1. Table updated description pins VDDA VDD(1V8). Table changed storage temperature range from °C/125 °C/150 Table added modified values IDD(act), IDD(pd), IBATpd, IBATact. Table removed "CCLK MHz" associated values IDD(act). Section added Figure Section added Figure Preliminary data sheet Preliminary data sheet LPC2101_02_03_1
LPC2101_02_03_3 Modifications:
20081007
LPC2101_02_03_2 LPC2101_02_03_1
20071218 20060118
LPC2101_02_03_4
B.V. 2009. rights reserved.
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Legal information
14.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
Product status[3] Development Qualification Production
Definition This document contains data from objective specification product development. This document contains data from preliminary specification. This document contains product specification.
Please consult most recently issued document before initiating completing design. term `short data sheet' explained section "Definitions". product status device(s) described this document have changed since this document published differ case multiple devices. latest product status information available Internet http://www.nxp.com.
14.2 Definitions
Draft document draft version only. content still under internal review subject formal approval, which result modifications additions. Semiconductors does give representations warranties accuracy completeness information included herein shall have liability consequences such information. Short data sheet short data sheet extract from full data sheet with same product type number(s) title. short data sheet intended quick reference only should relied upon contain detailed full information. detailed full information relevant full data sheet, which available request local Semiconductors sales office. case inconsistency conflict with short data sheet, full data sheet shall prevail.
damage. Semiconductors accepts liability inclusion and/or Semiconductors products such equipment applications therefore such inclusion and/or customer's risk. Applications Applications that described herein these products illustrative purposes only. Semiconductors makes representation warranty that such applications will suitable specified without further testing modification. Limiting values Stress above more limiting values defined Absolute Maximum Ratings System 60134) cause permanent damage device. Limiting values stress ratings only operation device these other conditions above those given Characteristics sections this document implied. Exposure limiting values extended periods affect device reliability. Terms conditions sale Semiconductors products sold subject general terms conditions commercial sale, published including those pertaining warranty, intellectual property rights infringement limitation liability, unless explicitly otherwise agreed writing Semiconductors. case inconsistency conflict between information this document such terms conditions, latter will prevail. offer sell license Nothing this document interpreted construed offer sell products that open acceptance grant, conveyance implication license under copyrights, patents other industrial intellectual property rights. Export control This document well item(s) described herein subject export control regulations. Export might require prior authorization from national authorities.
14.3 Disclaimers
General Information this document believed accurate reliable. However, Semiconductors does give representations warranties, expressed implied, accuracy completeness such information shall have liability consequences such information. Right make changes Semiconductors reserves right make changes information published this document, including without limitation specifications product descriptions, time without notice. This document supersedes replaces information supplied prior publication hereof. Suitability Semiconductors products designed, authorized warranted suitable medical, military, aircraft, space life support equipment, applications where failure malfunction Semiconductors product reasonably expected result personal injury, death severe property environmental
14.4 Trademarks
Notice: referenced brands, product names, service names trademarks property their respective owners. I2C-bus logo trademark B.V.
Contact information
more information, please visit: http://www.nxp.com sales office addresses, please send email salesaddresses@nxp.com
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Contents
6.5.1 6.7.1 6.8.1 6.9.1 6.10 6.10.1 6.11 6.11.1 6.12 6.12.1 6.13 6.13.1 6.14 6.14.1 6.15 6.15.1 6.16 6.16.1 6.17 6.17.1 6.17.2 6.17.3 6.17.4 6.17.5 6.17.6 General description Features Enhanced features features Ordering information Ordering options Block diagram Pinning information Pinning description Functional description Architectural overview. On-chip flash program memory On-chip static RAM. Memory map. Interrupt controller Interrupt sources. connect block Fast general purpose parallel Features 10-bit Features UARTs Features I2C-bus serial controllers. Features serial controller. Features serial controller Features General purpose 32-bit timers/external event counters Features General purpose 16-bit timers/external event counters Features Watchdog timer. Features Real-time clock Features System control Crystal oscillator Reset wake-up timer Code security (Code Read Protection CRP) External interrupt inputs Memory mapping control 6.17.7 Power control 6.17.8 6.18 Emulation debugging. 6.18.1 EmbeddedICE 6.18.2 RealMonitor Limiting values Static characteristics Power consumption Deep power-down mode Dynamic characteristics Application information 10.1 XTAL1 input 10.2 XTAL Printed Circuit Board (PCB) layout guidelines. Package outline Abbreviations Revision history Legal information 14.1 Data sheet status 14.2 Definitions 14.3 Disclaimers. 14.4 Trademarks Contact information Contents.
Please aware that important notices concerning this document product(s) described herein, have been included section `Legal information'.
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