Triacs logic level Passivated, sensitive gate triacs plastic enve

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

Triacs logic level Passivated, sensitive gate triacs plastic enve

Datasheet Thumbnail

Top Searches for this datasheet

Triacs logic level
Passivated, sensitive gate triacs plastic envelope suitable surface mounting, intended general purpose bidirectional switching phase control applications. These devices intended interfaced directly microcontrollers, logic integrated circuits other power gate trigger circuits.
BT131W series
QUICK REFERENCE DATA
SYMBOL VDRM IT(RMS) ITSM PARAMETER BT131WRepetitive peak off-state voltages on-state current Non-repetitive peak on-state current MAX. MAX. UNIT 12.5 12.5
PINNING SOT223
DESCRIPTION main terminal
CONFIGURATION
SYMBOL
main terminal gate main terminal
LIMITING VALUES
Limiting values accordance with Absolute Maximum System (IEC 134). SYMBOL VDRM IT(RMS) ITSM PARAMETER Repetitive peak off-state voltages on-state current Non-repetitive peak on-state current fusing Repetitive rate rise on-state current after triggering full sine wave; full sine wave; prior surge 16.7 dIG/dt A/µs GT2- GT2- CONDITIONS MIN. -500 5001 12.5 13.8 MAX. -600 6001 UNIT A/µs A/µs A/µs A/µs
dIT/dt
PG(AV) Tstg
Peak gate current Peak gate voltage Peak gate power Average gate power Storage temperature Operating junction temperature
over period
Although recommended, off-state voltages 800V applied without damage, triac switch on-state. rate rise current should exceed A/µs. January 2004 2.000
Triacs logic level
THERMAL RESISTANCES
SYMBOL j-sp PARAMETER Thermal resistance junction solder point Thermal resistance junction ambient CONDITIONS full half cycle mounted; minimum footprint mounted; area fig:14 MIN.
BT131W series
TYP.
MAX.
UNIT
STATIC CHARACTERISTICS
unless otherwise stated SYMBOL PARAMETER Gate trigger current CONDITIONS GT2- GT2- GT2- GT2- MIN. TYP. MAX. UNIT
Latching current
Holding current On-state voltage Gate trigger voltage Off-state leakage current
VDRM(max);
DYNAMIC CHARACTERISTICS
unless otherwise stated SYMBOL dVD/dt dVcom/dt PARAMETER Critical rate rise off-state voltage Critical rate change commutating voltage Gate controlled turn-on time CONDITIONS VDRM(max); exponential waveform; dIcom/dt A/ms VDRM(max); dIG/dt A/µs MIN. TYP. MAX. UNIT V/µs V/µs
January 2004
2.000
Triacs logic level
BT131W series
Ptot
(max) (°C)
IT(RMS)
IT(RMS)
Tlead (°C)
Fig.1. Maximum on-state dissipation, Ptot, versus on-state current, IT(RMS), where conduction angle.
Fig.4. Maximum permissible current IT(RMS) versus solder point temperature Tsp.
IT(RMS)
ITSM ITSM time
initial dIT/dt limit
0.01
quadrant
10-5
10-4
10-3
10-2
10-1
surge duration
Fig.2. Maximum permissible non-repetitive peak on-state current ITSM, versus pulse width sinusoidal currents, 20ms.
ITSM initial ITSM time
Fig.5. Maximum permissible repetitive on-state current IT(RMS), versus surge duration, sinusoidal currents, Tlead 110°C.
VGT(Tj) VGT(25
Number cycles 50Hz
Fig.3. Maximum permissible non-repetitive peak on-state current ITSM, versus number cycles, sinusoidal currents,
Fig.6. Normalised gate trigger voltage VGT(Tj)/ VGT(25°C), versus junction temperature
January 2004
2.000
Triacs logic level
BT131W series
IGT(Tj) IGT(25 GT2- GT2-
Fig.7. Normalised gate trigger current IGT(Tj)/ IGT(25°C), versus junction temperature
IL(Tj) IL(25
Fig.10. Typical maximum on-state characteristic.
j-sp (K/W)
unidirectional bidirectional
0.01 10us 0.1ms 10ms 0.1s
Fig.8. Normalised latching current IL(Tj)/ IL(25°C), versus junction temperature
IH(Tj) IH(25C)
Fig.11. Transient thermal impedance j-sp, versus pulse width
1000
dVD/dt (V/us)
Fig.9. Normalised holding current IH(Tj)/ IH(25°C), versus junction temperature
Fig.12. Minimum, critical rate rise off-state voltage, dVD/dt versus junction temperature
January 2004
2.000
Triacs logic level
MOUNTING INSTRUCTIONS
BT131W series
Dimensions
(3x)
Fig.13. soldering pattern surface mounting SOT223.
January 2004
2.000
Triacs logic level
MECHANICAL DATA
Dimensions Mass: 0.11
0.32 0.24
BT131W series
0.10 0.02
1.05 0.85
0.80 0.60
(4x)
Fig.14. SOT223 surface mounting package. Notes further information, refer Philips publication SC18 Footprint Design Soldering Guidelines". Order code: 9397 00505. Epoxy meets UL94 1/8".
January 2004
2.000
Triacs logic level
DEFINITIONS
Data sheet status Objective specification Product specification Limiting values
BT131W series
This data sheet contains target goal specifications product development. This data sheet contains final product specifications.
Preliminary specification This data sheet contains preliminary data; supplementary data published later.
Limiting values given accordance with Absolute Maximum Rating System (IEC 134). Stress above more limiting values cause permanent damage device. These stress ratings only operation device these other conditions above those given Characteristics sections this specification implied. Exposure limiting values extended periods affect device reliability. Application information Where application information given, advisory does form part specification. Philips Electronics N.V. 2004 rights reserved. Reproduction whole part prohibited without prior written consent copyright owner. information presented this document does form part quotation contract, believed accurate reliable changed without notice. liability will accepted publisher consequence use. Publication thereof does convey imply license under patent other industrial intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products designed life support appliances, devices systems where malfunction these products reasonably expected result personal injury. Philips customers using selling these products such applications their risk agree fully indemnify Philips damages resulting from such improper sale.
January 2004
2.000

Triacs logic level Passivated, sensitive gate triacs plastic enve

Top Searches for this datasheet

Other recent searches