Quad 2-input NAND gate Rev. December 2007 Product data sheet
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74LV00
Quad 2-input NAND gate
Rev. December 2007 Product data sheet
74LV00 low-voltage Si-gate CMOS device that function compatible with 74HC00 74HCT00. 74LV00 provides quad 2-input NAND function.
Features
Wide operating voltage: Optimized voltage applications: Accepts input levels between Typical output ground bounce Tamb Typical HIGH-level output voltage (VOH) undershoot: Tamb protection: JESD22-A114E exceeds 2000 JESD22-A115-A exceeds Multiple package options Specified from from +125
Ordering information
Table Ordering information Package Temperature range 74LV00N 74LV00D 74LV00DB 74LV00PW 74LV00BQ +125 +125 +125 +125 +125 Name DIP14 SO14 SSOP14 TSSOP14 Description plastic dual in-line package; leads (300 mil) plastic small outline package; leads; body width plastic shrink small outline package; leads; body width plastic thin shrink small outline package; leads; body width Version SOT27-1 SOT108-1 SOT337-1 SOT402-1 SOT762-1 Type number
DHVQFN14 plastic dual in-line compatible thermal enhanced very thin quad flat package; leads; terminals; body 0.85
Semiconductors
74LV00
Quad 2-input NAND gate
Functional diagram
mna212
mna246
mna211
Logic symbol
logic symbol
Logic diagram (one gate)
Pinning information
Pinning
74LV00
terminal index area VCC(1)
001aah092
001aac938
Transparent view
substrate attached this using conductive attach material. used supply input.
configuration DIP14, SO14 (T)SSOP14
configuration DHVQFN14
description
Table Symbol
74LV00_3
description Description data input data input data output data input data input data output
B.V. 2007. rights reserved.
Product data sheet
Rev. December 2007
Semiconductors
74LV00
Quad 2-input NAND gate
Table Symbol
description .continued Description ground data output data input data input data output data input data input supply voltage
Functional description
Table Input
Function table[1] Output
HIGH voltage level; voltage level; don't care
Limiting values
Table Limiting values accordance with Absolute Maximum Rating System (IEC 60134). Voltages referenced (ground Symbol IGND Tstg Ptot Parameter supply voltage input clamping current output clamping current output current supply current ground current storage temperature total power dissipation Tamb +125 DIP14 package SO14 package (T)SSOP14 package DHVQFN14 package
Conditions -0.5 -0.5 -0.5 (VCC
-0.5
+7.0 +150
Unit
input output voltage ratings exceeded input output current ratings observed. Ptot derates linearly with mW/K above Ptot derates linearly with mW/K above Ptot derates linearly with mW/K above Ptot derates linearly with mW/K above
B.V. 2007. rights reserved.
74LV00_3
Product data sheet
Rev. December 2007
Semiconductors
74LV00
Quad 2-input NAND gate
Recommended operating conditions
Table Recommended operating conditions Voltages referenced (ground Symbol Tamb Parameter supply voltage input voltage output voltage ambient temperature input transition rise fall rate
Conditions
+125
Unit ns/V ns/V ns/V ns/V
static characteristics guaranteed from devices guaranteed function down (with input levels VCC).
Static characteristics
Table Static characteristics Voltages referenced (ground Symbol Parameter HIGH-level input voltage Conditions LOW-level input voltage HIGH-level output voltage -100 -100 -100 -100 -100 2.82 0.7VCC Typ[1] 0.3VCC +125 Unit 0.7VCC
0.3VCC
74LV00_3
B.V. 2007. rights reserved.
Product data sheet
Rev. December 2007
Semiconductors
74LV00
Quad 2-input NAND gate
Table Static characteristics .continued Voltages referenced (ground Symbol Parameter LOW-level output voltage Conditions
Typ[1] 0.25 0.35 0.40 0.55 20.0
+125 Unit 0.50 0.65
input leakage current supply current additional supply current input capacitance
GND; GND; input;
Typical values measured Tamb
Dynamic characteristics
Table Dynamic characteristics test circuit Figure Symbol Parameter propagation delay Conditions Figure power dissipation capacitance MHz;
Typ[1]
+125
Unit
typical values measured Tamb same tPLH tPHL. Typical values measured nominal supply voltage (VCC used determine dynamic power dissipation µW). VCC2 VCC2 where: input frequency MHz, output frequency output load capacitance supply voltage number inputs switching VCC2 outputs.
B.V. 2007. rights reserved.
74LV00_3
Product data sheet
Rev. December 2007
Semiconductors
74LV00
Quad 2-input NAND gate
Waveforms
input tPLH output
001aah088
tPHL
Measurement points given Table typical voltage output levels that occur with output load.
input (nA, output (nY) propagation delays Table Measurement points Input 0.5VCC 0.5VCC Output 0.5VCC 0.5VCC
Supply voltage
PULSE GENERATOR D.U.T.
001aaa663
Test data given Table Definitions test circuit: Termination resistance should equal output impedance pulse generator. Load resistance. Load capacitance including probe capacitance.
Load circuit switching times Table Test data Input
Supply voltage
74LV00_3
B.V. 2007. rights reserved.
Product data sheet
Rev. December 2007
Semiconductors
74LV00
Quad 2-input NAND gate
Package outline
DIP14: plastic dual in-line package; leads (300 mil) SOT27-1
seating plane
index
scale
DIMENSIONS (inch dimensions derived from original dimensions) UNIT inches max. 0.17 min. 0.51 0.02 max. 0.13 1.73 1.13 0.068 0.044 0.53 0.38 0.021 0.015 0.36 0.23 0.014 0.009 19.50 18.55 0.77 0.73 6.48 6.20 0.26 0.24 2.54 7.62 3.60 3.05 0.14 0.12 8.25 7.80 0.32 0.31 10.0 0.39 0.33 0.254 0.01 max. 0.087
Note Plastic metal protrusions 0.25 (0.01 inch) maximum side included. OUTLINE VERSION SOT27-1 REFERENCES 050G04 JEDEC MO-001 JEITA SC-501-14 EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-13
Package outline SOT27-1 (DIP14)
74LV00_3 B.V. 2007. rights reserved.
Product data sheet
Rev. December 2007
Semiconductors
74LV00
Quad 2-input NAND gate
SO14: plastic small outline package; leads; body width
SOT108-1
index detail
scale
DIMENSIONS (inch dimensions derived from original dimensions) UNIT max. 1.75 0.25 0.10 1.45 1.25 0.25 0.01 0.49 0.36 0.25 0.19 8.75 8.55 0.16 0.15 1.27 0.05 1.05 0.028 0.024 0.25 0.01 0.25 0.01
0.010 0.057 inches 0.069 0.004 0.049
0.019 0.0100 0.35 0.014 0.0075 0.34
0.244 0.039 0.041 0.228 0.016
0.028 0.004 0.012
Note Plastic metal protrusions 0.15 (0.006 inch) maximum side included. OUTLINE VERSION SOT108-1 REFERENCES 076E06 JEDEC MS-012 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-19
Package outline SOT108-1 (SO14)
74LV00_3 B.V. 2007. rights reserved.
Product data sheet
Rev. December 2007
Semiconductors
74LV00
Quad 2-input NAND gate
SSOP14: plastic shrink small outline package; leads; body width
SOT337-1
index detail
scale
DIMENSIONS original dimensions) UNIT max. 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 0.65 1.25 1.03 0.63 0.13
Note Plastic metal protrusions 0.25 maximum side included. OUTLINE VERSION SOT337-1 REFERENCES JEDEC MO-150 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-19
Package outline SOT337-1 (SSOP14)
74LV00_3 B.V. 2007. rights reserved.
Product data sheet
Rev. December 2007
Semiconductors
74LV00
Quad 2-input NAND gate
TSSOP14: plastic thin shrink small outline package; leads; body width
SOT402-1
index
detail
scale
DIMENSIONS original dimensions) UNIT Notes Plastic metal protrusions 0.15 maximum side included. Plastic interlead protrusions 0.25 maximum side included. OUTLINE VERSION SOT402-1 REFERENCES JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 max. 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.65 0.75 0.50 0.13 0.72 0.38
Package outline SOT402-1 (TSSOP14)
74LV00_3 B.V. 2007. rights reserved.
Product data sheet
Rev. December 2007
Semiconductors
74LV00
Quad 2-input NAND gate
DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; leads; SOT762-1 terminals; body 0.85
terminal index area
detail
terminal index area
scale
DIMENSIONS original dimensions) UNIT A(1) max. 0.05 0.00 0.30 0.18 1.65 1.35 1.15 0.85 0.05 0.05
Note Plastic metal protrusions 0.075 maximum side included. OUTLINE VERSION SOT762-1 REFERENCES -JEDEC MO-241 JEITA -EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27
Package outline SOT762-1 (DHVQFN14)
74LV00_3 B.V. 2007. rights reserved.
Product data sheet
Rev. December 2007
Semiconductors
74LV00
Quad 2-input NAND gate
Abbreviations
Table Acronym CMOS Abbreviations Description Complementary Metal Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Machine Model Transistor-Transistor Logic
Revision history
Table 74LV00_3 Modifications: Revision history Release date 20071220 Data sheet status Product data sheet Change notice Supersedes 74LV00_2 Document
format this data sheet been redesigned comply with identity guidelines Semiconductors. Legal texts have been adapted company name where appropriate. Section DHVQFN14 package added. Section derating values added DHVQFN14 package. Section outline drawing added DHVQFN14 package. Product specification Product specification 74LV00_1
74LV00_2 74LV00_1
19980420 19970203
74LV00_3
B.V. 2007. rights reserved.
Product data sheet
Rev. December 2007
Semiconductors
74LV00
Quad 2-input NAND gate
Legal information
15.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
Product status[3] Development Qualification Production
Definition This document contains data from objective specification product development. This document contains data from preliminary specification. This document contains product specification.
Please consult most recently issued document before initiating completing design. term `short data sheet' explained section "Definitions". product status device(s) described this document have changed since this document published differ case multiple devices. latest product status information available Internet http://www.nxp.com.
15.2 Definitions
Draft document draft version only. content still under internal review subject formal approval, which result modifications additions. Semiconductors does give representations warranties accuracy completeness information included herein shall have liability consequences such information. Short data sheet short data sheet extract from full data sheet with same product type number(s) title. short data sheet intended quick reference only should relied upon contain detailed full information. detailed full information relevant full data sheet, which available request local Semiconductors sales office. case inconsistency conflict with short data sheet, full data sheet shall prevail.
malfunction Semiconductors product reasonably expected result personal injury, death severe property environmental damage. Semiconductors accepts liability inclusion and/or Semiconductors products such equipment applications therefore such inclusion and/or customer's risk. Applications Applications that described herein these products illustrative purposes only. Semiconductors makes representation warranty that such applications will suitable specified without further testing modification. Limiting values Stress above more limiting values defined Absolute Maximum Ratings System 60134) cause permanent damage device. Limiting values stress ratings only operation device these other conditions above those given Characteristics sections this document implied. Exposure limiting values extended periods affect device reliability. Terms conditions sale Semiconductors products sold subject general terms conditions commercial sale, published including those pertaining warranty, intellectual property rights infringement limitation liability, unless explicitly otherwise agreed writing Semiconductors. case inconsistency conflict between information this document such terms conditions, latter will prevail. offer sell license Nothing this document interpreted construed offer sell products that open acceptance grant, conveyance implication license under copyrights, patents other industrial intellectual property rights.
15.3 Disclaimers
General Information this document believed accurate reliable. However, Semiconductors does give representations warranties, expressed implied, accuracy completeness such information shall have liability consequences such information. Right make changes Semiconductors reserves right make changes information published this document, including without limitation specifications product descriptions, time without notice. This document supersedes replaces information supplied prior publication hereof. Suitability Semiconductors products designed, authorized warranted suitable medical, military, aircraft, space life support equipment, applications where failure
15.4 Trademarks
Notice: referenced brands, product names, service names trademarks property their respective owners.
Contact information
additional information, please visit: http://www.nxp.com sales office addresses, send email salesaddresses@nxp.com
74LV00_3
B.V. 2007. rights reserved.
Product data sheet
Rev. December 2007
Semiconductors
74LV00
Quad 2-input NAND gate
Contents
15.1 15.2 15.3 15.4 General description Features Ordering information Functional diagram Pinning information Pinning description Functional description Limiting values. Recommended operating conditions. Static characteristics. Dynamic characteristics Waveforms Package outline Abbreviations Revision history Legal information. Data sheet status Definitions Disclaimers Trademarks Contact information. Contents
Please aware that important notices concerning this document product(s) described herein, have been included section `Legal information'.
B.V. 2007.
rights reserved.
more information, please visit: http://www.nxp.com sales office addresses, please send email salesaddresses@nxp.com Date release: December 2007 Document identifier: 74LV00_3
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