Dual flip-flop with reset; negative-edge trigger Rev. March 2008

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Dual flip-flop with reset; negative-edge trigger Rev. March 2008

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74HC73
Dual flip-flop with reset; negative-edge trigger
Rev. March 2008 Product data sheet
74HC73 high-speed Si-gate CMOS device that complies with JEDEC standard compatible with Low-power Schottky (LSTTL). 74HC73 dual negative-edge triggered flip-flop featuring individual clock (nCP) reset (nR) inputs; also complementary outputs. inputs must stable set-up time prior HIGH-to-LOW clock transition predictable operation. reset (nR) asynchronous active input. When LOW, overrides clock data inputs, forcing output output HIGH. Schmitt-trigger action clock input makes circuit highly tolerant slower clock rise fall times.
Features
Low-power dissipation Complies with JEDEC standard protection: JESD22-A114E exceeds 2000 JESD22-A115-A exceeds Multiple package options Specified from from +125
Ordering information
Table Ordering information Package Temperature range Name 74HC73N 74HC73D 74HC73DB 74HC73PW +125 +125 +125 +125 DIP14 SO14 SSOP14 Description plastic dual in-line package; leads (300 mil) plastic small outline package; leads; body width plastic shrink small outline package; leads; body width Version SOT27-1 SOT108-1 SOT337-1 SOT402-1 Type number
TSSOP14 plastic thin shrink small outline package; leads; body width
Semiconductors
74HC73
Dual flip-flop with reset; negative-edge trigger
Functional diagram
001aab981
Functional diagram
001aab979
001aab980
Logic symbol
logic symbol
74HC73_4
B.V. 2008. rights reserved.
Product data sheet
Rev. March 2008
Semiconductors
74HC73
Dual flip-flop with reset; negative-edge trigger
001aab982
Logic diagram (one flip-flop)
Pinning information
Pinning
74HC73
001aab978
configuration
description
Table Symbol 1CP, description Description clock input (HIGH-to-LOW edge-triggered); also referred asynchronous reset input (active LOW); also referred synchronous input; also referred positive supply voltage ground true output; also referred complement output; also referred synchronous input; also referred
74HC73_4
B.V. 2008. rights reserved.
Product data sheet
Rev. March 2008
Semiconductors
74HC73
Dual flip-flop with reset; negative-edge trigger
Functional description
Table Input
Function table[1] Output asynchronous reset toggle load (reset) load (set) hold change) Operating mode
HIGH voltage level; HIGH voltage level set-up time prior HIGH-to-LOW clock transition; voltage level; voltage level set-up time prior HIGH-to-LOW clock transition; state referenced output set-up time prior HIGH-to-LOW clock transition; don't care; HIGH-to-LOW clock transition.
Limiting values
Table Limiting values accordance with Absolute Maximum Rating System (IEC 60134). Voltages referenced (ground Symbol IGND Tstg Ptot Parameter supply voltage input clamping current output clamping current output current supply current ground current storage temperature total power dissipation Tamb +125 DIP14 package SO14 package (T)SSOP14 package
Conditions -0.5 -0.5 -0.5
-0.5
+7.0 +150
Unit
input output voltage ratings exceeded input output current ratings observed. Ptot derates linearly with mW/K above Ptot derates linearly with mW/K above Ptot derates linearly with mW/K above
74HC73_4
B.V. 2008. rights reserved.
Product data sheet
Rev. March 2008
Semiconductors
74HC73
Dual flip-flop with reset; negative-edge trigger
Recommended operating conditions
Table Symbol Tamb Recommended operating conditions Parameter supply voltage input voltage output voltage ambient temperature input transition rise fall rate Conditions 1.67 +125 Unit
Static characteristics
Table Static characteristics recommended operating conditions; voltages referenced (ground Symbol Parameter HIGH-level input voltage Conditions LOW-level input voltage HIGH-level output voltage -5.2 LOW-level output voltage input leakage current GND; 0.33 0.33 ±1.0 40.0 ±1.0 80.0 3.84 5.34 3.15 1.35 3.15 1.35 +125 Unit 3.15 1.35
3.98 4.32 5.48 5.81
0.15 0.26 0.16 0.26 ±0.1
supply current GND; input capacitance
74HC73_4
B.V. 2008. rights reserved.
Product data sheet
Rev. March 2008
Semiconductors
74HC73
Dual flip-flop with reset; negative-edge trigger
Dynamic characteristics
Table Dynamic characteristics (ground unless otherwise specified; test circuit, Figure Symbol Parameter propagation delay Conditions Figure Figure Figure transition time Figure pulse width input, HIGH LOW; Figure input, HIGH LOW; Figure trec recovery time nCP; Figure set-up time nCP; Figure
+125 Unit
74HC73_4
B.V. 2008. rights reserved.
Product data sheet
Rev. March 2008
Semiconductors
74HC73
Dual flip-flop with reset; negative-edge trigger
Table Dynamic characteristics .continued (ground unless otherwise specified; test circuit, Figure Symbol Parameter hold time Conditions nCP; Figure fmax maximum frequency input; Figure power dissipation capacitance flip-flop;
+125 Unit
same tPHL, tPLH. same tTHL, tTLH. used determine dynamic power dissipation µW). VCC2 VCC2 where: input frequency MHz; output frequency MHz; output load capacitance supply voltage number inputs switching; VCC2 outputs.
74HC73_4
B.V. 2008. rights reserved.
Product data sheet
Rev. March 2008
Semiconductors
74HC73
Dual flip-flop with reset; negative-edge trigger
Waveforms
input
input
tPHL output output tTLH tPLH tPHL
001aab983
tPLH tTHL tTLH tTHL
shaded areas indicate when input permitted change predictable output performance. Measurement points given Table typical voltage output levels that occur with output load.
Waveforms showing clock (nCP) output (nQ, propagation delays, clock pulse width, set-up hold times, output transition times maximum clock frequency
input trec input output output
001aab984
tPHL
tPLH
Measurement points given Table typical voltage output levels that occur with output load.
Waveforms showing reset (nR) input output (nQ, propagation delays reset pulse width removal time
74HC73_4
B.V. 2008. rights reserved.
Product data sheet
Rev. March 2008
Semiconductors
74HC73
Dual flip-flop with reset; negative-edge trigger
Table Type 74HC73
Measurement points Input 0.5VCC Output 0.5VCC
negative pulse
positive pulse
001aah768
Test data given Table Definitions test circuit: Termination resistance should equal output impedance pulse generator. Load capacitance including probe capacitance.
Table Type 74HC73
Test circuit measuring switching times Test data Input Load
74HC73_4
B.V. 2008. rights reserved.
Product data sheet
Rev. March 2008
Semiconductors
74HC73
Dual flip-flop with reset; negative-edge trigger
Package outline
DIP14: plastic dual in-line package; leads (300 mil) SOT27-1
seating plane
index
scale
DIMENSIONS (inch dimensions derived from original dimensions) UNIT inches max. 0.17 min. 0.51 0.02 max. 0.13 1.73 1.13 0.068 0.044 0.53 0.38 0.021 0.015 0.36 0.23 0.014 0.009 19.50 18.55 0.77 0.73 6.48 6.20 0.26 0.24 2.54 7.62 3.60 3.05 0.14 0.12 8.25 7.80 0.32 0.31 10.0 0.39 0.33 0.254 0.01 max. 0.087
Note Plastic metal protrusions 0.25 (0.01 inch) maximum side included. OUTLINE VERSION SOT27-1 REFERENCES 050G04 JEDEC MO-001 JEITA SC-501-14 EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-13
74HC73_4
Package outline SOT27-1 (DIP14)
B.V. 2008. rights reserved.
Product data sheet
Rev. March 2008
Semiconductors
74HC73
Dual flip-flop with reset; negative-edge trigger
SO14: plastic small outline package; leads; body width
SOT108-1
index detail
scale
DIMENSIONS (inch dimensions derived from original dimensions) UNIT max. 1.75 0.25 0.10 1.45 1.25 0.25 0.01 0.49 0.36 0.25 0.19 8.75 8.55 0.16 0.15 1.27 0.05 1.05 0.028 0.024 0.25 0.01 0.25 0.01
0.010 0.057 inches 0.069 0.004 0.049
0.019 0.0100 0.35 0.014 0.0075 0.34
0.244 0.039 0.041 0.228 0.016
0.028 0.004 0.012
Note Plastic metal protrusions 0.15 (0.006 inch) maximum side included. OUTLINE VERSION SOT108-1 REFERENCES 076E06 JEDEC MS-012 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-19
Package outline SOT108-1 (SO14)
74HC73_4 B.V. 2008. rights reserved.
Product data sheet
Rev. March 2008
Semiconductors
74HC73
Dual flip-flop with reset; negative-edge trigger
SSOP14: plastic shrink small outline package; leads; body width
SOT337-1
index detail
scale
DIMENSIONS original dimensions) UNIT max. 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 0.65 1.25 1.03 0.63 0.13
Note Plastic metal protrusions 0.25 maximum side included. OUTLINE VERSION SOT337-1 REFERENCES JEDEC MO-150 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-19
Package outline SOT337-1 (SSOP14)
74HC73_4 B.V. 2008. rights reserved.
Product data sheet
Rev. March 2008
Semiconductors
74HC73
Dual flip-flop with reset; negative-edge trigger
TSSOP14: plastic thin shrink small outline package; leads; body width
SOT402-1
index
detail
scale
DIMENSIONS original dimensions) UNIT Notes Plastic metal protrusions 0.15 maximum side included. Plastic interlead protrusions 0.25 maximum side included. OUTLINE VERSION SOT402-1 REFERENCES JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 max. 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.65 0.75 0.50 0.13 0.72 0.38
Package outline SOT402-1 (TSSOP14)
74HC73_4 B.V. 2008. rights reserved.
Product data sheet
Rev. March 2008
Semiconductors
74HC73
Dual flip-flop with reset; negative-edge trigger
Abbreviations
Table Acronym CMOS Abbreviations Description Complementary Metal-Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Machine Model Transistor-Transistor Logic
Revision history
Table 74HC73_4 Modifications: Revision history Release date 20080319 Data sheet status Product data sheet Change notice Supersedes 74HC73_3 Document
format this data sheet been redesigned comply with identity guidelines Semiconductors. Legal texts have been adapted company name where appropriate. Quick reference data incorporated into Section Section "Recommended operating conditions" converted t/V. Product data sheet Product specification 74HC_HCT73_CNV_2
74HC73_3 74HC_HCT73_CNV_2
20041112 December 1990
74HC73_4
B.V. 2008. rights reserved.
Product data sheet
Rev. March 2008
Semiconductors
74HC73
Dual flip-flop with reset; negative-edge trigger
Legal information
15.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
Product status[3] Development Qualification Production
Definition This document contains data from objective specification product development. This document contains data from preliminary specification. This document contains product specification.
Please consult most recently issued document before initiating completing design. term `short data sheet' explained section "Definitions". product status device(s) described this document have changed since this document published differ case multiple devices. latest product status information available Internet http://www.nxp.com.
15.2 Definitions
Draft document draft version only. content still under internal review subject formal approval, which result modifications additions. Semiconductors does give representations warranties accuracy completeness information included herein shall have liability consequences such information. Short data sheet short data sheet extract from full data sheet with same product type number(s) title. short data sheet intended quick reference only should relied upon contain detailed full information. detailed full information relevant full data sheet, which available request local Semiconductors sales office. case inconsistency conflict with short data sheet, full data sheet shall prevail.
malfunction Semiconductors product reasonably expected result personal injury, death severe property environmental damage. Semiconductors accepts liability inclusion and/or Semiconductors products such equipment applications therefore such inclusion and/or customer's risk. Applications Applications that described herein these products illustrative purposes only. Semiconductors makes representation warranty that such applications will suitable specified without further testing modification. Limiting values Stress above more limiting values defined Absolute Maximum Ratings System 60134) cause permanent damage device. Limiting values stress ratings only operation device these other conditions above those given Characteristics sections this document implied. Exposure limiting values extended periods affect device reliability. Terms conditions sale Semiconductors products sold subject general terms conditions commercial sale, published including those pertaining warranty, intellectual property rights infringement limitation liability, unless explicitly otherwise agreed writing Semiconductors. case inconsistency conflict between information this document such terms conditions, latter will prevail. offer sell license Nothing this document interpreted construed offer sell products that open acceptance grant, conveyance implication license under copyrights, patents other industrial intellectual property rights.
15.3 Disclaimers
General Information this document believed accurate reliable. However, Semiconductors does give representations warranties, expressed implied, accuracy completeness such information shall have liability consequences such information. Right make changes Semiconductors reserves right make changes information published this document, including without limitation specifications product descriptions, time without notice. This document supersedes replaces information supplied prior publication hereof. Suitability Semiconductors products designed, authorized warranted suitable medical, military, aircraft, space life support equipment, applications where failure
15.4 Trademarks
Notice: referenced brands, product names, service names trademarks property their respective owners.
Contact information
more information, please visit: http://www.nxp.com sales office addresses, please send email salesaddresses@nxp.com
74HC73_4
B.V. 2008. rights reserved.
Product data sheet
Rev. March 2008
Semiconductors
74HC73
Dual flip-flop with reset; negative-edge trigger
Contents
15.1 15.2 15.3 15.4 General description Features Ordering information Functional diagram Pinning information Pinning description Functional description Limiting values. Recommended operating conditions. Static characteristics. Dynamic characteristics Waveforms Package outline Abbreviations Revision history Legal information. Data sheet status Definitions Disclaimers Trademarks Contact information. Contents
Please aware that important notices concerning this document product(s) described herein, have been included section `Legal information'.
B.V. 2008.
rights reserved.
more information, please visit: http://www.nxp.com sales office addresses, please send email salesaddresses@nxp.com Date release: March 2008 Document identifier: 74HC73_4

Dual flip-flop with reset; negative-edge trigger Rev. March 2008

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