layout guidelines MCUs packages Rev. January 2009 Application not
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AN10778
layout guidelines MCUs packages
Rev. January 2009 Application note
Document information Info Keywords Content LPC2220, LPC2292, LPC2364, LPC2368, LPC2458, LPC2468, LPC2470, LPC2478, LPC2880, LPC2888, LPC3130, LPC3131, LPC3151, LPC3152, LPC3153, LPC3154, LPC3180/10, LPC3220, LPC3230, LPC3240, LPC3250, LH79524, LH7A400, LH7A404, TFBGA100, TFBGA144, TFBGA208, TFBGA180, TFBGA296, LFBGA208, BGA256, LFBGA256, LFBGA324, LFBGA320, Layout Guidelines, BGA, PCB, Fan-out This application note focused Printed Circuit Board (PCB) layout issues when using (LF)(TF) packages from Microcontroller family.
Abstract
Semiconductors
AN10778
layout guidelines MCUs packages
Revision history Date 20090122 Description Initial release
Contact information
additional information, please visit: http://www.nxp.com sales office addresses, please send email salesaddresses@nxp.com
AN10778_1 B.V. 2009. rights reserved.
Application note
Rev. January 2009
Semiconductors
AN10778
layout guidelines MCUs packages
Introduction
plastic Ball Grid Array (BGA), including profile Fine pitch (LFBGA) Thin profile Fine pitch (TFBGA), packages have become, many applications, first choice designers requiring medium high pin-count packaging. this reason many Family Microcontrollers available LFBGA TFBGA package. When comparing other common alternative packages, such Quad Flat Pack (QFP), (LF)(TF)BGA device many advantages. Such (LF)(TF)BGA easy-to-bend leads that cause deviation from coplanarity. (LF)(TF)BGA typically smaller than equivalently functional QFP. Resolution smearing problems with respect stencil-print process less because pitch larger, apertures circular. self-alignment property component results large process window automatic placement. (LF) (TF)BGA compatible with today's assembly techniques, which means that adjustments necessary standard machines materials.
Scope
scope this application note focused Printed Circuit Board (PCB) layout issues when using (LF)(TF) packages from Microcontroller family. Including: Recommended footprint patterns TFBGA180, TFBGA208, TFBGA296 LFBGA320 packages. Recommended trace, space size fan-out routing TFBGA180, TFBGA208, TFBGA296 LFBGA320 packages
recommended that other assembly topics such solder paste chemistry, reflow solder profile solder paste stencil etching, which affected components board level assembly limited Microcontroller alone, collaborative effort between system designer assembly contractor.
Package Description
cross section typical (LF)(TF)BGA shown
(LF)(TF)BGA Cross Section
AN10778_1 B.V. 2009. rights reserved.
Application note
Rev. January 2009
Semiconductors
AN10778
layout guidelines MCUs packages
This application note applies packages listed Table
Table Packages Outline Code SOT1018-1 SOT926-1 SOT569-2 SOT570-2 SOT950-1 SOT1019-1 SOT1020-1 SOT1048-1 SOT1021-1 SOT930-1 SOT640-1 SOT824-1
Package Name BGA256 TFBGA100 TFBGA144 TFBGA180 TFBGA208 LFBGA208 LFBGA256 TFBGA296 LFBGA324 TFBGA208 TFBGA180 LFBGA320
Outline Dimensions 1.35mm 0.7mm 0.7mm 0.8mm 0.7mm 1.27mm 1.25mm 0.7mm 1.25mm 0.7mm 0.8mm 0.9mm
Ball Pitch 1.0mm 0.8mm 0.8mm 0.8mm 0.8mm 0.8mm 0.8mm 0.8mm 0.8mm 0.65mm 0.5mm 0.5mm
Ball Diam 0.50mm 0.45mm 0.45mm 0.45mm 0.45mm 0.45mm 0.45mm 0.45mm 0.45mm 0.40mm 0.30mm 0.30mm
Ball Configuration full matrix full matrix partial matrix partial matrix partial matrix partial matrix full matrix partial matrix partial matrix partial matrix partial matrix partial matrix
Reference JEDEC MO-216 Reference JEDEC MO-275 Reference JEDEC MO-195 Reference JEDEC MS-034 Reference JEDEC MO-205
Footprints
When building footprint number consideration ensuring ball pattern outline matches device package. This includes correct orientation ball matching ball column locations, ball-to-ball pitch. Solder joint reliability also primary concern. cost sensitive applications, minimizing number layers required route consideration. land pattern footprint plays role solder joint reliability, number layers required route balls.
Land Design
land pads have designed ensure solder joint reliability provide optimum manufacturability. basic types land design are: Solder mask defined land (SMD) Non-solder mask defined land (NSMD); recommended type
AN10778_1
B.V. 2009. rights reserved.
Application note
Rev. January 2009
Semiconductors
AN10778
layout guidelines MCUs packages
3.1.1 Solder mask defined land (SMD)
type land design characterized copper being larger than solder mask opening above this pad. Thus solder joint area land defined opening solder mask.
3.1.2 Non-solder mask defined land (NSMD)
NSMD type land design characterized copper being smaller than solder mask opening. Thus solder joint area land defined size land pad. solder mask clearance around land must large enough ensure that solder mask overlaps land pad. Typical solder mask land clearance range 0.06 0.075mm, depending manufacturer's solder mask alignment tolerance.
Solder mask non-solder mask defined land
Recommended Footprint
NSMD type land recommended footprint. addition surface land pad, reflowed solder paste will wett side wall making mechanically stronger solder joint than type pad. smaller NSMD land also leaves more space routing traces between land pads. been shown that matching solder joint area land that package substrate equalizes ball solder joint stress between package land thereby reducing chance solder joint stress crack. packages referenced this application note type pads. NSMD type pads should approximately smaller than pads achieve equalized stress. This difference between package recommended NSMD each package reflected Table generic footprint shown specific dimensions each package listed Table
AN10778_1
B.V. 2009. rights reserved.
Application note
Rev. January 2009
Semiconductors
AN10778
layout guidelines MCUs packages
Generic Footprint
Table
Recommended Footprints Ball Pitch Ball diameter substrate land Solder mask Land diameter 0.45 0.26 0.25 diameter 0.45 0.35 0.35 0.35 0.35 0.30 0.30 0.35 0.30 0.30 0.25 0.25 0.25 diameter 0.42 0.42 0.42 0.37 0.36 0.36 17.6 12.6 12.6 15.6 14.6 14.6 15.6 15.6 17.6 12.4 10.4 13.4 Outline
Package Name
BGA256 TFBGA100 TFBGA144 TFBGA180 TFBGA208 (SOT950-1) LFBGA208 LFBGA256 TFBGA296 TFBGA296 LFBGA324 TFBGA208 (SOT930-1) TFBGA180 (SOT640-1) LFBGA320
0.65
0.50 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45
Notes:
dimensions millimeters substrate land pads type land pads NSMD type recommended solder paste diameter same land recommended solder paste diameter 0.02mm larger than land Used routing trace between land pads Used routing traces between land pads
AN10778_1
B.V. 2009. rights reserved.
Application note
Rev. January 2009
Semiconductors
AN10778
layout guidelines MCUs packages
Recommended Fan-out Trace Space guidelines
small pitch between balls their matrix arrangement makes impractical route balls away from single layer. Fan-out vias (also called escape vias) required route balls other layers PCB. There several technologies used PCB's. They are: Through-via, Blind via, Buried via, Micro In-pad via. Through-vias, where drilled hole goes through layers PCB, cost considerably less than Blind, Buried, Micro In-pad vias. Throughvias generally larger than other types vias well. recommended fan-out examples this application note through-via exclusively.
Recommended 0.8mm pitch fan-out pattern
0.8mm pitch BGA's, recommended fan-out pattern centers each within space between four adjacent land pads shown Generally, single trace routed between adjacent land pads, allowing outer rows balls routed without fan-out via. BGA's with larger than 0.8mm ball pitch traces routed between adjacent land pads, allowing three outer most rows balls routed without via. reducing land pad, trace width trace-to-pad space design rules 0.8mm ball pitch TFBGA296, traces routed between land pads. Table layout tool design rules 0.8mm pitch fan-out.
0.8mm pitch fan-out pattern
AN10778_1
B.V. 2009. rights reserved.
Application note
Rev. January 2009
Semiconductors
AN10778
layout guidelines MCUs packages
Table Pitch
0.8mm pitch layout design rules land Land space Between vias Between Land pads Trace space traces Trace space 0.18 0.11 0.15 traces
Drill size Inner plane finished layer antihole size 0.18 0.25 0.25 0.25 0.800 0.695 0.695 0.695 0.24 0.148 0.173
0.45 0.45 0.35 0.30
0.55 0.485 0.485 0.485
0.15 0.105 0.105
Recommended 0.65mm pitch fan-out pattern
0.65mm pitch BGA's, recommended fan-out pattern centers each within space between four adjacent land pads. Instead placing vias 0.65mm apart they placed 1.3mm from each other, skipping every other location, staggering them between adjacent rows, partial fan-out example shown With this pattern TFGBA208 package 0.125mm (0.005") trace space design rules. With single trace routed between adjacent land pads, outer rows balls routed without fan-out via. Table layout tool design rules 0.65mm pitch fan-out.
Note: connect pins LPC3152/54
Recommended 0.65mm pitch fan-out pattern
AN10778_1 B.V. 2009. rights reserved.
Application note
Rev. January 2009
Semiconductors
AN10778
layout guidelines MCUs packages
Table Pitch
0.65mm pitch layout design rules land Land Between space vias Trace space Trace space 0.125 Between Land pads traces
Drill size Inner finished plane layer hole size anti-pad 0.05 0.122
0.65
0.25
0.425
0.125
Recommended 0.5mm pitch fan-out pattern
pattern centering through-via within four adjacent land pads used with 0.5mm pitch BGA's. This smallest through-via being large space available between land pads. With single trace routed between adjacent land pads, outer rows balls routed without fan-out via. inner rows balls must routed vias center area escape routed other layers. example fan-out LFBGA320 package shown Table layout tool design rules 0.5mm pitch fan-out.
Example fan-out LFBGA320
AN10778_1
B.V. 2009. rights reserved.
Application note
Rev. January 2009
Semiconductors
AN10778
layout guidelines MCUs packages
Table Pitch
0.5mm pitch layout design rules land Land Between space vias Trace space Trace space 0.08 Between Land pads traces
Drill size Inner finished plane layer hole size anti-pad 0.05
0.25
Board Cost considerations
cost affected many factors, generally increasing cost Overall area increases number layers increases Using in-pad via, blind via, buried via, micro diameter through-via decreases trace width decreases below 0.125mm mils) space between metal features decreases below 0.125mm mils) Therefore, selecting size, trace width spacing fan-out routing requires balance between feature size, number layers overall board area most economical layout.
Area Rules
many boards design rules size, trace width space fan-out routing require smaller feature sizes than other area board. your layout tool capable defining multiple rule areas, cost effective limit area around smaller feature sizes larger vias larger trace widths spacing balance board. other words fan-out trace space rules, then limiting trace space rules fan-out area have only small cost premium.
many layers fan-out
Generally trace routed between adjacent land pads, enabling outer rows balls routed same layer mounted next rows routed next signal layer, provided vias spaced enough apart allow trace between them, case 1.0mm, 0.8mm 0.65mm recommended fan-out patterns Each additional will take additional layer fan-out. example, TFBGA296 balls seven rows deep will take layers fan-out, including power ground. Because PCB's constructed even number layers, using TFBGA296 package would require minimum layers, including split power plane ground plane.
AN10778_1
B.V. 2009. rights reserved.
Application note
Rev. January 2009
Semiconductors
AN10778
layout guidelines MCUs packages
Power Ground
Microcontroller family devices have many power ground pins. This having multiple power domains, potential large simultaneous switching currents when 16-bit 32-bit external data outputs change from high, high low, same time. recommended that VDD(core) VDD(IO) power nets VSSx distributed plane layer instead routed thin traces, like those used carrying other signals. power ground balls typically routed near fan-out same signal. recommended that short trace between ball fan-out wider than 0.15mm (6mils). Although common wider trace (0.5mm) route power ground from other packages (SOIC, QFP, TSOP, etc.), using larger than 0.15mm begin like heat sink that could adversely affect solder joint. power ground must routed more than fan-out via, trace should routed first with 0.15mm trace then sized balance route. recommended that power ground vias that into plane solid degree connection, shown This provides lower inductance connection plane will provide more solid ground plane throughout area. Avoid thermal (4-point) connections, shown
Direct connection plane plane connection
Thermal (4-point) connection plane
AN10778_1
B.V. 2009. rights reserved.
Application note
Rev. January 2009
Semiconductors
AN10778
layout guidelines MCUs packages
Legal information
Definitions
Draft document draft version only. content still under internal review subject formal approval, which result modifications additions. Semiconductors does give representations warranties accuracy completeness information included herein shall have liability consequences such information. Suitability Semiconductors products designed, authorized warranted suitable medical, military, aircraft, space life support equipment, applications where failure malfunction Semiconductors product reasonably expected result personal injury, death severe property environmental damage. Semiconductors accepts liability inclusion and/or Semiconductors products such equipment applications therefore such inclusion and/or customer's risk. Applications Applications that described herein these products illustrative purposes only. Semiconductors makes representation warranty that such applications will suitable specified without further testing modification.
Disclaimers
General Information this document believed accurate reliable. However, Semiconductors does give representations warranties, expressed implied, accuracy completeness such information shall have liability consequences such information. Right make changes Semiconductors reserves right make changes information published this document, including without limitation specifications product descriptions, time without notice. This document supersedes replaces information supplied prior publication hereof.
Trademarks
Notice: referenced brands, product names, service names trademarks property their respective owners.
AN10778_1
B.V. 2009. rights reserved.
Application note
Rev. January 2009
Semiconductors
AN10778
layout guidelines MCUs packages
Contents
3.1.1 3.1.2 Introduction Scope Package Description Footprints.4 Land Design.4 Solder mask defined land (SMD) Non-solder mask defined land (NSMD).5 Recommended Footprint Recommended Fan-out Trace Space guidelines.7 Recommended 0.8mm pitch fan-out pattern.7 Recommended 0.65mm pitch fan-out pattern Recommended 0.5mm pitch fan-out pattern Board Cost considerations.10 Area Rules many layers fan-out BGA.10 Power Ground Legal information Definitions Disclaimers.12 Trademarks Contents.13
Please aware that important notices concerning this document product(s) described herein, have been included section 'Legal information'.
B.V. 2009. rights reserved.
more information, please visit: http://www.nxp.com sales office addresses, email salesaddresses@nxp.com Date release: January 2009 Document identifier: AN10778_1
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