3-channel Video Buffer with Built-in wideband SM5302A 3-channel v

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3-channel Video Buffer with Built-in wideband SM5302A 3-channel v

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SM5302A
3-channel Video Buffer with Built-in wideband
SM5302A 3-channel video buffer with built-in 5th-order lowpass filters. lowpass filter cutoff frequency range linearly controlled from 4.8MHz 43MHz*1. lowpass filter supports 480i 1080i format, video signal equipment analog input/outputs. video input systems, device functions nextstage system anti-aliasing filter. video output systems, filter removes video aliasing external noise drive maximum terminated loads. cutoff frequency, signal input type, output gain switching controlled using I2C*2 control bus, slave address (3-state input) allow maximum three devices used simultaneously.
When resistor connected ISET (RISET) 1.8k. registered trademark Philips Electronics N.V.
FEATURES
PINOUT
(Top view)
REF1 MUXSEL
REF2 REF3 VCC1 OUT1A OUT1B GND1 VCC2
Supply voltages Analog: 4.75 5.25V Digital: 5.5V Lowpass filter with linearly adjustable cutoff frequency (256 values) Cutoff frequency range: 4.8MHz 43MHz (RISET 1.8k) Filter bypass mode function display specifications SXGA resolution Passband: 80MHz (typ) Half mode switch function (CH-2, CH-3) suitable digital component signals 2-system input multiplexer function (switchable using MUXSEL input) Video input pins independently synctip clamp/bias/direct inputs Maximum terminated load drive capability Output gain switching: 0dB/6dB Disable function 300µA current consumption when disabled Output compensation circuit built-in interface control Slave address: 90h, 92h, three devices used simultaneously, selected input) Data transfer rate: Fast mode 400kbit/s) Operating ambient temperature range: 70°C Package: 28-pin HSOP
IN1A IN1B ISET IN2A IN2B IN3A IN3B
OUT2A OUT2B GND2 VCC3 OUT3A OUT3B GND3
PACKAGE DIMENSIONS
(Unit:
0.15
HDTVs PDPs Projectors
1.3TYP 18.6
5.15
0.10 0.35 0.05
0.12
Device SM5302AS
Package 28-pin HSOP
SEIKO CORPORATION
0.05
ORDERING INFORMATION
APPLICATIONS
SM5302A
BLOCK DIAGRAM
MUXSEL
ISET REF1
Control
Vref Current Source
REF2 REF3
Bypass 0dB/6dB IN1A IN1B
Clamp/Bias/Direct Clamp/Bias/Direct
VCC1 OUT1A
Order (Standard
Filter OUT1B GND1
CH-1
Bypass 0dB/6dB IN2A IN2B
Clamp/Bias/Direct Clamp/Bias/Direct
VCC2 OUT2A
Order (Standard /Half
Filter OUT2B GND2
CH-2
Bypass 0dB/6dB IN3A IN3B
Clamp/Bias/Direct Clamp/Bias/Direct
VCC3 OUT3A
Order (Standard /Half
Filter OUT3B GND3
CH-3
Note. recommended value external resistor connected ISET 1.8k.
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SM5302A
DESCRIPTION
Number input, output analog, digital Name REF1 MUXSEL IN1A IN1B ISET IN2A IN2B IN3A IN3B GND3 OUT3B OUT3A VCC3 GND2 OUT2B OUT2A VCC2 GND1 OUT1B OUT1A VCC1 REF3 REF2 I/O*1 A/D*2 Internal reference voltage Digital supply (3.0 5.5V) data signal input/output clock signal input Digital ground Input multiplexer switch control slave address select (3-state input) Video signal input (CH-1, input Video signal input (CH-1, input Internal current-setting resistor (RISET) connection (standard 1.8k) Video signal input (CH-2, input Video signal input (CH-2, input Video signal input (CH-3, input Video signal input (CH-3, input Analog ground (CH-3) Video signal output (CH-3, compensation) Video signal output (CH-3) Analog supply (CH-3) (4.75 5.25V) Analog ground (CH-2) Video signal output (CH-2, compensation) Video signal output (CH-2) Analog supply (CH-2) (4.75 5.25V) Analog ground (CH-1, Vref) Video signal output (CH-1, compensation) Video signal output (CH-1) Analog supply (CH-1, Vref) (4.75 5.25V) Internal reference voltage Internal reference voltage Description
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SM5302A
EQUIVALENT CIRCUITS
Number Name Equivalent circuit
VCCn
IN1A IN1B IN2A IN2B IN3A IN3B
INnA INnB
GNDn
VCCn
OUTnA
OUT1A OUT1B OUT2A OUT2B OUT3A OUT3B
GNDn VCCn
OUTnB
GNDn
VCC1
REF1
REF1
GND1
SEIKO CORPORATION
SM5302A
Number Name Equivalent circuit
VCC1
REF2
REF2 REF3
GND1 VCC1
REF3
GND1
MUXSEL
MUXSEL
Note. Resistance values indicate design values.
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SM5302A
SPECIFICATIONS
Absolute Maximum Ratings
GND1 GND2 GND3 VCC1 VCC2 VCC3
Parameter Supply voltage Input voltage Storage temperature range Power dissipation Junction temperature Symbol TSTG 60°C/W Note. measured quantity under mounted condition which specified. Condition VCC1, VCC2, VCC3, MUXSEL, ADS, SDA, SCL, INnA, INnB Rating Unit
Recommended Operating Conditions
Parameter Supply voltage Supply voltage difference Supply voltage Operating ambient temperature Symbol Condition VCC1, VCC2, VCC3 VCC1 VCC2, VCC1 VCC3, VCC2 VCC3 Rating 4.75 5.25 Unit
Note. VCC1 VCC3 should applied simultaneously.
Electrical Characteristics
Characteristics 5.0V, 5.5V, 25°C, 100kHz, 1.0Vp-p, RISET 1.8k, CH-1 clamp input, CH-2 CH-3 bias input, FCDATA 227, unless otherwise noted.
Rating Parameter Current consumption Current consumption Current consumption Current consumption HIGH-level input voltage LOW-level Input voltage HIGH-level input voltage LOW-level input voltage open-circuit input voltage LOW-level input leakage current HIGH-level input leakage current output voltage Symbol ICC1 ICC2 ICC3 ICC4 VIH1 VIL1 VIH2 VIL2 VOPEN Condition Filter mode, FCDATA Filter bypass mode Power-down mode, 3-address mode Power-down mode 2-address mode SDA, SCL, MUXSEL, 70°C SDA, SCL, MUXSEL, 70°C ADS, 70°C ADS, 70°C ADS, 70°C SDA, SCL, MUXSEL, SDA, SCL, MUXSEL, Sink current output VDD/2 VDD/2 Unit Test level
VCC1 VCC2 VCC3 VDD. input signals. SEIKO CORPORATION
SM5302A Characteristics (I2C) 5.0V, 5.5V, 25°C, unless otherwise noted.
Rating Parameter clock frequency hold time (start condition) clock LOW-level pulsewidth clock HIGH-level pulsewidth setup time (start condition) data hold time data setup time SDA, rise time SDA, fall time setup time (stop condition) SDA, input capacitance Symbol fSCL tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tSU;STO Condition 0.15*1 Unit Test level
This value conforming specification established Philips Corporation.
tLOW
tSU;DAT
tBUF
tHD;STA
tHD;STA
tHD;DAT
tHIGH
tSU;STA
tSU;STO
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SM5302A Analog Characteristics
Analog input characteristics
5.0V, 5.5V, 25°C, 100kHz, 1.0Vp-p, RISET 1.8k, CH-1 clamp input, CH-2 CH-3 bias input, FCDATA 227, unless otherwise noted. Internal mode settings shown table "Mode Condition Settings".
Rating Parameter Clamp voltage Bias voltage Input resistance Symbol VCLMP VBIAS RBIAS VAI1 Filter mode maximum input voltage VAI2 VAI3 VAI4 VAI5 Bias mode maximum input voltage VAI6 VAI7 VAI8 VIDC1 VIDC2 VIDC3 VIDC4 Clamp input Bias input Bias input Mode: (bias, 0dB), 1.0% Mode: (bias, 6dB), 1.0% Mode: (clamp, 0dB), 1.0% Mode: (clamp, 6dB), 1.5% Mode: (bias, 0dB), 1.0% Mode: (bias, 6dB), 1.5% Mode: (clamp, 0dB), 1.0% Mode: (clamp, 6dB), 1.5% Mode: 1.5%, 1.4Vp-p Mode: 1.5%, 1.2Vp-p Mode: 1.5%, 1.4Vp-p Mode: 1.5%, 1.2Vp-p Condition Vp-p Vp-p Vp-p Vp-p Vp-p Vp-p Vp-p Vp-p Unit Test level
Direct mode input voltage range
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SM5302A
Filter mode bypass mode frequency characteristics
5.0V, 5.5V, 25°C, 100kHz, 1.0Vp-p, RISET 1.8k, CH-1 clamp input, CH-2 CH-3 bias input, FCDATA 227, unless otherwise noted.
Rating Parameter Symbol Cutoff frequency Half mode cutoff frequency ratio attenuation Filter bypass mode passband Rhalf1 Rhalf2 FCDATA FCDATA FCDATA FCDATA Half mode, FCDATA Half mode, FCDATA 4fc, attenuation from 100kHz 0.7Vp-p, Gain Condition 5.98 32.5 4.74 6.79 36.89 43.73 7.60 41.3 Unit Test level
Analog output characteristics
5.0V, 5.5V, 25°C, 100kHz, 1.0Vp-p, RISET 1.8k, CH-1 clamp input, CH-2 CH-3 bias input, FCDATA 227, unless otherwise noted. Internal mode settings shown table "Mode Condition Settings".
Rating Parameter Symbol AVF1 AVF2 Filter bypass mode output gain AVB1 AVB2 Filter bypass mode gain error Channel channel gain error Maximum output voltage dAVBP dAVCH Vout1 Vout2 THDB1 Output distortion THDB2 THDC1 THDC2 Channel channel crosstalk input input crosstalk Drive load resistance response time MUXSEL switch response time XTLK1 XTLK2 Mode: (0dB), 1.0% Mode: (6dB), 1.5% Mode: 1kHz, 1.4Vp-p Mode: 1kHz, 1.2Vp-p Mode: 1kHz, 1.4Vp-p Mode: 1kHz, 1.0Vp-p 0.5Vp-p input, 1MHz, between channels 0.5Vp-p input, 1MHz, between INnA-INnB, load Response time from output when changing settings Response time Gain Gain Gain Gain Gain error between filter mode bypass mode Condition Filter mode output gain Vp-p Vp-p load Unit Test level
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SM5302A
Reference Voltage Characteristics (REF)
5.0V, 5.5V, 25°C, unless otherwise noted.
Rating Parameter Symbol output voltage REF1 REF2 REF3 Condition 2.45 2.65 1.90 Unit Test level
Test level 100% products tested 25°C. Guaranteed result design characteristics evaluation. Mode Condition Settings
Table Mode settings
Input type Mode setting CH-1 Clamp Bias Clamp Bias Clamp Bias Clamp Direct Bypass Standard Filter Half Bypass Half Filter Bias Bias Standard CH-2 CH-3 Output gain mode Filter/Bypass mode
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SM5302A Evaluation Circuit Diagram
Controller
REF1 MUXSEL 4.7µ
REF2 REF3 VCC1
100µ
0.1µ
100µ
OUT1A OUT1B GND1 VCC2
4.7µ
100µ
Output
4.7µ
IN1A IN1B
OUT2A OUT2B GND2 VCC3 OUT3A OUT3B GND3 100µ
Input 4.7µ
ISET IN2A IN2B 4.7µ
IN3A IN3B
4.7µ
RISET 1.8k
Note. This electrical characteristics evaluation circuit only, then recommended application circuit.
SEIKO CORPORATION
SM5302A
FUNCTIONAL DESCRIPTION
Control
SM5302A uses interface following functions. Cutoff frequency Output gain mode switching (1/2 cutoff frequency switching) Filter mode/filter bypass mode switching Input multiplexer selection Input type switching (sync-tip clamp, bias, direct) Disable function Maximum number slave addresses
supports fast-mode data transfer rate 400kbit/s). Note that SM5302A does have read function write only). Basic cycle
Start condition
Stop condition
start/stop condition basic access cycle comprises following elements. Start condition byte: Slave address byte: Subaddress byte: Control data Stop condition
input data does match slave address subaddress incorrect, corresponding (acknowledge) output LOW. However, output after byte irrespective byte data. Also note that does have subaddress auto-increment function, hence each subaddress access requires basic cycle steps
Start
byte:Slave address
byte:Subaddress
byte:Control data
Stop
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SM5302A byte: slave address three slave addresses. Note that must (Write)".
byte: slave address Open*1
When open (94h), control able address. "P16. Maximum number slave addresses."
byte: subaddress byte sets subaddress, selecting three registers.
byte: subaddress Register name FCSET CONDITION1 CONDITION2
byte: control data byte control data sets register flags corresponding subaddress selected byte. flags assigned shown following table.
byte: control data Register name FCSET CONDITION1 CONDITION2 HALF BYPASS
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SM5302A Flag settings Cutoff frequency Register name: FCSET Flag names: FCM, [6:0] FCSET register setting sets cutoff frequency using tuning adjustment functions, thus total values possible. cutoff frequency determined following equations. values shown "Lowpass Filter". FCDATA FCDATA2 FCDATA [MHz] FCDATA 255: FCDATA2 FCDATA [MHz] coefficients when RISET 1.8k are: 1.95e 2.07e 4.74 3.92e 4.33e 41.2
Flag name FCDATA FCSET 43.26 43.49 43.73 27.57 27.73 27.88 7.80 8.13 8.47 Cutoff frequency [MHz] 4.74 4.95 5.15 Default
Input type switching (sync-tip clamp, bias, direct) Register name: CONDITION1 Flag names: [5:4], [3:2], [1:0] These flags input type CH-1, CH-2, CH-3 three types: sync-tip clamp input, bias input, direct input.
Channel CH-1 CH-2 CH-3 Flag name Don't care Input type Default
Sync-tip clamp input Bias input Direct input*1
input coupling capacitor should connected when direct input selected.
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SM5302A Output gain Register name: CONDITION1 Flag name:
Flag name Output gain Default
Disable mode select Register name: CONDITION2 Flag name: This flag enables/disables analog block. When analog block disabled, output pins high impedance.
Flag name Mode Enable (normal operation) Disable operation) Default
Input multiplexer selection Register name: CONDITION2 Flag name: This flag selects input three channels Note that this flag significant only when MUXSEL input LOW. "Input Multiplexer Switching (MUXSEL)".
Flag name INnA INnB Input selection*1 Default
mode switching (1/2 cutoff frequency switching) Register name: CONDITION2 Flag name: HALF This flag switches cutoff frequency CH-2 CH-3 divide value FCSET register into halves. Note that CH-1 cutoff frequency cannot switched. This mode suitable systems where sampling frequency varies requirements, such digital component signals digital HDTV signals.
Flag name mode HALF Standard mode (CH-1, CH-2, CH-3 cutoff frequency identical) Half mode (CH-2, CH-3 cutoff frequency that CH-1) Default
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SM5302A Filter bypass mode Register name: CONDITION2 Flag name: BYPASS This flag allows lowpass filter bypassed. output gain switched, even filter bypass mode. input type, multiplexer function, output gain just filter mode. However, cutoff frequency mode settings have effect outputs.
Flag name BYPASS Filter Filter mode (signals pass through lowpass filter) Filter bypass mode (signals bypass lowpass filter) Default
Maximum number slave addresses Register name: CONDITION2 Flag name: flag sets maximum number slave addresses either setting modifies input equivalent circuit shown below. When (max switches SW31 SW33 OFF, reducing current consumed comparison when HIGH (max Note that only input levels (LOW HIGH) valid. When HIGH (max switches SW31 SW33 hence current consumed regardless whether input LOW, HIGH, Open. However, note that input levels valid. Note. default value HIGH (max once (max device addressed setting when Open, that device subsequently longer accessible.
Flag name Maximum number slave address (2-address mode) (3-address mode) Default level HIGH Open HIGH Open Slave address 1001000 1001001 Invalid 1001000 1001001 1001010 current flow
NCA=2
SW21
Control
NCA=L(2) Address decoder NCA=H(3)
SW31 SW32 SW33
NCA=3
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SM5302A
Lowpass Filter
built-in 5th-order lowpass filters with variable cutoff frequency. frequency range determined resistor (RISET) connected between ISET GND, cutoff frequency register FCDATA data. cutoff frequency FCDATA values listed table shown graphically figure
Table Cutoff frequency FCDATA (RISET 1.8k)
FCDATA FCSET (hex) Cutoff freq. [MHz] 4.74 4.95 5.15 5.36 5.56 5.77 5.97 6.18 6.38 6.59 6.79 6.99 7.20 7.40 7.60 7.80 8.00 8.20 8.40 8.60 8.80 9.00 9.20 9.40 9.60 9.79 9.99 10.19 10.38 10.58 10.77 10.97 11.16 11.36 11.55 11.75 11.94 12.13 12.32 12.52 12.71 12.90 13.09 13.28 13.47 13.66 13.85 14.04 14.23 14.41 14.60 14.79 14.98 15.16 15.35 15.54 15.72 15.91 16.09 16.27 16.46 16.64 16.82 17.01 FCDATA FCSET (hex) Cutoff freq. [MHz] 17.19 17.37 17.55 17.73 17.91 18.09 18.27 18.45 18.63 18.81 18.99 19.17 19.35 19.52 19.70 19.88 20.05 20.23 20.40 20.58 20.75 20.93 21.10 21.27 21.45 21.62 21.79 21.96 22.13 22.30 22.47 22.65 22.81 22.98 23.15 23.32 23.49 23.66 23.83 23.99 24.16 24.33 24.49 24.66 24.82 24.99 25.15 25.31 25.48 25.64 25.80 25.97 26.13 26.29 26.45 26.61 26.77 26.93 27.09 27.25 27.41 27.57 27.73 27.88 FCDATA FCSET (hex) Cutoff freq. [MHz] 7.80 8.13 8.47 8.80 9.13 9.45 9.78 10.11 10.44 10.76 11.09 11.41 11.74 12.06 12.38 12.70 13.02 13.34 13.66 13.98 14.30 14.61 14.93 15.25 15.56 15.87 16.19 16.50 16.81 17.12 17.43 17.74 18.04 18.35 18.66 18.96 19.27 19.57 19.88 20.18 20.48 20.78 21.08 21.38 21.68 21.98 22.27 22.57 22.87 23.16 23.45 23.75 24.04 24.33 24.62 24.91 25.20 25.49 25.78 26.06 26.35 26.63 26.92 27.20 FCDATA FCSET (hex) Cutoff freq. [MHz] 27.49 27.77 28.05 28.33 28.61 28.89 29.17 29.44 29.72 30.00 30.27 30.55 30.82 31.09 31.36 31.63 31.90 32.17 32.44 32.71 32.98 33.24 33.51 33.77 34.04 34.30 34.56 34.83 35.09 35.35 35.61 35.87 36.12 36.38 36.64 36.89 37.15 37.40 37.65 37.91 38.16 38.41 38.66 38.91 39.16 39.40 39.65 39.90 40.14 40.39 40.63 40.87 41.11 41.36 41.60 41.84 42.07 42.31 42.55 42.79 43.02 43.26 43.49 43.73
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SM5302A
FCDATA
Figure Cutoff frequency FCDATA (RISET 1.8k)
RISET
RISET controls internal current source, connection essential. recommended value 1.8k. disable mode filter bypass mode, ISET high impedance, current flows into RISET. Note. value other than 1.8k will change current consumption, caution should taken ensure power dissipation does exceed absolute maximum rating package.
Half Mode
half mode, CH-2 CH-3 cutoff frequency that CH-1 cutoff frequency setting. Half mode useful systems where sampling frequency varies luminance color difference signal (Cr, requirements digital component signals. Note figure that cutoff frequency ratio given cutoff frequency setting (FCDATA) constant.
Group Delay Characteristics
group delay varies with cutoff frequency setting, shown figure Note also that half mode, group delay between CH-1 CH-2/CH-3 varies.
HALF High RISET 1.8k
[MHz]
FCDATA
Group delay [ns]
Ratio
FCDATA
FCDATA
Frequency [MHz]
Figure Cutoff frequency ratio (half mode)
Ratio CH-2 CH-3 cutoff frequency half mode based CH-1 cutoff frequency.
Figure Group delay characteristics
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SM5302A
Filter Bypass Mode
filter bypass mode, lowpass filter bypassed signal input output buffer stage. input type, multiplexer function, output gain just filter mode. cutoff frequency setting mode setting have effect outputs. this mode, passband frequency 80MHz (typ), which support SXGA-class signals.
Input Multiplexer Switching (MUXSEL)
input multiplexer setting also using MUXSEL input. When using BUS, certain amount communication time required, setting made using MUXSEL input with arbitrary timing high-speed switching.
MUXSEL flag Multiplexer selection*1 INnA INnB INnB INnB
Power-ON Reset
When power applied, internal power-ON reset circuit operates initializing internal register flags their default settings. power-ON, supplies should applied simultaneously.
Compensation Circuit
compensation circuit built-in between OUTnA OUTnB pins. circuits where load resistance small capacitance required large, using compensation circuit allows total capacitance mounting area reduced. compensation circuit used, output OUTnA should connected OUTnB. electrical characteristics guaranteed OUTnB left open circuit.
OUTnA
OUTnA
OUTnB
OUTnB
Figure Connection without compensation circuit
Figure Connection with compensation circuit
Reference Voltage (REF)
REFn pins internal reference voltage outputs. capacitor connected ground recommended stability. REF1, REF2, REF3 independent reference voltage outputs, have correspondence with channels CH-1, CH-2, CH-3. disable mode, they high impedance outputs.
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SM5302A
USAGE PRECAUTIONS
Slave Address (94h) Setting
When slave address used, input must left open circuit. this case, external resistor should connected shown figure reduce risk malfunction large external spikes other noise. recommended value 10k.
Oscillation Prevention Capacitor Connection
compensation circuit used with output capacitors connected, capacitors should mounted within approximately pins. distance exceeds 8cm, they cause oscillation. 15pF oscillation prevention capacitor should connected between OUTnA OUTnB. compensation circuit used, OUTnA connected OUTnB. there only output capacitor, oscillation prevention capacitor required.
Unused Analog Inputs
recommended that unused analog inputs should connected ground through capacitor shown figure
Direct Input Mode
direct input mode, signal connected input without input capacitor. However, input voltage range varies with mode setting, hence signal must appropriately biased corresponding mode. recommended LOW-level voltage (VL) HIGH-level voltage (VH) each mode shown table (see figure 5V). input voltage exceeds these limits, harmonic distortion occur output signal. Note that even these limits exceeded, device breakdown will occur still within absolute maximum ratings.
OUTnA
OUTnB
Slave address
Figure Slave address setting
Figure Oscillation prevention capacitor connection
INnA (Used input)
Video Signal
Video Signal
INnA INnB
INnB (Unused input)
Figure Unused analog inputs
Figure Direct input mode
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SM5302A
Table Direct mode recommended input voltage range (VCC
Mode setting Gain mode Filter/Bypass mode compensation circuit*1 Used CH-2, CH-3 Standard CH-1 used CH-2, CH-3 Filter CH-1 Used CH-2, CH-3 Half CH-1 used CH-2, CH-3 CH-1 Used CH-2, CH-3 Bypass CH-1 used CH-2, CH-3 CH-1 Used CH-2, CH-3 Standard CH-1 used CH-2, CH-3 Filter CH-1 Used CH-2, CH-3 Half CH-1 used CH-2, CH-3 CH-1 Used CH-2, CH-3 Bypass CH-1 used CH-2, CH-3 Refer figure "Sag Compensation Circuit". 2.95 Channel
CH-1
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SM5302A
TYPICAL CHARACTERISTICS
5.0V, 5.0V, 25°C, 1.0Vp-p, RISET 1.8k, unless otherwise noted.
Gain Phase Frequency [MHz]
-180 -270 -360 -450 -540 -630
Gain
Group delay Frequency [MHz]
Figure Gain Phase characteristics (6dB, filter bypass mode)
Figure Gain Group delay characteristics (6dB, filter bypass mode)
Gain Phase Frequency [MHz]
-180 -270 -360 -450 -540 -630
Gain
Group delay
Frequency [MHz]
Figure Gain Phase characteristics (6dB, standard mode, FCDATA
Figure Gain Group delay characteristics (6dB, standard mode, FCDATA
Gain Phase Frequency [MHz]
-180 -270 -360 -450 -540 -630
Phase [deg]
Gain Group delay
Frequency [MHz]
Figure Gain Phase Characteristics (6dB, half mode, FCDATA
Figure Gain Group delay characteristics (6dB, half mode, FCDATA
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Group delay [ns]
Gain [dB]
Gain [dB]
Group delay [ns]
Phase [deg]
Gain [dB]
Gain [dB]
Group delay [ns]
Phase [deg]
Gain [dB]
Gain [dB]
SM5302A
Gain Phase Frequency [MHz]
-180 -270 -360 -450 -540 -630
Gain Group delay Frequency [MHz]
Figure Gain Phase characteristics (6dB, standard mode, FCDATA 227)
Figure Gain Group delay characteristics (6dB, standard mode, FCDATA 227)
Gain Phase Frequency [MHz]
-180 -270 -360 -450 -540 -630
Gain Group delay Frequency [MHz]
Figure Gain Phase characteristics (6dB, half mode, FCDATA 227)
Figure Gain Group delay characteristics (6dB, half mode, FCDATA 227)
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Group delay [ns]
Phase [deg]
Gain [dB]
Gain [dB]
Group delay [ns]
Phase [deg]
Gain [dB]
Gain [dB]
SM5302A
(Bypass mode)
(Bypass mode)
Phase [deg]
Gain [dB]
-180 -270 -360 -450 -540 -630
Frequency [MHz]
Frequency [MHz]
Figure Gain FCDATA, mode (6dB)
Figure Phase FCDATA, mode (6dB)
FCDATA
mode standard half standard half
FCDATA
mode standard half standard half
Group delay [ns]
(Bypass mode)
Frequency [MHz]
Figure Group delay FCDATA, mode (6dB)
FCDATA mode standard half standard half
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SM5302A
ICC1*1 ICC2*2 4.25 4.75 5.25 5.75
ICC1*1 ICC2*2
[mA]
[mA]
[°C]
Figure ICC1 (6dB, FCDATA 255)
filter mode, FCDATA filter bypass mode
Figure ICC1 (6dB, FCDATA 255)
filter mode, FCDATA filter bypass mode
Gain [dB] FCDATA Gain [dB] [°C] [°C] ICC1 [mA] 4.25 4.75 5.25 5.75
Figure ICC1 FCDATA (6dB)
Figure Gain (6dB)
Gain [dB]
-0.5
4.25 4.75 5.25 5.75
Figure Gain (6dB)
Figure Gain (0dB)
Gain [dB]
-0.5
Figure Gain (0dB)
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SM5302A
Please your attention following points time using products shown this document. products shown this document (hereinafter "Products") intended used apparatus that exerts harmful influence human lives defects, failure malfunction Products. Customers requested obtain prior written agreement such from SEIKO CORPORATION (hereinafter "NPC"). Customers shall solely responsible for, indemnify hold free harmless from, claims, damages, losses, expenses lawsuits, such without such agreement. reserves right change specifications Products order improve characteristic reliability thereof. makes claim warranty that contents described this document dose infringe intellectual property right other similar right owned third parties. Therefore, shall responsible such problems, even accordance with descriptions provided this document. descriptions including applications, circuits, parameters Products this document reference Products, shall guaranteed free from defect, inapplicability design mass-production products without further testing modification. Customers requested export re-export, directly indirectly, Products country entity compliance with violation national export administration laws, treaties, orders regulations. Customers requested appropriately take steps obtain required permissions approvals from appropriate government agencies.
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15-6, Nihombashi-kabutocho, Chuo-ku, Tokyo 103-0026, Japan Telephone: +81-3-6667-6601 Facsimile: +81-3-6667-6611 http://www.npc.co.jp/ Email: sales@npc.co.jp
NC0301BE 2006.04
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3-channel Video Buffer with Built-in wideband SM5302A 3-channel v

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