10/100 Mbps 3-port Ethernet Switch Controller with General Processor I
|
|
|
Top Searches for this datasheet
DM9013
10/100 Mbps 3-port Ethernet Switch Controller with General Processor Interface
Preliminary Version: DM9013-DS-P03 April 2009
DM9013
3-port switch with Processor Interface
CONTENT
GENERAL DESCRIPTION. BLOCK DIAGRAM. FEATURES CONFIGURATION LQFP. DESCRIPTION
Processor Interface General pins RMII Reverse Interfaces 5.3.1 Interfaces 5.3.2 RMII Interfaces. 5.3.3 Reverse Interfaces EEPROM Interfaces Pins Clock Interface. Network Interface Miscellaneous Pins Power Pins 5.10 Strap Pins Table 5.10.1 Strap 3-port mode. 5.10.2 Strap 2-port mode.
Preliminary datasheet DM9013-15-DS-P03 April 2009
DM9013
3-port switch with Processor Interface CONTROL STATUS REGISTER SET.
Network Control Register (00H) Network Status Register (01H). Control Register (02H). Control Register (05H) Status Register (06H) Receive Overflow Counter Register (07H) Flow Control Register (0AH). EEPROM Control Register (0BH) EEPROM Address Register (0CH) 6.10 EPROM Data Register (0DH~0EH) 6.11 Physical Address Register (10H~15H) 6.12 Multicast Address Register (16H~1DH). 6.13 General Purpose Control Register (1EH) 6.14 General Purpose Register (1FH) 6.15 Packet Length Register 6.16 Packet Length High Register 6.17 Additional Status Register 6.18 Additional Control Register 6.19 Vendor Register (28H~29H)
Preliminary datasheet DM9013-15-DS-P03 April 2009
DM9013
3-port switch with Processor Interface
6.20 Product Register (2AH~2BH) 6.21 Chip Revision Register (2CH) 6.22 Transmit Control Register (2DH) 6.23 Transmit Check Control Register (31H) 6.24 Receive Check Control Status Register (32H). 6.25 General Purpose Control Register (34H) 6.26 General Purpose Register (35H) 6.27 General Purpose Control Register (36H) 6.28 General Purpose Register (37H) 6.29 Processor Data driving capability Register (38H) 6.30 Port driving capability Register (3AH). 6.31 Control Register (39H) 6.32 Block Size Control Register (3FH) 6.33 Monitor Register (40H) 6.34 Monitor Register (41H) 6.35 Monitor Register (42H) 6.36 Monitor Register (43H) 6.37 Switch Control Register (52H). 6.38 VLAN Control Register (53H) 6.39 Switch Status Register (54H) 6.40 Bandwidth Control Register (55H).
Preliminary datasheet DM9013-15-DS-P03 April 2009
DM9013
3-port switch with Processor Interface
6.41 Port Control/Status Index Register (60H). 6.42 Port Control Data Register (61H) 6.43 Port Status Data Register (62H) 6.44 Port Forward Control Register (65H) 6.45 Port Ingress/Egress Control Register (66H) 6.46 Bandwidth Control Setting Register (67H). 6.47 Port Block Unicast ports Control Register (68H) 6.48 Port Block Multicast ports Control Register (69H). 6.49 Port Block Broadcast ports Control Register (6AH) 6.50 Port Block Unknown ports Control Register (6BH) 6.51 Port Priority Queue Control Register (6DH). 6.52 Port VLAN Byte Register (6EH) 6.53 Port VLAN High Byte Register (6FH). 6.54 counter Port Index Register (80H). 6.55 counter Data Register (81H~84H). 6.56 Port-based VLAN mapping table Registers (B0H~BFH). 6.57 Priority Registers (C0H~CFH). 6.58 VLAN Priority Registers (D0H~D1H) 6.59 Memory Data Pre-Fetch Read Command without Address Increment Register (F0H) 6.60 Memory Data Read Command with Address Increment Register (F2H).
Preliminary datasheet DM9013-15-DS-P03 April 2009
DM9013
3-port switch with Processor Interface
6.61 Memory Data Read address Register (F4H). 6.62 Memory Data Read address Register (F5H). 6.63 Memory Data Write Command without Address Increment Register (F6H). 6.64 Memory Data Write Command with Address Increment Register (F8H) 6.65 Memory Data Write address Register (FAH). 6.66 Memory Data Write address Register (FBH). 6.67 Packet Length Register (FCH~FDH) 6.68 Interrupt Status Register (FEH). 6.69 Interrupt Mask Register (FFH).
EEPROM FORMAT. REGISTERS
Basic Mode Control Register (BMCR) Basic Mode Status Register (BMSR) Identifier Register (PHYID1) 02H. Identifier Register (PHYID2) 03H. Auto-negotiation Advertisement Register (ANAR) 04H. Auto-negotiation Link Partner Ability Register (ANLPAR) Auto-negotiation Expansion Register (ANER) DAVICOM Specified Configuration Register (DSCR) DAVICOM Specified Configuration Status Register (DSCSR)
Preliminary datasheet DM9013-15-DS-P03 April 2009
DM9013
3-port switch with Processor Interface
8.10 10BASE-T Configuration/Status (10BTCSR) 12H. 8.11 Power Down Control Register (PWDOR) 13H. 8.12 (Specified config) Register 8.13 DAVICOM Specified Receive Error Counter Register (RECR) 8.14 DAVICOM Specified Disconnect Counter Register (DISCR) 8.15 Power Saving Control Register (PSCR)
FUNCTIONAL DESCRIPTION.
Processor memory management function: 9.1.1 Processor Interface 9.1.2 Direct Memory Access Control. 9.1.3 Packet Transmission. 9.1.4 Packet Reception Switch function:. 9.2.1 Address Learning 9.2.2 Address Aging 9.2.3 Packet Forwarding 9.2.4 Inter-Packet (IPG) 9.2.5 Back-off Algorithm. 9.2.6 Late Collision. 9.2.7 Full Duplex Flow Control 9.2.8 Half Duplex Flow Control 9.2.9 Partition Mode 9.2.10 Broadcast Storm Filtering. 9.2.11 Bandwidth Control. 9.2.12 Port Monitoring Support 9.2.13 VLAN Support 9.2.13.1 Port-Based VLAN. 9.2.13.2 802.1Q-Based VLAN.
Preliminary datasheet DM9013-15-DS-P03 April 2009
DM9013
3-port switch with Processor Interface
9.2.13.3 Tag/Untag 9.2.14 Priority Support 9.2.14.1 Port-Based Priority 9.2.14.2 802.1p-Based Priority. 9.2.14.3 DiffServ-Based Priority. Interface. 9.3.1 data interface 9.3.2 Serial Management 9.3.3 Serial Management Interface 9.3.4 Management Interface Read Frame Structure 9.3.5 Management Interface Write Frame Structure Internal functions 9.4.1 100Base-TX Operation 9.4.1.1 4B5B Encoder 9.4.1.2 Scrambler 9.4.1.3 Parallel Serial Converter 9.4.1.4 NRZI Encoder 9.4.1.5 MLT-3 Converter 9.4.1.6 MLT-3 Driver 9.4.1.7 4B5B Code Group. 9.4.2 100Base-TX Receiver 9.4.2.1 Signal Detect 9.4.2.2 Adaptive Equalization. 9.4.2.3 MLT-3 NRZI Decoder. 9.4.2.4 Clock Recovery Module 9.4.2.5 NRZI 9.4.2.6 Serial Parallel 9.4.2.7 Descrambler 9.4.2.8 Code Group Alignment. 9.4.2.9 4B5B Decoder. 9.4.3 10Base-T Operation. 9.4.4 Collision Detection 9.4.5 Carrier Sense
Preliminary datasheet DM9013-15-DS-P03 April 2009
DM9013
3-port switch with Processor Interface
9.4.6 Auto-Negotiation
ELECTRICAL CHARACTERISTICS
10.1 Absolute Maximum Ratings 10.2 Operating Conditions. 10.3 Electrical Characteristics 10.4 characteristics 10.4.1 Power Reset Timing 10.4.2 Processor Read Timing. 10.4.3 Processor Write Timing 10.4.4 Port Interface Transmit Timing. 10.4.5 Port Interface Receive Timing. 10.4.6 Management Interface Timing 10.4.7 EEPROM Timing.
APPLICATION CIRCUIT PACKAGE INFORMATION. ORDERING INFORMATION
Preliminary datasheet DM9013-15-DS-P03 April 2009
DM9013
3-port switch with Processor Interface General Description
DM9013 fully integrated cost-effective fast Ethernet switch controller with ports 10M/100M PHY, port RMII Reverse interface, general processor interface. controller provides basic Layer-2 switch functions advanced IEEE 802.1Q VLAN priority queuing scheme. integrated ports compliant with IEEE 802.3u standards. interface provides flexibility connect Ethernet with MII/RMII interface. DM9013 provides direct interface general processor with 16-, 32-bit data access internal memory.
Block Diagram
Switch Engine Port MDIX 10/100M 10/100M Switch Fabric Embedded Memory Memory BIST
Port MDIX
10/100M
10/100M
Switch Controller
Memory Management
Port RMII Reverse
10/100M Control Processor Interface Host Control Registers Counters EEPROM Interface Bandwidth LEDs
Processor
EEPROM
Preliminary datasheet DM9013-15-DS-P03 April 2009
DM9013
3-port switch with Processor Interface Features Ethernet Switch with 10/100Mb PHY, MII/RMII, general processor interface Support Reverse-MII Processor slave architecture EEPROM interface power configurations Support TCP/UDP/IPv4 checksum offload Support Auto-MDIX Support IEEE 802.3x Flow Control Full-duplex mode Support Back Pressure Flow Control Half-duplex mode port support priority queues Port-based, 802.1P VLAN, priority Support 802.1Q VLAN up-to VLAN group Support VLAN tag/untag options port support bandwidth, ingress egress rate control Support Broadcast Storming filter function Support Store Forward switching approach Support up-to Uni-cast addresses Automatic aging scheme Support counters diagnostic data driving capability adjustable Port TXD/TXE driving capability adjustable Auto. control prevent memory read count error 128-pin LQFP 1.8V internal core, 3.3V with tolerant
Preliminary datasheet DM9013-15-DS-P03 April 2009
DM9013
3-port switch with Processor Interface Configuration LQFP
BGRESG RXD2_1 RXD2_2 RXD2_3 RXD2_0 BGRES AVDD3 AVDD3
RXDV2
RXER2
TEST3
TEST2
AGND AGND
AVDDI
TEST1
AVDDI
AGND
AGND
VCC3
RX0+
VCNTL VREF AVDD3 VCC3 LNK1_LED SPD1_LED FDX1_LED LNK0_LED SPD0_LED FDX0_LED SCLK BWLED0 VCCI BWLED1 BWLED2 BWLED3 BWLED4 BWLED5 BWLED6 BWLED7
CRS2
RXC2
COL2
RX1+
RX0-
TX0TX0+
TX1+
RX1-
TX1-
TXC2 TXE2 VCC3 TXD2_0 TXD2_1 TXD2_2 TXD2_3 VCCI MDIO PWRST# EECS EECK EEDO EEDI VCC3 SD31 SD30 SD29 SD28 SD27 SD26 VCC3 SD25 SD24 SD23 SD22 SD21 SD20
DM9013
VCCI SD14
VCC3
VCC3
VCC3
SD10
SD15
SD17
SD18
SD11
SD13
SD12
IOW#
SD16
SD19
IOR#
Preliminary datasheet DM9013-15-DS-P03 April 2009
DM9013
3-port switch with Processor Interface Description
Input, Output, Input Output, Open Drain, Power, PD=internal pull-low (about Ohm) asserted Processor Interface
Name
Description Command Type When high, access this command cycle DATA port When low, access this command cycle INDEX port Processor Chip select Command Processor Write Command Processor Read Command Interrupt Request Processor Data 0~15 Processor Data 16~31 General purpose pins when data 16-bit mode Reserved
7,8,9,10,12,13,14,15, 16,17,19,20,22,23,25,26 28,29,30,31,33,34,36,37, 38,39,41,42,43,44,46,47
IOW# IOR# SD0~15 SD16~31 Reserved
General pins 118,117,115,114, 113,112,111 119,121,122,123, 124,126,127,128
Name GP0~6 BWLED0~7
Description General Ports Registers GPCR program these pins Bandwidth
RMII Reverse Interfaces 5.3.1 Interfaces 58,59,60,61
Preliminary datasheet DM9013-15-DS-P03 April 2009
Name MDIO TXD2_3~0 TXE2 TXC2 CRS2 COL2 RXER2
O,PD O,PD O,PD
Description Serial Management Data Clock Serial Management Data Port Transmit Data 4-bit nibble data outputs (synchronous TXC2) Port Transmit Enable Port Transmit Clock. Port Carrier Sense Port Collision Detect. Port Receive Error
DM9013
3-port switch with Processor Interface
71,72,73,74 RXC2 RXDV2 RXD2_3~0 Port Receive Clock Port Receive Data Valid Port Receive Data 4-bit nibble data input (synchronous RXC2)
5.3.2 RMII Interfaces 58,59 60,61 71,72 73,74
Name MDIO TXD2_3~2 TXD2_1~0 TXE2 TXC2 CRS2 COL2 RXER2 RXC2 RXDV2 RXD2_3~2 RXD2_1~0
O,PD O,PD O,PD O,PD
Description Serial Management Data Clock Serial Management Data Reserved RMII Transmit Data RMII Transmit Enable. Reserved RMII CRS_DV Reserved, ground application. Reserved, ground application. 50MHz reference clock. Reserved, ground application. Reserved, ground application. RMII Receive Data.
5.3.3 Reverse Interfaces Name 58,59,60,61 71,72,73,74 MDIO TXD2_3~0 TXE2 TXC2 CRS2 COL2 RXER2 RXC2 RXDV2 RXD2_3~0
O,PD O,PD O,PD
Description Reserved Reserved Port Transmit Data 4-bit nibble data outputs (synchronous TXC2) Port Transmit Enable 25MHz clock output Port carrier sense output when TXE2 RXDV2 asserted. Port collision output when TXE2 RXDV2 asserted. Port Receive Error Port Receive Clock Port Receive Data Valid Port Receive Data 4-bit nibble data input (synchronous RXC2)
Preliminary datasheet DM9013-15-DS-P03 April 2009
DM9013
3-port switch with Processor Interface
EEPROM Interfaces Name EEDI EEDO I,PD O,PD Description EEPROM Data EEPROM Data This used serially write op-codes, addresses data into EEPROM. EEPROM Serial Clock This used clock EEPROM data transfer. EEPROM Chip Selection.
Pins
EECK EECS
O,PD O,PD
Name LNK1_LED
Description Port Link Active combined link carrier sense signal internal PHY1 Port Speed output indicates that internal PHY1 operated 100M/S, floating mode internal PHY1 Port Full-duplex output indicates that internal PHY1 operated full-duplex mode, floating half-duplex mode internal PHY1 Port Link Active combined link carrier sense signal internal PHY0 Port Speed output indicates that internal PHY0 operated 100M/S, floating mode internal PHY0 Port Full-duplex output indicates that internal PHY0 operated full-duplex mode, floating half-duplex mode internal PHY0
SPD1_LED
FDX1_LED
LNK0_LED
SPD0_LED
FDX0_LED
Preliminary datasheet DM9013-15-DS-P03 April 2009
DM9013
3-port switch with Processor Interface
Clock Interface Network Interface 80,81 84,85 88,89 92,93 Miscellaneous Pins Name SCLK Description Crystal 25MHz Crystal 25MHz External system clock source
Name TX1+/RX1+/TX0+/RX0+/BGRES BGGND VCNTL VREF
Port Port Port Port Band Band Ground 1.8V Voltage control Voltage Reference
Description
Name PWRST# TEST1 TEST2
Description
Power Pins 4,18,32,40,48,62,75,100 24,57,120 11,21,27,35,45, 54,69,103,125 86,94,99 79,87 82,83,90,91
TEST3
Power Reset. I,PD ground application I,PD 3-port mode ports active this mode. 2-port mode Only ports active this mode. Port port disabled strap TXEN2. this mode, disabled port's memory resource shared processor port other ports. I,PD ground application
Name VCC3 VCCI AVDD3 AVDDI AGND
Description Digital 3.3V Internal 1.8V core power Digital Analog 3.3V power Analog 1.8V power Analog
Preliminary datasheet DM9013-15-DS-P03 April 2009
DM9013
3-port switch with Processor Interface
5.10 Strap Pins Table pull-high 1K~10K, default floating. 5.10.1 Strap 3-port mode
Name Description
EECK EEDO
EECS TXD2_3 TXD2_2
60,61
TXD2_1,0
TXEN2
Processor Data Width EECK EEDO data width 16-bit 32-bit 8-bit reserved internal system clock SCLK system clock Polarity high active active; control GP6/5 normal general purpose pins IO16, IOWAIT used only Port force mode strap link status, strap link status, strap full-duplex status, strap half-duplex status, strap speed100 status, strap speed10 status. mode (Default) reverse mode RMII mode reserved Output Type force output Open-Collect
Preliminary datasheet DM9013-15-DS-P03 April 2009
DM9013
3-port switch with Processor Interface
5.10.2 Strap 2-port mode Name Description EECK EEDO DATA Width EECK EEDO data width 16-bit 32-bit 8-bit reserved internal system clock SCLK system clock Polarity high active active; control GP6/5 normal general purpose pins IO16, IOWAIT used only Port force mode strap link status, strap link status, strap full-duplex status, strap half-duplex status, strap speed100 status, strap speed10 status. TXD2_1 TXD2_0 Port mode mode (Default) reverse mode RMII mode reserved port disabled port disabled
EECS
TXD2_3 TXD2_2
60,61
TXD2_1,0
TXEN2
Preliminary datasheet DM9013-15-DS-P03 April 2009
DM9013
3-port switch with Processor Interface Control Status Register
DM9013 implements several control status registers, which accessed host. These CSRs Register Description ROCR EPCR EPAR EPDRL EPDRH GPCR RXPLLR RXPLHR RASR RACR CHIPR TCR2 TCSCR RCSCSR GPCR2 GPR2 GPCR3 GPR3 DRIVER IRQCR P2FRV TXBSCR MONIR1 MONIR2 MONIR3 SWITCHCR VLANCR SWITCHSR BWLED P_INDEX
Preliminary datasheet DM9013-15-DS-P03 April 2009
byte aligned. CSRs their default values hardware software reset unless specified Offset Default value after reset Network Control Register Network Status Register Control Register Control Register Status Register Receive Overflow Counter Register Flow Control Register EEPROM Control Register EEPROM Address Register EEPROM Byte Data Register EEPROM High Byte Data Register Processor Port Physical Address Registers 10H-15H EEPROM Processor Port Multicast Address Registers 16H-1DH General Purpose Control Register General Purpose Register Packet Length Register Packet Length High Register Additional Status Register Additional Control Register Vendor 28H-29H 0A46H Product 2AH-2BH 9013H CHIP Revision Control Register Transmit Check Control Register Receive Check Control Status Register General Purpose Control Register General Purpose Register General Purpose Control Register General Purpose Register Data driving capability Register Control Register Port driving capability Register Block Size Control Register Monitor Register Monitor Register Monitor Register SWITCH Control Register VLAN Control Register SWITCH Status Register Bandwidth Control Register Port Control/Status Index Register
DM9013
3-port switch with Processor Interface
P_CTRL P_STUS P_RATE P_BW P_UNICAST P_MULTI P_BCAST P_UNKNWN P_PRI VLAN_TAGL VLAN_TAGH P_MIB_IDX MIB_DAT MIB_DAT MIB_DAT MIB_DAT PVLAN TOS_MAP VLAN_MAP MRCMDX MRCMD MRRL MRRH MWCMDX MWCMD Port Control Data Register Port Status Data Register Port Ingress Egress Rate Control Register Bandwidth Control Register Port Block Unicast ports Control Register Port Block Multicast ports Control Register Port Block Broadcast ports Control Register Port Block Unknown ports Control Register Port Priority Queue Control Register Port VLAN Byte Register Port VLAN High Byte Register Port counter Index Register counter Data Register counter Data Register 8~15 counter Data Register 16~23 counter Data Register 24~31 Port-based VLAN mapping table registers Priority Register VLAN priority Register Memory Data Pre-Fetch Read Command Without Address Increment Register Memory Data Read Command With Address Increment Register Memory Data Read address Register Byte Memory Data Read address Register High Byte Memory Data Write Command Without Address Increment Register Memory Data Write Command With Address Increment Register Memory Data Write address Register Byte Memory Data Write address Register High Byte Packet Length Byte Register Packet Length High Byte Register Interrupt Status Register Interrupt Mask Register B0-BFH C0-CFH D0-D1H 00H~FFH 50H,FAH
MWRL MWRH TXPLL TXPLH Default register description that follows, default column takes form: <Reset Value>, <Access Type> Where: <Reset Value>: logic logic zero default value power reset default value hardware reset command default value software reset default value
default value from EEPROM default value from strap <Access Type>: Read only Read/Write Read Clear RW/C1=Read/Write Cleared write Write only Reserved bits shaded should written with Reserved bits undefined read access.
Preliminary datasheet DM9013-15-DS-P03 April 2009
DM9013
3-port switch with Processor Interface
Network Control Register (00H) Name Default Description RESERVED 0,RO Reserved RESERVED P0,WO Reserved CLR1 PH0,RW REG. auto-cleared after read REG. cleared writing respected bit. RESERVED 0,RO Reserved PH0, Loopback test Mode PH0,RW Software reset auto clear after 10us Network Status Register (01H) Name Default Description RESERVED 0,RO Reserved RESERVED PH0, Reserved RESERVED 0,RO Reserved TX2END PHS0, Packet Complete Status. RW/C1 This after transmit completion packet index set, this cleared write Otherwise cleared read write TX1END PHS0, Packet Complete status. RW/C1 This after transmit completion packet index set, this cleared write Otherwise cleared read write RESERVED 0,RO Reserved Control Register (02H) Name Default RESERVED 0,RO CRC_DIS2 PHS0,RW RESERVED 0,RO CRC_DIS1 PHS0,RW TXREQ PHS0,RW Control Register (05H) Name Default HASHALL PHS0,RW RESERVED PHS0,RW RESERVED PHS0,RW RESERVED PHS0,RW PHS0,RW RESERVED PHS0,RW PRMSC PHS0,RW RXEN PHS0,RW
Description Reserved Appends Disable Packet Index Reserved Appends Disable Packet Index Request. Auto clears after transmit completely
Description Filter address Hash Table Reserved Reserved Reserved Pass Multicast Packets Reserved Promiscuous Mode Enable
Preliminary datasheet DM9013-15-DS-P03 April 2009
DM9013
3-port switch with Processor Interface
Status Register (06H) Name Default RESERVED 0,RO SRCP 0,RO PH0,RO RESERVED 0,RO Description Reserved Source Port Number Error indicate that received frame ends with error Reserved
Receive Overflow Counter Register (07H) Name Default Description RXFU PHS0,R/C Receive Overflow Counter Overflow This when overflow condition PHS0,R/C Receive Overflow Counter This statistic counter indicate received packet count upon FIFO overflow Flow Control Register (0AH) Name Default RESERVED 0,RO FLOW_EN RESERVED PHS0,RW 0,RO
Description Reserved Flow Control Enable Enables pause packet high/low water threshold control Reserved
EEPROM Control Register (0BH) Name Default Description RESERVED 0,RO Reserved REEP PH0,RW Reload EEPROM. Driver needs clear after operation completes PH0,RW Write EEPROM Enable EPOS PH0,RW EEPROM Operation Select When reset, select EEPROM; when set, select ERPRR PH0,RW EEPROM Read Register Read Command. Driver needs clear after operation completes. ERPRW PH0,RW EEPROM Write Register Write Command. Driver needs clear after operation completes. ERRE PH0,RO EEPROM Access Status Access Status When set, indicates that EEPROM access progress EEPROM Address Register (0CH) Name Default Description PHY_ADR PH01,RW Address address [4:2] force EROA PH0,RW EEPROM Word Address Register Address 6.10 EPROM Data Register (0DH~0EH) Name Default Description EE_PHY_L PH0,RW EEPROM Byte Data (0DH) This data made write byte word address defined Reg. EEPROM EE_PHY_H PH0,RW EEPROM High Byte Data (0EH) This data made write high byte word address defined Reg. EEPROM
Preliminary datasheet DM9013-15-DS-P03 April 2009
DM9013
3-port switch with Processor Interface
6.11 Physical Address Register (10H~15H) Name Default PAB5 E,RW Physical Address Byte PAB4 E,RW Physical Address Byte PAB3 E,RW Physical Address Byte PAB2 E,RW Physical Address Byte PAB1 E,RW Physical Address Byte PAB0 E,RW Physical Address Byte 6.12 Multicast Address Register (16H~1DH) Name Default MAB7 X,RW Multicast Address Byte MAB6 X,RW Multicast Address Byte MAB5 X,RW Multicast Address Byte MAB4 X,RW Multicast Address Byte MAB3 X,RW Multicast Address Byte MAB2 X,RW Multicast Address Byte MAB1 X,RW Multicast Address Byte MAB0 X,RW Multicast Address Byte
Description (15H) (14H) (13H) (12H) (11H) (10H)
Description (1DH) (1CH) (1BH) (1AH) (19H) (18H) (17H) (16H)
6.13 General Purpose Control Register (1EH) Name Default Description RESERVED 0,RO Reserved PH,0,RW General Purpose Control Define input/output direction pins GP6~0 respectively. output, 0:input 6.14 General Purpose Register (1FH) Name Default Description RESERVED 0,RO Reserved GEPIO X,RW General Purpose Data These bits reflect GP6~0 respectively.
6.15 Packet Length Register Name Default RXPLL PH,RO Packet Length byte
Description
6.16 Packet Length High Register Name Default RXPLH PH,RO Packet Length High byte
Description
Preliminary datasheet DM9013-15-DS-P03 April 2009
DM9013
3-port switch with Processor Interface
6.17 Additional Status Register Name Default Description RESERVED 0,RO Reserved received pointer status, only available when pointer restriction enabled Reg27h.7=0). RPTRS PH,RO Within buffer buffer Exceed buffer 6.18 Additional Control Register Name Default RPRD PHS0,RW pointer restriction disable RESERVED 0,RO Reserved 6.19 Vendor Register (28H~29H) Name Default VIDH PE,0AH,RO Vendor High Byte (29H) VIDL PE,46H.RO Vendor Byte (28H) 6.20 Product Register (2AH~2BH) Name Default PIDH PE,90H,RO Product High Byte (2BH) PIDL PE,13H.RO Product Byte (2AH) 6.21 Chip Revision Register (2CH) Name Default CHIPR P01H,RO CHIP Revision
Description
Description
Description
Description
6.22 Transmit Control Register (2DH) Name Default Description RESERVED 0,RW Reserved, Clear application. RESERVED 0,RO Reserved ONEPM P0,RW Packet Mode When set, only packet transmit command issued before transmit completed. When cleared, most packet transmit command issued before transmit completed. RESERVED 0,RO Reserved 6.23 Transmit Check Control Register (31H) Name Default Description RESERVED 0,RO Reserved UDPCSE HP0,RW Checksum Generation Enable TCPCSE HP0,RW Checksum Generation Enable IPCSE HP0,RW Checksum Generation Enable
Preliminary datasheet DM9013-15-DS-P03 April 2009
DM9013
3-port switch with Processor Interface
6.24 Receive Check Control Status Register (32H) Name Default Description UDPS HP0,RO Checksum Status packet checksum fail TCPS HP0,RO Checksum Status packet checksum fail HP0,RO Checksum Status packet checksum fail UDPP HP0,RO This Packet TCPP HP0,RO This Packet HP0,RO This Packet RCSEN HPS0,RW Receive Checksum Checking Enable When set, checksum status will store packet first byte status header. DCSE HPS0,RW Discard Checksum Error Packet When set, IP/TCP/UDP checksum field error, this packet will discarded. 6.25 General Purpose Control Register (34H) Name Default Description GPC2 HP0,RW General Purpose Control Define input/output direction pins SD23~16, which used general purpose pins when none 32-bit mode external mode, respectively.
6.26 General Purpose Register (35H) Name Default Description GPD2 HP0,RW General Purpose Register Data When correspondent General Purpose Control Register set, value reflected SD23~16 When correspondent General Purpose Control Register value read reflected from correspondent pins SD23~16 6.27 General Purpose Control Register (36H) Name Default Description GPC3 HP0,RW General Purpose Control Define input/output direction pins SD31~24, which used general purpose pins when none 32-bit mode external mode, respectively.
6.28 General Purpose Register (37H) Name Default Description GPD3 HP0,RW General Purpose Register Data When correspondent General Purpose Control Register set, value reflected SD31~24 When correspondent General Purpose Control Register value read reflected from correspondent pins SD31~24
Preliminary datasheet DM9013-15-DS-P03 April 2009
DM9013
3-port switch with Processor Interface
6.29 Processor Data driving capability Register (38H) Name Default RESERVED 0,RW reserved Description
ISA_CURR Reserved STEP IOW_SPIKE IOR_SPIKE P01,RW P0,RW P0,RW P0,RW P1,RW
Current Driving/Sinking Capability (default) Reserved Data Output stepping disabled enabled Eliminate spike eliminate about spike Eliminate spike eliminate about spike
6.30 Port driving capability Register (3AH) Name Default Description Reserved 0,RO Reserved Port TXD/TXECurrent Driving/Sinking Capability P2_CURR P01,RW (default) RESERVED P01,RW reserved 6.31 Control Register (39H) Name Default Reserved PS0,RO Reserved Output Type Control IRQ_TYPE PET0,RW direct output Open-Collector output Polarity Control IRQ_POL PET0,RW active high active
Description
6.32 Block Size Control Register (3FH) Name Default Description Reserved PS0,RO Reserved Block Size 2-Port Mode This value defines transmit block size 256-byte unit. memory size TX_SIZE bytes TX_SIZE P20h,RW then memory size 16KB (TX_SIZE 1)*256-Byte Note: value TX_SIZE should between
Preliminary datasheet DM9013-15-DS-P03 April 2009
DM9013
3-port switch with Processor Interface
6.33 Monitor Register (40H) Name Default BWIDTH T0,RO DWIDTH T0,RO IRQOC ET0,RO IRQP ET0,RO IO16OC E0,RO IO16P E0,RO RESERVED 0,RO 6.34 Monitor Register (41H) Name Default TEST3 TEST2 TEST1 T0,RO EECS T0,RO EECK T0,RO EEDO T0,RO EEDI T0,RO 6.35 Monitor Register (42H) Name Default RESERVED 0,RO TXE2 T0,RO TXD2_3 T0,RO TXD2_2 T0,RO TXD2_1 T0,RO TXD2_0 T0,RO 6.36 Monitor Register (43H) Name Default RESERVED 0,RO GPIO T0,RO Description 8-bit Data Strap Latch Status 32-bit Data Strap Latch Status Open-Collect Status Polarity Status IO16 Open-Collect Status IO16 Polarity Status Reserved
Description TEST3 TEST2 TEST1 Strap Status EECS Strap Status EECK Strap Status EEDO Strap Status EEDI Strap Status
Description Reserved TXE2 Strap Status TXD2_3 Strap Status TXD2_2 Strap Status TXD2_1 Strap Status TXD2_0 Strap Status Description Reserved GPIO Strap Status
6.37 Switch Control Register (52H) Name Default Description MEM_BIST PH0,RO Address Memory Test BIST Status Fail RST_SW P0,RW Reset Switch Core auto clear after 10us RST_ANLG P0,RW Reset Analog Core auto clear after 10us SNF_PORT PE00,RW Sniffer Port Number CRC_DIS PE0,RW checking disable PE0,RW Aging aging 64sec+/- 32sec 128sec+/- 64sec 256sec+/- 128sec
Preliminary datasheet DM9013-15-DS-P03 April 2009
DM9013
3-port switch with Processor Interface
6.38 VLAN Control Register (53H) Name Default Description TOS6 PE0,RW Full Using Enable check most significant 3-bit only check most significant 6-bit RESERVED 0,RO Reserved UNICAST PE0,RW Unicast packet across VLAN boundary VIDFF PE0,RW Replace VIDFF VID1 PE0,RW Replace VID01 VID0 PE0,RW Replace VID0 PE0,RW Replace priority field VLAN PE0,RW VLAN mode enable port-base VLAN 802.1Q base VLAN mode enable 6.39 Switch Status Register (54H) Name Default Description MEM_BIST PH0,RO Address Memory Test BIST Status Fail RESERVED 0,RO Reserved 6.40 Bandwidth Control Register (55H) Name Default Description RESERVED PH0,RW Reserved P2_TX PH1,RW Port transmit event bandwidth source P2_RX PH0,RW Port receive event bandwidth source P1_TX PH1,RW Port transmit event bandwidth source P1_RX PH0,RW Port receive event bandwidth source P0_TX PH1,RW Port transmit event bandwidth source P0_RX PH0,RW Port receive event bandwidth source 6.41 Port Control/Status Index Register (60H) Name Default Description reserved PHS0,RW reserved reserved 0,RO reserved INDEX PHS0,RW Port index register 61h~84h Write port number this register before write/read register 61h~84h. 6.42 Port Control Data Register (61H) Name Default Description RESERVED PE0,RW Reserved PARTI_EN PE0,RW Enable Partition Detection NO_DIS_RX PE0,RW Discard Packets when Ingress Bandwidth Control
Preliminary datasheet DM9013-15-DS-P03 April 2009
DM9013
3-port switch with Processor Interface
FLOW_DIS PE0,RW Flow control full duplex mode, back pressure half duplex mode enable enable disable Bandwidth Control Control with Ingress Egress separately, Register 66h. Control with Ingress Egress, Register Broadcast packet filter accept broadcast packets reject broadcast packets Multicast packet filter accept multicast packets reject multicast packets Broadcast Storm Control only broadcast packet also multicast packet
BANDWIDTH
PE0,RW
BP_DIS
PE0,RW
MP_DIS
PE0,RW
MP_STORM
PE0,RW
6.43 Port Status Data Register (62H) Name Default Description RESERVED P0,RO Reserved LP_FCS P0,RO Link Partner Flow Control Enable Status BIST P0,RO BIST status SRAM BIST pass SRAM BIST fail RESERVED 0,RO Reserved SPEED2 P0,RO 10Mbps, 1:100Mbps FDX2 P0,RO half-duplex, full-duplex LINK2 P0,RO Link status, Link status 6.44 Port Forward Control Register (65H) Name Default Description LOOPBACK PH0,RW Loop-back mode MONI_TX PH0,RW Packet Monitored MONI_RX PH0,RW Packet Monitored DIS_BMP PH0,RW Broad/Multicast packet monitored Reserved PH0,RW Reserved TX_DIS PH0,RW Packet Transmit disabled RX_DIS PH0,RW Packet receive disabled ADR_DIS PH0,RW Address learning disabled
Preliminary datasheet DM9013-15-DS-P03 April 2009
DM9013
3-port switch with Processor Interface
6.45 Port Ingress/Egress Control Register (66H) Name Default INGRESS PE0,RW Ingress Rate Control 0000: none 0001: 0010: 128K 0011: 256K 0100: 512K 0101: 0110: 0111: 1000: 1001: 1010: 1011: 1100: 1101: 1110: 1111: EGRESS PE0,RW Egress Rate Control 0000: none 0001: 0010: 128K 0011: 256K 0100: 512K 0101: 0110: 0111: 1000: 1001: 1010: 1011: 1100: 1101: 1110: 1111: Description
Preliminary datasheet DM9013-15-DS-P03 April 2009
DM9013
3-port switch with Processor Interface
6.46 Bandwidth Control Setting Register (67H) Name Default Description BSTH PE0,RW Broadcast Storm Threshold 0000: broadcast storm control 0001: packets/sec 0010: packets/sec 0011: packets/sec 0100: 0101: 0110: 0111: 1000: 1001: 1010: 1011: 1100: 1101: 111X: broadcast storm control CTRL PE0,RW Received packet length counted. Bandwidth table below. 0000: none 0001: 0010: 128K 0011: 256K 0100: 512K 0101: 0110: 0111: 1000: 1001: 1010: 1011: 1100: 1101: 1110: 1111: 6.47 Port Block Unicast ports Control Register (68H) Name Default Description RESERVED PH0,RW Reserved BLK_UP PH0,RW Ports unicast packet blocked 6.48 Port Block Multicast ports Control Register (69H) Name Default Description RESERVED PH0,RW Reserved BLK_MP PH0,RW Ports multicast packet blocked 6.49 Port Block Broadcast ports Control Register (6AH) Name Default Description RESERVED PH0,RW Reserved BLK_BP PH0,RW Ports broadcast packet blocked
Preliminary datasheet DM9013-15-DS-P03 April 2009
DM9013
3-port switch with Processor Interface
6.50 Port Block Unknown ports Control Register (6BH) Name Default Description RESERVED PH0,RW Reserved BLK_UKP PH0,RW Ports unknown packet blocked 6.51 Port Priority Queue Control Register (6DH) Name Default Description TAG_OUT PE0,RW Output Packet Tagging Enable PRI_DIS PE0,RW Priority Queue Disable WFQUE PE0,RW 8:4:2:1 queue 8:4:2:1 TOS_PRI PE0,RW Priority over VLAN TOS_OFF PE0,RW Priority Classification disable PRI_OFF PE0,RW 802.1 Priority Classification disable P_PRI PE0,RW Port Base priority queue 01=queue 10=queue 11=queue 6.52 Port VLAN Byte Register (6EH) Name Default VID70 PE01,RW VID[7:0] 6.53 Port VLAN High Byte Register (6FH) Name Default PE0,RW [15:13] PE0,RW Tag[12] VID118 PE0,RW VID[11:8]
Description
Description
6.54 counter Port Index Register (80H) Name Default Description READY P0,RO counter data ready When this register written with INDEX data, this cleared counter reading progress. After read counter, data loaded into register 81H~84H, this indicate that data ready. reserved 0,RO Reserved INDEX PHS0,RW counter index 0~9, each counter 32-bit Register 81h~84h. Write counter index this register before read them. 6.55 counter Data Register (81H~84H) Name Default Counter0 X,RO Counter's data Counter1 X,RO Counter's data 15~8 Counter2 X,RO Counter's data 23~16 Counter3 X,RO Counter's data 31~24
Description
Preliminary datasheet DM9013-15-DS-P03 April 2009
DM9013
3-port switch with Processor Interface
counter: Byte Counter Registers (00H) counter: Uni-cast Packet Counter Registers (01H) counter: Multi-cast Packet Counter Registers (02H) counter: Discard Packet Counter Registers (03H) counter: Error Packet Counter Registers (04H) counter: Byte Counter Registers (05H) counter: Uni-cast Packet Counter Registers (06H) counter: Multi-cast Packet Counter Registers (07H) counter: Discard Packet Counter Registers (08H) counter: Error Packet Counter Registers (09H) 6.56 Port-based VLAN mapping table Registers (B0H~BFH) Name Default RESERVED PE0,RO Reserved PORTS PEF,RW Port 3(uP) 6.57 Priority Registers (C0H~CFH) C0H: C1H: C2H: Name TOSB TOSA TOS9 TOS8 Default PE0,RW PE0,RW PE0,RW PE0,RW Description 53H.7 :TOS[7:2]=0BH 53H.7 :TOS[7:2]=0AH 53H.7 :TOS[7:2]=09H 53H.7 :TOS[7:2]=08H Name TOS7 TOS6 TOS5 TOS4 Default PE0/3,RW PE0/3,RW PE0/2,RW PE0/2,RW Description 53H.7 :TOS[7:2]=07H, otherwise TOS]7:5]=07H 53H.7 :TOS[7:2]=06H, otherwise TOS]7:5]=06H 53H.7 :TOS[7:2]=05H, otherwise TOS]7:5]=05H 53H.7 :TOS[7:2]=04H, otherwise TOS]7:5]=04H Name TOS3 TOS2 TOS1 TOS0 Default PE0/1,RW PE0,/1RW PE0,RW PE0,RW Description 53H.7 :TOS[7:2]=03H, otherwise TOS]7:5]=03H 53H.7 :TOS[7:2]=02H, otherwise TOS]7:5]=02H 53H.7 :TOS[7:2]=01H, otherwise TOS]7:5]=01H 53H.7 :TOS[7:2]=00H, otherwise TOS]7:5]=00H
Description
Preliminary datasheet DM9013-15-DS-P03 April 2009
DM9013
3-port switch with Processor Interface
C3H: C4H: C5H: C6H: C7H: C8H: Name TOS23 TOS22 TOS21 TOS20 Default PE2,RW PE2,RW PE2,RW PE2,RW Description 53H.7 :TOS[7:2]=23H 53H.7 :TOS[7:2]=22H 53H.7 :TOS[7:2]=21H 53H.7 :TOS[7:2]=20H Name TOS1F TOS1E TOS1D TOS1C Default PE1,RW PE1,RW PE1,RW PE1,RW Description 53H.7 :TOS[7:2]=1FH 53H.7 :TOS[7:2]=1EH 53H.7 :TOS[7:2]=1DH 53H.7 :TOS[7:2]=1CH Name TOS1B TOS1A TOS19 TOS18 Default PE1,RW PE1,RW PE1,RW PE1,RW Description 53H.7 :TOS[7:2]=1BH 53H.7 :TOS[7:2]=1AH 53H.7 :TOS[7:2]=19H 53H.7 :TOS[7:2]=18H Name TOS17 TOS16 TOS15 TOS14 Default PE1,RW PE1,RW PE1,RW PE1,RW Description 53H.7 :TOS[7:2]=17H 53H.7 :TOS[7:2]=16H 53H.7 :TOS[7:2]=15H 53H.7 :TOS[7:2]=14H Name TOS13 TOS12 TOS11 TOS10 Default PE1,RW PE1,RW PE1,RW PE1,RW Description 53H.7 :TOS[7:2]=13H 53H.7 :TOS[7:2]=12H 53H.7 :TOS[7:2]=11H 53H.7 :TOS[7:2]=10H Name TOSF TOSE TOSD TOSC Default PE0,RW PE0,RW PE0,RW PE0,RW Description 53H.7 :TOS[7:2]=0FH 53H.7 :TOS[7:2]=0EH 53H.7 :TOS[7:2]=0DH 53H.7 :TOS[7:2]=0CH
Preliminary datasheet DM9013-15-DS-P03 April 2009
DM9013
3-port switch with Processor Interface
C9H: CAH: CBH: CCH: CDH: CEH: Name TOS3B TOS3A TOS39 TOS38 Default PE3,RW PE3,RW PE3,RW PE3,RW Description 53H.7 :TOS[7:2]=3BH 53H.7 :TOS[7:2]=3AH 53H.7 :TOS[7:2]=39H 53H.7 :TOS[7:2]=38H Name TOS37 TOS36 TOS35 TOS34 Default PE3,RW PE3,RW PE3,RW PE3,RW Description 53H.7 :TOS[7:2]=37H 53H.7 :TOS[7:2]=36H 53H.7 :TOS[7:2]=35H 53H.7 :TOS[7:2]=34H Name TOS33 TOS32 TOS31 TOS30 Default PE3,RW PE3,RW PE3,RW PE3,RW Description 53H.7 :TOS[7:2]=33H 53H.7 :TOS[7:2]=32H 53H.7 :TOS[7:2]=31H 53H.7 :TOS[7:2]=30H Name TOS2F TOS2E TOS2D TOS2C Default PE2,RW PE2,RW PE2,RW PE2,RW Description 53H.7 :TOS[7:2]=2FH 53H.7 :TOS[7:2]=2EH 53H.7 :TOS[7:2]=2DH 53H.7 :TOS[7:2]=2CH Name TOS2B TOS2A TOS29 TOS28 Default PE2,RW PE2,RW PE2,RW PE2,RW Description 53H.7 :TOS[7:2]=2BH 53H.7 :TOS[7:2]=2AH 53H.7 :TOS[7:2]=29H 53H.7 :TOS[7:2]=28H Name TOS27 TOS26 TOS25 TOS24 Default PE2,RW PE2,RW PE2,RW PE2,RW Description 53H.7 :TOS[7:2]=27H 53H.7 :TOS[7:2]=26H 53H.7 :TOS[7:2]=25H 53H.7 :TOS[7:2]=24H
Preliminary datasheet DM9013-15-DS-P03 April 2009
DM9013
3-port switch with Processor Interface
CFH: Name TOS3F TOS3E TOS3D TOS3C Default PE3,RW PE3,RW PE3,RW PE3,RW Description 53H.7 :TOS[7:2]=3FH 53H.7 :TOS[7:2]=3EH 53H.7 :TOS[7:2]=3DH 53H.7 :TOS[7:2]=3CH
6.58 VLAN Priority Registers (D0H~D1H) D0H: D1H: Name TAG7 TAG6 TAG5 TAG4 Default PE3,RW PE3,RW PE2,RW PE2,RW Description VLAN priority value VLAN priority value VLAN priority value VLAN priority value Name TAG3 TAG2 TAG1 TAG0 Default PE1,RW PE1,RW PE0,RW PE0,RW Description VLAN priority value VLAN priority value VLAN priority value VLAN priority value
6.59 Memory Data Pre-Fetch Read Command without Address Increment Register (F0H) Name Default Description MRCMDX X,RO Read data from SRAM. After read this command, read pointer internal SRAM unchanged. DM9013 starts pre-fetch SRAM data internal data buffers. 6.60 Memory Data Read Command with Address Increment Register (F2H) When register "0", register value will returned 0000H, 16K-byte boundary reached. When register "1", register value will returned 0000H, processor port receive memory byte boundary address memory size, defined register with default 1F00H, reached. Name MRCMD Default X,RO Description Read data from SRAM. After read this command, read pointer increased 1,2, depends operator mode (8-bit,16-bit 32-bit respectively)
6.61 Memory Data Read address Register (F4H) When register "0", register used memory byte address read internal 64K-byte memory. When register "1", register used processor port receive memory byte address with memory space range from memory size defined register with default 1EFFH.
Name MDRAL
Default PHS0,RW
Description Memory Data Read_ address Byte
Preliminary datasheet DM9013-15-DS-P03 April 2009
DM9013
3-port switch with Processor Interface
6.62 Memory Data Read address Register (F5H) Name Default Description RESERVED P0,RO Reserved MDRAH65 PHS0,RW Port number MDRAH40 PHS0,RW Memory Data Read_ address [11:8] 6.63 Memory Data Write Command without Address Increment Register (F6H) Name Default Description MWCMDX X,WO Write data SRAM. After write this command, write pointer unchanged 6.64 Memory Data Write Command with Address Increment Register (F8H) Name Default Description MWCMD X,WO Write Data SRAM After write this command, write pointer increased depends operator mode. (8-bit, 16-bit,32-bit respectively) 6.65 Memory Data Write address Register (FAH) Name Default Description MDRAL PHS0,RW Memory Data Write_ address Byte 6.66 Memory Data Write address Register (FBH) Name Default Description RESERVED P0,RO Reserved MDRAH65 PHS0,RW Port number MDRAH40 PHS0,RW Memory Data Write_ address [11:8] 6.67 Packet Length Register (FCH~FDH) Name Default TXPLH PHS0,RW Packet Length High byte TXPLL PHS0,RW Packet Length byte 6.68 Interrupt Status Register (FEH) Name Default IOMODE
Description
Description 16-bit mode 32-bit mode 8-bit mode Reserved Link Status Change port Table Counter error Receive Overflow Counter Overflow Receive Overflow Packet Transmitted Packet Received
LNKCHG CNT_ERR
PHS0,RW/C1 PHS0,RW/C1 PHS0,RW/C1 PHS0,RW/C1 PHS0,RW/C1 PHS0,RW/C1
Preliminary datasheet DM9013-15-DS-P03 April 2009
DM9013
3-port switch with Processor Interface
6.69 Interrupt Mask Register (FFH) Name Default TXRX_EN PHS0,RW RESERVED 0,RO LNKCHGI PHS0,RW CNT_ERR PHS0,RW/C1 ROOI PHS0,RW PHS0,RW PHS0,RW PHS0,RW Description Enable SRAM read/write pointer used transmit /receive address. Reserved Enable Link Status Change port 1Interrupt Enable Table Counter error interrupt Enable Receive Overflow Counter Overflow Interrupt Enable Receive Overflow Interrupt Enable Packet Transmitted Interrupt Enable Packet Received Interrupt
Preliminary datasheet DM9013-15-DS-P03 April 2009
DM9013
3-port switch with Processor Interface EEPROM Format
name address Auto Load Control Word Description Byte Ethernet Address 1:0=01: Update vendor product 3:2=01: Accept setting WORD6 [4:0] 5:4= reserved 7:6=01: Accept setting WORD7 [3:0] 9:8=Reserved 11:10= Reserved, application 13:12= Reserved 15:14=01: Accept setting WORD7 [15:14] byte vendor (Default: 0A46H) byte product (Default: 9013H) When word [3:2] =01, these bits control CS#, IOR#, IOW# pins polarity. Bit0: active high when (default active low) Bit1: IOR# active high when (default: active low) Bit2: IOW# active high when (default: active low) Bit3: active when (default: active high) Bit4: open-collected (default: force output) 15:5: Reserved Bit0: active when (default: active high) Bit1: pulse mode when (default: level mode) Bit2: Reserved Bit3: Reserved 13:12 reserved, application Bit14: Port AUTO-MDIX control OFF(default Bit15: Port AUTO-MDIX control OFF(default Reserved 1:0=01: Accept setting WORD 17,18 3:2=01: Accept setting WORD 19~26 5:4=01: Accept setting WORD 27~30 7:6=01: Accept setting WORD 9:8=01: Accept setting WORD 32~39 11:10=01: Accept setting WORD 40~47 15:12 Reserved, 0000 application When word "01", after power reset: This word will loaded Reg. This word 15~8 will loaded Reg. This word must cleared 0000, word [1:0]=01 When word "01", after power reset: This word will loaded port Reg. This word 15~8 will loaded port Reg. When word "01", after power reset: This word will loaded port Reg. This word 15~8 will loaded port Reg. When word "01", after power reset: This word will loaded port Reg.
Vendor Product control
control
RESERVED Control
8~15
Switch Control
RESERVED Port Control
Port Control
Port Control
Preliminary datasheet DM9013-15-DS-P03 April 2009
DM9013
3-port switch with Processor Interface
Port Control This word 15~8 will loaded port Reg. When word "01", after power reset: This word will loaded port Reg. This word 15~8 will loaded port Reg. When word "01", after power reset: This word will loaded port Reg. This word 15~8 will loaded port Reg. When word "01", after power reset: This word will loaded port Reg. This word 15~8 will loaded port Reg. When word "01", after power reset: This word will loaded port Reg. This word 15~8 will loaded port Reg. When word "01", after power reset: This word will loaded port Reg. This word 15~8 will loaded port Reg. When word "01", after power reset: This word will loaded port Reg. This word 15~8 will loaded port Reg. When word "01", after power reset: This word will loaded port Reg. This word 15~8 will loaded port Reg. When word "01", after power reset: This word will loaded port Reg. This word 15~8 will loaded port Reg. When word "01", after power reset: This word will loaded port Reg. This word 15~8 will loaded port Reg. When word "01", after power reset: This word will loaded Reg. This word 15~8 will loaded Reg. When word "01", after power reset: This word will loaded Reg. This word 15~8 will loaded Reg. When word "01", after power reset: This word will loaded Reg. This word 15~8 will loaded Reg. When word "01", after power reset: This word will loaded Reg. This word 15~8 will loaded Reg. When word "01", after power reset: This word will loaded Reg. This word 15~8 will loaded Reg. When word "01", after power reset: This word will loaded Reg. This word 15~8 will loaded Reg. When word "01", after power reset: This word will loaded Reg. This word 15~8 will loaded Reg. When word "01", after power reset:
Preliminary datasheet DM9013-15-DS-P03 April 2009
Port Control
Port Control
Port Control
Port Control
Port VLAN
Port VLAN
Port VLAN
Port VLAN
VLAN Priority
Port VLAN Group Port VLAN Group Port VLAN Group Port VLAN Group Port VLAN Group Port VLAN Group 10,11 Port VLAN Group
DM9013
3-port switch with Processor Interface
12,13 Port VLAN Group 14,15 Priority This word will loaded Reg. This word 15~8 will loaded Reg. When word "01", after power reset: This word will loaded Reg. This word 15~8 will loaded Reg. When word 11:10 "01", after power reset: This word will loaded Reg. This word 15~8 will loaded Reg. When word 11:10 "01", after power reset: This word will loaded Reg. This word 15~8 will loaded Reg. When word 11:10 "01", after power reset: This word will loaded Reg. This word 15~8 will loaded Reg. When word 11:10 "01", after power reset: This word will loaded Reg. This word 15~8 will loaded Reg. When word 11:10 "01", after power reset: This word will loaded Reg. This word 15~8 will loaded Reg. When word 11:10 "01", after power reset: This word will loaded Reg. This word 15~8 will loaded Reg. When word 11:10 "01", after power reset: This word will loaded Reg. This word 15~8 will loaded Reg. When word 11:10 "01", after power reset: This word will loaded Reg. This word 15~8 will loaded Reg.
Priority
Priority
Priority
Priority
Priority
Priority
Priority
Preliminary datasheet DM9013-15-DS-P03 April 2009
DM9013
3-port switch with Processor Interface Registers Register Description
Name CONTR Reset STATUS Cap. PHYID1 PHYID2 Auto-Neg. Next Advertise Page Link Part. Ability Next Page Auto-Neg. Expansio Specifie 4B5B Config. Specifie Conf/Stat Rsvd Conf/Stat PWDOR Loop back Cap. Speed Auto-N Power select Enable Down Cap. Cap. Cap. Remote Fault Reserved Reserved Isolate Restart Full Auto-N Duplex Reserved Coll. Test Reserved
Reserved
Pream. Auto-N Supr. Compl. 0000 Model 01011
Remote Fault
000_0000 Auto-N Link Jabber Cap. Status Detect Version 0000 Advertised Protocol Selector Field Link Partner Protocol Selector Field
Extd Cap.
Pardet Fault
Next Able
Next Able Pream. Supr.
AutoN Cap. Sleep mode Remote LoopOut
Enable
BP_ADP Reserve ALIGN Enable
Reserve Reserve Force Reserve Reserve RPDCTR Reset 100LNK ADDR [4:0] Reserved PD10DR PD100l PDchip PDcrm PDaeq PDdrv
Reserve Reverse Reverse SQUE Enable Reserved Enable Reserve
Auto-N. Monitor [3:0] Polarity Reverse PDecli PDeclo PD10
Specifie TSTSE TSTSE FORCE FORCE PREA TX10M NWAY Reserv MDIX_ AutoNe Mdix_fix Mdix_d MonSel MonSel Reserv PD_val config _TXSD _FEF MBLEX _PWR _PWR CNTL g_dlpbk Value
RCVER DIS_conn Reversed Receiver Error Counter Disconnect_counter
PSCR
Reversed
PREA AMPLIT TX_P MBLE
Reversed
Default register description that follows, default column takes form: <Reset Value>, <Access Type> <Attribute(s)> Where: <Reset Value>: logic logic zero default value <Access Type>: Read only, Read/Write <Attribute (s)>: Self clearing, Value permanently
Preliminary datasheet DM9013-15-DS-P03 April 2009
DM9013
3-port switch with Processor Interface
Basic Mode Control Register (BMCR) Name Reset Default Description RW/SC Reset 0=Normal operation 1=Software reset This sets status controls registers their default states. This bit, which self-clearing, will keep returning value until reset process completed Loopback Loop-back control register Normal operation Loop-back enabled When 100Mbps operation mode, setting this cause descrambler lose synchronization produce 720ms "dead time" before valid data appears receive outputs Speed Select 10Mbps 100Mbps Link speed selected either this auto-negotiation. When auto-negotiation enabled set, this will return auto-negotiation selected medium type Auto-negotiation Enable Auto-negotiation disabled Auto-negotiation enabled, will auto-negotiation status Power Down While power-down state, should respond management transactions. During transition power-down state while power-down state, should generate spurious signals 0=Normal operation 1=Power down 0,RW Isolate Force application. 0,RW/SC Restart Auto-negotiation Normal operation Restart auto-negotiation. Re-initiates auto-negotiation process. When auto-negotiation disabled (bit this register cleared), this function should cleared. This self-clearing will keep returning value until auto-negotiation initiated DM9013. operation auto-negotiation process will affected management entity that clears this 1,RW Duplex Mode Normal operation Full duplex operation. Duplex selection allowed when Auto-negotiation disabled (bit this register cleared). With auto-negotiation enabled, this reflects duplex capability
Loopback
Speed selection
Auto-negotiation enable
Power down
Isolate Restart Auto-negotiation
Duplex mode
Preliminary datasheet DM9013-15-DS-P03 April 2009
DM9013
3-port switch with Processor Interface
selected auto-negotiation
Collision test
0,RW
Reserved
0,RO
Collision Test Normal operation Collision test enabled. When set, this will cause signal asserted response assertion TX_EN internal interface. Reserved Read ignore write
Basic Mode Status Register (BMSR) Name 100BASE-T4 Default 0,RO/P Description 100BASE-T4 Capable able perform 100BASE-T4 mode able perform 100BASE-T4 mode 100BASE-TX Full Duplex Capable able perform 100BASE-TX full duplex mode able perform 100BASE-TX full duplex mode 100BASE-TX Half Duplex Capable able perform 100BASE-TX half duplex mode able perform 100BASE-TX half duplex mode 10BASE-T Full Duplex Capable able perform 10BASE-TX full duplex mode able perform 10BASE-T full duplex mode 10BASE-T Half Duplex Capable able perform 10BASE-T half duplex mode able perform 10BASE-T half duplex mode Reserved Read ignore write Frame Preamble Suppression accept management frames with preamble suppressed accept management frames with preamble suppressed Auto-negotiation Complete Auto-negotiation process completed Auto-negotiation process completed Remote Fault remote fault condition detected Remote fault condition detected (cleared read chip reset). Fault criteria detection method DM9013 implementation specific. This will after ANLPAR (bit register address Auto Configuration Ability able perform auto-negotiation able perform auto-negotiation Link Status Link established
Preliminary datasheet DM9013-15-DS-P03 April 2009
100BASE-TX full-duplex 100BASE-TX half-duplex 10BASE-T full-duplex 10BASE-T half-duplex Reserved preamble suppression Auto-negotiation Complete Remote fault
1,RO/P
1,RO/P
1,RO/P
1,RO/P
10-7
0,RO 1,RO
0,RO
Auto-negotiation ability Link status
1,RO/P
0,RO
DM9013
3-port switch with Processor Interface
Valid link established (for either 10Mbps 100Mbps operation) link status implemented with latching function, that occurrence link failure condition causes link status cleared remain cleared until read management interface Jabber Detect jabber Jabber condition detected This implemented with latching function. Jabber conditions will this unless cleared read this register through management interface DM9013 reset. This works only 10Mbps mode Extended Capability Basic register capable only Extended register capable
Jabber detect
Extended capability
1,RO/P
Identifier Register (PHYID1) Identifier Registers work together single identifier DM9013. Identifier consists concatenation Organizationally Unique Identifier (OUI), vendor's model number, model revision number. DAVICOM Semiconductor's IEEE assigned 00606E. 15-0 Name OUI_MSB Default <0181h> Description Most Significant Bits This register stores (00606E) this register respectively. most significant bits ignored (the IEEE standard refers these
Identifier Register (PHYID2) 15-10 Name OUI_LSB Default <101110>, RO/P <001011>, RO/P <0000>, RO/P Description Least Significant Bits (00606E) mapped this register respectively Vendor Model Number Five bits vendor model number mapped (most significant Model Revision Number Five bits vendor model revision number mapped (most significant
VNDR_MDL
MDL_REV
Preliminary datasheet DM9013-15-DS-P03 April 2009
DM9013
3-port switch with Processor Interface
Auto-negotiation Advertisement Register (ANAR) This register contains advertised abilities this DM9013 device they will transmitted link partner during Auto-negotiation. Name Description Next page Indication next page available Next page available DM9013 next page, this permanently 0,RO Acknowledge acknowledged Link partner ability data reception acknowledged DM9013's auto-negotiation state machine will automatically control this outgoing bursts appropriate time during auto-negotiation process. Software should attempt write this bit. Remote Fault fault detected Local device senses fault condition Reserved Write ignore read Flow Control Support Controller chip doesn't support flow control ability Controller chip supports flow control ability RO/P 100BASE-T4 Support 100BASE-T4 supported 100BASE-T4 supported local device DM9013 does support 100BASE-T4 this permanently 100BASE-TX Full Duplex Support 100BASE-TX full duplex supported 100BASE-TX full duplex supported local device 100BASE-TX Support 100BASE-TX half duplex supported 100BASE-TX half duplex supported local device 10BASE-T Full Duplex Support 10BASE-T full duplex supported 10BASE-T full duplex supported local device 10BASE-T Support 10BASE-T half duplex supported 10BASE-T half duplex supported local device <00001>, Protocol Selection Bits These bits contain binary encoded protocol selector supported this node <00001> indicates that this device supports IEEE 802.3 CSMA/CD Default 0,RO/P
12-11
Reserved
TX_FDX
TX_HDX
10_FDX
10_HDX
Selector
Preliminary datasheet DM9013-15-DS-P03 April 2009
DM9013
3-port switch with Processor Interface
Auto-negotiation Link Partner Ability Register (ANLPAR) This register contains advertised abilities link partner when received during Auto-negotiation. Name Description Next Page Indication Link partner, next page available Link partner, next page available Acknowledge acknowledged Link partner ability data reception acknowledged DM9013's auto-negotiation state machine will automatically control this from incoming bursts. Software should attempt write this Remote Fault remote fault indicated link partner Remote fault indicated link partner Reserved Read ignore write Flow Control Support Controller chip doesn't support flow control ability link partner Controller chip supports flow control ability link partner 100BASE-T4 Support 100BASE-T4 supported link partner 100BASE-T4 supported link partner 100BASE-TX Full Duplex Support 100BASE-TX full duplex supported link partner 100BASE-TX full duplex supported link partner 100BASE-TX Support 100BASE-TX half duplex supported link partner 100BASE-TX half duplex supported link partner 10BASE-T Full Duplex Support 10BASE-T full duplex supported link partner 10BASE-T full duplex supported link partner 10BASE-T Support 10BASE-T half duplex supported link partner 10BASE-T half duplex supported link partner <00000>, Protocol Selection Bits Link partner's binary encoded protocol selector Default
12-11
Reserved
TX_FDX
TX_HDX
10_FDX
10_HDX
Selector
Preliminary datasheet DM9013-15-DS-P03 April 2009
DM9013
3-port switch with Processor Interface
Auto-negotiation Expansion Register (ANER) 15-5 Name Reserved Default RO/LH Description Reserved Read ignore write Local Device Parallel Detection Fault fault detected parallel detection function. fault detected parallel detection function Link Partner Next Page Able LP_NP_ABLE Link partner, next page available LP_NP_ABLE Link partner, next page Local Device Next Page Able NP_ABLE DM9013, next page available NP_ABLE DM9013, next page DM9013 does support this function, this always Page Received link code word page received. This will automatically cleared when register (register read management Link Partner Auto-negotiation Able this indicates that link partner supports Auto-negotiation
LP_NP_ABLE
NP_ABLE
0,RO/P
PAGE_RX
LP_AN_ABLE
DAVICOM Specified Configuration Register (DSCR) Name Default Description BP_4B5B 0,RW Bypass 4B5B Encoding 5B4B Decoding Normal 4B5B 5B4B operation 4B5B encoder 5B4B decoder function bypassed BP_SCR Bypass Scrambler/Descrambler Function Normal scrambler descrambler operation Scrambler descrambler function bypassed BP_ALIGN Bypass Symbol Alignment Function Normal operation Receive functions (descrambler, symbol alignment symbol decoding functions) bypassed. Transmit functions (symbol encoder scrambler) bypassed BP_ADPOK BYPASS ADPOK Force signal detector (SD) active. This register debug only, release customer 0=Normal operation 1=Forced Reserved Reserved Force application 100BASE-TX Mode Control 100BASE-FX operation 100BASE-TX operation Reserved Reserved Reserved Reserved F_LINK_100 Force Good Link 100Mbps Normal 100Mbps operation
Preliminary datasheet DM9013-15-DS-P03 April 2009
DM9013
3-port switch with Processor Interface
Reserved COL_LED RPDCTR-EN Force 100Mbps good link status This useful diagnostic purposes Reserved Force application. Control (valid test mode) Reduced Power Down Control Enable This used enable automatic reduced power down Disable automatic reduced power down Enable automatic reduced power down Reset State Machine When writes this bit, state machines will reset. This self-clear after reset completed Preamble Suppression Control frame preamble suppression control preamble suppression preamble suppression Sleep Mode Writing this will cause entering Sleep mode power down circuit except oscillator clock generator circuit. When waking from Sleep mode (write this configuration will back state before sleep; state machine will reset Remote Loop Control When this received data will loop transmit channel. This useful error rate testing
SMRST
MFPSC
SLEEP
RLOUT
Preliminary datasheet DM9013-15-DS-P03 April 2009
DM9013
3-port switch with Processor Interface
DAVICOM Specified Configuration Status Register (DSCSR) Name 100FDX Default Description 100M Full Duplex Operation Mode After auto-negotiation completed, results will written this bit. this means operation mode 100M full duplex mode. software read [15:12] which mode selected after auto-negotiation. This invalid when auto-negotiation mode 100M Half Duplex Operation Mode After auto-negotiation completed, results will written this bit. this means operation mode 100M half duplex mode. software read [15:12] which mode selected after auto-negotiation. This invalid when auto-negotiation mode Full Duplex Operation Mode After auto-negotiation completed, results will written this bit. this means operation mode Full Duplex mode. software read [15:12] which mode selected after auto-negotiation. This invalid when auto-negotiation mode Half Duplex Operation Mode After auto-negotiation completed, results will written this bit. this means operation mode half duplex mode. software read [15:12] which mode selected after auto-negotiation. This invalid when auto-negotiation mode Reserved Read ignore write Reserved Address first address transmitted received address (bit station management entity connected multiple entities must know appropriate address each Auto-negotiation Monitor Bits These bits debug only. auto-negotiation status will written these bits. IDLE state Ability match Acknowledge match Acknowledge match fail Consistency match Consistency match fail Parallel detects signal link ready Parallel detects signal link ready fail Auto-negotiation completed successfully
100HDX
10FDX
10HDX
10-9
Reserved Reserved PHYADR[4
0,RW
ANMB[3:0]
Preliminary datasheet DM9013-15-DS-P03 April 2009
DM9013
3-port switch with Processor Interface
8.10 10BASE-T Configuration/Status (10BTCSR) Name Reserved LP_EN Default Description Reserved Read ignore write Link Pulse Enable Link pulses disabled, good link condition forced Transmission link pulses enabled This valid only 10Mbps operation Heartbeat Enable Heartbeat function disabled Heartbeat function enabled When DM9013 configured full duplex operation, this will ignored (the collision/heartbeat function invalid full duplex mode) Squelch Enable squelch Normal squelch Jabber Enable Enables disables Jabber function when DM9013 10BASE-T full duplex 10BASE-T transceiver Loopback mode Jabber function disabled Jabber function enabled Serial Mode (valid test mode) Force application. Reserved Read ignore write Polarity Reversed When this indicates that 10Mbps cable polarity reversed. This automatically cleared 10BASE-T module
1,RW
SQUELCH
JABEN
SERIAL Reserved POLR
8.11 Power Down Control Register (PWDOR) Description Reserved Read ignore write PD10DRV Vendor power down control test PD100DL Vendor power down control test PDchip Vendor power down control test PDcrm Vendor power down control test PDaeq Vendor power down control test PDdrv Vendor power down control test PDedi Vendor power down control test PDedo Vendor power down control test PD10 Vendor power down control test When selected, power down value control Register 20.0 15-9 Name Reserved Default
Preliminary datasheet DM9013-15-DS-P03 April 2009
DM9013
3-port switch with Processor Interface
8.12 (Specified config) Register Description Vendor test select control Vendor test select control Force Signal Detect normal signal. force signal 100M FORCE_FEF 0,RW Vendor test select control PREAMBLEX 0,RW Preamble Saving Control when set, preamble count reduced. When register set, 12-bit preamble reduced; otherwise 22-bit preamble bits reduced. preamble count normal. TX10M_PWR 1,RW Power Saving Control enable power saving disable power saving NWAY_PWR 0,RW N-Way Power Saving Control disable N-Way power saving enable N-Way power saving Reserved Reserved Read ignore write MDIX_CNTL MDI/MDIX,RO polarity MDI/MDIX value mode MDIX mode AutoNeg_dpbk 0,RW Auto-negotiation Loopback normal. test internal digital auto-negotiation Loopback Mdix_fix Value MDIX_CNTL force value: When Mdix_down MDIX_CNTL value depend register value. Mdix_down 0,RW MDIX Down Manual force MDI/MDIX. Enable Auto-MDIX Disable Auto-MDIX MDIX_CNTL value depend 20.5 MonSel1 0,RW Vendor monitor select MonSel0 0,RW Vendor monitor select Reserved 0,RW Reserved Force application. PD_value 0,RW Power down control value Decision value each field Register normal power down Name TSTSE1 TSTSE2 FORCE_TXSD Default 0,RW 0,RW 0,RW
Preliminary datasheet DM9013-15-DS-P03 April 2009
DM9013
3-port switch with Processor Interface
8.13 DAVICOM Specified Receive Error Counter Register (RECR) 15-0 Name Rcv_ Err_ Default Description Receive Error Counter Receive error counter that increments upon detection RXER. Clean read this register.
8.14 DAVICOM Specified Disconnect Counter Register (DISCR) 15-8 Name Reserved Disconnect Counter Default Description Reserved Disconnect Counter that increment upon detection disconnection. Clean read this register.
8.15 Power Saving Control Register (PSCR) 15-12 Name RESERVED PREAMBLEX Default 0,RO 0,RW Description RESERVED Preamble Saving Control when both 10and register set, preamble count reduced. 12-bit preamble reduced. 22-bit preamble bits reduced. Amplitude Control Disabled when cable unconnected with link partner, amplitude reduced power saving. disable amplitude reduce function Power Saving Control Disabled when cable unconnected with link partner, driving current transmit reduced power saving. disable driving power saving function RESERVED
AMPLITUDE
0,RW
TX_PWR
0.RW
RESERVED
0,RO
Preliminary datasheet DM9013-15-DS-P03 April 2009
DM9013
3-port switch with Processor Interface Functional Description
Processor memory management function: 9.1.1 Processor Interface general processor mode, chip selection just coming from (CS#). There only addressing ports through access host interface. port INDEX port other DATA port. INDEX port decoded pin=0 DATA pin=1. contents INDEX port register address DATA port. Before access register, address register must saved INDEX port before. 9.1.2 Direct Memory Access Control DM9013 provides capability simplify access internal memory. After setting starting address internal memory then issuing dummy read/write command load current data internal data buffer, desired location internal memory accessed read/write command registers. memory's address will increased with size equal current operation mode (i.e. byte, word double-word mode) data next location will loaded internal data buffer automatically. noted that data first access (the dummy read/write command) sequential burst should ignored because that data contents last read/write command. There configured types internal memory which controlled IMR. When set, internal memory used transmit receive buffers. transmit buffer occupies 7.5K bytes 3-port mode bytes 2-port mode. receive buffer occupies 7.5K bytes 3-port mode 7.75K bytes 2-port mode. Both transmit receive buffer address need programmed instead that they managed DM9013 automatically. transmit function, after power reset each time after transmit command issued (bit set), next starting transmit buffer address loaded. receive function, 7.5K-byte 7.75K-byte) receive buffer treated continued logic memory space. memory address will wrap address address reached. When cleared, there 64Kbyte memory space DM9013 accessed. This configured type internal memory used testing only. memory write address (register FAh/FBh) memory read address (register F4h/F5h) represent physical memory address DM9013 internal memory. noted that after memory been written memory write command, switch reset command (bit register 52h) should before normal switch function operation, since controlled data internal memory corrupted.
9.1.3 Packet Transmission There packets, sequentially named index index stored SRAM same time. index register controls insertion CRC. start address transmission current packet index after software hardware reset. Firstly write data SRAM using port then write byte count byte count register index register 0fch 0fdh. control register. DM9013 starts transmit index packet. Before transmission index packet ends, data next (index packet moved SRAM. After index packet ends transmission, write byte count data index BYTE_COUNT register then control register transmit index packet. following packets, named index same transmitted. 9.1.4 Packet Reception SRAM ring data structure. Each packet 4-byte header followed with data reception packet which field included. format 4-byte header 01h, status, BYTE_COUNT low, BYTE_COUNT high. noted that start address each packet proper address boundary which depends operation mode (byte, word, double-word mode).
Preliminary datasheet DM9013-15-DS-P03 April 2009
DM9013
3-port switch with Processor Interface
Switch function: 9.2.1 Address Learning DM9013 self-learning mechanism learning addresses incoming packets real time. DM9013 stores addresses, port number time stamp information Hash-based Address Table. learn unicast address entry. switch engine updates address table with entry incoming packet's Source Address (SA) does exist incoming packet valid (non-error legal length). Besides, DM9013 option disable address learning individual port. This feature register 9.2.2 Address Aging time stamp information address table used aging process. switch engine updates time stamp whenever corresponding receives. switch engine would delete entry time stamp updated period time. period programmed disabled through register 52h. 9.2.3 Packet Forwarding DM9013 forwards incoming packet according following decision: (1). Multicast/Broadcast, packet forwarded ports, except port which packet received. (2). Switch engine would look address table based when incoming packets UNICAST. found address table, packet treated multicast packet forward other ports. found destination port number different source port number, packet forward destination port. (3). Switch engine also look VLAN, Port Monitor setting other forwarding constraints forwarding decision, more detail will discuss later sections. DM9013 will filter incoming packets under following conditions: (1). Error packets, including errors, alignment errors, illegal size errors.
Preliminary datasheet DM9013-15-DS-P03 April 2009
(2). PAUSE packets. (3). incoming packet UNICAST destination port number equal source port number. 9.2.4 Inter-Packet (IPG) idle time between valid packets same port. typical number bits time. other word, value 9.6u 10Mbps 960n 100Mbps. 9.2.5 Back-off Algorithm DM9013 implements binary exponential back-off algorithm half-duplex mode compliant IEEE standard 802.3. 9.2.6 Late Collision Late Collision type collision. collision error occurs after first times data transmitted, packet dropped. 9.2.7 Full Duplex Flow Control DM9013 supports IEEE standard 802.3x flow control frames both transmit receive sides. receive side, DM9013 will defer transmitting next normal frames, receives pause frame from link partner. transmit side, DM9013 issues pause frame with maximum pause time when internal resources such received buffers, transmit queue transmit descriptor ring unavailable. Once resources available, DM9013 sends pause frame with zero pause time allows traffic resume immediately. 9.2.8 Half Duplex Flow Control DM9013 supports half-duplex backpressure. inducement same full duplex mode. When flow control required, DM9013 sends pattern, thus forcing collision. flow control ability register 61h. 9.2.9 Partition Mode DM9013 provides partition mode each
DM9013
3-port switch with Processor Interface
port, register 61h. port enters partition mode when more than consecutive collisions occurred. partition mode port continuous transmit will receive. port returned normal operation mode when good packet seen wire. detail description partition mode represent following: (1). Entering Partition State port will enter Partition State when either following conditions occurs: port detects collision every consecutive re-transmit attempts same packet. port detects single collision which occurs more than times. Transmit defer timer time out, which indicates transmitting packet deferred long. (2). While Partition state: port will continue transmit pending packet, regardless collision detection, will allow usual Back-off Algorithm. Additional packets pending transmission will transmitted, while ignoring internal collision indication. This frees ports transmit buffers which would otherwise filled expense other ports buffers. assumption that partition signifying system failure situation (bad connection/cable/station), thus dropping packets small price cost halting switch buffer full condition. (3). Exiting from Partition State Port exits from Partition State, following successful packet transmission. successful packet transmission defined collisions were detected first bits transmission. 9.2.10 Broadcast Storm Filtering DM9013 option limit traffic broadcast multicast packets, protect switch from lower bandwidth availability. There type broadcast storm control, throttling broadcast packet only, other includes multicast. This feature through register 61h. broadcast storm threshold programmed EEPROM register 67h, default setting broadcast storm protecting.
9.2.11 Bandwidth Control DM9013 supports type bandwidth control each port. ingress egress bandwidth rate control separately, other combined together, this function through register 61h. bandwidth control disabled default. separated bandwidth control mode, threshold rate defined register 66h. combined mode, defined register 67h. behavior bandwidth control below: (1).For ingress control, flow control function enabled, Pause packet will transmitted. ingress packets will dropped flow control disabled. (2).For egress control, egress port will transmit packets. other hand, ingress bandwidth source port will throttled that prevent packets from forwarding. (3).In combined mode, ingress egress bandwidth over threshold, bandwidth will throttled. 9.2.12 Port Monitoring Support DM9013 supports "Port Monitoring" function port base, detail below: (1). Sniffer Port Monitor Port There only port selected "sniffer port" register 52h, multiple ports "receive monitor port" "transmit monitor port" per-port register 65h. (2).Receive monitor packets received "receive monitor port" send copy "sniffer port". example, port "receive monitor port" port selected "sniffer port". packet received form port predestined port after forwarding decision, DM9013 will forward port port end. (3).Transmit monitor packets transmitted "transmit monitor port" send copy "sniffer port". example, port "transmit monitor port" port selected "sniffer port". packet received from port predestined port after forwarding decision, DM9013 will forward port port end.
Preliminary datasheet DM9013-15-DS-P03 April 2009
DM9013
3-port switch with Processor Interface
(4).Exception DM9013 optional setting that broadcast/multicast packets monitored (see register 65h). It's useful avoid unnecessary bandwidth. (1). PVID Port 0x01h. (2). PVID Port 0x02h. (3). PVID Port 0x03h. (4). PVID Port 0x04h. (5). register 0x02h. (6). register 0x05h. (7). register 0x0Ah. (8). register 0x04h. 9.2.13.2 802.1Q-Based VLAN Regarding IEEE 802.1Q standard, Tag-based VLAN uses extra identify VLAN membership frame across VLAN-aware switch/router. tagged frame four bytes longer than untagged frame contains bytes TPID (Tag Protocol Identifier) bytes (Tag Control Information).
9.2.13 VLAN Support 9.2.13.1 Port-Based VLAN DM9013 supports port-based VLAN default, groups. Each port default called PVID (Port VID, register 6Fh). DM9013 used 4-bytes PVID index mapped register B0h~BFh, define VLAN groups. instance, intend partition DM9013's ports into three groups. Port port group port port group finally, port port group this case, setting below:
Dest.
Src.
Length/Type
Data
Standard frame
Dest.
Src.
TPID
0x8100 bytes
Length Type
Data
Tagged frame
Priority
bits
DM9013 also supports 802.1Q-based VLAN groups, specified register 53h. It's obvious that tagged packets assigned several different VLANs which determined according inside VLAN Tag. Therefore, operation similar port-based VLAN. DM9013 used 4-bytes received packet with VLAN VLAN Group Mapping Register (B0h~BFh) configure VLAN partition. destination port received packet same VLAN group with received port, will discarded.
bits
VLAN_9013.vsd
bits
9.2.13.3 Tag/Untag User define each port port Un-tag port register 802.1Q-based VLAN mode. operation Un-tag explain below conditions: (1). Receive untagged packet forward Un-tag port. Received packet will forward destination port without modification. (2). Receive tagged packet forward Un-tag port. DM9013 will remove from packet recalculate before sending out.
Preliminary datasheet DM9013-15-DS-P03 April 2009
DM9013
3-port switch with Processor Interface
(3). Receive untagged packet forward port. DM9013 will insert PVID when untagged packet enters port, recalculate before delivering (4). Receive tagged packet forward port. Received packet will forward destination port without modification. 9.2.14 Priority Support DM9013 supports Quality Service (QoS) mechanism multimedia communication such VoIP video conferencing. DM9013 provides three priority classifications: Port-based, 802.1p-based DiffServ-based priority. next section more detail. DM9013 offers four level queues transmit per-port based. DM9013 provides packet scheduling algorithms: Strict Priority Queuing. based their priority queue weight. Queues with larger weights more service than smaller. This mechanism highly efficient bandwidth smooth traffic. Strict Priority Queuing (SPQ) based priority only. Packet highest priority queue transmitted first. next highest-priority queue work until last queue empties, This feature register 6Dh. 9.2.14.1 Port-Based Priority Port based priority simplest scheme default. Each port 2-bit priority value index splitting ingress packets corresponding transmit queue. This value register 6Dh. 9.2.14.2 802.1p-Based Priority 802.1p priority disabled register 6Dh, enabled default. DM9013 extracts 3-bit priority field from received packet with 802.1p VLAN tag, maps this field against VLAN Priority Registers (D0h~D1h) determine which transmit queue designated. VLAN Priority programmable. 9.2.14.3 DiffServ-Based Priority DiffServ based priority uses most significant 6-bit field standard IPv4 header, maps this field against Priority Registers (C0h~CFh) determine which transmit queue designated. Priority programmable too. addition, User only refer most significant 3-bit field optionally, register 53h.
Preliminary datasheet DM9013-15-DS-P03 April 2009
DM9013
3-port switch with Processor Interface
Interface 9.3.1 data interface DM9013 port provides Media Independent Interface (MII) defined IEEE 802.3u standard (Clause 22). consists nibble wide receive data bus, nibble wide transmit data bus, control signals facilitate data transfers between DM9013 port external device reverse MII). TXD2 (transmit data) nibble bits) data that driven DM9013 synchronously with respect TXC2. each TXC2 period, which TXE2 asserted, TXD2 (3:0) accepted transmission external device. TXC2 (transmit clock) from external device continuous clock that provides timing reference transfer TXE2, TXD2. DM9013 drive 25MHz clock configured reversed mode. TXE2 (transmit enable) from DM9013 port indicates that nibbles being presented transmission external device. RXD2 (receive data) nibble bits) data that sampled DM9013 port synchronously with respect RXC2. each RXC2 period which RXDV2 asserted, RXD2 (3:0) transferred from external device DM9013 port reconciliation layer. RXC2 (receive clock) from external device DM9013 port reconciliation layer continuous clock that provides timing reference transfer RXDV2, RXD2, RXER2 signals. RXDV2 (receive data valid) input from external device indicates that external device presenting recovered decoded nibbles DM9013 port reconciliation layer. interpret receive frame correctly reconciliation layer, RXDV2 must encompass frame, starting later than Start-of-Frame delimiter excluding End-Stream delimiter. RXER2 (receive error) input from external device synchronously with respect RXC2. RXER2 will asserted more clock periods indicate reconciliation layer that error detected somewhere frame being
Preliminary datasheet DM9013-15-DS-P03 April 2009
transmitted from external device DM9013 port MAC. CRS2 (carrier sense) asserted external device when either transmit receive medium non-idle, de-asserted external device when transmit receive medium idle. CRS2 also output mode when DM9013 port configured reversed mode. COL2 (collision detection) asserted external device, when both transmit receive medium non-idle, de-asserted external device when either transmit receive medium idle. COL2 also output mode when DM9013 port configured reversed mode. 9.3.2 Serial Management serial management interface consists data interface, basic register DM9013 port serial management interface register set. Through this interface possible control configure multiple devices, include internal ports, status error information, determine type capabilities attached device(s). DM9013 default polling ports basic registers link, duplex, speed status automatically. Alternatively, DM9013 programmed read write registers ports section 6.8~11 DM9013 management functions correspond specification IEEE 802.3u-1995 (Clause registers through with vendor-specific registers 16,17, 24~27. read/write operation, management data frame 64-bits long starts with contiguous logic bits (preamble) synchronization clock cycles MDC. Start Frame Delimiter (SFD) indicated <01> pattern followed operation code (OP) indicates Read operation <01> indicates Write operation. read operation, 2-bit turnaround (TA) filing between Register Address field Data field provided MDIO avoid contention. Following turnaround time, 16-bit data read from written onto management registers.
DM9013
3-port switch with Processor Interface
9.3.3 Serial Management Interface serial control interface uses simple two-wired serial interface obtain control status physical layer through interface. serial control interface consists (Management Data Clock), MDI/O (Management Data Input/Output) signals. MDIO bi-directional shared devices.
9.3.4 Management Interface Read Frame Structure
MDIO Read "1"s Idle Preamble Address Write Data Read Idle
Code
Register Address
Turn Around
9.3.5 Management Interface Write Frame Structure
MDIO Write "1"s Idle Preamble Address Data Idle
Code
Register Address Write
Turn Around
Preliminary datasheet DM9013-15-DS-P03 April 2009
DM9013
3-port switch with Processor Interface
Internal functions 9.4.1 100Base-TX Operation transmitter section contains following functional blocks: 4B5B Encoder Scrambler Parallel Serial Converter NRZI Converter NRZI MLT-3 MLT-3 Driver 9.4.1.1 4B5B Encoder 4B5B encoder converts 4-bit (4B) nibble data generated Reconciliation Layer into 5-bit (5B) code group transmission, reference Table This conversion required control packet data combined code groups. 4B5B encoder substitutes first bits preamble with code-group pair (11000 10001) upon transmit. 4B5B encoder continues replace subsequent preamble data nibbles with corresponding code-groups. transmit packet, upon deassertion Transmit Enable signal from Reconciliation layer, 4B5B encoder injects code-group pair (01101 00111) indicating frame. After code-group pair, 4B5B encoder continuously injects IDLEs into transmit data stream until Transmit Enable asserted next transmit packet detected. scrambling data, total energy presented cable randomly distributed over wide frequency range. Without scrambler, energy levels cable could peak beyond limitations frequencies related repeated sequences, like continuous transmission IDLE symbols. scrambler output combined with data from code-group encoder logic function. result scrambled data stream with sufficient randomization decrease radiated emissions critical frequencies. 9.4.1.3 Parallel Serial Converter Parallel Serial Converter receives parallel scrambled data from scrambler, serializes (converts from parallel serial data stream). serialized data stream then presented NRZI encoder block 9.4.1.4 NRZI Encoder After transmit data stream been scrambled serialized, data must NRZI encoded compatibility with TP-PMD standard, 100Base transmission over Category-5 unshielded twisted pair cable. 9.4.1.5 MLT-3 Converter MLT-3 conversion accomplished converting data stream output, from NRZI encoder into binary data streams, with alternately phased logic event. 9.4.1.6 MLT-3 Driver binary data streams created MLT-3 converter twisted pair output driver, which converts these streams current sources alternately drives either side transmit transformer's primary winding, resulting minimal current MLT-3 signal.
9.4.1.2 Scrambler scrambler required control radiated emissions (EMI) spreading transmit energy across frequency spectrum media connector twisted pair cable 100Base-TX operation.
Preliminary datasheet DM9013-15-DS-P03 April 2009
DM9013
3-port switch with Processor Interface
9.4.1.7 4B5B Code Group
Symbol
Meaning Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data Idle Error Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid
code 3210 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 undefined 0101 0101 undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined Table
Code 43210 11110 01001 10100 10101 01010 01011 01110 01111 10010 10011 10110 10111 11010 11011 11100 11101 11111 11000 10001 01101 00111 00100 00000 00001 00010 00011 00101 00110 01000 01100 10000 11001
Preliminary datasheet DM9013-15-DS-P03 April 2009
DM9013
3-port switch with Processor Interface
9.4.2 100Base-TX Receiver 100Base-TX receiver contains several function blocks that convert scrambled 125Mb/s serial data synchronous 4-bit nibble data. receive section contains following functional blocks: Signal Detect Digital Adaptive Equalization MLT-3 Binary Decoder Clock Recovery Module NRZI Decoder Serial Parallel Descrambler Code Group Alignment 4B5B Decoder 9.4.2.1 Signal Detect signal detects function meets specifications mandated ANSI XT12 TP-PMD 100Base-TX standards both voltage thresholds timing parameters. 9.4.2.2 Adaptive Equalization When transmitting data over copper twisted pair cable high speed, attenuation based frequency becomes concern. high speed twisted pair signaling, frequency content transmitted signal vary greatly during normal operation based randomness scrambled data stream. This variation signal attenuation, caused frequency variations, must compensated ensure integrity received data. order ensure quality transmission when employing MLT-3 encoding, compensation must able adapt various cable lengths cable types depending installed environment. selection long cable lengths given implementation requires significant compensation, which will over-killed situation that includes shorter, less attenuating cable lengths. Conversely, selection short intermediate cable lengths requiring less compensation will cause serious under-compensation longer length cables. Therefore, compensation equalization must adaptive ensure proper conditioning received signal independent cable length.
Preliminary datasheet DM9013-15-DS-P03 April 2009
9.4.2.3 MLT-3 NRZI Decoder DM9013 decodes MLT-3 information from Digital Adaptive Equalizer into NRZI data. 9.4.2.4 Clock Recovery Module Clock Recovery Module accepts NRZI data from MLT-3 NRZI decoder. Clock Recovery Module locks onto data stream extracts reference clock. extracted synchronized clock data presented NRZI decoder.
9.4.2.5 NRZI transmit data stream required NRZI encoded compatibility with TP-PMD standard 100Base-TX transmission over Category-5 unshielded twisted pair cable. This conversion process must reversed receive end. NRZI decoder receives NRZI data stream from Clock Recovery Module converts data stream presented Serial Parallel conversion block. 9.4.2.6 Serial Parallel Serial Parallel Converter receives serial data stream from NRZI converter. converts data stream parallel data presented descrambler. 9.4.2.7 Descrambler Because scrambling process requires control radiated emissions transmit data streams, receiver must descramble receive data streams. descrambler receives scrambled parallel data streams from Serial Parallel converter, descrambles data streams, presents data streams Code Group alignment block.
DM9013
3-port switch with Processor Interface
9.4.2.8 Code Group Alignment Code Group Alignment block receives un-aligned data from descrambler converts into code group data. Code Group Alignment occurs after detected subsequent data aligned fixed boundary. 9.4.2.9 4B5B Decoder 4B5B Decoder functions look-up table that translates incoming code groups into (Nibble) data. When receiving frame, first 5-bit code groups receive start-of-frame delimiter (J/K symbols). symbol pair stripped nibbles preamble pattern substituted. last code groups end-of-frame delimiter (T/R Symbols). symbol pair also stripped from nibble, presented Reconciliation layer. 9.4.3 10Base-T Operation 10Base-T transceiver IEEE 802.3u compliant. When DM9013 operating 10Base-T mode, coding scheme Manchester. Data processed transmit presented nibble format, converted serial stream, then Manchester encoded. When receiving, stream, encoded Manchester, decoded converted into nibble format. 9.4.4 Collision Detection half-duplex operation, collision detected when transmit receive channels active simultaneously. Collision detection disabled full duplex operation. 9.4.5 Carrier Sense Carrier Sense (CRS) asserted half-duplex operation during transmission reception data. During full-duplex mode, asserted only during receive operations. 9.4.6 Auto-Negotiation objective Auto-negotiation provide means exchange information between linked devices automatically configure both devices take maximum advantage their abilities. important note that Auto-negotiation does test characteristics linked segment. Auto-Negotiation function provides means device advertise supported modes operation remote link partner, acknowledge receipt understanding common modes operation, reject un-shared modes operation. This allows devices both ends segment establish link best common mode operation. more than common mode exists between devices, mechanism provided allow devices resolve single mode operation using predetermined priority resolution function. Auto-negotiation also provides parallel detection function devices that support Auto-negotiation feature. During Parallel detection there exchange information configuration. Instead, receive signal examined. discovered that signal matches technology, which receiving device supports, connection will automatically established using that technology. This allows devices support Auto-negotiation support common mode operation establish link.
Preliminary datasheet DM9013-15-DS-P03 April 2009
DM9013
3-port switch with Processor Interface Electrical Characteristics
10.1 Absolute Maximum Ratings Symbol Parameter VCC3 3.3V Supply Voltage VCCI 1.8V core power supply AVDD3 Analog power supply 3.3V AVDDI Analog power supply 1.8V Input Voltage (VIN) Storage Temperature range TSTG Ambient Temperature Lead Temperature (TL, soldering, sec.). 10.2 Operating Conditions Symbol Parameter VCC3 3.3V Supply Voltage VCCI 1.8V core power supply AVDD3 Analog power supply 3.3V AVDDI Analog power supply 1.8V 100BASE-TX (Power Dissipation) 10BASE-TX Min. -0.3 -0.3 -0.3 -0.3 -0.5 Max. 1.95 1.95 +150 +260 Unit Conditions
Lead-free Device
Min. 3.135 1.71 3.135 1.71
Max. 3.465 1.89 3.465 1.89
Unit
Conditions
Auto-negotiation cable
1.8V only 3.3V only idle, 1.8V only utilization, 1.8V only 100% utilization, 1.8V only 3.3V only 1.8V only 3.3V only
Preliminary datasheet DM9013-15-DS-P03 April 2009
DM9013
3-port switch with Processor Interface
10.3 Electrical Characteristics Symbol Parameter Inputs Input Voltage Input High Voltage Input Leakage Current Input High Leakage Current Outputs Output Voltage Output High Voltage Receiver VICM RX+/RX- Common Mode Input Voltage Transmitter VTD100 100TX+/- Differential Output Voltage VTD10 10TX+/- Differential Output Voltage ITD100 100TX+/- Differential Output Current ITD10 10TX+/- Differential Output Current Min. Typ. Max. Unit Conditions Vcond1 Vcond1 0.0V, Vcond1 3.3V, Vcond1 -4mA Termination Across Peak Peak Peak Peak Absolute Value Absolute Value
Note: Vcond1 VCC3 3.3V, VCCI 1.8V, AVDD3 3.3V, AVDDI 1.8V. 10.4 characteristics 10.4.1 Power Reset Timing
PWRST#
Strap pins
EECS
Symbol
Parameter PWRST# Period Strap hold time with PWRST# PWRST# high EECS high PWRST# high EECS burst PWRST# high available
Min.
Typ. -400
Max.
Unit
Conditions Preliminary datasheet DM9013-15-DS-P03 April 2009
DM9013
3-port switch with Processor Interface
10.4.2 Processor Read Timing
CS#,CMD
IOR#
SD0~31
ior_9013.vsd
Parameter CS#,CMD valid IOR# valid IOR# invalid CS#,CMD invalid IOR# width IOR# invalid next IOR#/IOW# valid When read DM9003 register IOR# invalid next IOR#/IOW# valid When read DM9003 memory with register T3+T4 IOR# invalid next IOR#/IOW# valid When read DM9003 memory with register System Data(SD) Delay time IOR# invalid System Data(SD) invalid Note: Unit: under internal system clock 50MHz.
Symbol
Min.
Typ.
Max.
Unit clk* clk* clk*
Preliminary datasheet DM9013-15-DS-P03 April 2009
DM9013
3-port switch with Processor Interface
10.4.3 Processor Write Timing
CS#,CMD
IOW#
SD0~31
iow_9013.vsd
Parameter CS#,CMD valid IOW# valid IOW# Invalid CS#,CMD Invalid IOW# Width IOW# Invalid next IOW#/IOR# valid When write DM9013 INDEX port IOW# Invalid next IOW#/IOR# valid When write DM9013 DATA port System Data(SD) Hold Time System Data(SD) Setup Time T3+T4 IOW# Invalid next IOW#/IOR# valid When write DM9013 memory Note: Unit: under internal system clock 50MHz.
Symbol
Min.
Typ.
Max.
Unit clk* clk* clk*
Preliminary datasheet DM9013-15-DS-P03 April 2009
DM9013
3-port switch with Processor Interface
10.4.4 Port Interface Transmit Timing
TXC2
TXE2 TXD2_3~0
MIITX_9013.vsd
Symbol Parameter TXE2,TXD2_3~0 Setup Time TXE2,TXD2_3~0 Hold Time
Min.
Typ.
Max.
Unit
10.4.5 Port Interface Receive Timing
RXC2
RXER2,RXDV2 RXD2_3~0
MIIRX_9013.vsd
Symbol Parameter RXER2, RXDV2,RXD2_3~0 Setup Time RXER2, RXDV2,RXD2_3~0 Hold Time
Min.
Typ.
Max.
Unit
Preliminary datasheet DM9013-15-DS-P03 April 2009
DM9013
3-port switch with Processor Interface
10.4.6 Management Interface Timing
MDIO (drived DM9013) MDIO (drived exetrnal MII)
MDIO_9013.vsd
Symbol
Parameter Frequency MDIO DM9013 Setup Time MDIO DM9013 Hold Time MDIO External Setup Time MDIO External Hold Time
Min.
Typ. 0.52
Max.
Unit
10.4.7 EEPROM Timing
EECS EECK EEDO EEDI
eeprom_9013.vcd
Symbol
Parameter EECS Setup Time EECS Hold Time EECK Frequency EEDO Setup Time EEDO Hold Time EEDI Setup Time EEDI Hold Time
Min.
Typ. 2080 0.38 2100
Max.
Unit
Preliminary datasheet DM9013-15-DS-P03 April 2009
DM9013
3-port switch with Processor Interface Application circuit
DVDD_33V DVDD_18V DVDD_33V DVDD_33V 220uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 220uF 0.1uF 0.1uF 0.1uF EECK EEDO AVDD_33V AVDD_18V DVDD_33V HEADER_3 HEADER_3 4.7k TXD2_3 TXD2_0 TXD2_1 TXD2_2 TXE2 EECS MDIO 1.4K/1% TEST2 RX0+ RX0TX0+ TX0RX1+ RX1TX1+ TX1RXDV2 RXD2_3 RXD2_2 RXD2_1 RXD2_0 CRS2 COL2 RXER2 RXC2 AVDD_33V AVDD_18V AVDD_18V DVDD_18V DVDD_33V JUMPER JUMPER JUMPER JUMPER JUMPER JUMPER JUMPER JUMPER 4.7k IO16 IOWAIT 4.7k 4.7k 4.7k NC(4.7K) 4.7k NC(4.7K) 4.7k NC(4.7K) 4.7k 4.7k 4.7k NC(4.7K) 4.7k
Interface
SD10 SD11 SD12 SD13 SD14 SD15 PWRST# IOW# IOR# IO16 IOWAIT SD16 SD17 SD18 SD19 SD20 SD21 SD22 SD23 SD24 SD25 SD26 SD27 SD28 SD29 SD30 SD31
SD[00.31]
SD[00.31]
TEST2 220uF 0.1uF 0.1uF 0.1uF 220uF 0.1uF 0.1uF
DVDD_33V
AVDD_33V
F.B/120/SO805 VCNTL 2SB1386 DVDD_18V
PWRST# IOW# IOR# IO16 IOWAIT
F.B/120/SO805 0.1uF 0.1uF F.B/120/SO805 VREF 0.1uF HEADER_7 SCLK 25MHz/49US 22pF 22pF
Interface
TX0+ TX0RX0+ RX0TX1+ TX1RX1+ RX1LNK0_LED SPD0_LED FDX0_LED LNK1_LED SPD1_LED FDX1_LED BWLED[0.7] BWLED0 BWLED1 BWLED2 BWLED3 BWLED4 BWLED5 BWLED6 BWLED7 TX0+ TX0RX0+ RX0TX1+ TX1RX1+ RX1LNK0_LED SPD0_LED FDX0_LED LNK1_LED SPD1_LED FDX1_LED BWLED[0.7] BGRESG BGRES AVDD33 RX0RX0+ AGND AGND TX0TX0+ AVDD18 AVDD33 RX1RX1+ AGND AGND TX1TX1+ AVDD18 TEST3 TEST2 TEST1 DVDD33 RXD2_0 RXD2_1 RXD2_2 RXD2_3 RXDV2 RXC2 RXER2 COL2 CRS2
VCNTL VREF LNK1_LED SPD1_LED FDX1_LED LNK0_LED SPD0_LED FDX0_LED SCLK BWLED0 BWLED1 BWLED2 BWLED3 BWLED4 BWLED5 BWLED6 BWLED7
TEST_POINT
EEPROM
EECS EECK EEDO EEDI JUMPER 93LC46 DVDD_33V DVDD_33V
DVDD_33V
0.1uF
IOW# DVDD33 IOR# DVDD33 SD10 SD11 SD12 SD13 DVDD18 SD14 SD15 SD16 (GP2_0) SD17 (GP2_1) SD18 (GP2_2) SD19 (GP2_3) DVDD33
VCNTL VREF AVDD33 DVDD33 LNK1_LED SPD1_LED FDX1_LED LNK0_LED SPD0_LED FDX0_LED SCLK BWLED0 DVDD18 BWLED1 BWLED2 BWLED3 BWLED4 BWLED5 BWLED6 BWLED7
DM9013E Interface
TXC2 TXE2 VCC3 TXD2_0 TXD2_1 TXD2_2 TXD2_3 DVDD18 MDIO PWRST# EECS EECK EEDO EEDI DVDD33 (GP3_7) SD31 (GP3_6) SD30 (GP3_5) SD29 (GP3_4) SD28 (GP3_3) SD27 (GP3_2) SD26 DVDD33 (GP3_1) SD25 (GP3_0) SD24 (GP2_7) SD23 (GP2_6) SD22 (GP2_5) SD21 (GP2_4) SD20
TXC2 TXE2 TXD2_0 TXD2_1 TXD2_2 TXD2_3 MDIO PWRST# EECS EECK EEDO EEDI SD31 SD30 SD29 SD28 SD27 SD26 SD25 SD24 SD23 SD22 SD21 SD20
Interface
RXD2_0 RXD2_1 RXD2_2 RXD2_3 RXDV2 RXC2 CRS2 COL2 RXER2
RXD2_[0.3]
RXD2_[0.3]
RXDV2 RXC2 CRS2 COL2 RXER2 TXD2_[0.3] TXD2_[0.3]
1N4148
RESET_IC_(AP1701DW)
TXD2_0 TXD2_1 TXD2_2 TXD2_3 TXE2 TXC2 MDIO
TXE2 TXC2 MDIO
PWRST# Title Size Date:
Davicom Semiconductor Inc.
IOW# IOR# SD16 SD17 SD18 SD19 SD10 SD11 SD12 SD13 SD14 SD15 10uF
MAIN_CHIP
Document Number
DM9013E_EVB_BOARD
Tuesday December 2006 Sheet
Preliminary datasheet DM9013-15-DS-P03 April 2009
DM9013
3-port switch with Processor Interface
Interface
RXD2_0 RXD2_1 RXD2_2 RXD2_3 RXDV2 RXC2 CRS2 COL2 RXER2 TXD2_[0.3] TXD2_0 TXD2_1 TXD2_2 TXD2_3 TXE2 TXC2 MDIO DVDD_5V RXD2_[0.3] AP1117-3.3V 220uF 0.1uF RXD2_0 RXD2_1 RXD2_2 RXD2_3 CRS2 COL2 RXDV2 RXER2 RXC2 TXC2 TXD2_0 TXD2_1 TXD2_2 TXD2_3 MDIO DVDD_33V RXD2_[0.3]
RXDV2 RXC2 CRS2 COL2 RXER2 TXD2_[0.3]
TXE2 TXC2 MDIO TXE2
Interface
SD10 SD11 SD12 SD13 SD14 SD15 PWRST# IOW# IOR# IO16 IOWAIT SD16 SD17 SD18 SD19 SD20 SD21 SD22 SD23 SD24 SD25 SD26 SD27 SD28 SD29 SD30 SD31
SD[00.31]
SD[00.31]
DVDD_5V IOWAIT PWRST# IOW# IOR# IO16
PWRST# IOW# IOR# IO16 IOWAIT
Davicom Semiconductor Inc.
Title Size Date:
CONNECT_AND_POWER
Document Number
SD10 SD11 SD12 SD13 SD14 SD15 Sheet
HEADER_16
DM9013E_EVB_BOARD
Tuesday December 2006
HEADER_16X2 SD16 SD17 SD18 SD19 SD20 SD21 SD22 SD23 SD24 SD25 SD26 SD27 SD28 SD29 SD30 SD31
DVDD_5V DVDD_33V
HEADER_16X2
Preliminary datasheet DM9013-15-DS-P03 April 2009
DM9013
3-port switch with Processor Interface
Interface
TX0+ TX0RX0+ RX0TX1+ TX1RX1+ RX1TX0+ TX0RX0+ RX0TX1+ TX1RX1+ RX1LNK0_LED SPD0_LED FDX0_LED LNK1_LED SPD1_LED FDX1_LED BWLED[0.7] BWLED0 BWLED1 BWLED2 BWLED3 BWLED4 BWLED5 BWLED6 BWLED7 SPD0_LED DVDD_33V LNK0_LED SPD0_LED FDX0_LED LEDA LEDA LEDA LNK0_LED 74HC04 AVDD_18V RX1RX1+ TX1TX1+ DVDD_33V BWLED7 BWLED6 BWLED5 BWLED4 BWLED3 BWLED2 BWLED1 BWLED0 LEDA LEDA LEDA LEDA LEDA LEDA 49.9/1% 49.9/1% 49.9/1% 49.9/1% RJ-45 RXNC TXNC BWLED[0.7] AVDD_18V RX0RX0+ TX0TX0+ 49.9/1% 49.9/1% RDNC TDNC RXMCT TX16 RJ-45_LED
LED2+ LED216
LNK0_LED SPD0_LED FDX0_LED LNK1_LED SPD1_LED FDX1_LED
MAGCOM_HS9024 75/1% 75/1% 75/1% 0.1uF 0.01uF/2KV RJ45_SPD RJ45_LINK 74HC04
49.9/1% 49.9/1%
0.1uF
0.1uF
LNK1_LED SPD1_LED FDX1_LED
LEDA
LEDA LEDA
RDNC TDNC
MAGCOM_HS9016 75/1% 75/1% 75/1% 0.1uF 0.01uF/2KV
LEDA LEDA
0.1uF
0.1uF
0.1uF
Title Size Date:
Davicom Semiconductor Inc. RJ45_AND_LED
Document Number
0.1uF
DM9013E_EVB_BOARD
Tuesday December 2006 Sheet
Preliminary datasheet DM9013-15-DS-P03 April 2009
LED1+ LED1-
DM9013
3-port switch with Processor Interface Package Information
Pins LQFP Package Outline Information:
Symbol
Dimension 0.05 1.35 0.13 0.13 0.09 0.09 15.85 13.90 15.85 13.90 0.45 0.08 0.08 0.20
Dimension inch 1.60 1.45 0.23 0.19 0.20 0.16 16.15 14.10 16.15 14.10 0.75 0.20 0.002 0.053 0.005 0.005 0.004 0.004 0.624 0.547 0.624 0.547 0.018 0.003 0.003 0.008
1.40 0.18 0.16 16.00 14.00 16.00 14.00 0.40 0.60 1.00
0.055 0.007 0.006 0.630 0.551 0.630 0.551 0.016 0.024 0.039
0.063 0.057 0.009 0.007 0.008 0.006 0.636 0.555 0.636 0.555 0.030 0.008
Dimension include resin fin. dimensions base metric system. General appearance spec should base final visual inspection spec.
Preliminary datasheet DM9013-15-DS-P03 April 2009
DM9013
3-port switch with Processor Interface
Ordering Information
Part Number DM9013EP Count Package LQFP (Pb-free)
application circuits illustrated this document reference purposes only. DAVICOM's terms conditions printed order acknowledgment govern sales DAVICOM. DAVICOM will bound terms inconsistent with these unless DAVICOM agrees otherwise writing. Acceptance buyer's orders shall based these terms.
Disclaimer
information appearing this publication believed accurate. Integrated circuits sold DAVICOM Semiconductor covered warranty patent indemnification provisions stipulated terms sale only. DAVICOM makes warranty, express, statutory, implied description regarding information this publication regarding information this publication regarding freedom described chip(s) from patent infringement. FURTHER, DAVICOM MAKES WARRANTY MERCHANTABILITY FITNESS PURPOSE. DAVICOM reserves right halt production alter specifications prices time without notice. Accordingly, reader cautioned verify that data sheets other information this publication current before placing orders. Products described herein intended normal commercial applications. Applications involving unusual environmental reliability requirements, e.g. military equipment medical life support equipment, specifically recommended without additional processing DAVICOM such applications. Please note that
Company Overview
DAVICOM Semiconductor Inc. develops manufactures integrated circuits integration into data communication products. mission design produce products that industry's best value Data, Audio, Video, Internet/Intranet applications. achieve this goal, have built organization that able develop chipsets response evolving technology requirements customers while still delivering products that meet their cost requirements.
Products
offer only products that satisfy high performance requirements which compatible with major hardware software standards. currently available soon released products based proprietary designs deliver high quality, high performance chipsets that comply with modem communication standards Ethernet networking standards.
Contact Windows
additional information about DAVICOM products, contact Sales department
Headquarters
Hsin-chu Office: No.6 Li-Hsin Science-based Park, Hsin-chu City, Taiwan, R.O.C. TEL: 886-3-5798797 FAX: 886-3-5646929 MAIL: sales@davicom.com.tw HTTP: http://www.davicom.com.tw WARNING
Conditions beyond those listed absolute maximum destroy damage products. addition, conditions sustained periods near limits operating ranges will stress temporarily (and permanently) affect damage structure, performance and/or function. Preliminary datasheet DM9013-15-DS-P03 April 2009
Other recent searches
TA7522S - TA7522S TA7522S Datasheet
TA7522F - TA7522F TA7522F Datasheet
PTVSxP1UP - PTVSxP1UP PTVSxP1UP Datasheet
series - series series Datasheet
PSSP320 - PSSP320 PSSP320 Datasheet
PE4140 - PE4140 PE4140 Datasheet
LQ181E1DG01 - LQ181E1DG01 LQ181E1DG01 Datasheet
HT12A - HT12A HT12A Datasheet
HT12E - HT12E HT12E Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
