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10/100 Mbps 2-port Ethernet Switch Controller with General Processor I


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DM9003
10/100 Mbps 2-port Ethernet Switch Controller with General Processor Interface
Preliminary Version: DM9003-DS-P05 April 2009
DM9003
2-port Switch with Processor Interface
CONTENT
GENERAL DESCRIPTION. BLOCK DIAGRAM. FEATURES CONFIGURATION LQFP. DESCRIPTION
Processor interface EEPROM Interfaces Pins Clock Interface. Network Interface Miscellaneous Pins Power Pins Strap pins table.
CONTROL STATUS REGISTER SET.
Network Control Register (00H) Network Status Register (01H). Control Register (02H). Control Register (05H)
Preliminary datasheet DM9003-15-DS-P05 April 2009
DM9003
2-port Switch with Processor Interface
Status Register (06H) Receive Overflow Counter Register (07H) Flow Control Register (0AH). EEPROM Control Register (0BH) EEPROM Address Register (0CH) 6.10 EEPROM Data Registers (0DH~0EH). 6.11 Link Change Control Register (0FH) 6.12 Processor Port Physical Address Registers (10H~15H) 6.13 Processor Port Multicast Address Registers (16H~1DH). 6.14 Packet Length Register 6.15 Packet Length High Register 6.16 Additional Status Register 6.17 Additional Control Register 6.18 Vendor Registers (28H~29H) 6.19 Product Registers (2AH~2BH) 6.20 Chip Revision Register (2CH) 6.21 Transmit Check Control Register (31H) 6.22 Receive Check Control Status Register (32H). 6.23 Data driving capability Register (38H) 6.24 Control Register (39H)
Preliminary datasheet DM9003-15-DS-P05 April 2009
DM9003
2-port Switch with Processor Interface
6.25 TX/RX Memory Size Control Register (3FH) 6.26 Switch Control Register (52H). 6.27 VLAN Control Register (53H) 6.28 Control Register (58H~59H). 6.29 Port Control/Status Index Register (60H). 6.30 Port Control Data Register (61H) 6.31 Port Status Data Register (62H) 6.32 Port Forward Control Register (65H) 6.33 Port Ingress Egress Control Register (66H). 6.34 Port Bandwidth Control Setting Register (67H) 6.35 Port Block Unicast Ports Control Register (68H) 6.36 Port Block Multicast Ports Control Register (69H) 6.37 Port Block Broadcast Ports Control Register (6AH). 6.38 Port Block Unknown Ports Control Register (6BH) 6.39 Port Priority Queue Control Register (6DH). 6.40 Port VLAN Byte Register (6EH) 6.41 Port VLAN High Byte Register (6FH). 6.42 Counter Port Index Register (80H) 6.43 Counter Data Registers (81H~84H) 6.44 Port-Based VLAN Mapping Table Registers (B0H~BFH). 6.45 Priority Registers (C0H~CFH).
Preliminary datasheet DM9003-15-DS-P05 April 2009
DM9003
2-port Switch with Processor Interface
6.46 VLAN Priority Registers (D0H~D1H) 6.47 Memory Data Pre-Fetch Read Command without Address Increment Register (F0H) 6.48 Memory Data Read Command with Address Increment Register (F2H). 6.49 Memory Data Read Address Register (F4H) 6.50 Memory Data Read Address Register (F5H) 6.51 Memory Data Write Command without Address Increment Register (F6H). 6.52 Memory Data Write Command with Address Increment Register (F8H) 6.53 Memory Data Write Address Register (FAH) 6.54 Memory Data Write Address Register (FBH) 6.55 Packet Length Registers (FCH~FDH) 6.56 Interrupt Status Register (FEH). 6.57 Interrupt Mask Register (FFH).
EEPROM FORMAT. REGISTERS
Basic Mode Control Register (BMCR) Basic Mode Status Register (BMSR) Identifier Register (PHYID1) 02H. Identifier Register (PHYID2) 03H. Auto-negotiation Advertisement Register (ANAR) 04H. Auto-negotiation Link Partner Ability Register (ANLPAR)
Preliminary datasheet DM9003-15-DS-P05 April 2009
DM9003
2-port Switch with Processor Interface
Auto-negotiation Expansion Register (ANER) DAVICOM Specified Configuration Register (DSCR) DAVICOM Specified Configuration Status Register (DSCSR) 8.10 10BASE-T Configuration/Status (10BTCSR) 12H. 8.11 Power Down Control Register (PWDOR) 13H. 8.12 (Specified config) Register 8.13 DAVICOM Specified Receive Error Counter Register (RECR) 8.14 DAVICOM Specified Disconnect Counter Register (DISCR) 8.15 Power Saving Control Register (PSCR)
FUNCTIONAL DESCRIPTION.
Processor memory management function: 9.1.1 Processor Interface 9.1.2 Direct Memory Access Control. 9.1.3 Packet Transmission. 9.1.4 Packet Reception Switch function:. 9.2.1 Address Learning 9.2.2 Address Aging 9.2.3 Packet Forwarding 9.2.4 Inter-Packet (IPG) 9.2.5 Back-off Algorithm. 9.2.6 Late Collision. 9.2.7 Half Duplex Flow Control 9.2.8 Full Duplex Flow Control 9.2.9 Partition Mode 9.2.10 Broadcast Storm Filtering.
Preliminary datasheet DM9003-15-DS-P05 April 2009
DM9003
2-port Switch with Processor Interface
9.2.11 Bandwidth Control. 9.2.12 Port Monitoring Support 9.2.13 VLAN Support 9.2.13.1 Port-Based VLAN. 9.2.13.2 802.1Q-Based VLAN. 9.2.13.3 Tag/Untag 9.2.14 Priority Support 9.2.14.1 Port-Based Priority 9.2.14.2 802.1p-Based Priority. 9.2.14.3 DiffServ-Based Priority. Internal functions 9.3.1 100Base-TX Operation 9.3.1.1 4B5B Encoder 9.3.1.2 Scrambler 9.3.1.3 Parallel Serial Converter 9.3.1.4 NRZI Encoder 9.3.1.5 MLT-3 Converter 9.3.1.6 MLT-3 Driver 9.3.1.7 4B5B Code Group. 9.3.2 100Base-TX Receiver 9.3.2.1 Signal Detect 9.3.2.2 Adaptive Equalization. 9.3.2.3 MLT-3 NRZI Decoder. 9.3.2.4 Clock Recovery Module 9.3.2.5 NRZI 9.3.2.6 Serial Parallel 9.3.2.7 Descrambler 9.3.2.8 Code Group Alignment. 9.3.2.9 4B5B Decoder. 9.3.3 10Base-T Operation. 9.3.4 Collision Detection 9.3.5 Carrier Sense 9.3.6 Auto-Negotiation
Preliminary datasheet DM9003-15-DS-P05 April 2009
DM9003
2-port Switch with Processor Interface ELECTRICAL CHARACTERISTICS
10.1 Absolute Maximum Ratings 10.2 Operating Conditions. 10.3 Electrical Characteristics 10.4 characteristics 10.4.1 Power Reset Timing 10.4.2 Processor Read Timing. 10.4.3 Processor Write Timing 10.4.4 EEPROM timing
APPLICATION CIRCUIT PACKAGE INFORMATION. ORDERING INFORMATION
Preliminary datasheet DM9003-15-DS-P05 April 2009
DM9003
2-port Switch with Processor Interface GENERAL DESCRIPTION
DM9003 fully integrated, highperformance, cost-effective Fast Ethernet switch controller with general processor interface, port 10M/100Mbps PHYs. general processor connects directly internal host with 8-bit 16-bit data access internal memory. host similar functions other 10M/100Mbps This makes DM9003 extended three port switch shorten latency from processor port destination port. internal memory DM9003 supports uni-cast address table, serves ports' processor port's transmit receive buffers. efficient memory usage algorithm, total 48KB memory shared with ports processor port link list data structure. Each port DM9003 provides four priorities transmit queues, which defined port-based, 802.1p VLAN, packet field, various bandwidth latency requirement data, voice, video applications. Each port also supports ingress and/or egress rate control provide proper bandwidth. groups 802.1Q VLAN with Tag/Un-tag functions supported provide efficient packet forwarding. TCP/UDP/IPv4 checksum generation checking functions also provided processor port offload processor's computing load. addition packet transmit receive functions, processor port also provides various registers control status DM9003's operation. Each port, including processor port, provides counters, loop-back capability memory Build-in Self Test (BIST) system board level diagnostic. integrated ports compliant with IEEE 802.3u standards supports Auto-MDIX capabilities twisted-pair cable transmit/receive direction automatic switching.
BLOCK DIAGRAM
Switch Engine Port MDIX Switch Fabric Memory Embedded Memory BIST
Port MDIX
Switch Controller
Memory Management
Processor
Processor Interface
Host Control Registers Counters EEPROM Interface
EEPROM
Preliminary datasheet DM9003-15-DS-P05 April 2009
DM9003
2-port Switch with Processor Interface FEATURES Ethernet Switch with 10/100Mbps PHYs general processor interface Processor slave architecture EEPROM interface power-up configuration TCP/UDP/IPv4 checksum offload Support Auto-MDIX IEEE 802.3x Flow Control Full-duplex mode Back Pressure Flow Control Half-duplex mode Each port supports priority queues Port-based, 802.1P QoS, priority Support 802.1Q VLAN VLAN groups Support VLAN tag/untag option Each port supports bandwidth, ingress egress rate control Support Broadcast Storming filter function Support Store Forward switching approach Support uni-cast addresses Automatic aging scheme Support counters diagnostic data driving capability adjustable 64-pin LQFP 1.8V internal core, 3.3V with tolerant
Preliminary datasheet DM9003-15-DS-P05 April 2009
DM9003
2-port Switch with Processor Interface Configuration LQFP
BGRESG BGRES AVDD3 AVDD3 AVDDI RX0+ AGND AVDDI AGND
RX1+
TX0+
VCNTL VREF VCC3 LNK1_LED SPD1_LED LNK0_LED SPD0_LED TEST2 VCCI IOW#
DM9003
TX1+
RX0-
RX1-
TX0-
TX1-
TEST1 PWRST# EECS EECK EEDIO VCC3 SD15 SD14 SD13 SD12 SD11 SD10
VCC3
VCC3
IOR#
VCCI
Preliminary datasheet DM9003-15-DS-P05 April 2009
DM9003
2-port Switch with Processor Interface DESCRIPTION
Input, Output, Input Output, Open Drain, Power, PD=internal pull-low (approx. ohm) asserted
Processor interface
Name IOR#
Description Processor Read Command Default active. polarity changed setting EEPROM. Interrupt Request Default high active non-open collector type. polarity output type changed strap pins EEPROM setting. Processor Data 0~15 Command Type Upon transaction, when high, SD0~15 reflect value DATA port when low, SD0~15 reflect value INDEX port Processor Chip Select Command Default active. polarity changed EEPROM setting. Processor Write Command Default active. polarity changed EEPROM setting.
5,6,7,9,10,12,14,15, 17,18,19,20,21,22,24,25
SD0~15
IOW#
EEPROM Interfaces
Name EEDIO EECK EECS
I,/O O,PD O,PD
Description EEPROM Data In/Out EEPROM Serial Clock This used clock EEPROM data transfer. EEPROM Chip Selection.
Preliminary datasheet DM9003-15-DS-P05 April 2009
DM9003
2-port Switch with Processor Interface
Pins Name LNK1_LED Description Port Link Active combined link carrier sense signal port Port Speed It's indicate that port operates 100M mode. It's floating indicate that port operates mode. Port Link Active combined link carrier sense signal port Port Speed It's indicate that port operates 100M mode. It's floating indicate that port operates mode.
SPD1_LED
LNK0_LED
SPD0_LED
Clock Interface
Name
Crystal 25MHz Crystal 25MHz
Description
Network Interface 34,35
Name TX1+/-
Description Port These pins transmit output mode receive input MDIX mode. Port These pins receive input mode transmit output MDIX mode. Port These pins transmit output mode receive input MDIX mode. Port These pins receive input mode transmit output MDIX mode. Band Connect 1.4Kohm resistor BGRESG application. Band Ground 1.8V Voltage control Voltage Reference Connect 0.1uF capacitor ground application.
37,38
RX1+/-
41,42
TX0+/-
44,45
RX0+/-
BGRES
BGRESG VCNTL VREF
Preliminary datasheet DM9003-15-DS-P05 April 2009
DM9003
2-port Switch with Processor Interface
Miscellaneous Pins
Name PWRST# TEST1 TEST2
Description
Power-on Reset active with minimum I,PD ground application I,PD ground application
Power Pins 1,13,26,51 11,61 4,8,16,23,31,54,64 39,46 33,40 36,43
Name VCC3 VCCI AVDD3 AVDDI AGND
Description Digital 3.3V Internal 1.8V core power Digital Analog 3.3V power Analog 1.8V power Analog
Strap pins table pull-high 1K~10K, floating (default).
Name Description
EECK EECS
Processor Data Width 16-bit, 0-15 used processor data (default) 8-bit, used processor data bus; 8-15 left floating. Polarity high active (default) active
Preliminary datasheet DM9003-15-DS-P05 April 2009
DM9003
2-port Switch with Processor Interface CONTROL STATUS REGISTER
DM9003 implements several control status registers (CSR), which accessed host. Register ROCR EPCR EPAR EPDRL EPDRH LCCR RXPLLR RXPLHR RASR RACR CHIPR TCSCR RCSCSR DRIVER IRQCR SWITCHCR VLANCR DSP1,2 P_INDEX P_CTRL P_STUS P_RATE P_BW P_UNICAST P_MULTI P_BCAST P_UNKNWN P_PRI VLAN_TAGL
Preliminary datasheet DM9003-15-DS-P05 April 2009
their default values power software reset unless specified. Offset 10H-15H 16H-1DH 28H-29H 2AH-2BH 58H~59H Default value after reset EEPROM 0A46H 9003H 0000H
Description Network Control Register Network Status Register Control Register Control Register Status Register Receive Overflow Counter Register Flow Control Register EEPROM Control Register EEPROM Address Register EEPROM Byte Data Register EEPROM High Byte Data Register Link Change Control Register (0FH) Processor Port Physical Address Registers Processor Port Multicast Address Registers Packet Length Register Packet Length High Register Additional Status Register Additional Control Register Vendor Registers Product Registers CHIP Revision Registers Transmit Check Control Register Receive Check Control Status Register Data driving capability Register Control Register Switch Control Register VLAN Control Register Control Register I,II Port Control/Status Index Register Port Control Data Register Port Status Data Register Port Ingress Egress Rate Control Register Port Bandwidth Control Setting Register Port Block Unicast Ports Control Register Port Block Multicast Ports Control Register Port Block Broadcast Ports Control Register Port Block Unknown Ports Control Register Port Priority Queue Control Register Port VLAN Byte Register
DM9003
2-port Switch with Processor Interface
VLAN_TAGH P_MIB_IDX MIB_DAT Port VLAN High Byte Register Port counter Index Register counter Data Register counter Data Register 8~15 counter Data Register 16~23 counter Data Register 24~31 Port-based VLAN mapping table registers Priority Registers VLAN Priority Registers Memory Data Pre-Fetch Read Command Without Address Increment Register Memory Data Read Command With Address Increment Register Memory Data Read_ address Register Byte Memory Data Read_ address Register High Byte Memory Data Write Command Without Address Increment Register Memory Data Write Command With Address Increment Register Memory Data Write_ address Register Byte Memory Data Write address Register High Byte Packet Length Byte Register Packet Length High Byte Register Interrupt Status Register Interrupt Mask Register B0-BFH C0-CFH D0-D1H 00H~FFH 50H,FAH
PVLAN TOS_MAP VLAN_MAP MRCMDX MRCMD MRRL MRRH MWCMDX MWCMD MWRL MWRH TXPLL TXPLH
Preliminary datasheet DM9003-15-DS-P05 April 2009
DM9003
2-port Switch with Processor Interface
Default register description that follows, default column takes form: <Reset Value>, <Access Type> Where: <Reset Value>: logic logic zero default value power reset, PWRST# pin, default value hardware reset, Reg. default value software reset, Reg. default value
default value from EEPROM setting default value from strap <Access Type>: Read only Read/Write Read Clear RW/C1=Read/Write Cleared write Write only Reserved bits should written with Reserved bits undefined read access.
Network Control Register (00H) Name Default Description RESERVED 0,RO Reserved LNK_X_EN P0,WO Link Change Status Enable When set, enables report port link change status function. Clearing this will also clear link change status This will affected after software reset CLR1 PH0,RW REG. auto-cleared after read REG. cleared writing respected bit. RESERVED 0,RO Reserved PH0, Loopback test Mode transmit packets from processor port forward processor port itself. PH0,RW Software reset auto clear after 10us
Network Status Register (01H) Name Default Description RESERVED 0,RO Reserved Link Change Status. PH0, This after port link changed. LINK_X_ST W/C1 set, this cleared write Otherwise cleared read write RESERVED 0,RO Reserved TX2END PHS0, Packet Complete Status. RW/C1 This after transmit completion packet index set, this cleared write Otherwise cleared read write TX1END PHS0, Packet Complete status. RW/C1 This after transmit completion packet index set, this cleared write Otherwise cleared read write RESERVED 0,RO Reserved
Preliminary datasheet DM9003-15-DS-P05 April 2009
DM9003
2-port Switch with Processor Interface
Control Register (02H) Name Default RESERVED 0,RO CRC_DIS2 PHS0,RW RESERVED 0,RO CRC_DIS1 PHS0,RW TXREQ PHS0,RW Description Reserved Appends Disable Packet Index Reserved Appends Disable Packet Index Request. Auto clears after transmit completely
Control Register (05H) Name Default HASHALL PHS0,RW RESERVED PHS0,RW RESERVED PHS0,RW PHS0,RW
RESERVED PHS0,RW PRMSC PHS0,RW RXEN PHS0,RW
Description Filter address Hash Table Reserved Reserved Pass Multicast Packets received packets with Destination Address (DA) field accepted save receive memory. Reserved Promiscuous Mode received packets accepted save receive memory without field filter. Enable
Status Register (06H) Name Default RESERVED 0,RO SRCP 0,RO PH0,RO RESERVED 0,RO
Description Reserved Source Port Number Error indicate that received frame ends with error Reserved
Receive Overflow Counter Register (07H) Name Default Description RXFU PHS0,R/C Receive Overflow Counter Overflow This when overflow condition PHS0,R/C Receive Overflow Counter This statistic counter indicate received packet count upon FIFO overflow Flow Control Register (0AH) Name Default Description RESERVED 0,RO Reserved Flow Control Enable FLOW_EN PHS0,RW Enables pause packet high/low water threshold control RESERVED 0,RO Reserved EEPROM Control Register (0BH) Name Default Description RESERVED 0,RO Reserved REEP PH0,RW Reload EEPROM. Driver needs clear after operation completes PH0,RW Write EEPROM Enable
Preliminary datasheet DM9003-15-DS-P05 April 2009
DM9003
2-port Switch with Processor Interface
EPOS ERPRR ERPRW ERRE PH0,RW PH0,RW PH0,RW PH0,RO EEPROM Operation Select When reset, select EEPROM; when set, select EEPROM Read Register Read Command. Driver needs clear after operation completes. EEPROM Write Register Write Command. Driver needs clear after operation completes. EEPROM Access Status Access Status When set, indicates that EEPROM access progress
EEPROM Address Register (0CH) Name Default Description PHY_ADR PH01,RW Address address [4:2] force EROA PH0,RW EEPROM Word Address Register Address 6.10 EEPROM Data Registers (0DH~0EH) Name Default Description EPDRL PH0,RW EEPROM Byte Data (0DH) This data made write/read byte word address defined Reg. EEPROM EPDRH PH0,RW EEPROM High Byte Data (0EH) This data made write/read high byte word address defined Reg. EEPROM 6.11 Link Change Control Register (0FH) Name Type Description RESERVED 0,RO Reserved LINKEN PE0,RW Link Change Event Enable When both this NCR, enables link change status Event RESERVED 0,RO Reserved LINKST PH0,RO Link Change Event Status When set, indicates that Link Status Change Event (link port occurred This cleared write write NCR. RESERVED 0,RO Reserved 6.12 Processor Port Physical Address Registers (10H~15H) Name Default PAB5 E,RW Physical Address Byte (15H) PAB4 E,RW Physical Address Byte (14H) PAB3 E,RW Physical Address Byte (13H) PAB2 E,RW Physical Address Byte (12H) PAB1 E,RW Physical Address Byte (11H) PAB0 E,RW Physical Address Byte (10H)
Description
6.13 Processor Port Multicast Address Registers (16H~1DH) Name Default Description MAB7 X,RW Multicast Address Byte (1DH) MAB6 X,RW Multicast Address Byte (1CH) MAB5 X,RW Multicast Address Byte (1BH)
Preliminary datasheet DM9003-15-DS-P05 April 2009
DM9003
2-port Switch with Processor Interface
MAB4 MAB3 MAB2 MAB1 MAB0 X,RW X,RW X,RW X,RW X,RW Multicast Address Byte Multicast Address Byte Multicast Address Byte Multicast Address Byte Multicast Address Byte (1AH) (19H) (18H) (17H) (16H)
6.14 Packet Length Register Name Default RXPLL PH,RO Packet Length byte 6.15 Packet Length High Register Name Default RXPLH PH,RO Packet Length High byte
Description
Description
6.16 Additional Status Register Name Default Description RESERVED 0,RO Reserved received pointer status, only available when pointer restriction enabled (Reg27h.7=0). RPTRS PH,RO Within buffer buffer Exceed buffer 6.17 Additional Control Register Name Default RPRD PHS0,RW pointer restriction disable RESERVED 0,RO Reserved 6.18 Vendor Registers (28H~29H) Name Default VIDH PE,0AH,RO Vendor High Byte (29H) VIDL PE,46H.RO Vendor Byte (28H) 6.19 Product Registers (2AH~2BH) Name Default PIDH PE,90H,RO Product High Byte (2BH) PIDL PE,03H.RO Product Byte (2AH) 6.20 Chip Revision Register (2CH) Name Default CHIPR 01H,RO CHIP Revision
Description
Description
Description
Description
6.21 Transmit Check Control Register (31H) Name Default Description RESERVED 0,RO Reserved UDPCSE HP0,RW Checksum Generation Enable TCPCSE HP0,RW Checksum Generation Enable IPCSE HP0,RW Checksum Generation Enable
Preliminary datasheet DM9003-15-DS-P05 April 2009
DM9003
2-port Switch with Processor Interface
6.22 Receive Check Control Status Register (32H) Name Default Description UDPS HP0,RO Checksum Status packet checksum fail. packet checksum packet. TCPS HP0,RO Checksum Status packet checksum fail. packet checksum packet. HP0,RO Checksum Status packet checksum packet checksum packet. UDPP HP0,RO This Packet TCPP HP0,RO This Packet HP0,RO This Packet RCSEN HPS0,RW Receive Checksum Checking Enable When set, checksum status will store packet first byte status header. DCSE HPS0,RW Discard Checksum Error Packet When set, IP/TCP/UDP checksum field error, this packet will discarded. 6.23 Data driving capability Register (38H) Name Default RESERVED 0,RW reserved
Description
ISA_CURR Reserved STEP IOW_SPIKE IOR_SPIKE
P01,RW P0,RW P0,RW P0,RW P1,RW
Current Driving/Sinking Capability (default) Reserved Data Output stepping disabled enabled Eliminate spike eliminate about spike Eliminate spike eliminate about spike
6.24 Control Register (39H) Name Default Reserved PS0,RO Reserved Output Type Control IRQ_TYPE PET0,RW Open-Collector output direct output Polarity Control IRQ_POL PET0,RW active active high
Description
Preliminary datasheet DM9003-15-DS-P05 April 2009
DM9003
2-port Switch with Processor Interface
6.25 TX/RX Memory Size Control Register (3FH) Name Default Description Reserved PS0,RO Reserved Block Size 2-Port Mode This value defines transmit block size 256-byte unit. memory size TX_SIZE bytes TX_SIZE P20h,RW then memory size 16KB (TX_SIZE 1)*256-Byte Note: value TX_SIZE should between 6.26 Switch Control Register (52H) Name Default Description MEM_BIST PH0,RO Address Memory Test BIST Status Fail RST_SW P0,RW Reset Switch Core auto clear after 10us RST_ANLG P0,RW Reset Analog Core auto clear after 10us SNF_PORT PE00,RW Sniffer Port Number Define port number sniffer port CRC_DIS PE0,RW Checking Disable When set, received error packet also accepts receive memory. PE0,RW Aging aging ±128
6.27 VLAN Control Register (53H) Name Default Description TOS6 PE0,RW Full Using Enable check most significant 6-bit check most significant 3-bit only RESERVED 0,RO Reserved UNICAST PE0,RW Unicast packet across VLAN boundary VIDFF PE0,RW Replace VIDFF received packet tagged VLAN with equal "FFF", VLAN field replaced with VLAN defined Reg. 6FH. VID1 PE0,RW Replace VID01 received packet tagged VLAN with equal "001", VLAN field replaced with VLAN defined Reg. 6FH. VID0 PE0,RW Replace VID0 received packet tagged VLAN with equal "000", VLAN field replaced with VLAN defined Reg. 6FH. PE0,RW Replace priority field with value define 7~5. VLAN PE0,RW VLAN mode enable 802.1Q base VLAN mode enable port-base VLAN only
Preliminary datasheet DM9003-15-DS-P05 April 2009
DM9003
2-port Switch with Processor Interface
6.28 Control Register (58H~59H) 58H: 59H: Name DSP_CTL2 Default 0,RW Description Control Register testing only (register 59H) Name DSP_CTL1 Default 0,RW Description Control Register testing only (register 58H)
6.29 Port Control/Status Index Register (60H) Name Default Description reserved PHS0,RW reserved reserved 0,RO reserved INDEX PHS0,RW Port index register 61H~84H Write port number this register before write/read register 61H~84H. Note: processor port INDEX number 6.30 Port Control Data Register (61H) Name Default Description RESERVED PE0,RW Reserved PARTI_EN PE0,RW Enable Partition Detection NO_DIS_RX PE0,RW Discard Packets when Ingress Bandwidth Control When received packets bandwidth reach Ingress bandwidth threshold, packets over threshold discarded with flow control. FLOW_DIS PE0,RW Flow control full duplex mode, back pressure half duplex mode enable enable disable BANDWIDTH PE0,RW Bandwidth Control Control with Ingress Egress separately, Register 66H. Control with Ingress Egress, Register BP_DIS PE0,RW Broadcast packet filter accept broadcast packets reject broadcast packets MP_DIS PE0,RW Multicast packet filter accept multicast packets reject multicast packets MP_STORM PE0,RW Broadcast Storm Control only broadcast packets storm controlled multicast packets also same broadcast storm control.
Preliminary datasheet DM9003-15-DS-P05 April 2009
DM9003
2-port Switch with Processor Interface
6.31 Port Status Data Register (62H) Name Default Description RESERVED P0,RO Reserved LP_FCS P0,RO Link Partner Flow Control Enable Status BIST P0,RO BIST status SRAM BIST fail SRAM BIST pass RESERVED 0,RO Reserved SPEED2 P0,RO Speed Status 10Mbps, 100Mbps FDX2 P0,RO Duplex Status half-duplex, full-duplex LINK2 P0,RO Link Status link fail, link 6.32 Port Forward Control Register (65H) Name Default Description LOOPBACK PH0,RW Loop-Back Mode received packet will forward this port itself. MONI_TX PH0,RW Packet Monitored transmitted packets also forward sniffer port. MONI_RX PH0,RW Packet Monitored received packets also forward sniffer port. DIS_BMP PH0,RW Broad/Multicast Monitored received broadcast multicast packets forward sniffer port. Reserved PH0,RW Reserved TX_DIS PH0,RW Packet Transmit Disabled packets forward this port. RX_DIS PH0,RW Packet receive Disabled received packets discarded. ADR_DIS PH0,RW Address Learning Disabled Source Address (SA) field packet learned address table.
Preliminary datasheet DM9003-15-DS-P05 April 2009
DM9003
2-port Switch with Processor Interface
6.33 Port Ingress Egress Control Register (66H) Name Default Description INGRESS PE0,RW Ingress Rate Control These bits define bandwidth threshold that received packets over threshold discarded. Ingress Rate table below 0000: none 0001: 64Kbps 0010: 128Kbps 0011: 256Kbps 0100: 512Kbps 0101: 1Mbps 0110: 2Mbps 0111: 4Mbps 1000: 8Mbps 1001: 16Mbps 1010: 32Mbps 1011: 48Mbps 1100: 64Mbps 1101: 72Mbps 1110: 80Mbps 1111: 88Mbps Egress Rate Control These bits define bandwidth threshold that transmitted packets over threshold discarded. Egress Rate table below 0000: none 0001: 64Kbps 0010: 128Kbps 0011: 256Kbps 0100: 512Kbps 0101: 1Mbps 0110: 2Mbps 0111: 4Mbps 1000: 8Mbps 1001: 16Mbps 1010: 32Mbps 1011: 48Mbps 1100: 64Mbps 1101: 72Mbps 1110: 80Mbps 1111: 88Mbps
EGRESS
PE0,RW
Preliminary datasheet DM9003-15-DS-P05 April 2009
DM9003
2-port Switch with Processor Interface
6.34 Port Bandwidth Control Setting Register (67H) Name Default Description BSTH PE0,RW Broadcast Storm Threshold These bits define bandwidth threshold that received broadcast packets over threshold discarded. Threshold table below 0000: broadcast storm control 0001: packets/sec 0010: packets/sec 0011: packets/sec 0100: 0101: 0110: 0111: 1000: 1001: 1010: 1011: 1100: 1101: 111X: broadcast storm control Received packet length counted. Bandwidth table below These bits define bandwidth threshold that transmitted received packets over threshold discarded. Bandwidth table below 0000: none 0001: 64Kbps 0010: 128Kbps 0011: 256Kbps 0100: 512Kbps 0101: 1Mbps 0110: 2Mbps 0111: 4Mbps 1000: 8Mbps 1001: 16Mbps 1010: 32Mbps 1011: 48Mbps 1100: 64Mbps 1101: 72Mbps 1110: 80Mbps 1111: 88Mbps
CTRL
PE0,RW
Preliminary datasheet DM9003-15-DS-P05 April 2009
DM9003
2-port Switch with Processor Interface
6.35 Port Block Unicast Ports Control Register (68H) Name Default Description RESERVED PH0,RW Reserved BLK_UP PH0,RW Ports Unicast Packet Blocked received unicast packets forward assigned ports. Note: that assigned port definition: port port reserved, processor port. 6.36 Port Block Multicast Ports Control Register (69H) Name Default Description RESERVED PH0,RW Reserved BLK_MP PH0,RW Ports Multicast Packet Blocked received multicast packets forward assigned ports. 6.37 Port Block Broadcast Ports Control Register (6AH) Name Default Description RESERVED PH0,RW Reserved BLK_BP PH0,RW Ports Broadcast Packet Blocked received broadcast packets forward assigned ports. 6.38 Port Block Unknown Ports Control Register (6BH) Name Default Description RESERVED PH0,RW Reserved BLK_UKP PH0,RW Ports Unknown Packet Blocked packets with field found address table forward assigned ports.
6.39 Port Priority Queue Control Register (6DH) Name Default Description TAG_OUT PE0,RW Output Packet Tagging Enable transmitted packets containing VLAN tagged field. PRI_DIS PE0,RW Priority Queue Disable Only transmit queue supported this port. WFQUE PE0,RW Weighted Round-Robin Queuing priority weight queue respectively. queue highest priority, next priorities queue respectively. TOS_PRI PE0,RW Priority over VLAN packet with VLAN tag, priority this packet decode from field. TOS_OFF PE0,RW Priority Classification Disable priority information from field packet ignored. PRI_OFF PE0,RW 802.1 Priority Classification Disable priority information from VLAN field ignored.
Preliminary datasheet DM9003-15-DS-P05 April 2009
DM9003
2-port Switch with Processor Interface
P_PRI PE0,RW Port Base priority priority queue number port base. queue queue queue queue
6.40 Port VLAN Byte Register (6EH) Name Default VID70 PE01,RW VID[7:0] 6.41 Port VLAN High Byte Register (6FH) Name Default PE0,RW [15:13] PE0,RW Tag[12] VID118 PE0,RW VID[11:8]
Description
Description
6.42 Counter Port Index Register (80H) Name Default Description READY P0,RO counter data ready When this register written with INDEX data, this cleared counter reading progress. After read counter, data loaded into registers 81H~ this indicate that data ready, then data this INDEX cleared. reserved 0,RO Reserved INDEX PHS0,RW counter index 0~9, each counter 32-bit Register 81H~84H. Write counter index this register before read them. 6.43 Counter Data Registers (81H~84H) Register Name Default Description MIB_DAT X,RO counter Data Register MIB_DAT X,RO counter Data Register 8~15 MIB_DAT X,RO counter Data Register 16~23 MIB_DAT X,RO counter Data Register 24~31 counter: Byte Counter Registers (INDEX 00H) counter: Uni-cast Packet Counter Registers (INDEX 01H) counter: Multi-cast Packet Counter Registers (INDEX 02H) counter: Discard Packet Counter Registers (INDEX 03H) counter: Error Packet Counter Registers (INDEX 04H) counter: Byte Counter Registers (INDEX 05H) counter: Uni-cast Packet Counter Registers (INDEX 06H) counter: Multi-cast Packet Counter Registers (INDEX 07H) counter: Discard Packet Counter Registers (INDEX 08H) counter: Error Packet Counter Registers (INDEX 09H)
Preliminary datasheet DM9003-15-DS-P05 April 2009
DM9003
2-port Switch with Processor Interface
6.44 Port-Based VLAN Mapping Table Registers (B0H~BFH) Define port member VLAN group There VLAN group that defined Reg. B0H~BFH. Group defined Reg. B0H, group defined Reg. B1H, Name Default Description RESERVED PE0,RO Reserved PORT_UP PE1,RW Mapping processor RESERVED PE1,RW Reserved PORT_P1 PE1,RW Mapping port PORT_P0 PE1,RW Mapping port 6.45 Priority Registers (C0H~CFH) Define 6-bit 3-bit field mapping 2-bit priority queue number. 6-bit type, Reg. "1", Reg. [1:0] define mapping value Reg. [3:2] define mapping value till Reg. [7:6] define value 3-bit type, Reg. define mapping value Reg. [3:2] define mapping value till Reg. [7:6] define value Reg. C0H: Reg. C1H: Reg. C2H: Reg. C3H: Name TOSF TOSE TOSD TOSC Default PE0,RW PE0,RW PE0,RW PE0,RW Description Reg.53H. :TOS[7:2]=0FH Reg.53H. :TOS[7:2]=0EH Reg.53H. :TOS[7:2]=0DH Reg.53H. :TOS[7:2]=0CH
Name TOS3 TOS2 TOS1 TOS0
Default PE0/1,RW PE0,/1RW PE0,RW PE0,RW
Description Reg. 53H. :TOS[7:2]=03H, otherwise TOS]7:5]=03H Reg. 53H. :TOS[7:2]=02H, otherwise TOS]7:5]=02H Reg.53H. :TOS[7:2]=01H, otherwise TOS]7:5]=01H Reg.53H. :TOS[7:2]=00H, otherwise TOS]7:5]=00H
Name TOS7 TOS6 TOS5 TOS4
Default PE0/3,RW PE0/3,RW PE0/2,RW PE0/2,RW
Description Reg.53H. :TOS[7:2]=07H, otherwise TOS]7:5]=07H Reg.53H. :TOS[7:2]=06H, otherwise TOS]7:5]=06H Reg.53H. :TOS[7:2]=05H, otherwise TOS]7:5]=05H Reg.53H. :TOS[7:2]=04H, otherwise TOS]7:5]=04H
Name TOSB TOSA TOS9 TOS8
Default PE0,RW PE0,RW PE0,RW PE0,RW
Description Reg.53H. :TOS[7:2]=0BH Reg.53H. :TOS[7:2]=0AH Reg.53H. :TOS[7:2]=09H Reg.53H. :TOS[7:2]=08H
Preliminary datasheet DM9003-15-DS-P05 April 2009
DM9003
2-port Switch with Processor Interface
Reg. C4H: Reg. C5H: Reg. C6H: Reg. C7H: Reg. C8H: Reg. C9H: Name TOS27 TOS26 TOS25 TOS24 Default PE2,RW PE2,RW PE2,RW PE2,RW Description Reg.53H. :TOS[7:2]=27H Reg.53H. :TOS[7:2]=26H Reg.53H. :TOS[7:2]=25H Reg.53H. :TOS[7:2]=24H Name TOS23 TOS22 TOS21 TOS20 Default PE2,RW PE2,RW PE2,RW PE2,RW Description Reg.53H. :TOS[7:2]=23H Reg.53H. :TOS[7:2]=22H Reg.53H. :TOS[7:2]=21H Reg.53H. :TOS[7:2]=20H Name TOS1F TOS1E TOS1D TOS1C Default PE1,RW PE1,RW PE1,RW PE1,RW Description Reg.53H. :TOS[7:2]=1FH Reg.53H. :TOS[7:2]=1EH Reg.53H. :TOS[7:2]=1DH Reg.53H. :TOS[7:2]=1CH Name TOS1B TOS1A TOS19 TOS18 Default PE1,RW PE1,RW PE1,RW PE1,RW Description Reg.53H. :TOS[7:2]=1BH Reg.53H. :TOS[7:2]=1AH Reg.53H. :TOS[7:2]=19H Reg.53H. :TOS[7:2]=18H Name TOS17 TOS16 TOS15 TOS14 Default PE1,RW PE1,RW PE1,RW PE1,RW Description Reg.53H. :TOS[7:2]=17H Reg.53H. :TOS[7:2]=16H Reg.53H. :TOS[7:2]=15H Reg.53H. :TOS[7:2]=14H Name TOS13 TOS12 TOS11 TOS10 Default PE1,RW PE1,RW PE1,RW PE1,RW Description Reg.53H. :TOS[7:2]=13H Reg.53H. :TOS[7:2]=12H Reg.53H. :TOS[7:2]=11H Reg.53H. :TOS[7:2]=10H
Preliminary datasheet DM9003-15-DS-P05 April 2009
DM9003
2-port Switch with Processor Interface
Reg. CAH: Reg. CBH: Name TOS2F TOS2E TOS2D TOS2C Default PE2,RW PE2,RW PE2,RW PE2,RW Description Reg.53H. :TOS[7:2]=2FH Reg.53H. :TOS[7:2]=2EH Reg.53H. :TOS[7:2]=2DH Reg.53H. :TOS[7:2]=2CH Name TOS2B TOS2A TOS29 TOS28 Default PE2,RW PE2,RW PE2,RW PE2,RW Description Reg.53H. :TOS[7:2]=2BH Reg.53H. :TOS[7:2]=2AH Reg.53H. :TOS[7:2]=29H Reg.53H. :TOS[7:2]=28H
Reg. CCH: Reg. CDH: Reg. CEH: Reg. CFH: Name TOS3F TOS3E TOS3D TOS3C Default PE3,RW PE3,RW PE3,RW PE3,RW Description Reg.53H. :TOS[7:2]=3FH Reg.53H. :TOS[7:2]=3EH Reg.53H. :TOS[7:2]=3DH Reg.53H. :TOS[7:2]=3CH Name TOS3B TOS3A TOS39 TOS38 Default PE3,RW PE3,RW PE3,RW PE3,RW Description Reg.53H. :TOS[7:2]=3BH Reg.53H. :TOS[7:2]=3AH Reg.53H. :TOS[7:2]=39H Reg.53H. :TOS[7:2]=38H Name TOS37 TOS36 TOS35 TOS34 Default PE3,RW PE3,RW PE3,RW PE3,RW Description Reg.53H. :TOS[7:2]=37H Reg.53H. :TOS[7:2]=36H Reg.53H. :TOS[7:2]=35H Reg.53H. :TOS[7:2]=34H Name TOS33 TOS32 TOS31 TOS30 Default PE3,RW PE3,RW PE3,RW PE3,RW Description Reg.53H. :TOS[7:2]=33H Reg.53H. :TOS[7:2]=32H Reg.53H. :TOS[7:2]=31H Reg.53H. :TOS[7:2]=30H
Preliminary datasheet DM9003-15-DS-P05 April 2009
DM9003
2-port Switch with Processor Interface
6.46 VLAN Priority Registers (D0H~D1H) Define 3-bit priority field VALN mapping 2-bit priority queue number. Reg. D0H: Name TAG3 TAG2 TAG1 TAG0 Reg. D1H: Name TAG7 TAG6 TAG5 TAG4 Default PE1,RW PE1,RW PE0,RW PE0,RW Default PE3,RW PE3,RW PE2,RW PE2,RW Description VLAN priority value VLAN priority value VLAN priority value VLAN priority value Description VLAN priority value VLAN priority value VLAN priority value VLAN priority value
6.47 Memory Data Pre-Fetch Read Command without Address Increment Register (F0H) Name Default Description MRCMDX X,RO Read data from SRAM. After read this command, read pointer internal SRAM unchanged. DM9003 starts pre-fetch SRAM data internal data buffers. 6.48 Memory Data Read Command with Address Increment Register (F2H) When register "0", register value will returned 0000H, 16K-byte boundary reached. When register "1", register value will returned 0000H, processor port receive memory byte boundary address memory size, defined register with default 1F00H, reached. Name Default Description MRCMD X,RO Read data from SRAM. After read this command, read pointer increased 1,2, depends operator mode (8-bit,16-bit 32-bit respectively) 6.49 Memory Data Read Address Register (F4H) When register "0", register used memory byte address read internal 64K-byte memory. When register "1", register used processor port receive memory byte address with memory space range from memory size defined register with default 1EFFH. Name Default Description MDRAL PHS0,RW Memory Data Read Address Byte[7:0] 6.50 Memory Data Read Address Register (F5H) Name Default Description MDRAH50 PHS0,RW Memory Data Read Byte Address High Byte[15:8] 6.51 Memory Data Write Command without Address Increment Register (F6H) Name Default Description MWCMDX X,WO Write data SRAM. After write this command, write pointer unchanged
Preliminary datasheet DM9003-15-DS-P05 April 2009
DM9003
2-port Switch with Processor Interface
6.52 Memory Data Write Command with Address Increment Register (F8H) When register "0", register value will returned 0000H, 16K-byte boundary reached. Name Default Description MWCMD X,WO Write Data SRAM After write this command, write pointer increased depends operator mode. (8-bit, 16-bit,32-bit respectively) 6.53 Memory Data Write Address Register (FAH) When register "0", register used memory byte address write internal 64K-byte memory. When register "1", register reserved. processor port transmit memory address generated DM9003 automatically. Name Default Description MDWAL PHS0,RW Memory Data Write_ address Byte[7:0] 6.54 Memory Data Write Address Register (FBH) Name Default Description MDWAH PHS0,RW Memory Data Write Byte Address High Byte[15:8] 6.55 Packet Length Registers (FCH~FDH) Name Default TXPLH PHS0,RW Packet Length High byte TXPLL PHS0,RW Packet Length byte 6.56 Interrupt Status Register (FEH) Name Default IOMODE RESERVED LNKCHG CNT_ERR PHS0,RO PHS0,RW/C1 PHS0,RW/C1 PHS0,RW/C1 PHS0,RW/C1 PHS0,RW/C1 PHS0,RW/C1
Description
Description Width Processor Data 16-bit mode 8-bit mode Reserved Link Status Change port Memory Management error Receive Overflow Counter Overflow Receive Overflow Packet Transmitted Packet Received
6.57 Interrupt Mask Register (FFH) Name Default TXRX_EN PHS0,RW RESERVED P0,RO LNKCHGI PHS0,RW CNT_ERR PHS0,RW/C1 ROOI PHS0,RW PHS0,RW PHS0,RW PHS0,RW
Description Enable SRAM read/write pointer used transmit /receive address. Reserved Enable Link Status Change port 1Interrupt Enable Memory Management error interrupt Enable Receive Overflow Counter Overflow Interrupt Enable Receive Overflow Interrupt Enable Packet Transmitted Interrupt Enable Packet Received Interrupt
Preliminary datasheet DM9003-15-DS-P05 April 2009
DM9003
2-port Switch with Processor Interface EEPROM FORMAT
name address Auto Load Control Word Description byte Ethernet Address 1:0=01: Update vendor product 3:2=01: Accept setting WORD6 [4:0] 5:4= reserved 7:6= reserved, application 9:8=Reserved 11:10= Reserved, application 13:12= Reserved 15:14=01: Accept setting WORD7 [15:12] 2-byte vendor (Default: 0A46H) 2-byte product (Default: 9003H) When word [3:2] =01, these bits control CS#, IOR#, IOW# pins polarity. Bit0: active high when (default active low) Bit1: IOR# active high when (default: active low) Bit2: IOW# active high when (default: active low) Bit3: active when (default: active high) Bit4: open-collected (default: force output) 15:5: Reserved Bit11:0: reserved 13:12 reserved, application Bit14: Port AUTO-MDIX control OFF(default Bit15: Port AUTO-MDIX control OFF(default Reserved 1:0=01: Accept setting WORD 17,18 3:2=01: Accept setting WORD 19~26 5:4=01: Accept setting WORD 27~30 7:6=01: Accept setting WORD 9:8=01: Accept setting WORD 32~39 11:10=01: Accept setting WORD 40~47 15:12 Reserved, 0000 application When word "01", after power reset: This word will loaded Reg. This word 15~8 will loaded Reg. When word "01", after power reset: This word will loaded Reg. This word 15~8 will loaded Reg. When word "01", after power reset: This word will loaded port Reg. This word 15~8 will loaded port Reg. When word "01", after power reset: This word will loaded port Reg. This word 15~8 will loaded port Reg. When word "01", after power reset: This word will loaded port Reg. This word 15~8 will loaded port Reg.
Preliminary datasheet DM9003-15-DS-P05 April 2009
Vendor Product control
control
RESERVED Control
8~15
Switch Control
Switch Control
Port Control
Port Control
Port Control
DM9003
2-port Switch with Processor Interface
Port Control When word "01", after power reset: This word will loaded port Reg. This word 15~8 will loaded port Reg. Reserved When word "01", after power reset: This word will loaded port Reg. This word 15~8 will loaded port Reg. When word "01", after power reset: This word will loaded port Reg. This word 15~8 will loaded port Reg. When word "01", after power reset: This word will loaded port Reg. This word 15~8 will loaded port Reg. When word "01", after power reset: This word will loaded port Reg. This word 15~8 will loaded port Reg. Reserved When word "01", after power reset: This word will loaded port Reg. This word 15~8 will loaded port Reg. When word "01", after power reset: This word will loaded Reg. This word 15~8 will loaded Reg. When word "01", after power reset: This word will loaded Reg. This word 15~8 will loaded Reg. When word "01", after power reset: This word will loaded Reg. This word 15~8 will loaded Reg. When word "01", after power reset: This word will loaded Reg. This word 15~8 will loaded Reg. When word "01", after power reset: This word will loaded Reg. This word 15~8 will loaded Reg. When word "01", after power reset: This word will loaded Reg. This word 15~8 will loaded Reg. When word "01", after power reset: This word will loaded Reg. This word 15~8 will loaded Reg. When word "01", after power reset: This word will loaded Reg. This word 15~8 will loaded Reg. When word "01", after power reset: This word will loaded Reg. This word 15~8 will loaded Reg. When word 11:10 "01", after power reset: This word will loaded Reg.
RESERVED Port Control
23~24
Port Control
Port VLAN
Port VLAN
RESERVED Port VLAN
VLAN Priority
Port VLAN Group Port VLAN Group Port VLAN Group Port VLAN Group Port VLAN Group Port VLAN Group 10,11 Port VLAN Group 12,13 Port VLAN Group 14,15 Priority
Preliminary datasheet DM9003-15-DS-P05 April 2009
DM9003
2-port Switch with Processor Interface
Priority This word 15~8 will loaded Reg. When word 11:10 "01", after power reset: This word will loaded Reg. This word 15~8 will loaded Reg. When word 11:10 "01", after power reset: This word will loaded Reg. This word 15~8 will loaded Reg. When word 11:10 "01", after power reset: This word will loaded Reg. This word 15~8 will loaded Reg. When word 11:10 "01", after power reset: This word will loaded Reg. This word 15~8 will loaded Reg. When word 11:10 "01", after power reset: This word will loaded Reg. This word 15~8 will loaded Reg. When word 11:10 "01", after power reset: This word will loaded Reg. This word 15~8 will loaded Reg. When word 11:10 "01", after power reset: This word will loaded Reg. This word 15~8 will loaded Reg. application
Priority
Priority
Priority
Priority
Priority
Priority
RESERVED
Preliminary datasheet DM9003-15-DS-P05 April 2009
DM9003
2-port Switch with Processor Interface REGISTERS Register Description
Name CONTR Reset Loop Speed Auto-N Power Isolate Restart Full back select Enable Down Auto-N Duplex STATU Reserved Cap. Cap. Cap. Cap. Cap. 0000 PHYID1 PHYID2 OUI_LSB 101110 Auto-Ne Advertis Link Part. Ability Auto-Ne Expansi Specifi Config. Specifi Conf/Sta Conf/Sta PWDO Specifie config RCVER DIS_con nect PSCR Next Remote Page Fault Next Page Reserved Reserved Coll. Test Reserved 000_0000 Pream. Auto-N Remote Auto-N Link Supr. Compl. Fault Cap. Status
Jabber Detect
Extd Cap.
VNDR_MDL 001011
MDL_REV 0000 Advertised Protocol Selector Field
Reserved
Link Partner Protocol Selector Field Pardet Next Next Fault Able Able AutoN Cap.
4B5B Rsvd
Enable
BP_AD Reserv ALIGN
Force Rsvd. Reserv RMII mode 100LNK
RPDCT Reset Pream. R-EN Supr.
Sleep Remote mode LoopOut
Reserv Revers Revers Serial
ADDR [4:0]
Auto-N. Monitor [3:0]
SQUE Enable Enable Enable Reserved
Reserved
Polarity Reverse
PD10D PD100l PDchip PDcrm PDaeq PDdrv PDecli PDeclo PD10 TSTSE TSTSE FORCE FORCE PREA TX10M NWAY Reserv MDIX_ AutoNe Mdix_fix Mdix_d MonSel MonSel Reserv PD_val _TXSD _FEF MBLEX _PWR _PWR CNTL g_dlpbk Value Receiver Error Counter Reversed Reversed PREA AMPLIT TX_P MBLE Disconnect_counter Reversed
Default register description that follows, default column takes form: <Reset Value>, <Access Type> <Attribute(s)> Where: <Reset Value>: logic logic zero default value
<Access Type>: Read only, Read/Write <Attribute (s)>: Self clearing, Value permanently
Preliminary datasheet DM9003-15-DS-P05 April 2009
DM9003
2-port Switch with Processor Interface
Basic Mode Control Register (BMCR) Name Reset Default Description RW/SC Reset 1=Software reset 0=Normal operation This sets status controls registers their default states. This bit, which self-clearing, will keep returning value until reset process completed Loopback Loop-back control register Loop-back enabled Normal operation When 100Mbps operation mode, setting this cause descrambler lose synchronization produce 720ms "dead time" before valid data appears receive outputs Speed Select 100Mbps 10Mbps Link speed selected either this auto-negotiation. When auto-negotiation enabled set, this will return auto-negotiation selected medium type Auto-negotiation Enable Auto-negotiation enabled, will auto-negotiation status Power Down While power-down state, should respond management transactions. During transition power-down state while power-down state, should generate spurious signals 1=Power down 0=Normal operation 0,RW Isolate Force application. 0,RW/SC Restart Auto-negotiation Restart auto-negotiation. Re-initiates auto-negotiation process. When auto-negotiation disabled (bit this register cleared), this function should cleared. This self-clearing will keep returning value until auto-negotiation initiated DM9003. operation auto-negotiation process will affected management entity that clears this Normal operation 1,RW Duplex Mode Full duplex operation. Duplex selection allowed when Auto-negotiation disabled (bit this register cleared). With auto-negotiation enabled, this reflects duplex capability selected auto-negotiation Normal operation
Preliminary datasheet DM9003-15-DS-P05 April 2009
Loopback
Speed selection
Auto-negotiation enable Power down
Isolate Restart Auto-negotiation
Duplex mode
DM9003
2-port Switch with Processor Interface
Collision test 0,RW Collision Test Collision test enabled. When set, this will cause signal asserted response assertion TX_EN internal interface. Normal operation Reserved Read ignore write
Reserved
0,RO
Basic Mode Status Register (BMSR) Name 100BASE-T4 Default 0,RO/P Description 100BASE-T4 Capable DM9003 able perform 100BASE-T4 mode DM9003 able perform 100BASE-T4 mode 100BASE-TX Full Duplex Capable DM9003 able perform 100BASE-TX full duplex mode DM9003 able perform 100BASE-TX full duplex mode 100BASE-TX Half Duplex Capable DM9003 able perform 100BASE-TX half duplex mode DM9003 able perform 100BASE-TX half duplex mode 10BASE-T Full Duplex Capable DM9003 able perform 10BASE-T full duplex mode DM9003 able perform 10BASE-TX full duplex mode 10BASE-T Half Duplex Capable DM9003 able perform 10BASE-T half duplex mode DM9003 able perform 10BASE-T half duplex mode Reserved Read ignore write Frame Preamble Suppression will accept management frames with preamble suppressed will accept management frames with preamble suppressed Auto-negotiation Complete Auto-negotiation process completed Auto-negotiation process completed Remote Fault Remote fault condition detected (cleared read chip reset). Fault criteria detection method DM9003 implementation specific. This will after ANLPAR (bit register address remote fault condition detected Auto Configuration Ability DM9003 able perform auto-negotiation DM9003 able perform auto-negotiation Link Status Valid link established (for either 10Mbps 100Mbps operation) Link established link status implemented with latching function, that
100BASE-TX full-duplex 100BASE-TX half-duplex
1,RO/P
1,RO/P
10BASE-T full-duplex 10BASE-T half-duplex Reserved preamble suppression
1,RO/P
1,RO/P
10-7
0,RO 1,RO
Auto-negotiation Complete Remote fault
0,RO
Auto-negotiation ability Link status
1,RO/P
0,RO
Preliminary datasheet DM9003-15-DS-P05 April 2009
DM9003
2-port Switch with Processor Interface
occurrence link failure condition causes link status cleared remain cleared until read management interface Jabber Detect Jabber condition detected jabber This implemented with latching function. Jabber conditions will this unless cleared read this register through management interface DM9003 reset. This works only 10Mbps mode Extended Capability Extended register capable Basic register capable only
Jabber detect
Extended capability
1,RO/P
Identifier Register (PHYID1) Identifier Registers work together single identifier DM9003. Identifier consists concatenation Organizationally Unique Identifier (OUI), vendor's model number, model revision number. DAVICOM Semiconductor's IEEE assigned 00606E. 15-0 Name OUI_MSB Default <0181H> Description Most Significant Bits This register stores (00606E) this register respectively. most significant bits ignored (the IEEE standard refers these
Identifier Register (PHYID2) 15-10 Name OUI_LSB Default <101110>, RO/P <001011>, RO/P <0000>, RO/P Description Least Significant Bits (00606E) mapped this register respectively Vendor Model Number Five bits vendor model number mapped (most significant Model Revision Number Five bits vendor model revision number mapped (most significant
VNDR_MDL
MDL_REV
Auto-negotiation Advertisement Register (ANAR) This register contains advertised abilities this DM9003 device they will transmitted link partner during Auto-negotiation. Name Default 0,RO/P Description Next page Indication Next page available next page available DM9003 next page, this permanently Acknowledge Link partner ability data reception acknowledged
Preliminary datasheet DM9003-15-DS-P05 April 2009
0,RO
DM9003
2-port Switch with Processor Interface
acknowledged DM9003's auto-negotiation state machine will automatically control this outgoing bursts appropriate time during auto-negotiation process. Software should attempt write this bit. Remote Fault Local device senses fault condition fault detected Reserved Write ignore read Flow Control Support Controller chip supports flow control ability Controller chip doesn't support flow control ability RO/P 100BASE-T4 Support 100BASE-T4 supported local device 100BASE-T4 supported DM9003 does support 100BASE-T4 this permanently 100BASE-TX Full Duplex Support 100BASE-TX full duplex supported local device 100BASE-TX full duplex supported 100BASE-TX Support 100BASE-TX half duplex supported local device 100BASE-TX half duplex supported 10BASE-T Full Duplex Support 10BASE-T full duplex supported local device 10BASE-T full duplex supported 10BASE-T Support 10BASE-T half duplex supported local device 10BASE-T half duplex supported <00001>, Protocol Selection Bits These bits contain binary encoded protocol selector supported this node <00001> indicates that this device supports IEEE 802.3 CSMA/CD
12-11
Reserved
TX_FDX
TX_HDX
10_FDX
10_HDX
Selector
Auto-negotiation Link Partner Ability Register (ANLPAR) This register contains advertised abilities link partner when received during Auto-negotiation. Name Default Description Next Page Indication Link partner, next page available Link partner, next page available Acknowledge Link partner ability data reception acknowledged acknowledged DM9003's auto-negotiation state machine will automatically control this from incoming bursts. Software should attempt write this Remote Fault
Preliminary datasheet DM9003-15-DS-P05 April 2009
DM9003
2-port Switch with Processor Interface
12-11 Reserved Remote fault indicated link partner remote fault indicated link partner Reserved Read ignore write Flow Control Support Controller chip supports flow control ability link partner Controller chip doesn't support flow control ability link partner 100BASE-T4 Support 100BASE-T4 supported link partner 100BASE-T4 supported link partner 100BASE-TX Full Duplex Support 100BASE-TX full duplex supported link partner 100BASE-TX full duplex supported link partner 100BASE-TX Support 100BASE-TX half duplex supported link partner 100BASE-TX half duplex supported link partner 10BASE-T Full Duplex Support 10BASE-T full duplex supported link partner 10BASE-T full duplex supported link partner 10BASE-T Support 10BASE-T half duplex supported link partner 10BASE-T half duplex supported link partner <00000>, Protocol Selection Bits Link partner's binary encoded protocol selector
TX_FDX
TX_HDX
10_FDX
10_HDX
Selector
Auto-negotiation Expansion Register (ANER) 15-5 Name Reserved Default RO/LH Description Reserved Read ignore write Local Device Parallel Detection Fault fault detected parallel detection function. fault detected parallel detection function Link Partner Next Page Able LP_NP_ABLE Link partner, next page available LP_NP_ABLE Link partner, next page Local Device Next Page Able NP_ABLE DM9003, next page available NP_ABLE DM9003, next page DM9003 does support this function, this always Page Received link code word page received. This will automatically cleared when register (register read management Link Partner Auto-negotiation Able this indicates that link partner supports Auto-negotiation
LP_NP_ABLE
NP_ABLE
0,RO/P
PAGE_RX
LP_AN_ABLE
Preliminary datasheet DM9003-15-DS-P05 April 2009
DM9003
2-port Switch with Processor Interface
DAVICOM Specified Configuration Register (DSCR) Name Default Description BP_4B5B 0,RW Bypass 4B5B Encoding 5B4B Decoding 4B5B encoder 5B4B decoder function bypassed Normal 4B5B 5B4B operation BP_SCR Bypass Scrambler/Descrambler Function Scrambler descrambler function bypassed Normal scrambler descrambler operation BP_ALIGN Bypass Symbol Alignment Function Receive functions (descrambler, symbol alignment symbol decoding functions) bypassed. Transmit functions (symbol encoder scrambler) bypassed Normal operation BP_ADPOK BYPASS ADPOK Force signal detector (SD) active. This register debug only, release customer Forced Normal operation Reserved Reserved Force application 100BASE-TX Mode Control 100BASE-TX operation 100BASE-FX operation Reserved Reserved Reserved Reserved F_LINK_100 Force Good Link 100Mbps Force 100Mbps good link status Normal 100Mbps operation This useful diagnostic purposes Reserved Reserved Force application. COL_LED Control (valid test mode) RPDCTR-EN Reduced Power Down Control Enable This used enable automatic reduced power down Enable automatic reduced power down Disable automatic reduced power down SMRST Reset State Machine When writes this bit, state machines will reset. This self-clear after reset completed MFPSC Preamble Suppression Control frame preamble suppression control preamble suppression preamble suppression SLEEP Sleep Mode Writing this will cause entering Sleep mode power down circuit except oscillator clock generator circuit. When waking from Sleep mode (write this configuration will back state before sleep; state machine will reset
Preliminary datasheet DM9003-15-DS-P05 April 2009
DM9003
2-port Switch with Processor Interface
RLOUT Remote Loop Control When this received data will loop transmit channel. This useful error rate testing
DAVICOM Specified Configuration Status Register (DSCSR) Name Default Description 100FDX 100M Full Duplex Operation Mode After auto-negotiation completed, results will written this bit. this means operation mode 100M full duplex mode. software read [15:12] which mode selected after auto-negotiation. This invalid when auto-negotiation mode 100HDX 100M Half Duplex Operation Mode After auto-negotiation completed, results will written this bit. this means operation mode 100M half duplex mode. software read [15:12] which mode selected after auto-negotiation. This invalid when auto-negotiation mode 10FDX Full Duplex Operation Mode After auto-negotiation completed, results will written this bit. this means operation mode Full Duplex mode. software read [15:12] which mode selected after auto-negotiation. This invalid when auto-negotiation mode 10HDX Half Duplex Operation Mode After auto-negotiation completed, results will written this bit. this means operation mode half duplex mode. software read [15:12] which mode selected after auto-negotiation. This invalid when auto-negotiation mode Reserved Reserved Read ignore write Reserved 0,RW Reserved Reserved 0,RW Reserved PHYADR[4:0] Address first address transmitted received address (bit station management entity connected multiple entities must know appropriate address each ANMB[3:0] Auto-negotiation Monitor Bits These bits debug only. auto-negotiation status will written these bits. IDLE state Ability match Acknowledge match Acknowledge match fail Consistency match Consistency match fail Parallel detects signal link ready Parallel detects signal link ready fail Auto-negotiation completed successfully
Preliminary datasheet DM9003-15-DS-P05 April 2009
DM9003
2-port Switch with Processor Interface
8.10 10BASE-T Configuration/Status (10BTCSR) Name Reserved LP_EN Default Description Reserved Read ignore write Link Pulse Enable Transmission link pulses enabled Link pulses disabled, good link condition forced This valid only 10Mbps operation Heartbeat Enable Heartbeat function enabled Heartbeat function disabled When DM9003 configured full duplex operation, this will ignored (the collision/heartbeat function invalid full duplex mode) Squelch Enable Normal squelch squelch Jabber Enable Enables disables Jabber function when DM9003 10BASE-T full duplex 10BASE-T transceiver Loopback mode Jabber function enabled Jabber function disabled Serial Mode (valid test mode) Force application. Reserved Read ignore write Polarity Reversed When this indicates that 10Mbps cable polarity reversed. This automatically cleared 10BASE-T module
1,RW
SQUELCH
JABEN
SERIAL Reserved POLR
8.11 Power Down Control Register (PWDOR) Description Reserved Read ignore write PD10DRV Vendor power down control test PD100DL Vendor power down control test PDchip Vendor power down control test PDcrm Vendor power down control test PDaeq Vendor power down control test PDdrv Vendor power down control test PDedi Vendor power down control test PDedo Vendor power down control test PD10 Vendor power down control test When selected, power down value control Register 20.0 15-9 Name Reserved Default
Preliminary datasheet DM9003-15-DS-P05 April 2009
DM9003
2-port Switch with Processor Interface
8.12 (Specified config) Register Name Default TSTSE1 0,RW TSTSE2 0,RW FORCE_TXSD 0,RW Description Vendor test select control Vendor test select control Force Signal Detect force signal 100M normal signal. Vendor test select control Preamble Saving Control when set, 10BASE-T transmit preamble count reduced. When register set, 12-bit preamble reduced; otherwise 22-bit preamble reduced. transmit preamble count normal 10BASE-T mode 10BASE-T mode Transmit Power Saving Control enable transmit power saving 10BASE-T mode disable transmit power saving 10BASE-T mode Auto-negotiation Power Saving Control disable power saving during auto-negotiation period enable power saving during auto-negotiation period Reserved
FORCE_FEF PREAMBLEX
0,RW 0,RW
TX10M_PWR
1,RW
NWAY_PWR
0,RW
Reserved MDIX_CNTL
Read ignore write MDI/MDIX,RO polarity MDI/MDIX value MDIX mode mode AutoNeg_dpbk 0,RW Auto-negotiation Loopback test internal digital auto-negotiation Loopback normal. Mdix_fix Value MDIX_CNTL force value: When Mdix_down MDIX_CNTL value depend register value. Mdix_down 0,RW MDIX Down Manual force MDI/MDIX. Enable Auto-MDIX Disable Auto-MDIX MDIX_CNTL value depend Reg.14H.bit5 MonSel1 0,RW Vendor monitor select MonSel0 0,RW Vendor monitor select Reserved 0,RW Reserved Force application. PD_value 0,RW Power down control value Decision value each field Reg.13H. power down normal
Preliminary datasheet DM9003-15-DS-P05 April 2009
DM9003
2-port Switch with Processor Interface
8.13 DAVICOM Specified Receive Error Counter Register (RECR) 15-0 Name Rcv_ Err_ Default Description Receive Error Counter Receive error counter that increments upon detection RXER. Clean reading this register.
8.14 DAVICOM Specified Disconnect Counter Register (DISCR) 15-8 Name Reserved Disconnect Counter Default Description Reserved Disconnect Counter that increment upon detection disconnection. Clean reading this register.
8.15 Power Saving Control Register (PSCR) 15-12 Name RESERVED PREAMBLEX Default 0,RO 0,RW Description RESERVED Preamble Saving Control when both register set, 10BASE-T transmit preamble count reduced. 12-bit preamble reduced. 22-bit preamble reduced. Transmit Amplitude Control Disabled when cable unconnected with link partner, amplitude reduced power saving. disable Transmit amplitude reduce function Transmit Power Saving Control Disabled when cable unconnected with link partner, driving current transmit reduced power saving. disable transmit driving power saving function RESERVED
AMPLITUDE
0,RW
TX_PWR
0.RW
RESERVED
0,RO
Preliminary datasheet DM9003-15-DS-P05 April 2009
DM9003
2-port Switch with Processor Interface FUNCTIONAL DESCRIPTION
Processor memory management function: When cleared, there 64K9.1.1 Processor Interface byte memory space DM9003 accessed. general processor mode, chip selection This configured type internal memory used just coming from CS#. There only testing only. memory write address (register addressing ports through access host FAh/FBh) memory read address (register interface. F4h/F5h) represent physical memory address port INDEX port other DM9003 internal memory. noted that after DATA port. INDEX port decoded memory been written memory write command, pin=0 DATA pin=1. contents switch reset command (bit register 52h) INDEX port register address should before normal switch function operation, DATA port. Before access register, since controlled data internal memory address register must saved INDEX corrupted. port before. 9.1.2 Direct Memory Access Control DM9003 provides capability simplify access internal memory. After setting starting address internal memory then issuing dummy read/write command load current data internal data buffer, desired location internal memory accessed read/write command registers. memory's address will increased with size equal current operation mode (i.e. byte word mode) data next location will loaded internal data buffer automatically. noted that data first access (the dummy read/write command) sequential burst should ignored because that data contents last read/write command. There configured types internal memory which controlled IMR. When set, internal memory used transmit receive buffers. transmit buffer occupies bytes. receive buffer occupies 7.75K bytes. Both transmit receive buffer address need programmed instead that they managed DM9003 automatically. transmit function, after power reset each time after transmit command issued (bit set), next starting transmit buffer address loaded. receive function, 7.75K-byte receive buffer treated continued logic memory space. memory address will wrap address address reached.
9.1.3 Packet Transmission There packets, sequentially named index index stored SRAM same time. index register controls insertion CRC. start address transmission current packet index after software hardware reset. Firstly write data SRAM using port then write byte count byte count register index register 0fch 0fdh. control register. DM9003 starts transmit index packet. Before transmission index packet ends, data next (index packet moved SRAM. After index packet ends transmission, write byte count data index BYTE_COUNT register then control register transmit index packet. following packets, named index same transmitted. 9.1.4 Packet Reception SRAM ring data structure. Each packet 4-byte header followed with data reception packet which field included. format 4-byte header 01h, status, BYTE_COUNT low, BYTE_COUNT high. noted that start address each packet proper address boundary which depends operation mode (byte word mode).
Preliminary datasheet DM9003-15-DS-P05 April 2009
DM9003
2-port Switch with Processor Interface
Switch function: 9.2.1 Address Learning DM9003 self-learning mechanism learning addresses incoming packets real time. DM9003 stores addresses, port number time stamp information Hash-based Address Table. learn unicast address entry. switch engine updates address table with entry incoming packet's Source Address (SA) does exist incoming packet valid (non-error legal length). Besides, DM9003 option disable address learning individual port. This feature register 9.2.2 Address Aging time stamp information address table used aging process. switch engine updates time stamp whenever corresponding receives. switch engine would delete entry time stamp updated period time. period programmed disabled through register 52h. 9.2.3 Packet Forwarding DM9003 forwards incoming packet according following decision: (1). Multicast/Broadcast, packet forwarded ports, except port which packet received. (2). Switch engine would look address table based when incoming packets UNICAST. found address table, packet treated multicast packet forward other ports. found destination port number different source port number, packet forward destination port. (3). Switch engine also look VLAN, Port Monitor setting other forwarding constraints forwarding decision, more detail will discuss later sections. DM9003 will filter incoming packets under following conditions: (1). Error packets, including errors, alignment errors, illegal size errors. (2). PAUSE packets. (3). incoming packet UNICAST
Preliminary datasheet DM9003-15-DS-P05 April 2009
destination port number equal source port number. 9.2.4 Inter-Packet (IPG) idle time between valid packets same port. typical number bits time. other word, value 9.6u 10Mbps 960n 100Mbps. 9.2.5 Back-off Algorithm DM9003 implements binary exponential back-off algorithm half-duplex mode compliant IEEE standard 802.3. 9.2.6 Late Collision Late Collision type collision. collision error occurs after first times data transmitted, packet dropped. 9.2.7 Half Duplex Flow Control DM9003 supports IEEE standard 802.3x flow control frames both transmit receive sides. receive side, DM9003 will defer transmitting next normal frames, receives pause frame from link partner. transmit side, DM9003 issues pause frame with maximum pause time when internal resources such received buffers, transmit queue transmit descriptor ring unavailable. Once resources available, DM9003 sends pause frame with zero pause time allows traffic resume immediately. 9.2.8 Full Duplex Flow Control DM9003 supports half-duplex backpressure. inducement same full duplex mode. When flow control required, DM9003 sends pattern, thus forcing collision. flow control ability register 61h. 9.2.9 Partition Mode DM9003 provides partition mode each port, register 61h. port enters partition mode when more than consecutive collisions occurred. partition mode port continuous transmit will receive. port returned normal operation mode when good
DM9003
2-port Switch with Processor Interface
packet seen wire. detail description partition mode represent following: (1). Entering Partition State port will enter Partition State when either following conditions occurs: port detects collision every consecutive re-transmit attempts same packet. port detects single collision which occurs more than times. Transmit defer timer time out, which indicates transmitting packet deferred long. (2). While Partition state: port will continue transmit pending packet, regardless collision detection, will allow usual Back-off Algorithm. Additional packets pending transmission will transmitted, while ignoring internal collision indication. This frees ports transmit buffers which would otherwise filled expense other ports buffers. assumption that partition signifying system failure situation (bad connection/cable/station), thus dropping packets small price cost halting switch buffer full condition. (3). Exiting from Partition State Port exits from Partition State, following successful packet transmission. successful packet transmission defined collisions were detected first bits transmission. 9.2.10 Broadcast Storm Filtering DM9003 option limit traffic broadcast multicast packets, protect switch from lower bandwidth availability. There type broadcast storm control, throttling broadcast packet only, other includes multicast. This feature through register 61h. broadcast storm threshold programmed EEPROM register 67h, default setting broadcast storm protecting. 9.2.11 Bandwidth Control DM9003 supports type bandwidth control each port. ingress egress bandwidth rate control separately, other combined together, this function through
register 61h. bandwidth control disabled default. separated bandwidth control mode, threshold rate defined register 66h. combined mode, defined register 67h. behavior bandwidth control below: (1).For ingress control, flow control function enabled, Pause packet will transmitted. ingress packets will dropped flow control disabled. (2).For egress control, egress port will transmit packets. other hand, ingress bandwidth source port will throttled that prevent packets from forwarding. (3).In combined mode, ingress egress bandwidth over threshold, bandwidth will throttled. 9.2.12 Port Monitoring Support DM9003 supports "Port Monitoring" function port base, detail below: (1). Sniffer Port Monitor Port There only port selected "sniffer port" register 52h, multiple ports "receive monitor port" "transmit monitor port" per-port register 65h. (2).Receive monitor packets received "receive monitor port" send copy "sniffer port". example, port "receive monitor port" port (processor port) selected "sniffer port". packet received form port destined port after forwarding decision, DM9003 will forward port processor port end. (3).Transmit monitor packets transmitted "transmit monitor port" send copy "sniffer port". example, port "transmit monitor port" processor port selected "sniffer port". packet received from port predestined port after forwarding decision, DM9003 will forward port processor port end. (4).Exception DM9003 optional setting that broadcast/multicast packets monitored (see register 65h). It's useful avoid unnecessary bandwidth.
Preliminary datasheet DM9003-15-DS-P05 April 2009
DM9003
2-port Switch with Processor Interface
9.2.13 VLAN Support 9.2.13.1 Port-Based VLAN DM9003 supports port-based VLAN default, groups. Each port default called PVID (Port VID, register 6Fh). DM9003 used 4-bytes PVID index mapped register B0h~BFh, define VLAN groups. 9.2.13.2 802.1Q-Based VLAN Regarding IEEE 802.1Q standard, Tag-based VLAN uses extra identify VLAN membership frame across VLAN-aware switch/router. tagged frame four bytes longer than untagged frame contains bytes TPID (Tag Protocol Identifier) bytes (Tag Control Information).
Dest.
Src.
Length/Type
Data
Standard frame
Dest.
Src.
TPID
0x8100 bytes
Length Type
Data
Tagged frame
Priority
bits
bits bits port. DM9003 will remove from DM9003 also supports 802.1Q-based packet recalculate before sending out. VLAN groups, specified register 53h. It's (3). Receive untagged packet forward obvious that tagged packets assigned port. several different VLANs which determined DM9003 will insert PVID when according inside VLAN Tag. Therefore, untagged packet enters port, recalculate operation similar port-based VLAN. before delivering DM9003 used 4-bytes received packet (4). Receive tagged packet forward with VLAN VLAN Group Mapping Register port. (B0h~BFh) configure VLAN partition. Received packet will forward destination port destination port received packet same VLAN without modification. group with received port, will discarded.
9.2.13.3 Tag/Untag User define each port port Un-tag port register 802.1Q-based VLAN mode. operation Un-tag explain below conditions: (1). Receive untagged packet forward Un-tag port. Received packet will forward destination port without modification. (2). Receive tagged packet forward Un-tag
Preliminary datasheet DM9003-15-DS-P05 April 2009
9.2.14 Priority Support DM9003 supports Quality Service (QoS) mechanism multimedia communication such VoIP video conferencing. DM9003 provides three priority classifications: Port-based, 802.1p-based DiffServ-based priority. next section more detail. DM9003 offers four level queues transmit per-port based. DM9003 provides packet scheduling algorithms: Weighted Round-Robin Queuing
DM9003
2-port Switch with Processor Interface
Strict Priority Queuing. Weighted Round-Robin Queuing (WRR) based their priority queue weight. Queues with larger weights more service than smaller. This mechanism highly efficient bandwidth smooth traffic. Strict Priority Queuing (SPQ) based priority only. Packet highest priority queue transmitted first. next highest-priority queue work until last queue empties, This feature register 6Dh. 9.2.14.1 Port-Based Priority Port based priority simplest scheme default. Each port 2-bit priority value index splitting ingress packets corresponding transmit queue. This value register 6Dh. 9.2.14.2 802.1p-Based Priority 802.1p priority disabled register 6Dh, enabled default. DM9003 extracts 3-bit priority field from received packet with 802.1p VLAN tag, maps this field against VLAN Priority Registers (D0h~D1h) determine which transmit queue designated. VLAN Priority programmable. 9.2.14.3 DiffServ-Based Priority DiffServ based priority uses most significant 6-bit field standard IPv4 header, maps this field against Priority Registers (C0h~CFh) determine which transmit queue designated. Priority programmable too. addition, User only refer most significant 3-bit field optionally, register 53h.
Preliminary datasheet DM9003-15-DS-P05 April 2009
DM9003
2-port Switch with Processor Interface
Internal functions 9.3.1 100Base-TX Operation transmitter section contains following functional blocks: 4B5B Encoder Scrambler Parallel Serial Converter NRZI Converter NRZI MLT-3 MLT-3 Driver 9.3.1.1 4B5B Encoder 4B5B encoder converts 4-bit (4B) nibble data generated Reconciliation Layer into 5-bit (5B) code group transmission, reference Table This conversion required control packet data combined code groups. 4B5B encoder substitutes first bits preamble with code-group pair (11000 10001) upon transmit. 4B5B encoder continues replace subsequent preamble data nibbles with corresponding code-groups. transmit packet, upon deassertion Transmit Enable signal from Reconciliation layer, 4B5B encoder injects code-group pair (01101 00111) indicating frame. After code-group pair, 4B5B encoder continuously injects IDLEs into transmit data stream until Transmit Enable asserted next transmit packet detected. scrambling data, total energy presented cable randomly distributed over wide frequency range. Without scrambler, energy levels cable could peak beyond limitations frequencies related repeated sequences, like continuous transmission IDLE symbols. scrambler output combined with data from code-group encoder logic function. result scrambled data stream with sufficient randomization decrease radiated emissions critical frequencies. 9.3.1.3 Parallel Serial Converter Parallel Serial Converter receives parallel scrambled data from scrambler, serializes (converts from parallel serial data stream). serialized data stream then presented NRZI encoder block 9.3.1.4 NRZI Encoder After transmit data stream been scrambled serialized, data must NRZI encoded compatibility with TP-PMD standard, 100Base transmission over Category-5 unshielded twisted pair cable. 9.3.1.5 MLT-3 Converter MLT-3 conversion accomplished converting data stream output, from NRZI encoder into binary data streams, with alternately phased logic event. 9.3.1.6 MLT-3 Driver binary data streams created MLT-3 converter twisted pair output driver, which converts these streams current sources alternately drives either side transmit transformer's primary winding, resulting minimal current MLT-3 signal.
9.3.1.2 Scrambler scrambler required control radiated emissions (EMI) spreading transmit energy across frequency spectrum media connector twisted pair cable 100Base-TX operation.
Preliminary datasheet DM9003-15-DS-P05 April 2009
DM9003
2-port Switch with Processor Interface
9.3.1.7 4B5B Code Group
Symbol
Meaning Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data Idle Error Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid
code 3210 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 undefined 0101 0101 undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined Table
Code 43210 11110 01001 10100 10101 01010 01011 01110 01111 10010 10011 10110 10111 11010 11011 11100 11101 11111 11000 10001 01101 00111 00100 00000 00001 00010 00011 00101 00110 01000 01100 10000 11001
Preliminary datasheet DM9003-15-DS-P05 April 2009
DM9003
2-port Switch with Processor Interface
9.3.2 100Base-TX Receiver 100Base-TX receiver contains several function blocks that convert scrambled 125Mb/s serial data synchronous 4-bit nibble data. receive section contains following functional blocks: Signal Detect Digital Adaptive Equalization MLT-3 Binary Decoder Clock Recovery Module NRZI Decoder Serial Parallel Descrambler Code Group Alignment 4B5B Decoder 9.3.2.1 Signal Detect signal detects function meets specifications mandated ANSI XT12 TP-PMD 100Base-TX standards both voltage thresholds timing parameters. 9.3.2.2 Adaptive Equalization When transmitting data over copper twisted pair cable high speed, attenuation based frequency becomes concern. high speed twisted pair signaling, frequency content transmitted signal vary greatly during normal operation based randomness scrambled data stream. This variation signal attenuation, caused frequency variations, must compensated ensure integrity received data. order ensure quality transmission when employing MLT-3 encoding, compensation must able adapt various cable lengths cable types depending installed environment. selection long cable lengths given implementation requires significant compensation, which will over-killed situation that includes shorter, less attenuating cable lengths. Conversely, selection short intermediate cable lengths requiring less compensation will cause serious under-compensation longer length cables. Therefore, compensation equalization must adaptive ensure proper conditioning received signal independent cable length. 9.3.2.3 MLT-3 NRZI Decoder DM9003 decodes MLT-3 information from Digital Adaptive Equalizer into NRZI data. 9.3.2.4 Clock Recovery Module Clock Recovery Module accepts NRZI data from MLT-3 NRZI decoder. Clock Recovery Module locks onto data stream extracts reference clock. extracted synchronized clock data presented NRZI decoder. 9.3.2.5 NRZI transmit data stream required NRZI encoded compatibility with TP-PMD standard 100Base-TX transmission over Category-5 unshielded twisted pair cable. This conversion process must reversed receive end. NRZI decoder receives NRZI data stream from Clock Recovery Module converts data stream presented Serial Parallel conversion block. 9.3.2.6 Serial Parallel Serial Parallel Converter receives serial data stream from NRZI converter. converts data stream parallel data presented descrambler. 9.3.2.7 Descrambler Because scrambling process requires control radiated emissions transmit data streams, receiver must descramble receive data streams. descrambler receives scrambled parallel data streams from Serial Parallel converter, descrambles data streams, presents data streams Code Group alignment block.
Preliminary datasheet DM9003-15-DS-P05 April 2009
DM9003
2-port Switch with Processor Interface
9.3.2.8 Code Group Alignment Code Group Alignment block receives un-aligned data from descrambler converts into code group data. Code Group Alignment occurs after detected subsequent data aligned fixed boundary. 9.3.2.9 4B5B Decoder 4B5B Decoder functions look-up table that translates incoming code groups into (Nibble) data. When receiving frame, first 5-bit code groups receive start-of-frame delimiter (J/K symbols). symbol pair stripped nibbles preamble pattern substituted. last code groups end-of-frame delimiter (T/R Symbols). symbol pair also stripped from nibble, presented Reconciliation layer. 9.3.3 10Base-T Operation 10Base-T transceiver IEEE 802.3u compliant. When DM9003 operating 10Base-T mode, coding scheme Manchester. Data processed transmit presented nibble format, converted serial stream, then Manchester encoded. When receiving, stream, encoded Manchester, decoded converted into nibble format. 9.3.4 Collision Detection half-duplex operation, collision detected when transmit receive channels active simultaneously. Collision detection disabled full duplex operation. 9.3.5 Carrier Sense Carrier Sense (CRS) asserted half-duplex operation during transmission reception data. During full-duplex mode, asserted only during receive operations. 9.3.6 Auto-Negotiation objective Auto-negotiation provide means exchange information between linked devices automatically configure both devices take maximum advantage their abilities. important note that Auto-negotiation does test characteristics linked segment. Auto-Negotiation function provides means device advertise supported modes operation remote link partner, acknowledge receipt understanding common modes operation, reject un-shared modes operation. This allows devices both ends segment establish link best common mode operation. more than common mode exists between devices, mechanism provided allow devices resolve single mode operation using predetermined priority resolution function. Auto-negotiation also provides parallel detection function devices that support Auto-negotiation feature. During Parallel detection there exchange information configuration. Instead, receive signal examined. discovered that signal matches technology, which receiving device supports, connection will automatically established using that technology. This allows devices support Auto-negotiation support common mode operation establish link.
Preliminary datasheet DM9003-15-DS-P05 April 2009
DM9003
2-port Switch with Processor Interface ELECTRICAL CHARACTERISTICS
10.1 Absolute Maximum Ratings Symbol Parameter VCC3 3.3V Supply Voltage VCCI 1.8V core power supply AVDD3 Analog power supply 3.3V AVDDI Analog power supply 1.8V Input Voltage (VIN) Storage Temperature range TSTG Ambient Temperature Lead Temperature (TL, soldering, sec.). 10.2 Operating Conditions Symbol Parameter VCC3 3.3V Supply Voltage VCCI 1.8V core power supply AVDD3 Analog power supply 3.3V AVDDI Analog power supply 1.8V 100BASE-TX (Power Dissipation) 10BASE-TX Min. -0.3 -0.3 -0.3 -0.3 -0.5 Max. 1.95 1.95 +150 +260 Unit Conditions Lead-free Device
Min. 3.135 1.71 3.135 1.71
Typ. 3.300 1.80 3.300 1.80
Max. 3.465 1.89 3.465 1.89
Unit
Auto-negotiation cable
Conditions 1.8V only 3.3V only idle, 1.8V only utilization, 1.8V only 100% utilization, 1.8V only 3.3V only 1.8V only 3.3V only
Preliminary datasheet DM9003-15-DS-P05 April 2009
DM9003
2-port Switch with Processor Interface
10.3 Electrical Characteristics Symbol Parameter Min. Typ. Max. Unit Inputs Input Voltage Input High Voltage Input Leakage Current Input High Leakage Current Outputs Output Voltage Output High Voltage Receiver VICM RX+/RX- Common Mode Input Voltage Transmitter VTD100 100TX+/- Differential Output Voltage VTD10 10TX+/- Differential Output Voltage ITD100 100TX+/- Differential Output Current ITD10 10TX+/- Differential Output Current Note: Vcond1 VCC3 3.3V, VCCI 1.8V, AVDD3 3.3V, AVDDI 1.8V. Conditions Vcond1 Vcond1 0.0V, Vcond1 3.3V, Vcond1 =4mA -4mA Termination Across Peak Peak Peak Peak Absolute Value Absolute Value
Preliminary datasheet DM9003-15-DS-P05 April 2009
DM9003
2-port Switch with Processor Interface
10.4 characteristics 10.4.1 Power Reset Timing
PWRST#
Strap pins
EECS
Symbol
Parameter PWRST# Period Strap hold time with PWRST# PWRST# high EECS high PWRST# high EECS burst PWRST# high available
Min.
Typ. -400
Max.
Unit
Conditions
Preliminary datasheet DM9003-15-DS-P05 April 2009
DM9003
2-port Switch with Processor Interface
10.4.2 Processor Read Timing
CS#,CMD
IOR#
SD0~15
Parameter CS#,CMD valid IOR# valid IOR# invalid CS#,CMD invalid IOR# width IOR# invalid next IOR#/IOW# valid When read DM9003 register IOR# invalid next IOR#/IOW# valid When read DM9003 memory with register T3+T4 IOR# invalid next IOR#/IOW# valid When read DM9003 memory with register System Data(SD) Delay time IOR# invalid System Data(SD) invalid Unit: under internal system clock 50MHz.(20ns).
Symbol
Min.
Typ.
Max.
Unit
Preliminary datasheet DM9003-15-DS-P05 April 2009
DM9003
2-port Switch with Processor Interface
10.4.3 Processor Write Timing
CS#,CMD
IOW#
SD0~15
Parameter CS#,CMD valid IOW# valid IOW# Invalid CS#,CMD Invalid IOW# Width IOW# Invalid next IOW#/IOR# valid When write DM9003 INDEX port IOW# Invalid next IOW#/IOR# valid When write DM9003 DATA port T3+T4 IOW# Invalid next IOW#/IOR# valid When write DM9003 memory System Data(SD) Setup Time System Data(SD) Hold Time Unit: under internal system clock 50MHz.(20ns).
Symbol
Min.
Typ.
Max.
Unit
Preliminary datasheet DM9003-15-DS-P05 April 2009
DM9003
2-port Switch with Processor Interface
10.4.4 EEPROM timing
EECS EECK EEDIO
Symbol
Parameter EECS Setup Time EECS Hold Time EECK Frequency EEDIO Setup Time output state EEDIO Hold Time output state EEDIO Setup Time input state EEDIO Hold Time input state
Min.
Typ. 2080 0.38 2100
Max.
Unit
Preliminary datasheet DM9003-15-DS-P05 April 2009
DM9003
2-port Switch with Processor Interface APPLICATION CIRCUIT
DVDD_33V DVDD_33V DVDD_18V LNK0_LED SPD0_LED LNK1_LED SPD1_LED 0.1uF EECK EECS JUMPER JUMPER LEDA LEDA LEDA LEDA AVDD_18V RX0RX0+ TX0TX0+ 49.9/1% 49.9/1%
RJ-45 inclusion
RDNC TDNC RXMCT TX16 RJ-45_LED
220uF
0.1uF
0.1uF
0.1uF
0.1uF
220uF
DVDD_33V 4.7k 4.7k
LED2+ LED216
MAGCOM_HS9024 75/1% 75/1% 75/1% 0.1uF 0.01uF/2KV RJ45_SPD RJ45_LINK 74HC04 0.1uF 74HC04
AVDD_33V
AVDD_18V
EECS PULL HIGH ACTIVE OUTPUT EECK PULL HIGH, DM9003E 8-bit mode
49.9/1% 49.9/1%
220uF
0.1uF
0.1uF
220uF
0.1uF
0.1uF EECS EECK EEDIO
EEPROM
JUMPER 1.4K/1% RX0+ RX0TX0+ TX0RX1+ RX193LC46
DVDD_33V
0.1uF
0.1uF
0.1uF
SPD0_LED
LNK0_LED AVDD_33V DVDD_33V
0.1uF
F.B/120/SO805 VCNTL 2SB1386 AVDD_18V
AVDD_33V AVDD_18V DVDD_18V
DVDD_18V DVDD_33V RX1-
AVDD_18V 49.9/1%
normal RJ-45
RDNC TDNC RXNC TXNC
RJ-45
RX1+ TX1U5 TX1+ PWRST# EECS EECK EEDIO SD15 SD14 SD13 SD12 SD11 SD10 49.9/1%
F.B/120/SO805 0.1uF 0.1uF F.B/120/SO805 VCNTL VREF LNK1_LED SPD1_LED LNK0_LED SPD0_LED IOW# VCNTL VREF DVDD33 DGND LNK1_LED SPD1_LED LNK0_LED SPD0_LED ATPG DVDD18 IOW# DGND
BGRESG BGRES AVDD33 RX0RX0+ AGND TX0TX0+ AVDD18 AVDD33 RX1RX1+ AGND TX1TX1+ AVDD18
MAGCOM_HS9016 75/1% 75/1% 75/1% 0.1uF 0.01uF/2KV
VREF 0.1uF
25MHz/49US 22pF 22pF
DM9003E Interface
DVDD33 IOR# DGND DGND DVDD18 DVDD33 DGND
DM9003E
DVDD_5V
DVDD_33V
PWRST#
AP1117-3.3V 220uF 0.1uF IOR#
10uF SD10 SD11 SD12 SD13 SD14 SD15
R/C_RESET RESET_IC SELECT
Davicom Semiconductor Inc.
Title Size Date:
DM9003E_DEMO
Document Number
DM9003E_DEMO
Wednesday 2007 Sheet
Preliminary datasheet DM9003-15-DS-P05 April 2009
HEADER_16X2
1N4148
TEST DGND PWRST# EECS EECK EEDIO DVDD33 SD15 SD14 DGND SD13 SD12 SD11 SD10
49.9/1% 49.9/1%
0.1uF
0.1uF
DVDD_5V DVDD_33V DVDD_33V
RESET_IC_(AP1701DW)
IOW# IOR# IO16
LED1+ LED1-
TX1+ TX1-
IOWAIT PWRST#
DM9003
2-port Switch with Processor Interface PACKAGE INFORMATION
Pins LQFP Package Outline Information:
Symbol
0.05 1.35 0.17 0.17 0.09 0.09
0.45 0.08 0.08 0.20
Dimension 1.40 0.22 0.20 12.00 10.00 12.00 10.00 0.50 0.60 1.00
1.60 0.15 1.45 0.27 0.23 0.20 0.16
0.75 0.20
Dimension inch 0.063 0.002 0.006 0.053 0.055 0.057 0.007 0.009 0.011 0.007 0.008 0.009 0.004 0.008 0.004 0.006 0.472 0.394 0.472 0.394 0.020 0.018 0.024 0.030 0.039 0.003 0.003 0.008 0.008
Dimension include resin fin. dimensions base metric system. General appearance spec should base final visual inspection spec.
Preliminary datasheet DM9003-15-DS-P05 April 2009
DM9003
2-port Switch with Processor Interface ORDERING INFORMATION
Part Number DM9003EP Count Package LQFP (Pb-free) application circuits illustrated this document reference purposes only. DAVICOM's terms conditions printed order acknowledgment govern sales DAVICOM. DAVICOM will bound terms inconsistent with these unless DAVICOM agrees otherwise writing. Acceptance buyer's orders shall based these terms.
Disclaimer
information appearing this publication believed accurate. Integrated circuits sold DAVICOM Semiconductor covered warranty patent indemnification provisions stipulated terms sale only. DAVICOM makes warranty, express, statutory, implied description regarding information this publication regarding information this publication regarding freedom described chip(s) from patent infringement. FURTHER, DAVICOM MAKES WARRANTY MERCHANTABILITY FITNESS PURPOSE. DAVICOM reserves right halt production alter specifications prices time without notice. Accordingly, reader cautioned verify that data sheets other information this publication current before placing orders. Products described herein intended normal commercial applications. Applications involving unusual environmental reliability requirements, e.g. military equipment medical life support equipment, specifically recommended without additional processing DAVICOM such applications. Please note that
Company Overview
DAVICOM Semiconductor Inc. develops manufactures integrated circuits integration into data communication products. mission design produce products that industry's best value Data, Audio, Video, Internet/Intranet applications. achieve this goal, have built organization that able develop chipsets response evolving technology requirements customers while still delivering products that meet their cost requirements.
Products
offer only products that satisfy high performance requirements which compatible with major hardware software standards. currently available soon released products based proprietary designs deliver high quality, high performance chipsets that comply with modem communication standards Ethernet networking standards.
Contact Windows
additional information about DAVICOM products, contact Sales department Headquarters Hsin-chu Office: No.6 Li-Hsin Science-based Park, Hsin-chu City, Taiwan, R.O.C. TEL: 886-3-5798797 FAX: 886-3-5646929 E-MAIL: sales@davicom.com.tw Web: http://www.davicom.com.tw WARNING
Conditions beyond those listed absolute maximum destroy damage products. addition, conditions sustained periods near limits operating ranges will stress temporarily (and permanently) affect damage structure, performance and/or function.
Preliminary datasheet DM9003-15-DS-P05 April 2009

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