10/100 Mbps 2-port Ethernet Switch Controller With RMII Interface
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DM8203
10/100 Mbps 2-port Ethernet Switch Controller With RMII Interface
Preliminary Version: DM8203-DS-P05 October 2008
DM8203
2-port switch with RMII Interface
CONTENT
GENERAL DESCRIPTION. BLOCK DIAGRAM. FEATURES CONFIGURATION DESCRIPTION
RMII Reverse Interfaces. 5.1.1 Interfaces 5.1.2 RMII Interfaces 5.1.3 Reverse Interfaces EEPROM Interfaces. Pins. Clock Interface. Network Interface. Miscellaneous Pins. Power Pins. Strap pins table
CONTROL STATUS REGISTER SET.
EEPROM Control Register (0BH)
Preliminary datasheet DM8203-15-DS-P05 October 2008
DM8203
2-port switch with RMII Interface
EEPROM Address Register (0CH) EPROM Data Register (0DH~0EH) Vendor Register (28H~29H). Product Register (2AH~2BH) Port driving capability Register (3AH). Switch Control Register (52H) VLAN Control Register (53H). Switch Status Register (54H) 6.10 Port Control/Status Index Register (60H) 6.11 Port Control Data Register (61H) 6.12 Port Status Data Register (62H) 6.13 Port Forward Control Register (65H). 6.14 Port Ingress/Egress Control Register (66H). 6.15 Bandwidth Control Setting Register (67H) 6.16 Port Block Unicast ports Control Register (68H) 6.17 Port Block Multicast ports Control Register (69H) 6.18 Port Block Broadcast ports Control Register (6AH) 6.19 Port Block Unknown ports Control Register (6BH). 6.20 Port Priority Queue Control Register (6DH) 6.21 Port VLAN Byte Register (6EH)
Preliminary datasheet DM8203-15-DS-P05 October 2008
DM8203
2-port switch with RMII Interface
6.22 Port VLAN High Byte Register (6FH) 6.23 counters Port Index Register (80H). 6.24 counter Data Register (81H~84H) 6.25 VLAN grouping table Registers (B0H~BFH). 6.26 Priority Registers (C0H~CFH) 6.27 VLAN Priority Registers (D0H~D1H)
EEPROM FORMAT. REGISTERS
Basic Mode Control Register (BMCR) Basic Mode Status Register (BMSR) Identifier Register (PHYID1) 02H. Identifier Register (PHYID2) 03H. Auto-negotiation Advertisement Register (ANAR) Auto-negotiation Link Partner Ability Register (ANLPAR) Auto-negotiation Expansion Register (ANER) DAVICOM Specified Configuration Register (DSCR) DAVICOM Specified Configuration Status Register (DSCSR) 8.10 10BASE-T Configuration/Status (10BTCSR) 8.11 Power down Control Register (PWDOR) 13H. 8.12 (Specified config) Register
Preliminary datasheet DM8203-15-DS-P05 October 2008
DM8203
2-port switch with RMII Interface
8.13 DAVICOM Specified Receive Error Counter Register (RECR) 16H. 8.14 DAVICOM Specified Disconnect Counter Register (DISCR) 8.15 Power Saving Control Register (PSCR) 1DH.
FUNCTIONAL DESCRIPTION.
Serial Management Interface Switch function: 9.2.1 Address Learning 9.2.2 Address Aging 9.2.3 Packet Forwarding 9.2.4 Inter-Packet (IPG). 9.2.5 Back-off Algorithm. 9.2.6 Late Collision 9.2.7 Full Duplex Flow Control 9.2.8 Half Duplex Flow Control 9.2.9 Partition Mode. 9.2.10 Broadcast Storm Filtering 9.2.11 Bandwidth Control. 9.2.12 Port Monitoring Support 9.2.13 VLAN Support. 9.2.13.1 Port-Based VLAN 9.2.13.2 802.1Q-Based VLAN. 9.2.13.3 Tag/Untag 9.2.14 Priority Support. 9.2.14.1 Port-Based Priority 9.2.14.2 802.1p-Based Priority. 9.2.14.3 DiffServ-Based Priority. Interface. 9.3.1 data interface. 9.3.2 Serial Management
Preliminary datasheet DM8203-15-DS-P05 October 2008
DM8203
2-port switch with RMII Interface
9.3.3 Serial Management Interface 9.3.4 Management Interface Read Frame Structure. 9.3.5 Management Interface Write Frame Structure Internal functions 9.4.1 100Base-TX Operation. 9.4.1.1 4B5B Encoder 9.4.1.2 Scrambler. 9.4.1.3 Parallel Serial Converter 9.4.1.4 NRZI Encoder 9.4.1.5 MLT-3 Converter. 9.4.1.6 MLT-3 Driver. 9.4.1.7 4B5B Code Group 9.4.2 100Base-TX Receiver 9.4.2.1 Signal Detect 9.4.2.2 Adaptive Equalization. 9.4.2.3 MLT-3 NRZI Decoder. 9.4.2.4 Clock Recovery Module 9.4.2.5 NRZI 9.4.2.6 Serial Parallel 9.4.2.7 Descrambler 9.4.2.8 Code Group Alignment. 9.4.2.9 4B5B Decoder 9.4.3 10Base-T Operation 9.4.4 Collision Detection 9.4.5 Carrier Sense. 9.4.6 Auto-Negotiation. Auto-MDIX Functional Descriptions
ELECTRICAL CHARACTERISTICS
10.1 Absolute Maximum Ratings 10.2 Operating Conditions
Preliminary datasheet DM8203-15-DS-P05 October 2008
DM8203
2-port switch with RMII Interface
10.3 Electrical Characteristics 10.4 characteristics. 10.4.1 Power Reset Timing. 10.4.2 Port Interface Transmit Timing. 10.4.3 Port Interface Receive Timing. 10.4.4 Management host Interface Timing 10.4.5 EEPROM timing
APPLICATION CIRCUIT
11.1 Main circuit. 11.2 Application Reverse MII.
PACKAGE INFORMATION. ORDERING INFORMATION
Preliminary datasheet DM8203-15-DS-P05 October 2008
DM8203
2-port switch with RMII Interface General Description
DM8203 fully integrated, high performance, cost-effective fast Ethernet switch controller, ports 10M/100Mbps PHY, port MII, Reverse RMII interface. DM8203 with ports 10M/100Mbps PHY, port MII, Reverse RMII interface fully integrated, high performance, cost-effective fast Ethernet switch controller internal memory DM8203 supports uni-cast address table, provided three ports' usage. Each port DM8203 provides four priorities transmit queues that defined port-based, 802.1p VLAN, packet field automatically, various bandwidth latency requirement data, voice, video application. Besides, it's internal memory three ports usage, supporting uni-case address table. Each port DM8203 provides four priorities transmit queens that defined port-based, 802.1p VLAN, packet field automatically, applies various bandwidth latency requirement data, voice, video application. Each port also supports ingress and/or egress rate control provide proper bandwidth. groups 802.1Q VLAN with Tag/Un-tag functions supported provide efficient packet forwarding. Each port, provide counters loop-back capability build memory self test (BIST) system board level diagnostic. proper bandwidth, each port also supports ingress and/or egress rate control, groups 802.1Q VLAN with Tag/Un-tag functions support packet forwarding efficiently. Each port provides counters, loop-back capability build memory self test (BIST) system board level diagnostic. integrated ports compliant with IEEE 802.3u standards. interface provides flexibility connect Ethernet PHY, configured Reversed interface with interface. alternative interface, RMII interface, also provided connect lower count Ethernet with RMII interface.
Block Diagram
Switch Engine Switch Fabric Port MDIX 10/100M 10/100M Embedded Memory Memory BIST
Port MDIX
10/100M
10/100M
Switch Controller
Memory Management
Port RMII Reverse
10/100M
Control
LEDs
Control Registers
Counters
EEPROM Interface
EEPROM
Preliminary datasheet DM8203-15-DS-P05 October 2008
DM8203
2-port switch with RMII Interface Features Ethernet Switch with 10/100Mbps PHY, MII/RMII Support Reverse-MII EEPROM interface power configurations Support Auto-MDIX Support IEEE 802.3x Flow Control Full-duplex mode Support Back Pressure Flow Control Half-duplex mode port support priority queues Port-based, 802.1P VLAN, priority Support 802.1Q VLAN up-to VLAN group Support VLAN tag/untag options port support bandwidth, ingress egress rate control Support Broadcast Storming filter function Support Store Forward switching approach Support up-to Uni-cast addresses Support Serial data management interface Automatic aging scheme Support counters diagnostic 64-pin LQFP 1.8V/3.3V dual power 3.3V with tolerant
Preliminary datasheet DM8203-15-DS-P05 October 2008
DM8203
2-port switch with RMII Interface Configuration LQFP:
BGGND
BGRES AVDD
AVDDI
VCNTL VREF VCC3 LNK1_LED SPD1_LED LNK0_LED SPD0_LED TEST2 SMI_CK VCCI SMI_DIO TEST3
AVDDI
AGND
AGND
AVDD
RX0+
RX1+
TX0TX0+
TX1+
RX0-
RX1-
TX1-
DM8203
TEST1 PWRST# EECS EECK EEDIO VCC3 RXD2_0 RXD2_1 RXD2_2 RXD2_3 RXDV2 RXC2 RXER COL2
MDIO
TXE2
VCCI
TXER2
CRS2
VCC3
VCC3
TXD2_3
TXD2_1
TXD2_2
TXD2_0
TXC2
Preliminary datasheet DM8203-15-DS-P05 October 2008
DM8203
2-port switch with RMII Interface Description
Input, Output, Input Output, Open Drain, Power, PD=internal pull-low (about Ohm) asserted RMII Reverse Interfaces
5.1.1 Interfaces 5,6,7,9 21,22,24,25
Name MDIO TXD2_3~0 TXE2 TXC2 TXER2 CRS2 COL2 RXER2 RXC2 RXDV2 RXD2_3~0
O,PD O,PD O,PD O,PD
Description Serial Management Data Clock Serial Management Data Port Transmit Data 4-bit nibble data outputs (synchronous TXC2) Port Transmit Enable Port Transmit Clock. Port Transmit Error Port Carrier Sense Port Collision Detect. Port Receive Error Port Receive Clock Port Receive Data Valid Port Receive Data 4-bit nibble data input (synchronous RXC2)
5.1.2 RMII Interfaces 21,22 24,25
Name MDIO TXD2_3~2 TXD2_1~0 TXE2 TXC2 TXER2 CRS2 COL2 RXER2 RXC2 RXDV2 RXD2_3~2 RXD2_1~0
O,PD O,PD O,PD O,PD
Description Serial Management Data Clock Serial Management Data Reserved RMII Transmit Data RMII Transmit Enable. Reserved Port Transmit Error RMII CRS_DV Reserved, ground application. Reserved, ground application. 50MHz reference clock. Reserved, ground application. Reserved, ground application. RMII Receive Data.
Preliminary datasheet DM8203-15-DS-P05 October 2008
DM8203
2-port switch with RMII Interface
5.1.3 Reverse Interfaces Name 5,6,7,9 21,22,24,25 MDIO TXD2_3~0 TXE2 TXC2 TXER2 CRS2 COL2 RXER2 RXC2 RXDV2 RXD2_3~0
O,PD O,PD O,PD O,PD
Description Reserved Reserved Port Transmit Data 4-bit nibble data outputs (synchronous TXC2) Port Transmit Enable 25MHz clock output Port Transmit Error Port carrier sense output when TXE2 RXDV2 asserted. Port collision output when TXE2 RXDV2 asserted. Port Receive Error Port Receive Clock Port Receive Data Valid Port Receive Data 4-bit nibble data input (synchronous RXC2)
EEPROM Interfaces
Name EEDIO EECK EECS
O,PD O,PD
Description EEPROM Data In/Out EEPROM Serial Clock This used clock EEPROM data transfer. EEPROM Chip Selection.
Pins
Name LNK1_LED
Description Port Link Active combined link carrier sense signal internal PHY1 Port Speed output indicates that internal PHY1 operated 100M/S, floating mode internal PHY1 Port Link Active combined link carrier sense signal internal PHY0 Port Speed output indicates that internal PHY0 operated 100M/S, floating mode internal PHY0
SPD1_LED
LNK0_LED
SPD0_LED
Preliminary datasheet DM8203-15-DS-P05 October 2008
DM8203
2-port switch with RMII Interface
Clock Interface Network Interface 34,35 Name Crystal 25MHz Crystal 25MHz Description
Name TX1+/-
Description Port These pins Twisted Pair transmit mode receive MDIX mode. Port These pins Twisted Pair receive mode transmit MDIX mode. Port These pins Twisted Pair transmit mode receive MDIX mode. Port These pins Twisted Pair receive mode transmit MDIX mode. Band Connect 1.4K resistor BGGND application. Band Ground 1.8V Voltage control Voltage Reference Connect 0.1u capacitor ground application.
37,38
RX1+/-
41,42
TX0+/-
44,45
RX0+/-
BGRES BGGND VCNTL VREF
Miscellaneous Pins Power Pins 1,13,26,51 11,61 4,8,16,23,31,54,64 39,46 33,40 36,43
Name PWRST# SMI_CK SMI_DIO TEST1 TEST2 TEST3
Description
Power Reset active with minimum Serial data management interface clock Serial data management interface I,PD VCC3 application I,PD application I,PD VCC3 application
Name VCC3 VCCI AVDD3 AVDDI AGND
Description Digital 3.3V Internal 1.8V core power Digital Analog 3.3V power Analog 1.8V power Analog
Preliminary datasheet DM8203-15-DS-P05 October 2008
DM8203
2-port switch with RMII Interface
Strap pins table pull-high 1K~10K, floating (default).
Name Description
EECK EECS TXER2 TXD2_3 TXD2_2
TXD2_1 TXD2_0 TXE2
Port force Mbps mode Port force Mbps mode Port mode Port Fiber mode Port mode Port Fiber mode BIST Bypass BIST TXD2_3 TXD2_2 Mode mode Reverse mode RMII mode Reserved USE) device address device address Port normal mode Port force mode
Preliminary datasheet DM8203-15-DS-P05 October 2008
DM8203
2-port switch with RMII Interface Control Status Register
DM8203 implements several control status registers, which accessed serial management interface. These CSRs byte aligned. CSRs Register Description their default values hardware software reset unless specified Offset Default value after reset 0A46H 8203H 0000H 00H~FFH 50H,FAH
EPCR EEPROM Control Register EPAR EEPROM Address Register EPDRL EEPROM Byte Data Register EPDRH EEPROM High Byte Data Register Vendor 28H-29H Product 2AH-2BH P2FRV Port driving capability Register SWITCHCR SWITCH Control Register VLANCR VLAN Control Register SWITCHSR SWITCH Status Register DSP1,2 Control Register I,II 58H~59H P_INDEX Port Control/Status Index Register P_CTRL Port Control Data Register P_STUS Port Status Data Register P_RATE Port Ingress Egress Rate Control Register P_BW Port Bandwidth Control Register P_UNICAST Port Block Unicast ports Control Register P_MULTI Port Block Multicast ports Control Register P_BCAST Port Block Broadcast ports Control Register P_UNKNWN Port Block Unknown ports Control Register P_PRI Port Priority Queue Control Register VLAN_TAGL Port VLAN Byte Register VLAN_TAGH Port VLAN High Byte Register P_MIB_IDX Port counter Index Register MIB_DAT counter Data Register MIB_DAT counter Data Register 8~15 MIB_DAT counter Data Register 16~23 MIB_DAT counter Data Register 24~31 PVLAN Port-based VLAN mapping table registers B0-BFH TOS_MAP Priority Register C0-CFH VLAN_MAP VLAN priority Register D0-D1H Default register description that follows, default column default value from EEPROM setting takes form: default value from strap <Reset Value>, <Access Type> <Access Type>: Where: Read only <Reset Value>: Read/Write logic Read Clear logic zero RW/C1=Read/Write Cleared write default value Write only power reset default value Reserved bits should written with hardware reset, Reg. default value Reserved bits undefined read access.
Preliminary datasheet DM8203-15-DS-P05 October 2008
DM8203
2-port switch with RMII Interface
EEPROM Control Register (0BH) Name Default Description RESERVED 0,RO Reserved REEP PH0,RW Reload EEPROM. Driver needs clear after operation completes PH0,RW Write EEPROM Enable EPOS PH0,RW EEPROM Operation Select When reset, select EEPROM; when set, select ERPRR PH0,RW EEPROM Read Register Read Command. Driver needs clear after operation completes. ERPRW PH0,RW EEPROM Write Register Write Command. Driver needs clear after operation completes. ERRE PH0,RO EEPROM Access Status Access Status When set, indicates that EEPROM access progress EEPROM Address Register (0CH) Name Default Description PHY_ADR PH01,RW Address address [4:2] force EROA PH0,RW EEPROM Word Address Register Address EPROM Data Register (0DH~0EH) Name Default Description EE_PHY_L PH0,RW EEPROM Byte Data (0DH) This data made write/read byte word address defined Reg. EEPROM EE_PHY_H PH0,RW EEPROM High Byte Data (0EH) This data made write/read high byte word address defined Reg. EEPROM Vendor Register (28H~29H) Name Default VIDH PE,0AH,RO Vendor High Byte (29H) VIDL PE,46H.RO Vendor Byte (28H) Product Register (2AH~2BH) Name Default PIDH PE,82H,RO Product High Byte (2BH) PIDL PE,03H.RO Product Byte (2AH)
Description
Description
Port driving capability Register (3AH) Name Default Description Reserved 0,RO Reserved Port TXD/TXE Driving/Sinking Capability P2_CURR P01,RW (default) RESERVED P01,RW reserved
Preliminary datasheet DM8203-15-DS-P05 October 2008
DM8203
2-port switch with RMII Interface
Switch Control Register (52H) Name Default Description MEM_BIST PH0,RO Address Table Memory Test BIST Status Fail RST_SW P0,RW Reset Switch Core auto clear after 10us RST_ANLG P0,RW Reset Analog Core auto clear after 10us SNF_PORT PE00,RW Sniffer Port Number Define port number sniffer port Port Port Port Reserved CRC_DIS PE0,RW Checking Disable When set, received error packet also accepts receive memory. PE0,RW Address Table Aging aging ±128 VLAN Control Register (53H) Name Default Description TOS6 PE0,RW Full Field Priority Queue check most significant 6-bit check most significant 3-bit only RESERVED 0,RO Reserved UNICAST PE0,RW Unicast packet across VLAN boundary VIDFF PE0,RW Replace VIDFF received packet tagged VLAN with equal "FFF", VLAN field replaced with VLAN defined Reg. 6FH. VID1 PE0,RW Replace VID01 received packet tagged VLAN with equal "001", VLAN field replaced with VLAN defined Reg. 6FH. VID0 PE0,RW Replace VID0 received packet tagged VLAN with equal "000", VLAN field replaced with VLAN defined Reg. 6FH. PE0,RW Replace priority field with value define 7~5. VLAN PE0,RW VLAN mode enable 802.1Q base VLAN mode enable port-base VLAN only Switch Status Register (54H) Name Default Description MEM_BIST PH0,RO Address Table Memory Test BIST Status Fail RESERVED 0,RO Reserved
Preliminary datasheet DM8203-15-DS-P05 October 2008
DM8203
2-port switch with RMII Interface
6.10 Port Control/Status Index Register (60H) Name Default Description reserved PH0,RW reserved reserved 0,RO reserved INDEX PH0,RW Port index register 61h~84h Write port number this register before write/read register 61h~84h.
6.11 Port Control Data Register (61H) Name Default Description RESERVED PE0,RW Reserved PARTI_EN PE0,RW Enable Partition Detection NO_DIS_RX PE0,RW Discard Packets when Ingress Bandwidth Control When received packets bandwidth reach Ingress bandwidth threshold, packets over threshold discarded with flow control. FLOW_DIS PE0,RW Flow control full duplex mode, back pressure half duplex mode enable enable disable BANDWIDTH PE0,RW Bandwidth Control Control with Ingress Egress separately, Register 66h. Control with Ingress Egress, Register BP_DIS PE0,RW Broadcast packet filter accept broadcast packets reject broadcast packets MP_DIS PE0,RW Multicast packet filter accept multicast packets reject multicast packets MP_STORM PE0,RW Broadcast Storm Control only broadcast packets storm controlled Multicast packets also same broadcast storm control.
Preliminary datasheet DM8203-15-DS-P05 October 2008
DM8203
2-port switch with RMII Interface
6.12 Port Status Data Register (62H) Name Default Description RESERVED P0,RO Reserved LP_FCS P0,RO Link Partner Flow Control Enable Status BIST P0,RO BIST status SRAM BIST fail SRAM BIST pass RESERVED 0,RO Reserved SPEED2 P0,RO Speed Status 10Mbps, 1:100Mbps FDX2 P0,RO Duplex Status half-duplex, 1:full-duplex LINK2 P0,RO Link Status link fail, link 6.13 Port Forward Control Register (65H) Name Default Description LOOPBACK PH0,RW Loop-Back Mode transmitted packet will forward this port itself. MONI_TX PH0,RW Packet Monitored transmitted packets also forward sniffer port. MONI_RX PH0,RW Packet Monitored received packets also forward sniffer port. DIS_BMP PH0,RW Broad/Multicast Monitored received broadcast multicast packets forward sniffer port. Reserved PH0,RW Reserved TX_DIS PH0,RW Packet Transmit Disabled packets forward this port. RX_DIS PH0,RW Packet receive Disabled received packets discarded. ADR_DIS PH0,RW Address Learning Disabled Source Address (SA) field packet learned address table.
Preliminary datasheet DM8203-15-DS-P05 October 2008
DM8203
2-port switch with RMII Interface
6.14 Port Ingress/Egress Control Register (66H) Name Default Description INGRESS PE0,RW Ingress Rate Control These bits define bandwidth threshold that received packets over threshold discarded. 0000: none 0001: 64Kbps 0010: 128Kbps 0011: 256Kbps 0100: 512Kbps 0101: 1Mbps 0110: 2Mbps 0111: 4Mbps 1000: 8Mbps 1001: 16Mbps 1010: 32Mbps 1011: 48Mbps 1100: 64Mbps 1101: 72Mbps 1110: 80Mbps 1111: 88Mbps EGRESS PE0,RW Egress Rate Control These bits define bandwidth threshold that transmitted packets over threshold discarded. 0000: none 0001: 64Kbps 0010: 128Kbps 0011: 256Kbps 0100: 512Kbps 0101: 1Mbps 0110: 2Mbps 0111: 4Mbps 1000: 8Mbps 1001: 16Mbps 1010: 32Mbps 1011: 48Mbps 1100: 64Mbps 1101: 72Mbps 1110: 80Mbps 1111: 88Mbps
Preliminary datasheet DM8203-15-DS-P05 October 2008
DM8203
2-port switch with RMII Interface
6.15 Bandwidth Control Setting Register (67H) Name Default Description BSTH PE0,RW Broadcast Storm Threshold These bits define bandwidth threshold that received broadcast packets over threshold discarded 0000: broadcast storm control 0001: packets/sec 0010: packets/sec 0011: packets/sec 0100: 0101: 0110: 0111: 1000: 1001: 1010: 1011: 1100: 1101: 111X: broadcast storm control CTRL PE0,RW Received Transmitted Bandwidth Control These bits define bandwidth threshold that transmitted received packets over threshold discarded 0000: none 0001: 64Kbps 0010: 128Kbps 0011: 256Kbps 0100: 512Kbps 0101: 1Mbps 0110: 2Mbps 0111: 4Mbps 1000: 8Mbps 1001: 16Mbps 1010: 32Mbps 1011: 48Mbps 1100: 64Mbps 1101: 72Mbps 1110: 80Mbps 1111: 88Mbps 6.16 Port Block Unicast ports Control Register (68H) Name Default Description RESERVED PH0,RW Reserved BLK_UP PH0,RW Ports Unicast Packet Blocked received unicast packets forward assigned ports. Note that assigned port definition: port port
Preliminary datasheet DM8203-15-DS-P05 October 2008
DM8203
2-port switch with RMII Interface
6.17 Port Block Multicast ports Control Register (69H) Name Default Description RESERVED PH0,RW Reserved BLK_MP PH0,RW Ports Multicast Packet Blocked received multicast packets forward assigned ports. 6.18 Port Block Broadcast ports Control Register (6AH) Name Default Description RESERVED PH0,RW Reserved BLK_BP PH0,RW Ports Broadcast Packet Blocked received broadcast packets forward assigned ports. 6.19 Port Block Unknown ports Control Register (6BH) Name Default Description RESERVED PH0,RW Reserved BLK_UKP PH0,RW Ports Unknown Packet Blocked packets with field found address table forward assigned ports. 6.20 Port Priority Queue Control Register (6DH) Name Default Description TAG_OUT PE0,RW Output Packet Tagging Enable transmitted packets containing VLAN tagged field. PRI_DIS PE0,RW Priority Queue Disable Only transmit queue supported this port. WFQUE PE0,RW Weighted Fair Queuing priority weight queue respectively. queue highest priority, next priorities queue respectively. TOS_PRI PE0,RW Priority over VLAN packet with VLAN tag, priority this packet decode from field. TOS_OFF PE0,RW Priority Classification Disable priority information from field packet ignored. PRI_OFF PE0,RW 802.1 Priority Classification Disable priority information from VLAN field ignored. P_PRI PE0,RW Port Base priority priority queue number port base. queue 01=queue 10=queue 11=queue
6.21 Port VLAN Byte Register (6EH) Name Default VID70 PE01,RW VID[7:0]
Description
Preliminary datasheet DM8203-15-DS-P05 October 2008
DM8203
2-port switch with RMII Interface
6.22 Port VLAN High Byte Register (6FH) Name Default PE0,RW [15:13] PE0,RW Tag[12] VID118 PE0,RW VID[11:8] Description
6.23 counters Port Index Register (80H) Name Default Description READY P0,RO counter data ready When this register written with INDEX data, this cleared counter reading progress. After read counter, data loaded into register 81H~84H, this indicate that data ready. reserved 0,RO Reserved INDEX PHS0,RW counter index 0~9, each counter 32-bit Register 81h~84h. Write counter index this register before read them. 6.24 counter Data Register (81H~84H) Name Default Counter0 X,RO Counter's data Counter1 X,RO Counter's data 15~8 Counter2 X,RO Counter's data 23~16 Counter3 X,RO Counter's data 31~24 counter: Byte Counter Registers (INDEX 00H) counter: Uni-cast Packet Counter Registers (INDEX 01H) counter: Multi-cast Packet Counter Registers (INDEX 02H) counter: Discard Packet Counter Registers (INDEX 03H) counter: Error Packet Counter Registers (INDEX 04H) counter: Byte Counter Registers (INDEX 05H) counter: Uni-cast Packet Counter Registers (INDEX 06H) counter: Multi-cast Packet Counter Registers (INDEX 07H) counter: Discard Packet Counter Registers (INDEX 08H) counter: Error Packet Counter Registers (INDEX 09H)
Description
Preliminary datasheet DM8203-15-DS-P05 October 2008
DM8203
2-port switch with RMII Interface
6.25 VLAN grouping table Registers (B0H~BFH) Define port member VLAN group There VLAN group that defined Reg. B0H~BFH. Group defined Reg. B0H, group defined Reg. Name Default Description RESERVED PE0,RO Reserved PORT_P2 PE1,RW Mapping port PORT_P1 PE1,RW Mapping port PORT_P0 PE1,RW Mapping port 6.26 Priority Registers (C0H~CFH) Define 6-bit 3-bit field mapping 2-bit priority queue number. 6-bit type, Reg. "1", Reg. [1:0] define mapping value Reg. [3:2] define mapping value till Reg. [7:6] define value 3-bit type, Reg. [1:0] defines mapping value Reg. [3:2] defines mapping value till Reg. [7:6] define value C0H: C1H: C2H: C3H: Name TOSF TOSE TOSD TOSC Default PE0,RW PE0,RW PE0,RW PE0,RW Description 53H.7 :TOS[7:2]=0FH 53H.7 :TOS[7:2]=0EH 53H.7 :TOS[7:2]=0DH 53H.7 :TOS[7:2]=0CH Name TOSB TOSA TOS9 TOS8 Default PE0,RW PE0,RW PE0,RW PE0,RW Description 53H.7 :TOS[7:2]=0BH 53H.7 :TOS[7:2]=0AH 53H.7 :TOS[7:2]=09H 53H.7 :TOS[7:2]=08H Name TOS7 TOS6 TOS5 TOS4 Default PE0/3,RW PE0/3,RW PE0/2,RW PE0/2,RW Description 53H.7 :TOS[7:2]=07H, otherwise TOS]7:5]=07H 53H.7 :TOS[7:2]=06H, otherwise TOS]7:5]=06H 53H.7 :TOS[7:2]=05H, otherwise TOS]7:5]=05H 53H.7 :TOS[7:2]=04H, otherwise TOS]7:5]=04H Name TOS3 TOS2 TOS1 TOS0 Default PE0/1,RW PE0,/1RW PE0,RW PE0,RW Description 53H.7 :TOS[7:2]=03H, otherwise TOS]7:5]=03H 53H.7 :TOS[7:2]=02H, otherwise TOS]7:5]=02H 53H.7 :TOS[7:2]=01H, otherwise TOS]7:5]=01H 53H.7 :TOS[7:2]=00H, otherwise TOS]7:5]=00H
Preliminary datasheet DM8203-15-DS-P05 October 2008
DM8203
2-port switch with RMII Interface
C4H: C5H: C6H: C7H: C8H: C9H: Name TOS27 TOS26 TOS25 TOS24 Default PE2,RW PE2,RW PE2,RW PE2,RW Description 53H.7 :TOS[7:2]=27H 53H.7 :TOS[7:2]=26H 53H.7 :TOS[7:2]=25H 53H.7 :TOS[7:2]=24H Name TOS23 TOS22 TOS21 TOS20 Default PE2,RW PE2,RW PE2,RW PE2,RW Description 53H.7 :TOS[7:2]=23H 53H.7 :TOS[7:2]=22H 53H.7 :TOS[7:2]=21H 53H.7 :TOS[7:2]=20H Name TOS1F TOS1E TOS1D TOS1C Default PE1,RW PE1,RW PE1,RW PE1,RW Description 53H.7 :TOS[7:2]=1FH 53H.7 :TOS[7:2]=1EH 53H.7 :TOS[7:2]=1DH 53H.7 :TOS[7:2]=1CH Name TOS1B TOS1A TOS19 TOS18 Default PE1,RW PE1,RW PE1,RW PE1,RW Description 53H.7 :TOS[7:2]=1BH 53H.7 :TOS[7:2]=1AH 53H.7 :TOS[7:2]=19H 53H.7 :TOS[7:2]=18H Name TOS17 TOS16 TOS15 TOS14 Default PE1,RW PE1,RW PE1,RW PE1,RW Description 53H.7 :TOS[7:2]=17H 53H.7 :TOS[7:2]=16H 53H.7 :TOS[7:2]=15H 53H.7 :TOS[7:2]=14H Name TOS13 TOS12 TOS11 TOS10 Default PE1,RW PE1,RW PE1,RW PE1,RW Description 53H.7 :TOS[7:2]=13H 53H.7 :TOS[7:2]=12H 53H.7 :TOS[7:2]=11H 53H.7 :TOS[7:2]=10H
Preliminary datasheet DM8203-15-DS-P05 October 2008
DM8203
2-port switch with RMII Interface
CAH: CBH: CCH: CDH: CEH: CFH: Name TOS3F TOS3E TOS3D TOS3C Default PE3,RW PE3,RW PE3,RW PE3,RW Description 53H.7 :TOS[7:2]=3FH 53H.7 :TOS[7:2]=3EH 53H.7 :TOS[7:2]=3DH 53H.7 :TOS[7:2]=3CH Name TOS3B TOS3A TOS39 TOS38 Default PE3,RW PE3,RW PE3,RW PE3,RW Description 53H.7 :TOS[7:2]=3BH 53H.7 :TOS[7:2]=3AH 53H.7 :TOS[7:2]=39H 53H.7 :TOS[7:2]=38H Name TOS37 TOS36 TOS35 TOS34 Default PE3,RW PE3,RW PE3,RW PE3,RW Description 53H.7 :TOS[7:2]=37H 53H.7 :TOS[7:2]=36H 53H.7 :TOS[7:2]=35H 53H.7 :TOS[7:2]=34H Name TOS33 TOS32 TOS31 TOS30 Default PE3,RW PE3,RW PE3,RW PE3,RW Description 53H.7 :TOS[7:2]=33H 53H.7 :TOS[7:2]=32H 53H.7 :TOS[7:2]=31H 53H.7 :TOS[7:2]=30H Name TOS2F TOS2E TOS2D TOS2C Default PE2,RW PE2,RW PE2,RW PE2,RW Description 53H.7 :TOS[7:2]=2FH 53H.7 :TOS[7:2]=2EH 53H.7 :TOS[7:2]=2DH 53H.7 :TOS[7:2]=2CH Name TOS2B TOS2A TOS29 TOS28 Default PE2,RW PE2,RW PE2,RW PE2,RW Description 53H.7 :TOS[7:2]=2BH 53H.7 :TOS[7:2]=2AH 53H.7 :TOS[7:2]=29H 53H.7 :TOS[7:2]=28H
Preliminary datasheet DM8203-15-DS-P05 October 2008
DM8203
2-port switch with RMII Interface
6.27 VLAN Priority Registers (D0H~D1H) Define 3-bit priority field VALN mapping 2-bit priority queue number. D0H: D1H: Name TAG7 TAG6 TAG5 TAG4 Default PE3,RW PE3,RW PE2,RW PE2,RW Description VLAN priority value VLAN priority value VLAN priority value VLAN priority value Name TAG3 TAG2 TAG1 TAG0 Default PE1,RW PE1,RW PE0,RW PE0,RW Description VLAN priority value VLAN priority value VLAN priority value VLAN priority value
Preliminary datasheet DM8203-15-DS-P05 October 2008
DM8203
2-port switch with RMII Interface EEPROM Format
name RESERVED Auto Load Control Vendor Product RESERVED Control RESERVED Control Word 8~15 Description Reserved [1:0] Auto Load Control Vendor Product Reserved Control Reserved 1:0=01: Accept setting WORD 17,18 3:2=01: Accept setting WORD 19~26 5:4=01: Accept setting WORD 27~30 7:6=01: Accept setting WORD 9:8=01: Accept setting WORD 32~39 11:10=01: Accept setting WORD 40~47 15:12 =01: Reserved When word "01", after power reset: This word will loaded Reg. This word 15~8 will loaded Reg. When word "01", after power reset: This word will loaded Reg. This word 15~8 will loaded Reg. When word "01", after power reset: This word will loaded port Reg. This word 15~8 will loaded port Reg. When word "01", after power reset: This word will loaded port Reg. This word 15~8 will loaded port Reg. When word "01", after power reset: This word will loaded port Reg. This word 15~8 will loaded port Reg. When word "01", after power reset: This word will loaded port Reg. This word 15~8 will loaded port Reg. When word "01", after power reset: This word will loaded port Reg. This word 15~8 will loaded port Reg. When word "01", after power reset: This word will loaded port Reg. This word 15~8 will loaded port Reg. Reserved When word "01", after power reset: This word will loaded port Reg. This word 15~8 will loaded port Reg. When word "01", after power reset: This word will loaded port Reg. This word 15~8 will loaded port Reg. When word "01", after power reset:
Preliminary datasheet DM8203-15-DS-P05 October 2008
Switch Control
Switch Control
Port Control
Port Control
Port Control
Port Control
Port Control
Port Control
RESERVED Port VLAN
25-26
Port VLAN
Port VLAN
DM8203
2-port switch with RMII Interface
This word will loaded port Reg. This word 15~8 will loaded port Reg. Reserved When word "01", after power reset: This word will loaded Reg. This word 15~8 will loaded Reg. When word "01", after power reset: This word will loaded Reg. This word 15~8 will loaded Reg. When word "01", after power reset: This word will loaded Reg. This word 15~8 will loaded Reg. When word "01", after power reset: This word will loaded Reg. This word 15~8 will loaded Reg. When word "01", after power reset: This word will loaded Reg. This word 15~8 will loaded Reg. When word "01", after power reset: This word will loaded Reg. This word 15~8 will loaded Reg. When word "01", after power reset: This word will loaded Reg. This word 15~8 will loaded Reg. When word "01", after power reset: This word will loaded Reg. This word 15~8 will loaded Reg. When word "01", after power reset: This word will loaded Reg. This word 15~8 will loaded Reg. When word 11:10 "01", after power reset: This word will loaded Reg. This word 15~8 will loaded Reg. When word 11:10 "01", after power reset: This word will loaded Reg. This word 15~8 will loaded Reg. When word 11:10 "01", after power reset: This word will loaded Reg. This word 15~8 will loaded Reg. When word 11:10 "01", after power reset: This word will loaded Reg. This word 15~8 will loaded Reg. When word 11:10 "01", after power reset: This word will loaded Reg. This word 15~8 will loaded Reg. When word 11:10 "01", after power reset: This word will loaded Reg. This word 15~8 will loaded Reg. When word 11:10 "01", after power reset:
RESERVED VLAN Priority
Port VLAN Group Port VLAN Group Port VLAN Group Port VLAN Group Port VLAN Group Port VLAN Group 10,11 Port VLAN Group 12,13 Port VLAN Group 14,15 Priority
Priority
Priority
Priority
Priority
Priority
Priority
Preliminary datasheet DM8203-15-DS-P05 October 2008
DM8203
2-port switch with RMII Interface
This word will loaded Reg. This word 15~8 will loaded Reg. When word 11:10 "01", after power reset: This word will loaded Reg. This word 15~8 will loaded Reg. Priority
Preliminary datasheet DM8203-15-DS-P05 October 2008
DM8203
2-port switch with RMII Interface Registers Register Description
Name CONTR Reset STATUS Cap. PHYID1 PHYID2 Auto-Neg. Next Advertise Page Link Part. Ability Next Page Auto-Neg. Expansio Specifie 4B5B Config. Specifie Conf/Stat Rsvd Conf/Stat PWDOR Loop back Cap. Speed Auto-N Power select Enable Down Cap. Cap. Cap. Remote Fault Reserved Reserved Isolate Restart Full Auto-N Duplex Reserved Coll. Test Reserved
Reserved
Pream. Auto-N Supr. Compl. 0000 Model 01011
Remote Fault
000_0000 Auto-N Link Jabber Cap. Status Detect Version 0000 Advertised Protocol Selector Field Link Partner Protocol Selector Field
Extd Cap.
Pardet Fault
Next Able
Next Able Pream. Supr.
AutoN Cap. Sleep mode Reserved
Enable
BP_ADP Reserve ALIGN Enable
Reserve Reserve Force Reserve Reserve RPDCTR Reset 100LNK ADDR [4:0] Reserved PD10DR PD100l PDchip PDcrm PDaeq PDdrv
Reserve Reverse Reverse SQUE Enable Reserved Enable Reserve
Auto-N. Monitor [3:0] Polarity Reverse PDecli PDeclo PD10
Specified TSTSE1 TSTSE FORCE_ FORCE_ PREA TX10M NWAY_ Reserved MDIX_C AutoNeg Mdix_fix Mdix_do MonSel1 MonSel0 Reserve PD_valu config TXSD _dlpbk Value MBLE _PWR
RCVER DIS_conn Reversed Receiver Error Counter Disconnect_counter
PSCR
Reversed
PREA AMPLIT TX_PW MBLEX
Reversed
Default register description that follows, default column takes form: <Reset Value>, <Access Type> <Attribute(s)> Where: <Reset Value>: logic logic zero default value <Access Type>: Read only, Read/Write <Attribute (s)>: Self clearing, Value permanently
Preliminary datasheet DM8203-15-DS-P05 October 2008
DM8203
2-port switch with RMII Interface
Basic Mode Control Register (BMCR) Name Reset Default Description RW/SC Reset 1=Software reset 0=Normal operation This sets status controls registers their default states. This bit, which self-clearing, will keep returning value until reset process completed Loopback Loop-back control register Loop-back enabled Normal operation When 100Mbps operation mode, setting this cause descrambler lose synchronization produce 720ms "dead time" before valid data appears receive outputs Speed Select 100Mbps 10Mbps Link speed selected either this auto-negotiation. When auto-negotiation enabled set, this will return auto-negotiation selected medium type Auto-negotiation Enable Auto-negotiation enabled, will auto-negotiation status Power Down While power-down state, should respond management transactions. During transition power-down state while power-down state, should generate spurious signals 1=Power down 0=Normal operation 0,RW Isolate Force application. 0,RW/SC Restart Auto-negotiation Restart auto-negotiation. Re-initiates auto-negotiation process. When auto-negotiation disabled (bit this register cleared), this function should cleared. This self-clearing will keep returning value until auto-negotiation initiated DM8203. operation auto-negotiation process will affected management entity that clears this Normal operation 1,RW Duplex Mode Full duplex operation. Duplex selection allowed when Auto-negotiation disabled (bit this register cleared). With auto-negotiation enabled, this reflects duplex capability selected auto-negotiation Normal operation
Preliminary datasheet DM8203-15-DS-P05 October 2008
Loopback
Speed selection
Auto-negotiation enable Power down
Isolate Restart Auto-negotiation
Duplex mode
DM8203
2-port switch with RMII Interface
Collision test 0,RW Collision Test Collision test enabled. When set, this will cause signal asserted response assertion TX_EN internal interface. Normal operation Reserved Read ignore write
Reserved
0,RO
Basic Mode Status Register (BMSR) Name 100BASE-T4 Default 0,RO/P Description 100BASE-T4 Capable DM8203 able perform 100BASE-T4 mode DM8203 able perform 100BASE-T4 mode 100BASE-TX Full Duplex Capable DM8203 able perform 100BASE-TX full duplex mode DM8203 able perform 100BASE-TX full duplex mode 100BASE-TX Half Duplex Capable DM8203 able perform 100BASE-TX half duplex mode DM8203 able perform 100BASE-TX half duplex mode 10BASE-T Full Duplex Capable DM8203 able perform 10BASE-T full duplex mode DM8203 able perform 10BASE-TX full duplex mode 10BASE-T Half Duplex Capable DM8203 able perform 10BASE-T half duplex mode DM8203 able perform 10BASE-T half duplex mode Reserved Read ignore write Frame Preamble Suppression will accept management frames with preamble suppressed will accept management frames with preamble suppressed Auto-negotiation Complete Auto-negotiation process completed Auto-negotiation process completed Remote Fault Remote fault condition detected (cleared read chip reset). Fault criteria detection method DM8203 implementation specific. This will after ANLPAR (bit register address remote fault condition detected Auto Configuration Ability DM8203 able perform auto-negotiation DM8203 able perform auto-negotiation Link Status Valid link established (for either 10Mbps 100Mbps operation) Link established
100BASE-TX full-duplex 100BASE-TX half-duplex
1,RO/P
1,RO/P
10BASE-T full-duplex 10BASE-T half-duplex Reserved preamble suppression
1,RO/P
1,RO/P
10-7
0,RO 1,RO
Auto-negotiation Complete Remote fault
0,RO
Auto-negotiation ability Link status
1,RO/P
0,RO
Preliminary datasheet DM8203-15-DS-P05 October 2008
DM8203
2-port switch with RMII Interface
link status implemented with latching function, that occurrence link failure condition causes link status cleared remain cleared until read management interface Jabber Detect Jabber condition detected jabber This implemented with latching function. Jabber conditions will this unless cleared read this register through management interface DM8203 reset. This works only 10Mbps mode Extended Capability Extended register capable Basic register capable only
Jabber detect
Extended capability
1,RO/P
Identifier Register (PHYID1) Identifier Registers work together single identifier DM8203. Identifier consists concatenation Organizationally Unique Identifier (OUI), vendor's model number, model revision number. DAVICOM Semiconductor's IEEE assigned 00606E. 15-0 Name OUI_MSB Default <0181h> Description Most Significant Bits This register stores (00606E) this register respectively. most significant bits ignored (the IEEE standard refers these
Identifier Register (PHYID2) 15-10 Name OUI_LSB Default <101110>, RO/P <001011>, RO/P <0000>, RO/P Description Least Significant Bits (00606E) mapped this register respectively Vendor Model Number Five bits vendor model number mapped (most significant Model Revision Number Five bits vendor model revision number mapped (most significant
VNDR_MDL
MDL_REV
Preliminary datasheet DM8203-15-DS-P05 October 2008
DM8203
2-port switch with RMII Interface
Auto-negotiation Advertisement Register (ANAR) This register contains advertised abilities this DM8203 device they will transmitted link partner during Auto-negotiation. Name Description Next page Indication next page available Next page available DM8203 next page, this permanently 0,RO Acknowledge Link partner ability data reception acknowledged acknowledged DM8203's auto-negotiation state machine will automatically control this outgoing bursts appropriate time during auto-negotiation process. Software should attempt write this bit. Remote Fault Local device senses fault condition fault detected Reserved Write ignore read Flow Control Support Controller chip supports flow control ability Controller chip doesn't support flow control ability RO/P 100BASE-T4 Support 100BASE-T4 supported local device 100BASE-T4 supported DM8203 does support 100BASE-T4 this permanently 100BASE-TX Full Duplex Support 100BASE-TX full duplex supported local device 100BASE-TX full duplex supported 100BASE-TX Support 100BASE-TX half duplex supported local device 100BASE-TX half duplex supported 10BASE-T Full Duplex Support 10BASE-T full duplex supported local device 10BASE-T full duplex supported 10BASE-T Support 10BASE-T half duplex supported local device 10BASE-T half duplex supported <00001>, Protocol Selection Bits These bits contain binary encoded protocol selector supported this node <00001> indicates that this device supports IEEE 802.3 CSMA/CD Default 0,RO/P
12-11
Reserved
TX_FDX
TX_HDX
10_FDX
10_HDX
Selector
Preliminary datasheet DM8203-15-DS-P05 October 2008
DM8203
2-port switch with RMII Interface
Auto-negotiation Link Partner Ability Register (ANLPAR) This register contains advertised abilities link partner when received during Auto-negotiation. Name Description Next Page Indication Link partner, next page available Link partner, next page available Acknowledge Link partner ability data reception acknowledged acknowledged DM8203's auto-negotiation state machine will automatically control this from incoming bursts. Software should attempt write this Remote Fault Remote fault indicated link partner remote fault indicated link partner Reserved Read ignore write Flow Control Support Controller chip supports flow control ability link partner Controller chip doesn't support flow control ability link partner 100BASE-T4 Support 100BASE-T4 supported link partner 100BASE-T4 supported link partner 100BASE-TX Full Duplex Support 100BASE-TX full duplex supported link partner 100BASE-TX full duplex supported link partner 100BASE-TX Support 100BASE-TX half duplex supported link partner 100BASE-TX half duplex supported link partner 10BASE-T Full Duplex Support 10BASE-T full duplex supported link partner 10BASE-T full duplex supported link partner 10BASE-T Support 10BASE-T half duplex supported link partner 10BASE-T half duplex supported link partner <00000>, Protocol Selection Bits Link partner's binary encoded protocol selector Default
12-11
Reserved
TX_FDX
TX_HDX
10_FDX
10_HDX
Selector
Preliminary datasheet DM8203-15-DS-P05 October 2008
DM8203
2-port switch with RMII Interface
Auto-negotiation Expansion Register (ANER) 15-5 Name Reserved Default RO/LH Description Reserved Read ignore write Local Device Parallel Detection Fault fault detected parallel detection function. fault detected parallel detection function Link Partner Next Page Able LP_NP_ABLE Link partner, next page available LP_NP_ABLE Link partner, next page Local Device Next Page Able NP_ABLE DM8203, next page available NP_ABLE DM8203, next page DM8203 does support this function, this always Page Received link code word page received. This will automatically cleared when register (register read management Link Partner Auto-negotiation Able this indicates that link partner supports Auto-negotiation
LP_NP_ABLE
NP_ABLE
0,RO/P
PAGE_RX
LP_AN_ABLE
DAVICOM Specified Configuration Register (DSCR) Name BP_4B5B Default 0,RW Description Bypass 4B5B Encoding 5B4B Decoding 4B5B encoder 5B4B decoder function bypassed Normal 4B5B 5B4B operation Bypass Scrambler/Descrambler Function Scrambler descrambler function bypassed Normal scrambler descrambler operation Bypass Symbol Alignment Function Receive functions (descrambler, symbol alignment symbol decoding functions) bypassed. Transmit functions (symbol encoder scrambler) bypassed Normal operation BYPASS ADPOK Force signal detector (SD) active. This register debug only, release customer 1=Forced 0=Normal operation Reserved Force application 100BASE-TX Mode Control 100BASE-TX operation 100BASE-FX operation Reserved
BP_SCR
BP_ALIGN
BP_ADPOK
Reserved
Reserved
Preliminary datasheet DM8203-15-DS-P05 October 2008
DM8203
2-port switch with RMII Interface
Reserved F_LINK_100 Reserved Force application. Force Good Link 100Mbps Normal 100Mbps operation Force 100Mbps good link status This useful diagnostic purposes Reserved Force application. Reserved Force application. Reduced Power Down Control Enable This used enable automatic reduced power down Disable automatic reduced power down Enable automatic reduced power down Reset State Machine When writes this bit, state machines will reset. This self-clear after reset completed Preamble Suppression Control frame preamble suppression control preamble suppression preamble suppression Sleep Mode Writing this will cause entering Sleep mode power down circuit except oscillator clock generator circuit. When waking from Sleep mode (write this configuration will back state before sleep; state machine will reset Reserved Force application.
Reserved Reserved RPDCTR-EN
SMRST
MFPSC
SLEEP
Reserved
Preliminary datasheet DM8203-15-DS-P05 October 2008
DM8203
2-port switch with RMII Interface
DAVICOM Specified Configuration Status Register (DSCSR) Name 100FDX Default Description 100M Full Duplex Operation Mode After auto-negotiation completed, results will written this bit. this means operation mode 100M full duplex mode. software read [15:12] which mode selected after auto-negotiation. This invalid when auto-negotiation mode 100M Half Duplex Operation Mode After auto-negotiation completed, results will written this bit. this means operation mode 100M half duplex mode. software read [15:12] which mode selected after auto-negotiation. This invalid when auto-negotiation mode Full Duplex Operation Mode After auto-negotiation completed, results will written this bit. this means operation mode Full Duplex mode. software read [15:12] which mode selected after auto-negotiation. This invalid when auto-negotiation mode Half Duplex Operation Mode After auto-negotiation completed, results will written this bit. this means operation mode half duplex mode. software read [15:12] which mode selected after auto-negotiation. This invalid when auto-negotiation mode Reserved Read ignore write Reserved Reserved Address first address transmitted received address (bit station management entity connected multiple entities must know appropriate address each Auto-negotiation Monitor Bits These bits debug only. auto-negotiation status will written these bits. IDLE state Ability match Acknowledge match Acknowledge match fail Consistency match Consistency match fail Parallel detects signal link ready Parallel detects signal link ready fail Auto-negotiation completed successfully
100HDX
10FDX
10HDX
Reserved Reserved Reserved PHYADR[4:
0,RW 0,RW
ANMB[3:0]
Preliminary datasheet DM8203-15-DS-P05 October 2008
DM8203
2-port switch with RMII Interface
8.10 10BASE-T Configuration/Status (10BTCSR) Name Reserved LP_EN Default Description Reserved Read ignore write Link Pulse Enable Transmission link pulses enabled Link pulses disabled, good link condition forced This valid only 10Mbps operation Heartbeat Enable Heartbeat function enabled Heartbeat function disabled When DM8203 configured full duplex operation, this will ignored (the collision/heartbeat function invalid full duplex mode) Squelch Enable Normal squelch squelch Jabber Enable Enables disables Jabber function when DM8203 10BASE-T full duplex 10BASE-T transceiver Loopback mode Jabber function enabled Jabber function disabled 10Mbps Serial Mode (only valid test mode) Force application. Reserved Read ignore write Polarity Reversed When this indicates that 10Mbps cable polarity reversed. This automatically cleared 10BASE-T module
1,RW
SQUELCH
JABEN
SERIAL Reserved POLR
8.11 Power down Control Register (PWDOR) Description Reserved Read ignore write PD10DRV Vendor power down control test PD100DL Vendor power down control test PDchip Vendor power down control test PDcrm Vendor power down control test PDaeq Vendor power down control test PDdrv Vendor power down control test PDedi Vendor power down control test PDedo Vendor power down control test PD10 Vendor power down control test When selected, power down value control Register 15-9 Name Reserved Default
Preliminary datasheet DM8203-15-DS-P05 October 2008
DM8203
2-port switch with RMII Interface
8.12 (Specified config) Register Name Default TSTSE1 0,RW TSTSE2 0,RW FORCE_TXSD 0,RW Description Vendor test select control Vendor test select control Force Signal Detect force signal 100BASE-TX mode normal signal. Vendor test select control Preamble Saving Control when set, 10BASE-T transmit preamble count reduced. When register set, 12-bit preamble reduced; otherwise 22-bit preamble reduced. transmit preamble count normal 10BASE-T mode 10BASE-T mode Transmit Power Saving Control enable transmit power saving 10BASE-T mode disable transmit power saving 10BASE-T mode Auto-negotiation Power Saving Control disable power saving during auto-negotiation period enable power saving during auto-negotiation period Reserved
FORCE_FEF PREAMBLEX
0,RW 0,RW
TX10M_PWR
1,RW
NWAY_PWR
0,RW
Reserved MDIX_CNTL
Read ignore write MDI/MDIX,RO polarity MDI/MDIX value MDIX mode mode AutoNeg_dpbk 0,RW Auto-negotiation Loopback test internal digital auto-negotiation Loopback normal. Mdix_fix Value MDIX_CNTL force value: When Mdix_down MDIX_CNTL value depend register value. Mdix_down 0,RW MDIX Down Manual force MDI/MDIX. Enable Auto-MDIX Disable Auto-MDIX MDIX_CNTL value depend Reg.14H.bit5 MonSel1 0,RW Vendor monitor select MonSel0 0,RW Vendor monitor select Reserved 0,RW Reserved Force application. PD_value 0,RW Power down control value Decision value each field Reg.13H. power down normal
Preliminary datasheet DM8203-15-DS-P05 October 2008
DM8203
2-port switch with RMII Interface
8.13 DAVICOM Specified Receive Error Counter Register (RECR) 15-0 Name Rcv_ Err_ Default Description Receive Error Counter Receive error counter that increments upon detection RXER. Clean read this register.
8.14 DAVICOM Specified Disconnect Counter Register (DISCR) 15-8 Name Reserved Disconnect Counter Default Description Reserved Disconnect Counter that increment upon detection disconnection. Clean read this register.
8.15 Power Saving Control Register (PSCR) 15-12 Name RESERVED PREAMBLEX Default 0,RO 0,RW Description RESERVED Preamble Saving Control when both 10and register set, 10BASE-T transmit preamble count reduced. 12-bit preamble reduced. 22-bit preamble reduced. Transmit Amplitude Control Disabled when cable unconnected with link partner, amplitude reduced power saving. disable Transmit amplitude reduce function Transmit Power Saving Control Disabled when cable unconnected with link partner, driving current transmit reduced power saving. disable transmit driving power saving function RESERVED
AMPLITUDE
0,RW
TX_PWR
0.RW
RESERVED
0,RO
Preliminary datasheet DM8203-15-DS-P05 October 2008
DM8203
2-port switch with RMII Interface Functional Description
Serial Management Interface
Host
SMI_CK SMI_DIO
(SMI device address 0~3)
MDIO
Host
Only host allowed acccess SMI_CK, SMI_DIO
DM8203
MDIO MDIO Port2
(PHY Address
External accessed MDC, MDIO
Host Read Frame Structure
SMI_CK SMI_DIO Read "1"s Idle Preamble Data Read Idle SMI_R_8203
Code
Device Address Write
Register Address
Turn Around
Host Write Frame Structure
SMI_CK SMI_DIO Write "1"s Idle Preamble Data Idle
Code
Device Address
Register Address Write
Turn Around
SMI_W_8203
DM8203 supports type serial management interface (SMI), Host SMI. application illustrated below. Host consists pins, SMI_CK another SMI_DIO. User access DM8203's EEPROM, registers, counters Configuration registers through Host SMI. format following. <Device Address> field frame means device address that configured strap
Preliminary datasheet DM8203-15-DS-P05 October 2008
(TXD2_0 TXD2_1). <Register Address> field frame mapped address control status register DM8203. read/writ data valid byte (D7~D0) <Data> field, high byte (D15~D8) data reserved. DM8203 supports auto-polling configuring speed, duplex mode, 802.3x flow control capability external (Port2) MDC, MDIO. More detail description frame format refer section 9.3.2.
DM8203
2-port switch with RMII Interface
Switch function: 9.2.1 Address Learning DM8203 self-learning mechanism learning addresses incoming packets real time. DM8203 stores addresses, port number time stamp information Hash-based Address Table. learn unicast address entry. switch engine updates address table with entry incoming packet's Source Address (SA) does exist incoming packet valid (non-error legal length). Besides, DM8203 option disable address learning individual port. This feature register 9.2.2 Address Aging time stamp information address table used aging process. switch engine updates time stamp whenever corresponding receives. switch engine would delete entry time stamp updated period time. period programmed disabled through register 52h. 9.2.3 Packet Forwarding DM8203 forwards incoming packet according following decision: (1). Multicast/Broadcast, packet forwarded ports, except port which packet received. (2). Switch engine would look address table based when incoming packets UNICAST. found address table, packet treated multicast packet forward other ports. found destination port number different source port number, packet forward destination port. (3). Switch engine also look VLAN, Port Monitor setting other forwarding constraints forwarding decision, more detail will discuss later sections. DM8203 will filter incoming packets under following conditions: (1). Error packets, including errors, alignment errors, illegal size errors. (2). PAUSE packets.
Preliminary datasheet DM8203-15-DS-P05 October 2008
(3). incoming packet UNICAST destination port number equal source port number. 9.2.4 Inter-Packet (IPG) idle time between valid packets same port. typical number bits time. other word, value 9.6u 10Mbps 960n 100Mbps. 9.2.5 Back-off Algorithm DM8203 implements binary exponential back-off algorithm half-duplex mode compliant IEEE standard 802.3. 9.2.6 Late Collision Late Collision type collision. collision error occurs after first times data transmitted, packet dropped. 9.2.7 Full Duplex Flow Control DM8203 supports IEEE standard 802.3x flow control frames both transmit receive sides. receive side, DM8203 will defer transmitting next normal frames, receives pause frame from link partner. transmit side, DM8203 issues pause frame with maximum pause time when internal resources such received buffers, transmit queue transmit descriptor ring unavailable. Once resources available, DM8203 sends pause frame with zero pause time allows traffic resume immediately. 9.2.8 Half Duplex Flow Control DM8203 supports half-duplex backpressure. inducement same full duplex mode. When flow control required, DM8203 sends pattern results collision. flow control ability register 61h.
DM8203
2-port switch with RMII Interface
9.2.9 Partition Mode DM8203 provides partition mode each port, register 61h. port enters partition mode when more than consecutive collisions occurred. partition mode port continuous transmit will receive. port returned normal operation mode when good packet seen wire. detail description partition mode represent following: (1). Entering Partition State port will enter Partition State when either following conditions occurs: port detects collision every consecutive re-transmit attempts same packet. port detects single collision which occurs more than times. Transmit defer timer time out, which indicates transmitting packet deferred long. (2). While Partition state: port will continue transmit pending packet, regardless collision detection, will allow usual Back-off Algorithm. Additional packets pending transmission will transmitted, while ignoring internal collision indication. This frees ports transmit buffers which would otherwise filled expense other ports buffers. assumption that partition signifying system failure situation (bad connection/cable/station), thus dropping packets small price cost halting switch buffer full condition. (3). Exiting from Partition State Port exits from Partition State, following successful packet transmission. successful packet transmission defined collisions were detected first bits transmission. 9.2.10 Broadcast Storm Filtering DM8203 option limit traffic broadcast multicast packets, protect switch from lower bandwidth availability. There types broadcast storm control, throttling broadcast packet only, other includes multicast. This feature through register 61h. broadcast storm threshold
Preliminary datasheet DM8203-15-DS-P05 October 2008
programmed EEPROM register 67h, default setting broadcast storm protecting.
9.2.11 Bandwidth Control DM8203 supports types bandwidth control each port. ingress egress bandwidth rate controlled separately, other combined together, this function through register 61h. bandwidth control disabled default. separate bandwidth control mode, threshold rate defined register 66h. combined mode, defined register 67h. behavior bandwidth control below: (1).For ingress control, flow control function enabled, Pause packet will transmitted. ingress packets will dropped flow control disabled. (2).For egress control, egress port will transmit packets. other hand, ingress bandwidth source port will throttled that prevent packets from forwarding. (3).In combined mode, ingress egress bandwidth over threshold, bandwidth will throttled. 9.2.12 Port Monitoring Support DM8203 supports "Port Monitoring" function port base, detail below: (1). Sniffer Port Monitor Port There only port selected "sniffer port" register 52h, multiple ports "receive monitor port" "transmit monitor port" per-port register 65h. (2).Receive monitor packets received "receive monitor port" send copy "sniffer port". example, port "receive monitor port" port selected "sniffer port". packet received form port predestined port after forwarding decision, DM8203 will forward port port end. (3).Transmit monitor packets transmitted "transmit monitor port" send copy "sniffer port". example, port "transmit monitor port" port selected "sniffer port". packet received from port predestined port after forwarding decision, DM8203 will forward port port
DM8203
2-port switch with RMII Interface
end. (4).Exception DM8203 optional setting that broadcast/multicast packets monitored (see register 65h). It's useful avoid unnecessary bandwidth. 9.2.13 VLAN Support 9.2.13.1 Port-Based VLAN DM8203 supports port-based VLAN default, groups. Each port default called PVID (Port VID, register 6Fh). DM8203 used 4-bytes PVID index mapped register B0h~BFh, define VLAN groups. instance, intend partition DM8203's ports into three groups. Port port group port port group finally, port port group this case, setting below: (1). PVID Port 0x01h. (2). PVID Port 0x02h. (3). PVID Port 0x03h. (4). register 0x06h. (5). register 0x05h. (6). register 0x03h.
9.2.13.2 802.1Q-Based VLAN Regarding IEEE 802.1Q standard, Tag-based VLAN uses extra identify VLAN membership frame across VLAN-aware switch/router. tagged frame four bytes longer than untagged frame contains bytes TPID (Tag Protocol Identifier) bytes (Tag Control Information).
Dest.
Src.
Length/Type
Data
Standard frame
Dest.
Src.
TPID
0x8100 bytes
Length Type
Data
Tagged frame
Priority
bits
DM8203 also supports 802.1Q-based VLAN groups, specified register 53h. It's obvious that tagged packets assigned several different VLANs which determined according inside VLAN Tag. Therefore, operation similar port-based VLAN. DM8203 used 4-bytes received packet with VLAN VLAN Group Mapping Register (B0h~BFh) configure VLAN partition. destination port received packet same VLAN group with received port, will discarded. 9.2.13.3 Tag/Untag
bits
VLAN_9013.vsd
bits User define each port port Un-tag port register 802.1Q-based VLAN mode. operation Un-tag explain below conditions: (1). Receive untagged packet forward Un-tag port. Received packet will forward destination port without modification. (2). Receive tagged packet forward Un-tag port. DM8203 will remove from packet recalculate before sending out. (3). Receive untagged packet forward port.
Preliminary datasheet DM8203-15-DS-P05 October 2008
DM8203
2-port switch with RMII Interface
DM8203 will insert PVID when untagged packet enters port, recalculate before delivering (4). Receive tagged packet forward port. Received packet will forward destination port without modification. 9.2.14 Priority Support DM8203 supports Quality Service (QoS) mechanism multimedia communication such VoIP video conferencing. DM8203 provides three priority classifications: Port-based, 802.1p-based DiffServ-based priority. next section more detail. DM8203 offers four level queues transmit per-port based. DM8203 provides packet scheduling algorithms: Weighted Fair Queuing Strict Priority Queuing. Weighted Fair Queuing (WFQ) based their priority queue weight. Queues with larger weights more service than smaller. This mechanism highly efficient bandwidth smooth traffic. Strict Priority Queuing (SPQ) based priority only. Packet highest priority queue transmitted first. next highest-priority queue work until last queue empties, This feature register 6Dh. 9.2.14.1 Port-Based Priority Port based priority simplest scheme default. Each port 2-bit priority value index splitting ingress packets corresponding transmit queue. This value register 6Dh. 9.2.14.2 802.1p-Based Priority 802.1p priority disabled register 6Dh, enabled default. DM8203 extracts 3-bit priority field from received packet with 802.1p VLAN tag, maps this field against VLAN Priority Registers (D0h~D1h) determine which transmit queue designated. VLAN Priority programmable. 9.2.14.3 DiffServ-Based Priority DiffServ based priority uses most significant 6-bit field standard IPv4 header, maps this field against Priority Registers (C0h~CFh) determine which transmit queue designated. Priority programmable too. addition, User only refer most significant 3-bit field optionally, register 53h.
Preliminary datasheet DM8203-15-DS-P05 October 2008
DM8203
2-port switch with RMII Interface
Interface 9.3.1 data interface DM8203 port provides Media Independent Interface (MII) defined IEEE 802.3u standard (Clause 22). consists nibble wide receive data bus, nibble wide transmit data bus, control signals facilitate data transfers between DM8203 port external device reverse MII). TXD2 (transmit data) nibble bits) data that driven DM8203 synchronously with respect TXC2. each TXC2 period, which TXE2 asserted, TXD2 (3:0) accepted transmission external device. TXC2 (transmit clock) from external device continuous clock that provides timing reference transfer TXE2, TXD2. DM8203 drive 25MHz clock configured reversed mode. TXE2 (transmit enable) from DM8203 port indicates that nibbles being presented transmission external device. RXD2 (receive data) nibble bits) data that sampled DM8203 port synchronously with respect RXC2. each RXC2 period which RXDV2 asserted, RXD2 (3:0) transferred from external device DM8203 port reconciliation layer. RXC2 (receive clock) from external device DM8203 port reconciliation layer continuous clock that provides timing reference transfer RXDV2, RXD2, RXER2 signals. RXDV2 (receive data valid) input from external device indicates that external device presenting recovered decoded nibbles DM8203 port reconciliation layer. interpret receive frame correctly reconciliation layer, RXDV2 must encompass frame, starting later than Start-of-Frame delimiter excluding End-Stream delimiter. RXER2 (receive error) input from external device synchronously with respect RXC2. RXER2 will asserted more clock periods indicate reconciliation layer that error detected somewhere frame being
transmitted from external device DM8203 port MAC. CRS2 (carrier sense) asserted external device when either transmit receive medium non-idle, de-asserted external device when transmit receive medium idle. CRS2 also output mode when DM8203 port configured reversed mode. COL2 (collision detection) asserted external device, when both transmit receive medium non-idle, de-asserted external device when either transmit receive medium idle. COL2 also output mode when DM8203 port configured reversed mode. 9.3.2 Serial Management serial management interface consists data interface, basic register DM8203 port serial management interface register set. Through this interface possible control configure multiple devices, include internal ports, status error information, determine type capabilities attached device(s). DM8203 default polling ports basic registers link, duplex, speed status automatically. Alternatively, DM8203 programmed read write registers ports section 6.8~11 DM8203 management functions correspond specification IEEE 802.3u-1995 (Clause registers through with vendor-specific registers 16,17, 24~27. read/write operation, management data frame 64-bits long starts with contiguous logic bits (preamble) synchronization clock cycles MDC. Start Frame Delimiter (SFD) indicated <01> pattern followed operation code (OP) indicates Read operation <01> indicates Write operation. read operation, 2-bit turnaround (TA) filing between Register Address field Data field provided MDIO avoid contention. Following turnaround time, 16-bit data read from written onto management registers.
Preliminary datasheet DM8203-15-DS-P05 October 2008
DM8203
2-port switch with RMII Interface
9.3.3 Serial Management Interface serial control interface uses simple two-wired serial interface obtain control status physical layer through interface. serial control interface consists (Management Data Clock), MDI/O (Management Data Input/Output) signals. MDIO bi-directional shared devices.
9.3.4 Management Interface Read Frame Structure
MDIO Read "1"s Idle Preamble Address Write Data Read Idle
Code
Register Address
Turn Around
9.3.5 Management Interface Write Frame Structure
MDIO Write "1"s Idle Preamble Address Data Idle
Code
Register Address Write
Turn Around
Preliminary datasheet DM8203-15-DS-P05 October 2008
DM8203
2-port switch with RMII Interface
Internal functions 9.4.1 100Base-TX Operation transmitter section contains following functional blocks: 4B5B Encoder Scrambler Parallel Serial Converter NRZI Converter NRZI MLT-3 MLT-3 Driver 9.4.1.1 4B5B Encoder 4B5B encoder converts 4-bit (4B) nibble data generated Reconciliation Layer into 5-bit (5B) code group transmission, reference Table This conversion required control packet data combined code groups. 4B5B encoder substitutes first bits preamble with code-group pair (11000 10001) upon transmit. 4B5B encoder continues replace subsequent preamble data nibbles with corresponding code-groups. transmit packet, upon desertions Transmit Enable signal from Reconciliation layer, 4B5B encoder injects code-group pair (01101 00111) indicating frame. After code-group pair, 4B5B encoder continuously injects IDLEs into transmit data stream until Transmit Enable asserted next transmit packet detected. scrambling data, total energy presented cable randomly distributed over wide frequency range. Without scrambler, energy levels cable could peak beyond limitations frequencies related repeated sequences, like continuous transmission IDLE symbols. scrambler output combined with data from code-group encoder logic function. result scrambled data stream with sufficient randomization decrease radiated emissions critical frequencies. 9.4.1.3 Parallel Serial Converter Parallel Serial Converter receives parallel scrambled data from scrambler, serializes (converts from parallel serial data stream). serialized data stream then presented NRZI encoder block 9.4.1.4 NRZI Encoder After transmit data stream been scrambled serialized, data must NRZI encoded compatibility with TP-PMD standard, 100Base transmission over Category-5 unshielded twisted pair cable. 9.4.1.5 MLT-3 Converter MLT-3 conversion accomplished converting data stream output, from NRZI encoder into binary data streams, with alternately phased logic event. 9.4.1.6 MLT-3 Driver binary data streams created MLT-3 converter twisted pair output driver, which converts these streams current sources alternately drives either side transmit transformer's primary winding, resulting minimal current MLT-3 signal.
9.4.1.2 Scrambler scrambler required control radiated emissions (EMI) spreading transmit energy across frequency spectrum media connector twisted pair cable 100Base-TX operation.
Preliminary datasheet DM8203-15-DS-P05 October 2008
DM8203
2-port switch with RMII Interface
9.4.1.7 4B5B Code Group
Symbol
Meaning Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data Idle Error Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid
code 3210 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 undefined 0101 0101 undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined Table
Code 43210 11110 01001 10100 10101 01010 01011 01110 01111 10010 10011 10110 10111 11010 11011 11100 11101 11111 11000 10001 01101 00111 00100 00000 00001 00010 00011 00101 00110 01000 01100 10000 11001
Preliminary datasheet DM8203-15-DS-P05 October 2008
DM8203
2-port switch with RMII Interface
9.4.2 100Base-TX Receiver 100Base-TX receiver contains several function blocks that convert scrambled 125Mb/s serial data synchronous 4-bit nibble data. receive section contains following functional blocks: Signal Detect Digital Adaptive Equalization MLT-3 Binary Decoder Clock Recovery Module NRZI Decoder Serial Parallel Descrambler Code Group Alignment 4B5B Decoder 9.4.2.1 Signal Detect signal detects function meets specifications mandated ANSI XT12 TP-PMD 100Base-TX standards both voltage thresholds timing parameters. 9.4.2.2 Adaptive Equalization When transmitting data over copper twisted pair cable high speed, attenuation based frequency becomes concern. high speed twisted pair signaling, frequency content transmitted signal vary greatly during normal operation based randomness scrambled data stream. This variation signal attenuation, caused frequency variations, must compensated ensure integrity received data. order ensure quality transmission when employing MLT-3 encoding, compensation must able adapt various cable lengths cable types depending installed environment. selection long cable lengths given implementation requires significant compensation, which will over-killed situation that includes shorter, less attenuating cable lengths. Conversely, selection short intermediate cable lengths requiring less compensation will cause serious under-compensation longer length cables. Therefore, compensation equalization must adaptive ensure proper conditioning received signal independent cable length.
9.4.2.3 MLT-3 NRZI Decoder DM8203 decodes MLT-3 information from Digital Adaptive Equalizer into NRZI data. 9.4.2.4 Clock Recovery Module Clock Recovery Module accepts NRZI data from MLT-3 NRZI decoder. Clock Recovery Module locks onto data stream extracts reference clock. extracted synchronized clock data presented NRZI decoder.
9.4.2.5 NRZI transmit data stream required NRZI encoded compatibility with TP-PMD standard 100Base-TX transmission over Category-5 unshielded twisted pair cable. This conversion process must reversed receive end. NRZI decoder receives NRZI data stream from Clock Recovery Module converts data stream presented Serial Parallel conversion block. 9.4.2.6 Serial Parallel Serial Parallel Converter receives serial data stream from NRZI converter. converts data stream parallel data presented descrambler. 9.4.2.7 Descrambler Because scrambling process requires control radiated emissions transmit data streams, receiver must descramble receive data streams. descrambler receives scrambled parallel data streams from Serial Parallel converter, descrambles data streams, presents data streams Code Group alignment block.
Preliminary datasheet DM8203-15-DS-P05 October 2008
DM8203
2-port switch with RMII Interface
9.4.2.8 Code Group Alignment Code Group Alignment block receives un-aligned data from descrambler converts into code group data. Code Group Alignment occurs after detected subsequent data aligned fixed boundary. 9.4.2.9 4B5B Decoder 4B5B Decoder functions look-up table that translates incoming code groups into (Nibble) data. When receiving frame, first 5-bit code groups receive start-of-frame delimiter (J/K symbols). symbol pair stripped nibbles preamble pattern substituted. last code groups end-of-frame delimiter (T/R Symbols). symbol pair also stripped from nibble, presented Reconciliation layer. 9.4.3 10Base-T Operation 10Base-T transceiver IEEE 802.3u compliant. When DM8203 operating 10Base-T mode, coding scheme Manchester. Data processed transmit presented nibble format, converted serial stream, then Manchester encoded. When receiving, stream, encoded Manchester, decoded converted into nibble format. 9.4.4 Collision Detection half-duplex operation, collision detected when transmit receive channels active simultaneously. Collision detection disabled full duplex operation. 9.4.5 Carrier Sense Carrier Sense (CRS) asserted half-duplex operation during transmission reception data. During full-duplex mode, asserted only during Receive operations.
9.4.6 Auto-Negotiation objective Auto-negotiation provide means exchange information between linked devices automatically configure both devices take maximum advantage their abilities. important note that Auto-negotiation does test characteristics linked segment. Auto-Negotiation function provides means device advertise supported modes operation remote link partner, acknowledge receipt understanding common modes operation, reject un-shared modes operation. This allows devices both ends segment establish link best common mode operation. more than common mode exists between devices, mechanism provided allow devices resolve single mode operation using predetermined priority resolution function. Auto-negotiation also provides parallel detection function devices that support Auto-negotiation feature. During Parallel detection there exchange information configuration. Instead, receive signal examined. discovered that signal matches technology, which receiving device supports, connection will automatically established using that technology. This allows devices support Auto-negotiation support common mode operation establish link.
Auto-MDIX Functional Descriptions DM8203 supports automatic detect cable connection type, MDI/MDIX (straight through/cross over). manual configuration register MDIX still accepted. When automatic, polarity MDI/MDIX controlled timing generated 16-bits LFSR. switching cycle time located from 200ms 420ms. polarity control always switch until detect received signal. After selected MDIX, This feature able detect required cable connection type. (Straight through crossed over) make correction automatically
Preliminary datasheet DM8203-15-DS-P05 October 2008
DM8203
2-port switch with RMII Interface
from DM8203
RX+/- RJ45
from DM8203 MDI: MDIX:
TX+/- RJ45
Preliminary datasheet DM8203-15-DS-P05 October 2008
DM8203
2-port switch with RMII Interface Electrical Characteristics
10.1 Absolute Maximum Ratings Symbol Parameter VCC3 3.3V Supply Voltage VCCI 1.8V core power supply AVDD3 Analog power supply 3.3V AVDDI Analog power supply 1.8V Input Voltage (VIN) Storage Temperature range TSTG Ambient Temperature Lead Temperature (TL, soldering, sec.). 10.2 Operating Conditions Symbol VCC3 VCCI AVDD3 AVDDI (Power Dissipation) Parameter 3.3V Supply Voltage 1.8V core power supply Analog power supply 3.3V Analog power supply 1.8V 100BASE-TX 10BASE-TX Min. 3.135 1.71 3.135 1.71 Typ. Max. 3.465 1.89 3.465 1.89 Unit Conditions 1.8V only 3.3V only idle, 1.8V only utilization, 1.8V only 100% utilization, 1.8V only 3.3V only 1.8V only 3.3V only Min. -0.3 -0.3 -0.3 -0.3 -0.5 Max. 1.95 1.95 +150 +260 Unit Conditions
Lead-free Device
Auto-negotiation cable
Preliminary datasheet DM8203-15-DS-P05 October 2008
DM8203
2-port switch with RMII Interface
10.3 Electrical Characteristics Symbol Inputs Outputs Receiver VICM Parameter Input Voltage Input High Voltage Input Leakage Current Input High Leakage Current Output Voltage Output High Voltage Min. Typ. Max. Unit Conditions Vcond1 Vcond1 0.0V, Vcond1 3.3V, Vcond1 -4mA Termination Across Peak Peak Peak Peak Absolute Value Absolute Value
RX+/RX- Common Mode Input Voltage Transmitter VTD100 100TX+/- Differential Output Voltage VTD10 10TX+/- Differential Output Voltage ITD100 100TX+/- Differential Output Current ITD10 10TX+/- Differential Output Current
Note: Vcond1 VCC3 3.3V, VCCI 1.8V, AVDD3 3.3V, AVDDI 1.8V. 10.4 characteristics 10.4.1 Power Reset Timing
PWRST#
Strap pins
EECS
Symbol
Parameter PWRST# Period Strap hold time with PWRST# PWRST# high EECS high PWRST# high EECS burst
Min.
Typ.
Max.
Unit
Conditions
Preliminary datasheet DM8203-15-DS-P05 October 2008
DM8203
2-port switch with RMII Interface
10.4.2 Port Interface Transmit Timing
TXC2
TXE2 TXD2_3~0
Symbol Parameter TXE2,TXD2_3~0 Setup Time TXE2,TXD2_3~0 Hold Time 10.4.3 Port Interface Receive Timing
Min.
Typ.
Max.
Unit
RXC2
RXER2,RXDV2 RXD2_3~0
Symbol Parameter RXER2, RXDV2,RXD2_3~0 Setup Time RXER2, RXDV2,RXD2_3~0 Hold Time
Min.
Typ.
Max.
Unit
Preliminary datasheet DM8203-15-DS-P05 October 2008
DM8203
2-port switch with RMII Interface
10.4.4 Management host Interface Timing
SMI_CK MDIO (drived DM8203) SMI_DIO MDIO (drived exetrnal MII) SMI_DIO
Symbol
Parameter SMI_CK Frequency MDIO SMI_DIO DM8203 Setup Time MDIO SMI_DIO DM8203 Hold Time MDIO SMI_DIO External Setup Time MDIO SMI_DIO External Hold Time
Min.
Typ. 0.52
Max.
Unit
Preliminary datasheet DM8203-15-DS-P05 October 2008
DM8203
2-port switch with RMII Interface
10.4.5 EEPROM timing
EECS EECK EEDIO
Symbol
Parameter EECS Setup Time EECS Hold Time EECK Frequency EEDIO Setup Time output state EEDIO Hold Time output state EEDIO Setup Time input state EEDIO Hold Time input state
Min.
Typ. 2080 0.38 2100
Max.
Unit
Preliminary datasheet DM8203-15-DS-P05 October 2008
DM8203
2-port switch with RMII Interface Application circuit
11.1 Main circuit
DVDD_33V DVDD_18V DVDD_5V 220uF 0.1uF 0.1uF 0.1uF 0.1uF 220uF 0.1uF DVDD_33V AP1117-3.3V 220uF 0.1uF DVDD_33V DVDD_33V
1N4148
RESET_IC_(AP1701DW)
force link mode (100Mbus FULL mode) mode (100Mbps mode) Reverse-MII mode RMII mode DVDD_33V EEPROM
TXE2 EECK TXD2_2 TXC2 TXD2_3 Port mode Port mode EECS TXER2 TXD2_0 TXD2_1 MDIO TXD2_0 TXD2_1 RXER2 DC-JACK JUMPER JUMPER RXC2 4.7k 4.7k 4.7k 4.7k DVDD_5V TXD2_0 TXD2_1 TXD2_2 TXD2_3 CRS2 COL2 TXE2 RXER2 TXC2 RXC2 RXD2_0 RXD2_1 RXD2_2 RXD2_3 SMI_DIO JUMPER JUMPER JUMPER NC(4.7k) NC(4.7k) NC(4.7k) NC(4.7k) 4.7k 4.7k 4.7k 4.7k
AVDD_33V
AVDD_18V LNK0_LED SPD0_LED LNK1_LED SPD1_LED LEDA LEDA LEDA LEDA
DVDD_33V
PWRST#
10uF
220uF
0.1uF
0.1uF
220uF
0.1uF
0.1uF
power reset (select use)
DVDD_33V
AVDD_33V EECS EECK EEDIO AVDD_18V
F.B/120/SO805 VCNTL 2SB1386 DVDD_18V
JUMPER
EEPROM
93LC46
DVDD_33V AVDD_18V 0.1uF RX0RX0+ TX01 49.9/1% 75/1% 75/1% 75/1% 0.1uF 0.01uF/2KV RJ45_SPD RJ45_LINK 74HC04 SPD0_LED Disable Port MDIO pull Low, TXE2 float off). Enable please remove MDIO pull resister (R51) RXMCT TX16 RJ-45_LED
RDNC TDNC
LED2+ LED216
0.1uF
0.1uF
TX0+ 49.9/1%
F.B/120/SO805
25MHz/49US 22pF 22pF
MAGCOM_HS9024 49.9/1% 49.9/1%
LED1+ LED1-
F.B/120/SO805
1.4K/1% RX0+ RX0TX0+ TX0RX1+ RX1TX1+ TX1AVDD_33V AVDD_18V DVDD_18V DVDD_33V
0.1uF
0.1uF
VREF
0.1uF
0.1uF 0.1uF FX_SD FX_SD_TEST
VCNTL VREF LNK1_LED SPD1_LED LNK0_LED SPD0_LED SMI_CK SMI_DIO
BGRESG BGRES AVDD33 RX0RX0+ AGND TX0TX0+ AVDD18 AVDD33 RX1RX1+ AGND TX1TX1+ AVDD18
LNK0_LED
74HC04
VCNTL VREF DVDD33 DGND LNK1_LED SPD1_LED LNK0_LED SPD0_LED TEST2 SMI_CK DVDD18 SMI_DIO TEST3 DGND
DM8203E Port switch
DVDD33 MDIO DGND TXD2_3 TXD2_2 TXD2_1 DGND TXD2_0 TXE2 DVDD18 TXC2 DVDD33 TXER2 CRS2 DGND
TEST1 DGND PWRST# EECS EECK EEDIO DVDD33 RXD2_0 RXD2_1 DGND RXD2_2 RXD2_3 RXDV2 RXC2 RXER2 COL2
PWRST# EECS EECK EEDIO RXD2_0 RXD2_1 RXD2_2 RXD2_3 RXDV2 RXC2 RXER2 COL2
0.1uF
49.9/1%
49.9/1% AVDD_18V 49.9/1% RDNC TDNC RXNC TXNC RJ-45 RX1+ RX1- 127/1% 127/1% FX_RX+ FX_RXFX_SD FX_TXFX_TX+ 83/1% 83/1%
127/1%69/1%
RX1-
TP_RXTP_RX+ TP_TXTP_TX+ 49.9/1%
RX1+ TX1TX1+
TX1TX1+
MAGCOM_HS9016 75/1% 75/1% 75/1% 0.1uF 0.01uF/2KV
83/1% 182/1%
DM8203E 0.1uF
Title TXD2_3 TXD2_2 TXD2_1 TXD2_0 TXE2 TXER2 CRS2 MDIO TXC2 Size Date:
DAVICOM Semiconductor Inc.
DM8203E_EVB circuit DM8203-E5 Document Number DM8203E Tuesday August 2008 Sheet V1.0
Preliminary datasheet DM8203-15-DS-P05 October 2008
MDIO RXDV2 SMI_CK DVDD_33V 69/1% 182/1% Fiber_3.3v PWRST# TXER2
DVDD_33V DVDD_5V
HEADER_16X2
DM8203
2-port switch with RMII Interface
11.2 Application Reverse
Preliminary datasheet DM8203-15-DS-P05 October 2008
DM8203
2-port switch with RMII Interface Package Information
Pins LQFP Package Outline Information:
Symbol
0.05 1.35 0.17 0.17 0.09 0.09
0.45 0.08 0.08 0.20
Dimension 1.40 0.22 0.20 12.00 10.00 12.00 10.00 0.50 0.60 1.00
1.60 0.15 1.45 0.27 0.23 0.20 0.16
0.75 0.20
Dimension inch 0.063 0.002 0.006 0.053 0.055 0.057 0.007 0.009 0.011 0.007 0.008 0.009 0.004 0.008 0.004 0.006 0.472 0.394 0.472 0.394 0.020 0.018 0.024 0.030 0.039 0.003 0.003 0.008 0.008
Dimension include resin fin. dimensions base metric system. General appearance spec should base final visual inspection spec.
Preliminary datasheet DM8203-15-DS-P05 October 2008
DM8203
2-port switch with RMII Interface Ordering Information
Part Number DM8203EP Count Package LQFP (Pb-free) reference purposes only. DAVICOM's terms conditions printed order acknowledgment govern sales DAVICOM. DAVICOM will bound terms inconsistent with these unless DAVICOM agrees otherwise writing. Acceptance buyer's orders shall based these terms.
Disclaimer
information appearing this publication believed accurate. Integrated circuits sold DAVICOM Semiconductor covered warranty patent indemnification provisions stipulated terms sale only. DAVICOM makes warranty, express, statutory, implied description regarding information this publication regarding information this publication regarding freedom described chip(s) from patent infringement. FURTHER, DAVICOM MAKES WARRANTY MERCHANTABILITY FITNESS PURPOSE. DAVICOM reserves right halt production alter specifications prices time without notice. Accordingly, reader cautioned verify that data sheets other information this publication current before placing orders. Products described herein intended normal commercial applications. Applications involving unusual environmental reliability requirements, e.g. military equipment medical life support equipment, specifically recommended without additional processing DAVICOM such applications. Please note that application circuits illustrated this document
Company Overview
DAVICOM Semiconductor Inc. develops manufactures integrated circuits integration into data communication products. mission design produce products that industry's best value Data, Audio, Video, Internet/Intranet applications. achieve this goal, have built organization that able develop chipsets response evolving technology requirements customers while still delivering products that meet their cost requirements.
Products
offer only products that satisfy high performance requirements which compatible with major hardware software standards. currently available soon released products based proprietary designs deliver high quality, high performance chipsets that comply with modem communication standards Ethernet networking standards.
Contact Windows
additional information about DAVICOM products, contact Sales department
Headquarters
Hsin-chu Office: No.6 Li-Hsin Science-based Park, Hsin-chu City, Taiwan, R.O.C. TEL: +886-3-5798797 FAX: +886-3-5646929 MAIL: sales@davicom.com.tw HTTP: http://www.davicom.com.tw WARNING
Conditions beyond those listed absolute maximum destroy damage products. addition, conditions sustained periods near limits operating ranges will stress temporarily (and permanently) affect damage structure, performance and/or function. Preliminary datasheet DM8203-15-DS-P05 October 2008
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