ISL6411 November 2003 FN9081.2 Triple Output, Low-Noise Regu

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ISL6411 November 2003 FN9081.2 Triple Output, Low-Noise Regu

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L6414 Sheet Data
ISL6411
November 2003 FN9081.2
Triple Output, Low-Noise Regulator with Integrated Reset Circuit
ISL6411 ultra noise triple output regulator with microprocessor reset circuit optimized powering wireless chip sets. accepts input voltage range 3.0V 3.6V provides three regulated output voltages: 1.8V (LDO1), 2.84V (LDO2), another ultra clean 2.84V (LDO3). chip logic provides sequencing between LDO1 LDO2 BBP/MAC supply voltage outputs. LDO3 features ultra noise that does typically exceed 30µV stability. High integration thin Quad Flat No-lead (QFN) package makes ISL6411 ideal choice power many today's small form factor industry standard wireless cards, such PCMCIA, mini-PCI Cardbus-32. ISL6411 uses internal PMOS transistor pass device. SHDN controls LDO1 LDO2 outputs whereas SHDN3 controls LDO3 output. Internal voltage sequencing insures that LDO1 output (1.8V supply) always stabilized before LDO2 turned When powering down, power LDO2 removed before LDO1 output goes off. ISL6411 also integrates RESET function, which eliminates need additional RESET required WLAN applications. asserts RESET signal whenever supply voltage drops below preset threshold, keeping asserted least 25ms after risen above reset threshold. output fault detection circuit indicates loss regulation three outputs. Other features include over current protection, thermal shutdown reverse battery protection.
Features
Small DC/DC Converter Size Three LDOs RESET Circuitry Low-Profile 4x4mm Package High Output Current LDO1, 1.8V. 500mA LDO2, 2.84V. 300mA LDO3, 2.84V. 200mA Ultra-Low Dropout Voltage LDO2, 2.84V. 125mV (typ.) 300mA LDO3, 2.84V. 100mV (typ.) 200mA Ultra-Low Output Voltage Noise <30µVRMS (typ.) LDO3 (VCO Supply) Stable with Smaller Ceramic Output Capacitors Voltage Sequencing BBP/MAC Analog Supplies Extensive Protection Monitoring Features Over current protection Short circuit protection Thermal shutdown Reverse battery protection FAULT indicator Logic-Controlled Dual Shutdown Pins Integrated Microprocessor Reset Circuit Programmable Reset Delay Complimentary Reset Outputs Proven Reference Design Total WLAN System Solution Package Option Compliant JEDEC PUB95 MO-220 Quad Flat Leads Product Outline Near Chip-Scale Package Footprint Improves Efficiency Thinner Profile Pb-Free Plus Anneal Available (RoHS Compliant)
Ordering Information
PART NUMBER ISL6411IR ISL6411IRZ (Note) TEMP. RANGE (°C) PACKAGE PKG. DWG. L16.4x4 L16.4x4
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials 100% matte plate termination finish, which RoHS compliant compatible with both SnPb Pb-free soldering operations. Intersil Pb-free products classified Pb-free peak reflow temperatures that meet exceed Pb-free requirements IPC/JEDEC STD-020.
Applications
PRISM® PRISM GTTM, PRISM Chipsets WLAN Cards PCMCIA, Cardbus32, MiniPCI Cards Compact Flash Cards Hand-Held Instruments
CAUTION: These devices sensitive electrostatic discharge; follow proper Handling Procedures. 1-888-INTERSIL 1-888-468-3774 Intersil (and design) registered trademark Intersil Americas Inc. Copyright Intersil Americas Inc. 2003. Rights Reserved. PRISM® PRISM GTare trademarks GlobespanVirata, Inc. other trademarks mentioned property their respective owners.
ISL6411 Pinout
ISL6411 (QFN) VIEW
RESET FAULT
RESET SHDN SHDN3 OUT3
OUT1 OUT2
GND3
Typical Application Schematic
+3.3V 3.3µF
RESET
FAULT
+1.8V VOUT1 +2.84V VOUT2
0.033µF 0.033µF 3.3µF 3.3µF
0.01µF
RESET SHDN SHDN3
ISL6411
OUT1 OUT2
+2.84V VOUT3
3.3µF
0.033µF
OUT3 GND3
FN9081.2 November 2003
ISL6411 Functional Block Diagram
LDO1 BAND REF. 1.2V OUT1
WINDOW COMP
THERMAL SHUT DOWN 150°C LDO2 FAULT WINDOW COMP OUT2
CONTROL LOGIC SHDN SHDN3 LDO3
OUT3
ENABLES
WINDOW COMP
RESET
RESET
RESET
GND3
FN9081.2 November 2003
ISL6411
Absolute Maximum Ratings (Note
VIN, SHDN/SHDN3 GND/GND3 -7.0V 7.0V SET, FAULT GND/GND3 -0.3V 7.0V Output Current (Continuous) LDO1 500mA LDO2 300mA LDO3 200mA Classification Class
Thermal Information
Thermal Resistance (Typical, Notes (°C/W) (°C/W) Package. Maximum Junction Temperature (Plastic Package) -55°C 150°C Maximum Storage Temperature Range -65°C 150°C Maximum Lead Temperature (Soldering 10s) 300°C Operating Temperature Range -40°C 85°C
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
NOTES: voltages with respect GND. measured free with component mounted high effective thermal conductivity test board with "direct attach" features. Tech Brief TB379. "case temp" location center exposed metal package underside. Tech Brief TB379.
Electrical Specifications
PARAMETER GENERAL SPECIFICATIONS Voltage Range Operating Supply Current Shutdown Supply Current SHDN/SHDN3 Input Threshold
+3.3V, Compensation Capacitor 33nF, 25°C, Unless Otherwise Noted. TEST CONDITIONS UNITS
IOUT SHDN/SHDN3 VIH, 3.6V VIL, 3.6V COUT 10µF, VOUT final value Rising 75mV Hysteresis
2.45
0.25 2.65
FAULT Output Voltage Thermal Shutdown Temperature (Note Thermal Shutdown Hysteresis Start-up Time Input Undervoltage Lockout (Note LDO1 SPECIFICATIONS Output Voltage (VOUT1) Output Voltage Accuracy Line Regulation Load Regulation Maximum Output Current (IOUT1) (Note Output Current Limit (Note Output Voltage Noise LDO2 SPECIFICATIONS Output Voltage (VOUT2) Output Voltage Accuracy Maximum Output Current (IOUT2) (Note Output Current Limit (Note Dropout Voltage (Note Line Regulation
ISINK
IOUT 10mA 3.0V 3.6V, IOUT 10mA IOUT 10mA 500mA -1.5 -0.15 -1.5 0.55 10Hz 100kHz, COUT 4.7µF, IOUT 50mA
0.15
µVRMS
IOUT 10mA 3.6V -1.5 IOUT 300mA 3.0V 3.6V, IOUT 10mA -0.15
2.84
0.15
FN9081.2 November 2003
ISL6411
Electrical Specifications
PARAMETER Load Regulation Output Voltage Noise +3.3V, Compensation Capacitor 33nF, 25°C, Unless Otherwise Noted. (Continued) TEST CONDITIONS IOUT 10mA 300mA 10Hz 100kHz, IOUT 10mA COUT 2.2µF COUT 10µF LDO3 SPECIFICATIONS Output Voltage (VOUT3) Output Voltage Accuracy Maximum Output Current (IOUT3) (Note Output Current Limit (Note Dropout Voltage (Note Line Regulation Load Regulation Output Voltage Noise IOUT 200mA 3.0V 3.6V, IOUT 10mA IOUT 10mA 200mA 10Hz 100kHz, IOUT 10mA COUT 2.2µF COUT 10µF RESET BLOCK SPECIFICATIONS RESET Threshold RESET Threshold Hysteresis (Note RESET Delay RESET/RESET Active Timeout Period (Notes NOTES: Specifications -40°C guaranteed design/characterization, production tested. dropout voltage defined VOUT when VOUT 50mV below value VOUT VOUT 0.5V. RESET time linear with slope 2.5ms/nF. Thus, 10nF (0.01µF) RESET time 25ms; 100nF (0.1µF) RESET time would 250ms. Guaranteed design, production tested. 100mV 2.564 2.630 2.696 µVRMS µVRMS IOUT 10mA 3.6V -1.5 -0.15 2.84 0.15 µVRMS µVRMS UNITS
Typical Performance Curves
0.140 0.120 0.100 0.080 0.060 0.040 0.020 0.000 0.00 0.100 0.090 0.080 0.070 0.060 0.050 0.040 0.030 0.020 0.010 0.05 0.10 0.15 0.20 (Amps) 0.25 0.30 0.000 0.00 0.05 0.10 (Amps) 0.15 0.30
FIGURE LD02 DROPOUT VOLTAGE
FIGURE LD03 DROPOUT VOLTAGE
FN9081.2 November 2003
ISL6411 Typical Performance Curves (Continued)
INPUT OUTPUT VOLTAGE VOLTAGE (mV) INPUT OUTPUT VOLTAGE VOLTAGE (mV) VOUT 1.8V LOAD 50mA VOUT 2.84V LOAD 50mA
TIME (1ms/DIV)
TIME (1ms/DIV)
FIGURE LINE REGULATION RESPONSE (VOUT1)
FIGURE LINE REGULATION RESPONSE (VOUT2)
INPUT OUTPUT VOLTAGE VOLTAGE (mV)
VOUT 2.84V LOAD 50mA
LOAD OUTPUT VOLTAGE CURRENT (mA) DEVIATION (mV)
VOUT 1.8V 3.3V
TIME (1ms/DIV)
TIME (2ms/DIV)
FIGURE LINE REGULATION RESPONSE (VOUT3)
FIGURE LOAD REGULATION RESPONSE (VOUT1)
LOAD OUTPUT VOLTAGE CURRENT (mA) DEVIATION (mV)
LOAD OUTPUT VOLTAGE CURRENT (mA) DEVIATION (mV)
VOUT 2.84V 3.3V
VOUT 2.84V 3.3V
TIME (2ms/DIV)
TIME (2ms/DIV)
FIGURE LOAD REGULATION RESPONSE (VOUT2)
FIGURE LOAD REGULATION RESPONSE (VOUT3)
FN9081.2 November 2003
ISL6411 Typical Performance Curves (Continued)
LOAD REGULATION LOAD REGULATION TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE LD01 LOAD REGULATION TEMPERATURE
FIGURE LD02 LOAD REGULATION TEMPERATURE
LINE REGULATION (%/V) TEMPERATURE (°C) LOAD REGULATION
0.04 0.03 0.02 0.01 -0.01 -0.02 -0.03 -0.04
-0.05
TEMPERATURE (°C)
FIGURE LD03 LOAD REGULATION TEMPERATURE
FIGURE LD01 LINE REGULATION TEMPERATURE
LINE REGULATION (%/V) LINE REGULATION (%/V) -0.01 -0.02 -0.03 -0.04 -0.05
-0.002 -0.004 -0.006 -0.008 -0.001 -0.012 -0.014
-0.06
TEMPERATURE (°C)
-0.016
TEMPERATURE (°C)
FIGURE LD02 LINE REGULATION TEMPERATURE
FIGURE LD03 LINE REGULATION TEMPERATURE
FN9081.2 November 2003
ISL6411 Typical Performance Curves (Continued)
OPERATING CURRENT (µA) 8.25 8.15 8.05 OPERATING CURRENT (µA) TEMPERATURE (°C) TEMPERATURE (°C)
FIGURE SHUTDOWN CURRENT TEMPERATURE
FIGURE OPERATING CURRENT TEMPERATURE
DROPOUT VOLTAGE (mV) TEMPERATURE (°C) DROPOUT (mV)
TEMPERATURE (°C)
FIGURE LD02 DROPOUT VOLTAGE TEMPERATURE
FIGURE LD03 DROPOUT VOLTAGE TEMPERATURE
VOLTAGE
TIME (µs)
FIGURE SHUTDOW
FN9081.2 November 2003
ISL6411 Descriptions
OUT1 This output LDO1. Bypass with minimum 2.2µF, capacitor stable operation. Supply input pins. Connect input power source. Bypass with 2.2µF capacitor GND. Both pins must tied together board, close Ground LDO1 LDO2. Compensation Capacitor LDO1. Connect 0.033µF capacitor from GND. SHDN Shutdown input LDO1 LDO2. Connect normal operation. Drive SHDN turn LDO1 LDO2. OUT2 This output LDO2. Bypass with minimum 2.2µF, capacitor stable operation. Timing RESET circuit pulse width. Compensation capacitor LDO2. Connect 0.033µF capacitor from GND. OUT3 This output LDO3. Bypass with minimum 2.2µF, capacitor GND3 stable operation. GND3 Ground LDO3. Compensation capacitor LDO3. Connect 0.033µF capacitor from GND3. SHDN3 Shutdown input LDO3. Connect normal operation. Drive SHDN3 turn LDO3. FAULT FAULT output LDO's. This output combined LDO1, LDO2 LDO3. When regulation, FAULT goes LOW; when SHDN inputs low, FAULT will high (refer Figure 19). Connect GND, unused. RESET This active-LOW output push-pull output stage integrated reset supervisory circuit. reset circuit monitors asserts RESET output this pin, falls below RESET threshold. RESET output remains LOW, while voltage below reset threshold, least 25ms, after rises above RESET threshold. RESET This active-HIGH output push-pull output stage integrated reset supervisory circuit. reset circuit monitors asserts RESET output this pin, falls below RESET threshold. RESET output remains HIGH, while voltage below RESET threshold, least 25ms, after rises above RESET threshold.
Functional Description
ISL6411 3-in-1 multi-output, dropout, regulator designed wireless chipset power applications. supplies three fixed output voltages 1.8V, 2.84V 2.84V. Each consists 1.2V reference, error amplifier, MOSFET driver, P-Channel pass transistor, dual-mode comparator internal feedback voltage divider. 1.2V band reference connected error amplifier's inverting input. error amplifier compares this reference selected feedback voltage amplifies difference. MOSFET driver reads error signal applies appropriate drive P-Channel pass transistor. feedback voltage lower then reference voltage, pass transistor gate pulled lower, allowing more current pass increasing output voltage. feedback voltage higher then reference voltage, pass transistor gate driven higher, allowing less current pass output. output voltage back through internal resistor divider connected OUT1/2/3 pins. Additional blocks include output over-current protection, reverse battery protection, thermal sensor, fault detector, RESET function shutdown logic.
Internal P-Channel Pass Transistors
ISL6411 features typical RDS(ON) P-channel MOSFET pass transistors. This provides several advantages over similar designs using bipolar pass transistors. P-Channel MOSFET requires base drive, which reduces quiescent current considerably. based regulators waste considerable current dropout when pass transistor saturates. They also high base drive currents under large loads. ISL6411 does suffer from these problems.
Integrated RESET MAC/Baseband Processors
ISL6411 includes microprocessor supervisory block. This block eliminates extra RESET external components needed wireless chipset applications. This block performs single function; asserts RESET signal whenever supply voltage decreases below preset threshold, keeping asserted programmable time (set external capacitor after voltage risen above RESET threshold. push pull output stage reset circuit provides both active-Low active-HIGH output. This function guaranteed correct state down reset comparator designed ignore transients pin. RESET threshold ISL6411 2.63V typical. addition issuing reset microprocessor during power-up, power down brownout conditions, this block relatively immune short duration, negative-going transients/glitches.
FN9081.2 November 2003
ISL6411
Output Voltages
ISL6411 provides fixed output voltages Wireless Chipset applications. Internal trimmed resistor networks typical output voltages shown here: VOUT1 1.8V; VOUT2 2.84V; VOUT3 2.84V. ISL6411 package features exposed thermal underside. This lowers thermal resistance package providing direct heat conduction path from board. Additionally, ISL6411's ground (GND/GND3) performs dual function providing electrical connection system ground channeling heat away. Connect exposed backside system ground using large ground plane, through multiple vias ground plane layer.
Shutdown
Driving SHDN input puts both LDO1 LDO2 shutdown mode. Driving SHDN3 input puts LDO3 shutdown mode. Pulling SHDN SHDN3 pins simultaneously, puts complete chip into shutdown mode, supply current drops typical. Both SHDN SHDN3 inputs have internal pull-up resistors, that normal operation outputs always enabled; external pull-up resistors required. During shutdown mode using SHDN pin, FAULT output will remain HIGH (refer Figure 19).
Reverse Input Protection
ISL6411 unique protection scheme that limits reverse supply current less than when falls below GND. circuitry monitors polarity these pins, disconnecting internal circuitry parasitic diodes when applied voltage reversed. This feature prevents device from overheating damaging improperly installed input supply.
Current Limit
ISL6411 monitors controls pass transistor's gate voltage limit output current. current limit LDO1 550mA, LDO2 330mA LDO3 250mA. output shorted ground without damaging part current limit thermal protection features.
Integrator Circuitry
ISL6411 uses external 33nF compensation capacitor minimizing load line regulation errors lowering output noise. When output voltage shifts varying load current input voltage, integrator capacitor voltage raised lowered compensate systematic offset error amplifier. Compensation limited minimize transient overshoot when device goes dropout, current limit, thermal shutdown.
Thermal Overload Protection
Thermal overload protection limits total power dissipation ISL6411. When junction temperature (TJ) exceeds +150°C, thermal sensor sends signal shutdown logic, turning pass transistor allowing cool. pass transistor turns again after IC's junction temperature typically cools 20°C, resulting pulsed output during continuous thermal overload conditions. Thermal overload protection protects ISL6411 against fault conditions. continuous operation, exceed absolute maximum junction temperature rating +150°C.
Fault-Detection Circuitry
FAULT monitors three outputs regulation well fault conditions such current limit thermal shutdown. FAULT output goes outputs regulation device fault modes. addition, fault-detection circuitry detects when inputto-output voltage differential LDO2/3 (<90mV) insufficient ensure good load line regulation output. During shutdown mode using SHDN pin, FAULT output will remain HIGH (refer Figure 19).
Operating Region Power Dissipation
maximum power dissipation ISL6411 depends thermal resistance package circuit board, temperature difference between junction ambient air, rate flow. power dissipated device where Iout1 (Vin Vout1) Iout2 (Vin Vout2) Iout3 (Vin- Vout3) maximum power dissipation Pmax (Tjmax Ta)/JA Where Tjmax 150°C, ambient temperature, thermal resistance from junction surrounding environment.
Applications Information
Capacitor Selection Regulator Stability
Capacitors required ISL6411's input output stable operation over entire load range full temperature range. >1µF capacitor input ISL6411. input capacitor lowers source impedance input supply. Larger capacitor values lower provides better PSRR line transient response. input capacitor must located distance more then inches from pins returned clean analog ground. good quality ceramic tantalum used input capacitor. output capacitor must meet requirements minimum amount capacitance three
FN9081.2 November 2003
ISL6411
LDO's. ISL6411 specifically designed work with small ceramic output capacitors. output capacitor's affects stability output noise. output capacitor with less insure stability optimum transient response. stable operation, ceramic capacitor whose value minimum 3.3µF recommended Vout1 300mA output current 2.2µF recommended Vout2 Vout3 each 200mA load current. There upper limit output capacitor value. Larger capacitor reduce noise improve load transient response, stability PSRR. output capacitor should located very close Vout pins minimize impact board inductances should returned clean analog ground.
Noise, PSSR Transient Response
ISL6411 designed operate with dropout voltages quiescent current while still maintaining good noise, transient response, rejection. When operating from noisy sources, improved supply-noise rejection transient response achieved increasing values input output bypass capacitors through passive filtering techniques. ISL6411 load transient response graph presented application note An1036. Increasing output capacitor value decreasing attenuates overshoot.
Input-Output (Dropout) Voltage
regulator's minimum input-output voltage differential dropout voltage) determines lowest usable supply voltage. battery-powered systems, this determines useful end-of-life battery voltage. Because ISL6411 uses P-channel MOSFET pass transistor, dropout voltage function RDS(ON) (typically 0.5) multiplied load current.
FN9081.2 November 2003
ISL6411 Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP)
L16.4x4
LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT JEDEC MO-220-VGGC ISSUE MILLIMETERS SYMBOL 0.25 0.35 1.95 1.95 0.23 0.80 NOMINAL 0.90 0.20 0.28 4.00 3.75 2.10 4.00 3.75 2.10 0.65 0.60 0.60 0.75 0.15 2.25 2.25 0.38 1.00 0.05 1.00 NOTES Rev. 10/02 NOTES: Dimensioning tolerancing conform ASME Y14.5-1994. number terminals. refer number terminals each dimensions millimeters. Angles degrees. Dimension applies metallized terminal measured between 0.15mm 0.30mm from terminal tip. configuration identifier optional, must located within zone indicated. identifier either mold mark feature. Dimensions exposed pads which provide improved electrical thermal performance. Nominal dimensions provided assist with Land Pattern Design efforts, Intersil Technical Brief TB389. Features dimensions present when Anvil singulation method used present singulation. Depending method lead termination edge package, maximum 0.15mm pull back (L1) maybe present. minus equal greater than 0.3mm.
Intersil U.S. products manufactured, assembled tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications viewed www.intersil.com/design/quality
Intersil products sold description only. Intersil Corporation reserves right make changes circuit design, software and/or specifications time without notice. Accordingly, reader cautioned verify that data sheets current before placing orders. Information furnished Intersil believed accurate reliable. However, responsibility assumed Intersil subsidiaries use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Intersil subsidiaries.
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FN9081.2 November 2003

ISL6411 November 2003 FN9081.2 Triple Output, Low-Noise Regu

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