X4163, X4165 16K, November 2007 FN8120.2 Supervisor wit

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X4163, X4165 16K, November 2007 FN8120.2 Supervisor wit

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SSIBLE DataL880 Sheet
X4163, X4165
16K,
November 2007 FN8120.2
Supervisor with EEPROM
FEATURES Selectable watchdog timer detection reset assertion -Four standard reset threshold voltages -Adjust reset threshold voltage using special programming sequence -Reset signal valid power CMOS -<20µA standby current, watchdog -<1µA standby current, watchdog -3mA active current 16Kbits EEPROM -64-byte page write mode -Self-timed write cycle -5ms write cycle time (typical) Built-in inadvertent write protection -Power-up/power-down protection circuitry -Block Lock pages, all, none) 400kHz 2-wire interface 2.7V 5.5V power supply operation Available Packages SOIC TSSOP Pb-free plus anneal available (RoHS compliant)
DESCRIPTION X4163, X4165 combines four popular functions, Power-on Reset Control, Watchdog Timer, Supply Voltage Supervision, Serial EEPROM Memory package. This combination lowers system cost, reduces board space requirements, increases reliability. Applying power device activates power reset circuit which holds RESET/RESET active period time. This allows power supply oscillator stabilize before processor execute code. Watchdog Timer provides independent protection mechanism microcontrollers. When microcontroller fails restart timer within selectable time interval, device activates RESET/RESET signal. user selects interval from three preset values. Once selected, interval does change, even after cycling power. device's detection circuitry protects user's system from voltage conditions, resetting system when falls below minimum trip point. RESET/RESET asserted until returns proper operating level stabilizes. Four industry standard VTRIP thresholds available, however, Intersil's unique circuits allow threshold reprogrammed meet custom requirements fine-tune threshold applications requiring higher precision.
BLOCK DIAGRAM
Watchdog Transition Detector Data Register Command Decode Control Logic Threshold Reset logic Block Lock Control Protect Logic Status Register EEPROM Array RESET (X4163) RESET (X4165) Reset Watchdog Timebase Watchdog Timer Reset
VTRIP
Power Voltage Reset Generation
CAUTION: These devices sensitive electrostatic discharge; follow proper Handling Procedures. 1-888-INTERSIL 1-888-468-3774 Intersil (and design) registered trademark Intersil Americas Inc. Copyright Intersil Americas Inc. 2005-2006. Rights Reserved other trademarks mentioned property their respective owners.
X4163, X4165 Ordering Information
PART NUMBER RESET (ACTIVE LOW) X4163S8-4.5A PART MARKING X4163 PART NUMBER RESET (ACTIVE HIGH) X4165S8-4.5A X4165S8Z-4.5A (Note) X4165S8I-4.5A X4165S8IZ-4.5A (Note) X4165V8-4.5A X4165V8Z-4.5A (Note) X4165V8I-4.5A X4165V8IZ-4.5A (Note) X4165S8-2.7 X4165S8Z-2.7 (Note) X4165S8I-2.7 X4165S8IZ-2.7 (Note) X4165V8-2.7 X4165V8Z-2.7 (Note) X4165V8I-2.7 X4165V8IZ-2.7 (Note) X4165S8-2.7A X4165S8Z-2.7A (Note) X4165S8I-2.7A X4165S8IZ-2.7A (Note) X4165V8-2.7A X4165V8Z-2.7A (Note) X4165V8I-2.7A X4165V8IZ-2.7A (Note) PART MARKING X4165 X4165 X4165 X4165 4165AL 4165AL 4165AM 4165AM X4165 X4165 X4165 X4165 4165F 4165F 4165G 4165G X4165 X4165 X4165 X4165 4165AN 4165AN 4165AP 4165AP 2.7-5.5 2.85-3.0 2.7-5.5 2.85-3.0 2.7-5.5 2.55-2.7 RANGE 4.5-5.5 VTRIP RANGE 4.5-4.75 TEMP RANGE (°C) PACKAGE SOIC SOIC (Pb-free) SOIC SOIC (Pb-free) TSSOP (4.4mm) PKG. DWG. MDP0027 MDP0027 MDP0027 MDP0027 M8.173
X4163S8Z-4.5A X4163 (Note) X4163S8I-4.5A X4163
X4163S8IZ-4.5A X4163 (Note) X4163V8-4.5A 4163AL
X4163V8Z-4.5A 4163AL (Note) X4163V8I-4.5A 4163AM
TSSOP M8.173 (4.4mm) (Pb-free) TSSOP (4.4mm) M8.173
X4163V8IZ-4.5A 4163AM (Note) X4163S8-2.7 X4163S8Z-2.7 (Note) X4163S8I-2.7 X4163S8IZ-2.7 (Note) X4163V8-2.7 X4163V8Z-2.7 (Note) X4163V8I-2.7 X4163V8IZ-2.7 (Note) X4163S8-2.7A* X4163 X4163 X4163 X4163 4163F 4163F 4163G 4163G X4163
TSSOP M8.173 (4.4mm) (Pb-free) SOIC SOIC (Pb-free) SOIC SOIC (Pb-free) TSSOP (4.4mm) MDP0027 MDP0027 MDP0027 MDP0027 M8.173
TSSOP M8.173 (4.4mm) (Pb-free) TSSOP (4.4mm) M8.173
TSSOP M8.173 (4.4mm) (Pb-free) SOIC SOIC (Pb-free) SOIC SOIC (Pb-free) TSSOP (4.4mm) MDP0027 MDP0027 MDP0027 MDP0027 M8.173
X4163S8Z-2.7A* X4163 (Note) X4163S8I-2.7A X4163
X4163S8IZ-2.7A X4163 (Note) X4163V8-2.7A 4163AN
X4163V8Z-2.7A 4163AN (Note) X4163V8I-2.7A 4163AP
TSSOP M8.173 (4.4mm) (Pb-free) TSSOP (4.4mm) M8.173
X4163V8IZ-2.7A 4163AP (Note)
TSSOP M8.173 (4.4mm) (Pb-free)
FN8120.2 November 2007
X4163, X4165 Ordering Information (Continued)
PART NUMBER RESET (ACTIVE LOW) X4163S8 X4163S8Z (Note) X4163S8I X4163S8IZ (Note) X4163V8 X4163V8Z (Note) X4163V8I X4163V8IZ (Note) PART MARKING X4163 X4163 X4163 X4163 4163 4163 4163I 4163I PART NUMBER RESET (ACTIVE HIGH) X4165S8* X4165S8Z* (Note) X4165S8I X4165S8IZ (Note) X4165V8 PART MARKING X4165 X4165 X4165 X4165 4165 RANGE 4.5-5.5 VTRIP RANGE 4.25-4.5 TEMP RANGE (°C) PACKAGE SOIC SOIC (Pb-free) SOIC SOIC (Pb-free) TSSOP (4.4mm) PKG. DWG. MDP0027 MDP0027 MDP0027 MDP0027 M8.173
X4165V8Z (Note) 4165 X4165V8I X4165V8IZ (Note) 4165I 4165I
TSSOP M8.173 (4.4mm) (Pb-free) TSSOP (4.4mm) M8.173
TSSOP M8.173 (4.4mm) (Pb-free)
*Add "-T1" suffix tape reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials 100% matte plate termination finish, which RoHS compliant compatible with both SnPb Pb-free soldering operations. Intersil Pb-free products classified Pb-free peak reflow temperatures that meet exceed Pb-free requirements IPC/JEDEC STD-020.
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CONFIGURATION
JEDEC SOIC RESET/RESET TSSOP RESET/RESET
FUNCTION (SOIC)
(TSSOP)
Name
Device Select Input Device Select Input
Function
RESET/ RESET
Reset Output. RESET/RESET active LOW/HIGH, open drain output which goes active whenever falls below minimum sense level. will remain active until rises above minimum sense level 250ms. RESET/RESET goes active Watchdog Timer enabled remains either HIGH longer than selectable Watchdog time period. falling edge SDA, while HIGH, resets Watchdog Timer. RESET/RESET goes active power remains active 250ms after power supply stabilizes. Ground Serial Data. bidirectional used transfer data into device. open drain output wire ORed with other open drain open collector outputs. This requires pull resistor input buffer always active (not gated). Watchdog Input. HIGH transition (while HIGH) restarts Watchdog timer. absence HIGH transition within watchdog time period results RESET/RESET going active. Serial Clock. Serial Clock controls serial timing data input output. Write Protect. HIGH used conjunction with WPEN prevents writes control register. Supply Voltage
FN8120.2 November 2007
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PRINCIPLES OPERATION Power Reset Application power X4163, X4165 activates Power Reset Circuit that pulls RESET/RESET active. This signal provides several benefits.
prevents system microprocessor from starting operate with insufficient voltage. prevents processor from operating prior stabilization oscillator. allows time FPGA download configuration prior initialization circuit. prevents communication EEPROM, greatly reducing likelihood data corruption power When exceeds device VTRIP threshold value 200ms (nominal) circuit releases RESET/RESET allowing system begin operation.
WATCHDOG TIMER
Watchdog Timer circuit monitors microprocessor activity monitoring pins. microprocessor must periodically send start followed stop prior expiration watchdog time period prevent RESET/RESET signal. start stop bits need separated toggling then high least time. state nonvolatile control bits Status Register determine watchdog timer period. microprocessor change these watchdog bits, they "locked" tying HIGH.
EEPROM INADVERTENT WRITE PROTECTION When RESET/RESET goes active result voltage condition Watchdog Timer Time Out, inprogress communications terminated. While RESET/RESET active, communications allowed nonvolatile write operation start. Nonvolatile writes in-progress when RESET/RESET goes active allowed finish. Additional protection mechanisms provided with memory Block Lock Write Protect (WP) pin. These discussed elsewhere this document. THRESHOLD RESET PROCEDURE X4163, X4165 shipped with standard threshold (VTRIP) voltage. This value will change over normal operating storage conditions. However, applications where standard VTRIP exactly right, higher precision needed VTRIP value, X4163, X4165 threshold adjusted. procedure described below, uses application nonvolatile control signal.
VOLTAGE MONITORING
During operation, X4163, X4165 monitors level asserts RESET/RESET supply voltage falls below preset minimum VTRIP. RESET/RESET signal prevents microprocessor from operating power fail brownout condition. RESET/RESET signal remains active until voltage drops below also remains active until returns exceeds VTRIP 200ms.
Figure VTRIP Level Sequence (VCC desired VTRIP values set)
12-15V
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Setting VTRIP Voltage This procedure used VTRIP higher lower voltage value. necessary reset trip point before setting value. VTRIP voltage, start setting control register, then apply desired VTRIP threshold voltage programming voltage, byte address byte "00" data. stop following valid write operation initiates VTRIP programming sequence. Bring complete operation. Resetting VTRIP Voltage This procedure used VTRIP "native" voltage level. example, current VTRIP 4.4V VTRIP must 4.0V, then VTRIP must reset. When VTRIP reset, VTRIP something less than 1.7V. This procedure must used voltage lower value. reset VTRIP voltage start setting control register, apply programming voltage, byte address byte "00" data. stop valid write operation initiates VTRIP programming sequence. Bring complete operation.
Figure Reset VTRIP Level Sequence (VCC 12-15V, set)
12-15V
Figure Sample VTRIP Reset Circuit
SOIC 4.7K RESET VTRIP Adj. X4163 Adjust
FN8120.2 November 2007
X4163, X4165
Figure VTRIP Programming Sequence
VTRIP Programming
Execute Reset VTRIP Sequence
Applied Desired VTRIP
Applied Applied Error
Execute VTRIP Sequence
Applied Applied Error
Apply
Execute Reset VTRIP Sequence
Decrement (VCC 50mV)
RESET goes active?
Error -Emax
Measured VTRIP Desired VTRIP
Error Emax
-Emax Error Emax DONE
Emax Maximum Allowed VTRIP Error
Control Register Control Register provides user mechanism changing Block Lock Watchdog Timer settings. Block Lock Watchdog Timer bits nonvolatile change when power removed. Control Register accessed address FFFFh. only modified performing byte write operation directly address register only data byte allowed each register write operation. Prior writing Control Register, RWEL bits must using step process, with whole sequence requiring steps. "Writing Control Register" below.
user must issue stop after sending this byte register initiate nonvolatile cycle that stores WD1, WD0. X4163, X4165 will acknowledge data bytes written after first byte entered. state Control Register read time performing random read address FFFFh. Only byte read each register read operation. X4163, X4165 resets itself after first byte
FN8120.2 November 2007
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read. master should supply stop condition consistent with protocol, stop required this operation. zeroes other bits control register. Once set, remains until either reset writing zeroes other bits control register) until part powers again. Writes cause nonvolatile write cycle, device ready next operation immediately after stop condition. WD1, WD0: Watchdog Timer Bits bits control period Watchdog Timer. options shown below.
WPEN RWEL
BP2, BP1, BP0: Block Protect Bits (Nonvolatile) Block Protect Bits, BP2, BP0, determine which blocks array write protected. write protected block memory ignored. block protect bits will prevent write operations following segments array. Protected Addresses (Size)
None (factory setting) None None 0000h 7FFh bytes) 000h 03Fh bytes) 000h 07Fh (128 bytes) 000h 0FFh (256 bytes) 000h 1FFh (512 bytes)
Watchdog Time Period
seconds milliseconds milliseconds disabled (factory setting)
Array Lock
None None None Full Array (All) First Page (P1) First (P2) First (P4) First (P8)
Write Protect Enable These devices have advanced Block Lock scheme that protects five blocks array when enabled. provides hardware write protection through nonvolatile Write Protect Enable (WPEN) bit. Write Protect (WP) Write Protect Enable (WPEN) Control Register control programmable Hardware Write Protect feature. Hardware Write Protection enabled when WPEN HIGH disabled when either WPEN LOW. When chip Hardware Write Protected, nonvolatile writes block protected sections memory array cannot written block protect bits cannot changed. Only sections memory array that block protected written. Note that since WPEN write protected, cannot changed back state; write protection enabled long held HIGH.
RWEL: Register Write Enable Latch (Volatile) RWEL must prior write Control Register. WEL: Write Enable Latch (Volatile) controls access memory Register during write operation. This volatile latch that powers (disabled) state. While LOW, writes address, including control registers will ignored acknowledge will issued after Data Byte). writing Table Write Protect Enable Function
HIGH HIGH
WPEN
Memory Array Block Protected
Writes Writes Writes
Memory Array Block Protected
Writes Blocked Writes Blocked Writes Blocked
WPEN
Writes Writes Writes Blocked
Protection
Software Software Hardware
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Writing Control Register Changing nonvolatile bits control register requires following steps: Write Control Register Write Enable Latch (WEL). This volatile operation, there delay after write. (Operation preceeded start ended with stop). Write Control Register both Register Write Enable Latch (RWEL) bit. This also volatile cycle. zeros data byte required. (Operation preceeded start ended with stop). Write value Control Register that control bits desired state. This represented 0xys t01r binary, where bits. (Operation preceeded start ended with stop). Since this nonvolatile write cycle will take 10ms complete. RWEL reset this cycle sequence must repeated change nonvolatile bits again. this third step (0xys t11r) then RWEL set, BP2, BP1, BP0, bits remain unchanged. Writing second byte control register allowed. Doing aborts write operation returns NACK. read operation occurring between previous operations will interrupt register write operation. Figure Valid Data Changes
RWEL cannot reset without writing nonvolatile control bits control register, power cycling device attempting write write protected block. illustrate, sequence writes device consisting [02H, 06H, 02H] will reset nonvolatile bits Control Register sequence [02H, 06H, 06H] will leave nonvolatile bits unchanged RWEL remains set. SERIAL INTERFACE Serial Interface Conventions device supports bidirectional oriented protocol. protocol defines device that sends data onto transmitter, receiving device receiver. device controlling transfer called master device being controlled called slave. master always initiates data transfers, provides clock both transmit receive operations. Therefore, devices this family operate slaves applications. Serial Clock Data Data states line change only during LOW. state changes during HIGH reserved indicating start stop conditions. Figure
Data Stable
Data Change
Data Stable
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Figure Valid Start Stop Conditions
Start Stop
Serial Start Condition commands preceded start condition, which HIGH transition when HIGH. device continuously monitors lines start condition will respond command until this condition been met. Figure Serial Stop Condition communications must terminated stop condition, which HIGH transition when HIGH. stop condition also used place device into Standby power mode after read sequence. stop condition only issued after transmitting device released bus. Figure Serial Acknowledge Acknowledge software convention used indicate successful data transfer. transmitting device, either master slave, will release after trans-
mitting eight bits. During ninth clock cycle, receiver will pull line acknowledge that received eight bits data. Refer Figure device will respond with acknowledge after recognition start condition correct Device Identifier Select bits contained Slave Address Byte. write operation selected, device will respond with acknowledge after receipt each subsequent eight word. device will acknowledge incoming data address bytes, except Slave Address Byte when Device Identifier and/or Select bits incorrect. read mode, device will transmit eight bits data, release line, then monitor line acknowledge. acknowledge detected stop condition generated master, device will continue transmit data. device will terminate further data transmissions acknowledge detected. master must then issue stop condition return device Standby mode place device into known state.
Figure Acknowledge Response From Receiver
from Master Data Output from Transmitter Data Output from Receiver Start Acknowledge
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Figure Byte Write Sequence
Signals from Master
Slave Address
Word Address Byte
Word Address Byte
Data
Signals from Slave
Serial Write Operations BYTE WRITE write operation, device requires Slave Address Byte Word Address Byte. This gives master access words array. After receipt Word Address Byte, device responds with acknowledge, awaits next eight bits data. After receiving bits Data Byte, device again responds with acknowledge. master then terminates transfer generating stop condition, which time device begins internal write cycle nonvolatile memory. During this internal write cycle, device inputs disabled, device will respond requests from master. output high impedance. Figure write protected block memory will suppress acknowledge bit. Figure Page Write Operation
Signals from Master
Page Write device capable page write operation. initiated same manner byte write operation; instead terminating write cycle after first data byte transferred, master transmit unlimited number 8-bit bytes. After receipt each byte, device will respond with acknowledge, address internally incremented one. page address remains constant. When counter reaches page, "rolls over" goes back same page. This means that master write bytes page starting location that page. master begins writing location loads 12-bytes, then first 4bytes written locations through last 8-bytes written locations through Afterwards, address counter would point location page that just written. master supplies more than 64-bytes data, then data over-writes previous data, byte time.
Slave Address Word Address Byte Word Address Byte Data Data
Signals from Slave
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Figure Writing 12-bytes 64-byte page starting location
Bytes Address Pointer Ends Here Addr
Bytes
Address
Address
Address
master terminates Data Byte loading issuing stop condition, which causes device begin nonvolatile write cycle. with byte write operation, inputs disabled until completion internal write cycle. Figure address, acknowledge, data transfer sequence. Stops Write Modes Stop conditions that terminate write operations must sent master after sending least full data byte plus subsequent signal. stop issued middle data byte, before full data byte plus associated sent, then device will reset itself without performing write. contents array will effected. Acknowledge Polling disabling inputs during nonvolatile cycles used take advantage typical write cycle time. Once stop condition issued indicate master's byte load operation, device initiates internal nonvolatile cycle. Acknowledge polling initiated immediately. this, master issues start condition followed Slave Address Byte write read operation. device still busy with nonvolatile cycle then will returned. device completed write operation, will returned host then proceed with read write operation. Refer flow chart Figure
Figure Acknowledge Polling Sequence
Byte load completed issuing STOP. Enter Polling
Issue START
Issue Slave Address Byte (Read Write)
Issue STOP
returned? Nonvolatile Cycle complete. Continue command sequence?
Issue STOP
Continue Normal Read Write Command Sequence
PROCEED
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Figure Current Address Read Sequence
Signals from Master
Slave Address
Data
Signals from Slave
Serial Read Operations Read operations initiated same manner write operations with exception that Slave Address Byte one. There three basic read operations: Current Address Reads, Random Reads, Sequential Reads. Current Address Read Internally device contains address counter that maintains address last word read incremented one. Therefore, last read address next read operation would access data from address n+1. power address address counter undefined, requiring read write operation initialization. Upon receipt Slave Address Byte with one, device issues acknowledge then transmits eight bits Data Byte. master terminates read operation when does respond with acknowledge during ninth clock then issues stop condition. Refer Figure address, acknowledge, data transfer sequence. should noted that ninth clock cycle read operation "don't care." terminate read operation, master must either issue stop condition during ninth cycle hold HIGH during ninth clock cycle then issue stop condition. Figure Random Address Read Sequence
Signals from Master
Random Read Random read operation allows master access memory location array. Prior issuing Slave Address Byte with one, master must first perform "dummy" write operation. master issues start condition Slave Address Byte, receives acknowledge, then issues Word Address Bytes. After acknowledging receipts Word Address Bytes, master immediately issues another start condition Slave Address Byte with one. This followed acknowledge from device then eight word. master terminates read operation responding with acknowledge then issuing stop condition. Refer Figure address, acknowledge, data transfer sequence. There similar operation, called "Set Current Address" where device does operation, enters address into address counter stop issued instead second start shown Figure device goes into standby mode after stop activity will ignored until start detected. next Current Address Read operation reads from newly loaded address. This operation could useful master knows next address needs read, ready data.
Slave Address
Word Address Byte
Word Address Byte
Slave Address
Signals from Slave
Data
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Figure Sequential Read Sequence
Signals from Master Slave Address
Signals from Slave
Data
Data
Data (n-1)
Data
integer greater than
Sequential Read Sequential reads initiated either current address read random address read. first Data Byte transmitted with other modes; however, master responds with acknowledge, indicating requires additional data. device continues output data each acknowledge received. master terminates read operation responding with acknowledge then issuing stop condition. data output sequential, with data from address followed data from address address counter read operations increments through page column addresses, allowing entire memory contents serially read during operation. address space counter "rolls over" address 0000H device continues output data each acknowledge received. Refer Figure acknowledge data transfer sequence.
X4163, X4165 Addressing SLAVE ADDRESS BYTE Following start condition, master must output Slave Address Byte. This byte consists several parts: device type identifier that `1010' access array. bits `0'. next bits device address. slave command byte bit. Slave Address Byte defines operation performed. When one, then read operation selected. zero selects write operation. Refer Figure After loading entire Slave Address Byte from bus, device compares input slave byte data proper slave byte. Upon correct compare, device outputs acknowledge line. Word Address word address either supplied master obtained from internal counter. internal counter undefined power condition.
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Figure X4163, X4165 Addressing
Device Identifier Device Select
Slave Address Byte High Order Word Address
(X4)
(X3)
(X2)
Word Address Byte 0-16K Order Word Address
(X1)
(X0)
(Y5)
(Y4)
(Y3)
(Y2)
(Y1)
(Y0)
Word Address Byte options
Data Byte options
Operational Notes device powers-up following state: device power standby state. `0'. this state possible write device. input mode. RESET/RESET Signal active tPURST. Data Protection following circuitry been included prevent inadvertent writes: must allow write operations. proper clock count sequence required prior stop order start nonvolatile write cycle. three step sequence required before writing into Control Register change Watchdog Timer Block Lock settings. pin, when held HIGH, WPEN logic HIGH will prevent writes Control Register.
Communication device inhibited while RESET/RESET active in-progress communication terminated. Block Lock bits protect sections memory array from write operations. SYMBOL TABLE
WAVEFORM INPUTS Must steady change from HIGH change from HIGH Don't Care: Changes Allowed OUTPUTS Will steady Will change from HIGH Will change from HIGH Changing: State Known Center Line High Impedance
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ABSOLUTE MAXIMUM RATINGS Temperature under bias -65°C +135°C Storage temperature -65°C +150°C Voltage with respect VSS. -1.0V D.C. output current Lead temperature (soldering, 10s) 300°C COMMENT Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only; functional operation device these other conditions above those listed operational sections this specification) implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
RECOMMENDED OPERATING CONDITIONS Temperature
Commercial Industrial
Min.
-40°C
Max.
70°C +85°C
Option
-2.7 -2.7A Blank -4.5A
Supply Voltage Limits
2.7V 5.5V 4.5V 5.5V
D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.) 5.5V Symbol
ICC1(1) ICC2(1) ISB(2) ISB(2) VIL(3)
Parameter
Active Supply Current Read Active Supply Current Write Standby Current (WDT off) Standby Current (WDT Input Leakage Current Output Leakage Current Input Voltage Input nonvolatile Schmitt Trigger Input Hysteresis Fixed input level related level Output Voltage
Unit
Test Conditions
0.1, fSCL 400kHz, Commands VSDA VSCL Others VSDA=VSCL=VSB Others VSDA Device Standby(2)
-0.5
VHYS
3.0mA (2.7- 5.5V)
Notes: device enters Active state after start, remains active until: clock cycles later Device Select Bits Slave Address Byte incorrect; 200ns after stop ending read operation; after stop ending write operation. device goes into Standby: 200ns after stop, except those that initiate nonvolatile write cycle; after stop that initiates nonvolatile cycle; clock cycles after start that followed correct Device Select Bits Slave Address Byte. Min. Max. reference only tested.
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CAPACITANCE 25°C, MHz, Symbol
COUT
Parameter
Output Capacitance (SDA, RST/RST) Input Capacitance (SCL,
Max.
Unit
Test Conditions
VOUT
Notes: This parameter periodically sampled 100% tested.
EQUIVALENT A.C. LOAD CIRCUIT
1533 VOL= 0.4V
A.C. TEST CONDITIONS
Input pulse levels Input rise fall times Input output timing levels Output load 0.1VCC 0.9VCC 10ns 0.5VCC Standard output load
RESET
100pF
A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified) Symbol
fSCL tBUF tLOW tHIGH tSU:STA tHD:STA tSU:DAT tHD:DAT tSU:STO tSU:WP tHD:WP Clock Frequency Pulse width Suppression Time inputs Data Valid Time free before start transmission Clock Time Clock HIGH Time Start Condition Setup Time Start Condition Hold Time Data Setup Time Data Hold Time Stop Condition Setup Time Data Output Hold Time Rise Time Fall Time Setup Time Hold Time Capacitive load each line
Parameter
Min.
.1Cb .1Cb
Max.
Unit
Notes: Typical values +25°C 5.0V total capacitance line
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TIMING DIAGRAMS Timing
tSU:STA tHD:STA tSU:DAT tHD:DAT tSU:STO tHIGH tLOW
tBUF
Timing
START Slave Address Byte tSU:WP tHD:WP
Write Cycle Timing
Last Byte
Stop Condition Start Condition
Nonvolatile Write Cycle Timing Symbol
Parameter
Write Cycle Time
Min.
Typ.(1)
Max.
Unit
Notes: time from valid stop condition write sequence self-timed internal nonvolatile write cycle. minimum cycle time allowed nonvolatile write user, unless Acknowledge Polling used.
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Power-Up Power-Down Timing
Volts VTRIP tPURST tRPD
tPURST
RESET (X4165)
VRVALID
RESET (X4163)
VRVALID
RESET Output Timing Symbol
VTRIP
Parameter
Reset Trip Point Voltage, X4163, X4165-4.5A Reset Trip Point Voltage, X4163, X4165 Reset Trip Point Voltage, X4163, X4165-2.7A Reset Trip Point Voltage, X4163, X4165-2.7 Power-up Reset Time Detect Reset/Output Fall Time Rise Time Reset Valid
Min.
4.25 2.85 2.55
Typ.
4.62 4.38 2.92 2.62
Max.
4.75
Unit
tPURST tRPD
VRVALID
Notes: This parameter periodically sampled 100% tested.
RESET Timing
tRSP tRSP<tWDO tRSP>tWDO tRST tRSP>tWDO tRST
RESET Note: inputs ignored during active reset period (tRST).
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RESET Output Timing Symbol
tWDO
Parameter
Watchdog Time Period, (factory setting) Reset Time
Min.
Typ.
Max.
Units
tRST
VTRIP Programming Timing Diagram (WEL
(VTRIP) tVPS tVPH tVPO
VTRIP tTSU tTHD
VTRIP Programming Parameters Parameter
tVPS tVPH tTSU tTHD tVPO VTRAN Vta1 Vta2
Description
VTRIP Program Enable Voltage Setup time VTRIP Program Enable Voltage Hold time VTRIP Setup time VTRIP Hold (stable) time VTRIP Write Cycle Time VTRIP Program Enable Voltage time (Between successive adjustments) VTRIP Program Recovery Period (Between successive adjustments) Programming Voltage VTRIP Programmed Voltage Range Initial VTRIP Program Voltage accuracy (VCC applied VTRIP) (Programmed 25°C.) Subsequent VTRIP Program Voltage accuracy [(VCC applied Vta1) VTRIP. Programmed 25°C.] VTRIP Program Voltage repeatability (Successive program operations. Programmed 25°C.) VTRIP Program variation after programming (0-75°C). (Programmed 25°C.)
Min.
Max.
Unit
2.55 -0.1 4.75 +0.4
VTRIP programming parameters periodically sampled 100% tested.
FN8120.2 November 2007
X4163, X4165 Small Outline Package Family (SO)
(N/2)+1
I.D. MARK DETAIL
(N/2)
0.010 GAUGE PLANE 0.004 0.010 DETAIL
SEATING PLANE
0.010
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO) SYMBOL NOTES: Plastic metal protrusions 0.006" maximum side included. Plastic interlead protrusions 0.010" maximum side included. Dimensions "E1" measured Datum Plane "H". Dimensioning tolerancing ASME Y14.5M-1994 SO-8 0.068 0.006 0.057 0.017 0.009 0.193 0.236 0.154 0.050 0.025 0.041 0.013 SO-14 0.068 0.006 0.057 0.017 0.009 0.341 0.236 0.154 0.050 0.025 0.041 0.013 SO16 (0.150") 0.068 0.006 0.057 0.017 0.009 0.390 0.236 0.154 0.050 0.025 0.041 0.013 SO16 (0.300") (SOL-16) 0.104 0.007 0.092 0.017 0.011 0.406 0.406 0.295 0.050 0.030 0.056 0.020 SO20 (SOL-20) 0.104 0.007 0.092 0.017 0.011 0.504 0.406 0.295 0.050 0.030 0.056 0.020 SO24 (SOL-24) 0.104 0.007 0.092 0.017 0.011 0.606 0.406 0.295 0.050 0.030 0.056 0.020 SO28 (SOL-28) 0.104 0.007 0.092 0.017 0.011 0.704 0.406 0.295 0.050 0.030 0.056 0.020 TOLERANCE ±0.003 ±0.002 ±0.003 ±0.001 ±0.004 ±0.008 ±0.004 Basic ±0.009 Basic Reference Reference NOTES Rev. 2/01
FN8120.2 November 2007
X4163, X4165 Thin Shrink Small Outline Plastic Packages (TSSOP)
INDEX AREA 0.05(0.002) -CSEATING PLANE 0.25 0.010 0.25(0.010) GAUGE PLANE
M8.173
LEAD THIN SHRINK NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL 0.002 0.031 0.0075 0.0035 0.116 0.169 0.246 0.0177 0.047 0.006 0.051 0.0118 0.0079 0.120 0.177 0.256 0.0295 MILLIMETERS 0.05 0.80 0.19 0.09 2.95 4.30 6.25 0.45 1.20 0.15 1.05 0.30 0.20 3.05 4.50 6.50 0.75 NOTES Rev. 12/00
0.10(0.004)
0.10(0.004)
0.026
0.65
NOTES: These package dimensions within allowable dimensions JEDEC MO-153-AC, Issue Dimensioning tolerancing ANSI Y14.5M-1982. Dimension does include mold flash, protrusions gate burrs. Mold flash, protrusion gate burrs shall exceed 0.15mm (0.006 inch) side. Dimension "E1" does include interlead flash protrusions. Interlead flash protrusions shall exceed 0.15mm (0.006 inch) side. chamfer body optional. present, visual index feature must located within crosshatched area. length terminal soldering substrate. number terminal positions. Terminal numbers shown reference only. Dimension does include dambar protrusion. Allowable dambar protrusion shall 0.08mm (0.003 inch) total excess dimension maximum material condition. Minimum space between protrusion adjacent lead 0.07mm (0.0027 inch). Controlling dimension: MILLIMETER. Converted inch dimensions necessarily exact. (Angles degrees)
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FN8120.2 November 2007

X4163, X4165 16K, November 2007 FN8120.2 Supervisor wit

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