ISL54105 June 2008 FN6723.0 TMDS Regenerator ISL54105 h

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ISL54105 June 2008 FN6723.0 TMDS Regenerator ISL54105 h

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Features SIGNS OMMEN 4105A ISL5 Data Sheet
ISL54105
June 2008 FN6723.0
TMDS Regenerator
ISL54105 high-performance TMDS timing regenerator containing programmable equalizer clock data recovery (CDR) function each TMDS pairs HDMI signal. TMDS data outputs ISL54105 regenerated perfectly aligned regenerated TMDS clock signal, creating extremely clean, low-jitter DVI/HDMI signal that easily decoded TMDS receiver. ISL54105 used cable extender, clean noisy/jittery TMDS source, provide very stable TMDS signal finicky HDMI receiver.
Features
Clock Data Recovery Retiming Programmable pre-emphasis output driver Programmable internal 100, high-Z termination Stand-alone software-controlled operation lead, 10mm 10mm package Pb-free (RoHS compliant)
Applications
DVI/HDMI extenders Televisions/PC monitors/projectors
Block Diagram
TERMINATION
TERMINATION EQUALIZATION
FIFO
RES_TERM
RES_BIAS
BIAS GENERATION
ADDR RESET CONFIGURATION CONTROL ACTIVITY DETECT
Ordering Information
PART NUMBER ISL54105CRZ TEMP. RANGE (°C) PACKAGE (Pb-Free) PKG. DWG. L72.10x10B
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, 100% matte plate plus anneal termination finish, which RoHS compliant compatible with both SnPb Pb-free soldering operations). Intersil Pb-free products classified Pb-free peak reflow temperatures that meet exceed Pb-free requirements IPC/JEDEC STD-020.
CAUTION: These devices sensitive electrostatic discharge; follow proper Handling Procedures. 1-888-INTERSIL 1-888-468-3774 Intersil (and design) registered trademark Intersil Americas Inc. Copyright Intersil Americas Inc. 2008. Rights Reserved other trademarks mentioned property their respective owners.
ISL54105
Absolute Maximum Ratings
Voltage (referenced GND). 4.0V Voltage Input (referenced GND) -0.3V VD+0.3V Voltage Tolerant" Input (referenced GND). -0.3V +6.0V Current into Output ±20mA Classification Human Body Model >4000V, higher voltage testing progress Machine Model .>200V, higher voltage testing progress
Thermal Information
Thermal Resistance (Typical, Note (°C/W) Package. Maximum Biased Junction Temperature +125°C Storage Temperature .-65°C +150°C Pb-Free Reflow Profile. .see link below
Recommended Operating Conditions
Temperature +70°C Supply Voltage. 3.3V
CAUTION: operate near maximum ratings listed extended periods time. Exposure such conditions adversely impact product reliability result failures covered warranty.
NOTE: measured free with component mounted high effective thermal conductivity test board with "direct attach" features. Tech Brief TB379.
Electrical Specifications
Specifications apply 3.3V, pixel rate 165MHz, +25°C, RES_TERM RES_BIAS 3.16k, TMDS output load TMDS output termination voltage VTERM 3.3V unless otherwise noted. COMMENT (Note (Note UNIT
SYMBOL
PARAMETER
FULL CHANNEL CHARACTERISTICS fDATA_MAX fDATA_MIN Maximum Clock Frequency/Pixel Rate Minimum Clock Frequency/Pixel Rate (Note
TMDS RECEIVER CHARACTERISTICS VSENS R100 CLKDUTY Minimum Differential Input Sensitivity Termination Resistance Termination Resistance Clock Duty Cycle mVP-P
TMDS TRANSMITTER CHARACTERISTICS jTX_CLOCK jTX_DATA Total Jitter Clock Outputs Total Jitter Data Outputs Independent incoming jitter Independent incoming jitter Added with respect incoming inter-pair skew VTERM VTERM VTERM VTERM
SKEWINTRA Intra-Pair Differential Skew SKEWINTER Inter-Pair (channel-to-channel) Skew tRISE tFALL Rise Time into Load 3.3V Fall Time into Load 3.3V Single-Ended High Level Output Voltage Single-Ended Level Output Voltage
DIGITAL SCHMITT INPUT CHARACTERISTICS High Threshold Voltage High Threshold Voltage Input Leakage Current Internal Pull-Up Resistance Internal Pull-Down Resistance Input Capacitance pins AUTO_CH_SEL, CH_SEL_x, RESET, ADDRx, pins
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ISL54105
Electrical Specifications
Specifications apply 3.3V, pixel rate 165MHz, +25°C, RES_TERM RES_BIAS 3.16k, TMDS output load TMDS output termination voltage VTERM 3.3V unless otherwise noted. COMMENT (Note (Note UNIT
SYMBOL
PARAMETER
DIGITAL OUTPUT CHARACTERISTICS Output HIGH Voltage, Output Voltage, -8mA
POWER SUPPLY REQUIREMENTS Supply Voltage Supply Current Inputs driven 165Mpixel/s TMDS signals. Default register settings available inputs driven 165Mpixel/s TMDS signals.
Supply Current Power-down Mode
TIMING CHARACTERISTICS (2-WIRE INTERFACE) fSCL tBUF tLOW tHIGH tSU:STA tHD:STA tSU:DAT tHD:DAT tSU:STO NOTE: Parameters with and/or limits 100% tested +25°C, unless otherwise specified. Temperature limits established characterization production tested. Operation 165MHz guaranteed. While many parts will typically operate 225MHz, operation above 165MHz guaranteed. Clock Frequency Data Valid Time Must Free Before Transmission Start Clock Time Clock HIGH Time Start Condition Setup Time Start Condition Hold Time Data Setup Time Data Hold Time Stop Condition Setup Time Data Output Hold Time 0.03 0.07 0.03
tHIGH
tLOW
tSU:STA tHD:STA
tSU:DAT
tHD:DAT
tBUF
tSU:STO
FIGURE 2-WIRE INTERFACE TIMING
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ISL54105 ISL54105 Configuration
ADDR2 ADDR1 ADDR0 VD_ESD TXC+ TXC48 TX2+ TX246 TX1+ TX144 TX0+ TX042 VD_ESD TEST ADDR3 ADDR4 RX123 RX1+ RX226 RX2+ ADDR5 ADDR6
RES_TERM RES_BIAS RXCRXC+ RX0RX0+ RESET
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ISL54105 Descriptions
SYMBOL RX0-, RX0+, RX1-, RX1+, RX2-, RX2+ TMDS Inputs. Incoming TMDS data signals. RXC-, RXC+ TX0-, TX0+, TX1-, TX1+, TX1-, TX1+ TXC-, TXC+ ADDR[6:0] RES_BIAS RES_TERM TMDS Inputs. Incoming TMDS clock signals. TMDS Outputs. TMDS output data selected channel. TMDS Outputs. TMDS output clock selected channel. Digital input, tolerant, 500mV hysteresis. Serial data clock 2-wire interface. Note: Internal pull-up Bidirectional Digital I/O, open drain, tolerant. Serial data 2-wire interface. Note: Internal pull-up Digital inputs, tolerant. 7-Bit address serial interface. Note: Internal pull-down GND. Digital Output, 3.3V. Activity Detect. Output goes high when active TMDS clock detected RXC. through 3.16k external resistor. Sets internal bias currents. through 1.0k external resistor. During calibration, termination resistor closest value RES_TERM/20 selected. Digital Input, 3.3V. Power-down. Pull high ISL54105 minimum power consumption mode. Note: ensure proper operation, this must held during power-up. taken high 100ms after power supplies have settled 3.3V ±10%. When exiting Power-down, termination resistor Recalibration cycle must re-trim termination resistors (see register 0x03[7]). Note: Internal pull-down GND. Digital Input, 3.3V. Pull high then reset mux. final application. Note: Internal pull-down GND. Digital Input. Used production testing only. final application. This internal pulldown GND, also acceptable leave this floating. Power supply. Connect 3.3V supply bypass each with 0.1µF. Power supply protection diodes. Connect these pins (pin 3.3V supply rail with (0.4V lower) Schottky diode, with cathode connected VD_ESD anode connected Bypass each with 0.1µF. Ground return entire chip. thermal must have impedance connection ISL54105 function all. lower electrical impedance, better ground, better performance. thermal impedance between thermal plane will dissipate heat from package more efficiently well recommended. DESCRIPTION
RESET TEST VD_ESD
THERMAL (GND)
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ISL54105 Register Listing
ADDRESS 0x00 REGISTER (DEFAULT VALUE) Device (read only) BIT(S) 0x01 Channel Activity Detect (read only) 0x02 Channel Selection (0x0C) FUNCTION NAME Device Revision Device Reserved Activity Detect Reserved Reset Power-down DESCRIPTION initial silicon, second revision, etc. ISL54105 Reserved TMDS clock present TMDS clock detected This nibble should always 0xC. Full chip reset. Write reset. Will itself when reset complete. Normal Operation Puts chip minimal power consumption mode, turning TMDS outputs open-circuiting TMDS inputs. This OR'ed with Power-down input pin. either set, chip will enter power-down. Serial stays operational mode. Note: When exiting Power-down, termination resistor Recalibration cycle must re-trim termination resistors (see register 0x03[7]). Default value slightly reduce power consumption. Clock inputs terminated into 50/100. Clock inputs tri-stated allow chip operate parallel with another TMDS receiver with fixed termination) Data inputs terminated into 50/100. Data inputs tri-stated allow chip operate parallel with another TMDS receiver with fixed termination)
0x03
Input Control (0x12) Recommended default: 0x63
Reserved Reserved Tri-state Clock Inputs
Tri-state Data Inputs
Activity Detect Mode Activity. Activity detection based presence activity TMDS clock inputs. This setting (along with hysteresis 20mV enabled) provides reliable activity detection. (recommended setting) Common Mode Voltage. common mode voltage above ~3.05V, input considered active. This method been found unreliable with small signal swings should used. This setting silicon default should changed software more reliable activity detection. Clock Hysteresis Enables hysteresis clock inputs prevent false clock detection when both inputs high. Data inputs hysteresis. TMDS input hysteresis disabled TMDS input hysteresis enabled. Eliminates false activity detects unconnected channels. (recommended setting) Controls amount hysteresis clock inputs. 10mV 20mV (recommended setting) Normal Operation Recalibrates termination resistance. recalibrate, take this high, wait least 1ms, then take this low. Calibration automatically done after power-on, performing recalibration after supply voltage temperature have stabilized result termination resistances closer desired
Clock Hysteresis Magnitude Recalibrate
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ISL54105 Register Listing (Continued)
ADDRESS 0x04 REGISTER (DEFAULT VALUE) Termination Control (0x00) BIT(S) FUNCTION NAME Reserved Data Termination TMDS Data inputs terminated into (normal operation) TMDS Data inputs terminated into (for paralleled inputs) 000. TMDS Clock inputs terminated into (normal operation) TMDS Clock inputs terminated into (for paralleled inputs) Normal Operation Clock outputs tri-stated (allows another chip drive output clock pins) Normal Operation Data outputs tri-stated (allows another chip drive output data pins) Normal Operation polarity TMDS data outputs inverted becomes becomes TMDS clock unchanged. Normal Operation data output data output CH0. change CH1. Transmit Drive Current data signals, adjustable 0.125mA steps. Clock current fixed 10mA. 0x0: 10mA 0x8: 11mA 0xF: 11.875mA Drive boost 0.125mA steps) added during first half each period data signals. Clock signals have pre-emphasis. 0x0: 0x8: 0xF: 1.875mA Default value 0xCC also 0x00. Boost (dB) <gain value> 0.8dB 0x0: boost 800MHz 0xC: 10.6dB boost 800MHz (default) 0xF: 13dB boost 800MHz 0x09 Test Pattern Generator (0x00) Reserved Generator Mode Default value also 0x0. When 25MHz 165MHz clock applied clock input, this function will output PRBS7 pattern pins. Normal operation (test patterns disabled) PRBS7 pattern frequency toggle (0000011111.) High frequency toggle (1010101010.) Note: When switching from high frequency toggle pattern frequency toggle pattern, must first select normal operation. DESCRIPTION
Reserved Termination
0x05 Output Options (0x00)
Reserved Tri-state Clock Outputs Tri-state Data Outputs Invert Output Polarity Reverse Output Order Transmit Current
0x06
Data Output Drive (0x00)
Transmit Pre-emphasis
0x07 0x08
Reserved (0xCC) Equalization (0xCC)
Reserved Equalizer Gain
Enable PRBS7 Error Enables PRBS7 error counter registers 0x0A 0x0C. Counter Disable PRBS7 Error Counter Enable PRBS7 Error Counter
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ISL54105 Register Listing (Continued)
ADDRESS 0x0A 0x0B 0x0C 0x10 REGISTER (DEFAULT VALUE) PRBS7 Error Counter Link (read only) PRBS7 Error Counter Link (read only) PRBS7 Error Counter Link (read only) Bandwidth (0x10) Recommended default: 0x12 BIT(S) FUNCTION NAME PRBS7 Error Counter Link PRBS7 Error Counter Link PRBS7 Error Counter Link Bandwidth DESCRIPTION PRBS7 Error Counter Link Saturates 0xFF. Reading this register clears this register read PRBS7 Error Counter Link Saturates 0xFF. Reading this register clears this register read PRBS7 Error Counter Link Saturates 0xFF. Reading this register clears this register read Selects between bandwidth settings 4MHz (silicon default) 2MHz 1MHz (recommended default) 500kHz 1MHz provides slightly better performance with high jitter/ high noise signals. Keep 000100 binary.
Reserved
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ISL54105 Application Information
ISL54105 TMDS regenerator, locking incoming HDMI signal with triple Clock Data Recovery units (CDRs) Phase Locked Loop (PLL). generates jitter pixel clock from incoming TMDS clock. TMDS data signals equalized, sliced CDR, re-aligned clock, sent TMDS outputs.
Bandwidth
2-bit Bandwidth register controls loop bandwidth used recover incoming clock signal. default 4MHz setting works well most applications, however lower bandwidth 1MHz proven work just well with good TMDS sources slightly better with marginal sources.
Activity Detection
TMDS input considered active using methods. original default activity detect method (register 0x03b4 measure common mode TMDS clock input each channel. common mode 3.3V, indicates that there nothing connected that input, that whatever connected turned (inactive). This been found relatively unreliable, particularly with weak signals. preferred method activity detection looking active signal TMDS clock input that channel (register 0x03b4 This more robust, however disconnected inputs will cause both inputs differential receiver same level 3.3V. offset error differential TMDS receiver very small, receiver resolve will randomly switch between states, which detected active clock. Register 0x03 bits allow 10mV 20mV offset added input stage clock inputs, eliminating this problem. This offset will slightly reduce sensitivity TMDS receiver clock lines, since clock signals much lower frequency than data, they will nearly attenuated, this problem practice. Again, using activity detection method (register 0x03b4 recommended.
Power-down
chip placed Power-down mode when conserve power. Setting Power-down (register 0x02 pulling input high places chip minimal power consumption mode, turning TMDS outputs disconnecting TMDS inputs. Serial stays operational mode. Note that must during power-on order initialize interface. Note: When exiting Power-down, termination resistor Recalibration cycle must re-trim termination resistors (see register 0x03[7]).
Typical Performance
Setup (Figure used capture TMDS diagrams shown Figure Figure
CHROMA 2326 VIDEO PATTERN GENERATOR UXGA 60Hz
DUAL-LINK CABLE
DELL 2000FP UXGA MONITOR
FIGURE
FIGURE
FIGURE TEST SETUP
Equalization
Register 0x08 bits control amount equalization applied TMDS inputs, providing bits control. equalization range available from minimum boost maximum 13dB 800MHz, 0.8dB increments. Ideally, equalization adjusted final application provide optimal performance with specific DVI/HDMI transmitter cable used. general, amount equalization required proportional cable length. equalization must fixed (can adjusted final application), equalization setting works well with short cables well medium longer cables.
162.5Mpixel/s (UXGA 60Hz) output Chroma 2326 terminated into TPA2 Plug adapter measured with LeCroy differential probe 6MHz using LeCroy's software clock recovery. Figure shows, amplitude TMDS signal slightly low, otherwise acceptable.
Pre-emphasis
transmit pre-emphasis function sinks additional current during first after every transition, increasing slew rate given capacitance, helping maintain slew rate when using longer/higher capacitance cables. Pre-emphasis controlled register 0x06 bits 7:4, ranges from minimum pre-emphasis) 1.875mA (max pre-emphasis).
FIGURE DIAGRAM OUTPUT CHROMA GENERATOR
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ISL54105
Next, DualLink cable attached terminated into female TPA2 adapter captured Figure
FIGURE DIAGRAM OUTPUT ISL54105
FIGURE CHROMA DIAGRAM AFTER CABLE
meeting minimum requirements either HDMI standards Dell Monitor unable recover data display image. Setup inserts ISL54105 additional cable between pattern generator monitor:
CHROMA 2326 VIDEO PATTERN GENERATOR
cleaner signal generated output ISL54105 results improved another cable (Figure open enough that Dell 2000FP display UXGA image with visible sparkle other artifacts.
FIGURE
DUAL-LINK CABLE
FIGURE
FIGURE
ISL54105
DUAL-LINK CABLE
DELL 2000FP UXGA MONITOR
FIGURE ISL54105 DIAGRAM AFTER CABLE
FIGURE
Loading Considerations
When ISL54105 powered-up outputs disabled, either (power-down) pin, power-down register (register 0x02[5]), tri-state outputs bits (register 0x05[1:0]), pins high impedance. this state, they will draw current from pins TMDS receiver they connected However, power ISL54105 removed, pins longer high-impedance. Figure shows relevant equivalent circuit, including internal protection diodes. simplicity, only eight outputs, protection diodes, termination resistors shown. When ISL54105 drops below ~2.7V power applied external TMDS receiver, protection diodes inside ISL54105 become forward-biased,
FIGURE TEST SETUP
Given input signal shown Figure ISL54105's TMDS output signal (Figure extremely clean. output improvement over original signal coming from pattern generator both amplitude jitter.
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ISL54105
drawing current from external TMDS receiver attached
3.3VTX 3.3VRX
Using ISL54105A layout designed ISL54105 (Figure will result same behavior original version. Table full matrix.
TABLE VERSION/LAYOUT MATRIX VERSION ISL54105 FIGURE Fails Fails FIGURE Fails (not badly) Passes
VD_ESD
(41,
ISL54105A
Intersil recommends adding Schottky circuit designs reduce current drain systems using original version completely eliminate systems using ISL54105A.
ISL54105
FIGURE ISL54105 PROTECTION DIODES
Inter-Pair (Channel-to-Channel) Skew
read pointers Channel FIFO that follows have same clock, channels transition within picoseconds each other there essentially skew between transitions three channels. However FIFO read pointers positioned bits apart relative each other, introducing random, fixed channel-to-channel skew skew (much less frequently) bits. random skew introduced whenever there discontinuity input signal (typically video mode change channel selection). After CDRs lock, skew fixed until next discontinuity. This adds bits skew addition incoming skew, shown following examples. Figure shows input (the three signals) with essentially skew. After ISL54105 locks signal, there skew output, shown Figure
This non-ideal cause ISL54105 fail HDMI Compliance Test ("VOFF"). VOFF voltage across each resistor when power removed from device containing ISL54105. Modifying layout Figure Schottky diode between power VD_ESD pins, eliminates current flow from into This reduces amount current drawn from supply, there still some circuitry attached internal that will sink some current. current drawn from will lower than diode were there (reducing VOFF magnitude), still enough pass Test 7-3.
3.3VTX VD_ESD 0.1F (41, 3.3VRX
INPUT SKEW (none, this example)
ISL54105
FIGURE SCHOTTKY DIODE MODIFICATION
Intersil currently sampling ISL54105A, which fully compliant with Test when applied using circuit shown Figure ISL54105A 100% drop-in backwards compatible with ISL54105.
OUTPUT SKEW 615ps 162.5Mpixels/s)
FIGURE MAXIMUM ADDITIONAL INTERCHANNEL SKEW INPUTS WITH LITTLE SKEW
When there pre-existing skew input, ISL54105 bits channel-to-channel skew. example Figure incoming channel bits
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ISL54105
skew relative incoming green blue. FIFO's quantization (worst case) increases total skew bits.
(such vias circuitous paths) taken when routing clock lines. Minimize capacitance TMDS lines. lower capacitance, sharper rise fall times. Maintain constant, solid ground power) plane under high speed TMDS signals. route signals over gaps ground plane over other traces. Ideally each supply should bypassed ground with 0.1µF capacitor. Minimize trace length vias minimize inductance maximize noise rejection. Figure demonstrates common non-ideal layout equivalent circuit. additional trace resistance between bypass capacitor power supply/IC reduces effectiveness. Figure demonstrates better layout. this case there still series trace resistance impossible completely eliminate it), being good use, part filter, attenuating supply noise before gets reducing amount IC-generated noise that gets injected into supply. Follow good supply bypassing rules shown Figure extent possible.
POWER PLANE CBYPASS VIAS EQUIVALENT CIRCUIT POWER PLANE RVIA
INPUT SKEW (2.3 bits/1.4ns this example)
OUTPUT SKEW bits/2.5ns 162.5Mpixels/s)
FIGURE MAXIMUM ADDITIONAL INTERCHANNEL SKEW INPUTS WITH MODERATE LARGE SKEW
While increasing skew desirable, HDMI receivers required have minimum bits inter-pair skew tolerance, addition bits skew only problem with most pathological cables transmitters. does, however, limit number ISL54105s that series (although statistically, unlikely that skews would line worst-case configuration).
Layout Recommendations
Because high speed TMDS signals, careful layout critical maximize performance. following guidelines should adhered closely possible: TMDS pair traces should have characteristic impedance with respect power/ground planes with respect each other. Failure meet this requirement will increase reflections, shrinking available eye. Avoid vias high speed TMDS pairs. Vias inductance which causes discontinuity characteristic impedance trace. Keep traces bottom) PCB. TMDS clock have vias necessary, since lower speed less critical. must via, ensure vias symmetrical (put identical vias both lines differential pair). each TMDS channel, trace lengths TMDS pairs should ideally same reduce inter channel skew introduced board. trace length clock pair critical all. Since clock only used frequency reference, phase/delay inconsequential. addition, since TMDS clock frequency 1/10th pixel rate, clock signal itself much more noise-immune. liberties
RTRACE
RTRACE
CBYPASS
GROUND PLANE
FIGURE SUB-OPTIMAL BYPASS CAPACITOR LAYOUT
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ISL54105
POWER PLANE CBYPASS VIAS EQUIVALENT CIRCUIT POWER PLANE RVIA
ISL54105 7-bit address serial bus, determined ADDR0-ADDR6 bits. This allows ISL54105s independently controlled same serial bus. nominally inactive, with high. Communication begins when host issues START command taking while high (Figure 14). ISL54105 continuously monitors lines start condition will respond command until this condition been met. host then transmits 7-bit serial address plus bit, indicating next transaction will Read (R/W Write (R/W address transmitted matches that device bus, that device must respond with ACKNOWLEDGE (Figure 15). Once serial address been transmitted acknowledged, more bytes information written read from slave. Communication with selected device selected direction (read write) ended STOP command, where rises while high (Figure 14), second START command, which commonly used reverse data direction without relinquishing bus. Data serial must valid entire time high (Figure 16). achieve this, data being written ISL54105 latched delayed version rising edge SCL. delayed deglitched inside ISL54105 three crystal clock periods (120ns 25MHz crystal) eliminate spurious clock pulses that could disrupt serial communication. When contents ISL54105 being read, line updated after falling edge SCL, delayed deglitched same manner.
RTRACE
RTRACE
CBYPASS
GROUND PLANE
FIGURE OPTIMAL ("T") BYPASS CAPACITOR LAYOUT
ISL54105 Serial Communication
Overview
ISL54105 uses 2-wire serial communication with host. Serial Clock line, driven host Serial Data line, which driven devices bus. open drain allow multiple devices share same simultaneously. Communication accomplished three steps: Host selects ISL54105 wishes communicate with. Host writes initial ISL54105 Configuration Register address wishes write read from. Host writes reads from ISL54105's Configuration Register. ISL54105's internal address pointer auto increments, read registers 0x00 through 0x1B, example, would write 0x00 step then repeat step three times, with each read returning next register value.
Configuration Register Write
Figure shows views steps necessary write more words Configuration Register.
Configuration Register Read
Figure shows views steps necessary read more words from Configuration Register.
START STOP
FIGURE VALID START STOP CONDITIONS
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ISL54105
FROM HOST DATA OUTPUT FROM TRANSMITTER
DATA OUTPUT FROM RECEIVER
START
ACKNOWLEDGE
FIGURE ACKNOWLEDGE RESPONSE FROM RECEIVER
DATA STABLE DATA CHANGE DATA STABLE
FIGURE VALID DATA CHANGES
START Command ISL54105 Serial ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0
Signals beginning serial
ISL54105 Device Select Address Write first bits first byte select ISL54105 2-wire address ADDR[6:0} pins. indicating that next transaction will write. ISL54105 Register Address Write This address ISL54105's configuration register that following byte will written ISL54105 Register Data Write(s) This data written ISL54105's configuration register. Note: ISL54105's Configuration Register's address pointer auto increments after each data write: repeat this step write multiple sequential bytes data Configuration Register. Signals ending serial Data Write* dddddddd
(Repeat desired)
STOP Command Serial Address aaaaaaa0 Register Address AAAAAAAA
Signals from Host Signals from ISL54105
data write step repeated write ISL54105's Configuration Register sequentially, beginning Register Address written previous step.
FIGURE CONFIGURATION REGISTER WRITE
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ISL54105
START Command ISL54105 Serial ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 ISL54105 Device Select Address Write first bits first byte select ISL54105 2-wire address ADDR[6:0} pins. indicating that next transaction will write. ISL54105 Register Address Write This sets initial address ISL54105's configuration register subsequent reading. Ends previous transaction starts ISL54105 Serial Address Write This same 7-bit address that sent previously, however indicating that next transaction(s) will read. ISL54105 Register Data Read(s) This data read from ISL54105's configuration register. Note: ISL54105's Configuration Register's address pointer auto increments after each data read: repeat this step read multiple sequential bytes data from Configuration Register. Signals ending serial Serial Address aaaaaaa1 Adddddddd Signals beginning serial
START Command ISL54105 Serial ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0
(Repeat desired) STOP Command Serial Address aaaaaaa0
Signals from Host
Register Address AAAAAAAA
Data Read*
Signals from ISL54105
data read step repeated read from ISL54105's Configuration Register sequentially, beginning Register Address written steps previous.
FIGURE CONFIGURATION REGISTER READ
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FN6723.0 June 2008
ISL54105
Package Outline Drawing
L72.10x10B
LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (PUNCH QFN) 5/07
10.00 9.75 INDEX AREA EXPOSED AREA INDEX AREA
9.75
10.00
8.50 (4X)
0.50 0.23
(4X)
0.15
0.40 ±0.1 VIEW 4.70 REF. (4X) BOTTOM VIEW PACKAGE OUTLINE
0.100
4.70 10.00 (68X 0.50) (72X 0.23) R0.200 TYP. (72X 0.20) (72X 0.60) TYPICAL RECOMMENDED LAND PATTERN
R0.200 0.450 C0.400 (4X)
DETAIL R0.115 TYP.
DETAIL AROUND 9.75
10.00 SIDE VIEW
0.100
R0.200 AROUND
NOTES: Dimensions millimeters. Dimensions Reference Only. Dimensioning tolerancing conform JESD-MO220. Unless otherwise specified, tolerance Decimal 0.05; body tolerance: ±0.1mm Dimension applies metallized terminal measured between 0.15mm 0.30mm from terminal tip. Tiebar shown present) non-functional feature. configuration identifier optional, must located within zone indicated. identifier either mold mark feature.
0.19~ 0.245
0.08
0.65 0.85
SEATING PLANE
0.100 0.050
0.25 ±0.02
DETAIL
FN6723.0 June 2008

ISL54105 June 2008 FN6723.0 TMDS Regenerator ISL54105 h

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