Integrated-Power Buck Converter Controller with Synchronous Rectificat
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HIP5020
Integrated-Power Buck Converter Controller with Synchronous Rectification
HIP5020 high-efficiency, buck converter controller with synchronous rectification integral power MOSFETs. Integrated current sensing eliminates external resistor saves power. controller combines methods regulation: Current mode control outstanding regulation response large signal load transients, Hysteretic mode control high efficiency output currents. HIP5020 controller offers high degree flexibility. Small components switching frequency, soft-start interval load current boundary between Hysteretic modes. These adjustments enable designer best optimize trade-offs cost, efficiency size. example application guide section illustrates these trade-offs with component vendor suggestions three circuit designs. These designs suitable without modification. However, block diagram, detailed description HIP5020 component specifications enable further optimization meet specific requirements
January 1997
Features
High Efficiency Above Integrated N-Channel Synchronous Rectifier Upper MOSFETs Each Wide Input Voltage Load Range 4.5VDC 18VDC NiCd Battery Cells) 3.5ADC Automatically Switches Regulation Mode Current Mode Control Excellent Performance High Load Currents Hysteretic Control High Efficiency Light Load Currents Flexible Easy Ready-to-Use Example Applications Custom Optimization with Small Components Design Simulation Software Available Integrated, Low-Loss Current Sensing Over-Current Protection Adaptive Dead-Time Eliminates Shoot-Through 100kHz 1MHz Switching Frequency Thermally Enhanced SOIC Package
Ordering Information
PART NUMBER HIP5020DB TEMP. RANGE (oC) PACKAGE SOIC PKG. M28.3
Applications
Notebook Computers Portable Telecommunications Portable Instruments
Pinout
HIP5020 (SOIC) VIEW
PHASE PHASE PGND (WEB) VINF SLOPE PHASE PHASE SOFT OVLD CP18 BOOT
Typical Application
HIP5020 MODE CONTROL PROTECTION EFFICIENCY 0.001 3.3V
INTERNAL SUPPLY
PGND (WEB) 14µH
0.01 LOAD CURRENT
440µF REGULATION CONTROL
VOUT
CAUTION: These devices sensitive electrostatic discharge. Users should follow proper Handling Procedures. Copyright
Harris Corporation 1997
File Number
4243
HIP5020 Functional Block Diagram
CPCHARGE PUMP REGULATOR BOOT
OSCILLATOR
LATCH
UPPER GATE DRIVE
SLOPE
SLOPE GENERATOR CURRENT SENSOR
MODE CONTROL LOGIC SOFTSTART OVER-CURRENT PROTECTION
PHASE
PHASE
SOFT VINF
REFERENCE 1.26V
ERROR
LOWER GATE DRIVE LOGIC PGND 20µA
HYSTERETIC
12pF
OVLD
DESIGNATOR PHASE PGND VINF SLOPE BOOT CPOVLD SOFT FUNCTION Input Voltage Switch Node Power Ground Signal Ground Voltage Sense Filtered Input Hysteretic Current Ramp Frequency Bootstrap Bias Bias Voltage Charge Pump Capacitor Over-Load Soft Start Shutdown DESCRIPTION Connection power source (Battery). Operates from 4.5VDC 18VDC Connect output Inductor Power Return thermal interface. Solder these pins large copper ground plane. Connect output load return. divider network scales output voltage 1.26VDC. Connect low-pass (R-C) filter from VIN. resistor sets peak inductor current level during hysteretic mode. capacitor ground sets compensation ramp current mode control. capacitor ground sets oscillator frequency. capacitor Phase stores energy upper MOSFET drive. Output charge pump regulator. bypass capacitor ground. Connect capacitor between these pins charge pump generate bias power. internal charge pump inverter synchronized oscillator. high level this signals activation current limit protection. capacitor ground sets soft start interval. level suspends operation low-dissipation shutdown mode.
HIP5020
Absolute Maximum Ratings
Input Voltage, -0.3V +20.0V Supply Voltage, VCC. -0.3V +20.0V Shutdown Voltage. -0.3V +0.3V Voltage PGND (Transient) NOTE: voltages relative GND, unless otherwise specified.
Thermal Information
Thermal Resistance (Typical, Note (oC/W) Plastic SOIC Package Plastic SOIC Package (with 1in2 copper) Plastic SOIC Package (with 3in2 copper) Maximum Junction Temperature (Plastic Package) 125oC Maximum Storage Temperature Range .-65oC 150oC Maximum Lead Temperature (Soldering 10s) 300oC (SOIC Lead Tips Only)
Operating Conditions
Voltage Range, +4.5V +18.0V Temperature Range .0oC 70oC Oscillator Frequency Range 100kHz 1MHz
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
NOTE: measured with component mounted evaluation board free air.
Electrical Specifications
6.3VDC, Components referenced from Figure values 25oC MIN, limits from 125oC; Unless Otherwise Specified 25oC 125oC UNITS
PARAMETER REFERENCE Reference Voltage Temperature Stability Hysteresis Width MODE CONTROL LOGIC Under-Voltage Lockout Threshold Under-Voltage Lockout Hysteresis Shutdown Threshold Current Source POWER MOSFETs Drain Leakage Current State Resistance Phase Rise Fall Time CHARGE PUMP REGULATOR Regulation Charge Pump Disable Current Mode VINF Current Hysteretic Mode Current Shutdown
SYMBOL
TEST CONDITIONS
Total Variation, IHMI
1.26
1.235
1.285
Hysteresis Mode; IHMI
VCCUV VCCUV IHMI
IDSS rDS(ON)
VDSS 20V, VPHASE VBOOT VPHASE 12.6V; IPHASE 2ADC
0.35
VINCPN Idle
8.65V; 100kHz; 1.0µF
14.8
14.0
16.0
100kHz GND,
HIP5020
Electrical Specifications
6.3VDC, Components referenced from Figure values 25oC MIN, limits from 125oC; Unless Otherwise Specified (Continued) 25oC PARAMETER ERROR AMPLIFIER Internal Integration Capacitor Open-Loop Voltage Gain Gain-Bandwidth Product Input Bias Current SOFT START Current Source OSCILLATOR Charging Current Initial Frequency Accuracy Total Frequency Variation PROTECTIVE FUNCTION Current Limit Threshold MODULATOR Modulator Gain Minimum Time Minimum Time HYSTERETIC COMPARATOR Propagation Delay SLOPE GENERATOR Slope Capacitor Charge Current ISLOPE Step ISOFT 1.26VDC SYMBOL TEST CONDITIONS 125oC UNITS
HIP5020 Example Application Guide
HIP5020 provides flexibility meet differing needs. This section illustrates trade-off component selection three DC-DC converter circuit designs. Each circuit optimized specific goal: Circuit optimized high efficiency, Circuit optimized small size, Circuit optimized cost. Figure shows schematic common three converter designs. Table shows expected performance parameters each circuit. Table gives value each component referenced Figure Table provides listing suggested vendors major critical) components. Figures show efficiency transient performance each circuit.
BOOT
HIP5020 PHASE CPVINF PGND SLOPE OVLD
ON/OFF
SOFT
FIGURE EXAMPLE APPLICATION CIRCUIT
TABLE EXAMPLE APPLICATION PERFORMANCE PARAMETERS These characteristics circuit shown Figure with components given Tables PARAMETER Input Voltage Typical Range Switching Frequency Output Voltage Variation Line Regulation Load Regulation Output Voltage Ripple Full Load Light Load Efficiency Full load Peak Light Load Estimated Circuit Area Tallest Component Normalized Circuit Cost Ratio total circuit cost Circuit Initial Setting Input Voltage Range; 1ADC 3ADC, Typical Bandwidth 20MHz 3ADC, Typical 50mADC, Typical CONDITIONS CIRCUIT HIGH EFFICIENCY Li-Ion Cells: 11.1 ±15% ±3.5% ±0.1 ±0.3 CIRCUIT SMALL SIZE Li-Ion Cells: ±15% ±2.2% ±0.1 ±0.3 CIRCUIT COST Nicd Cells: 10.8 ±20% ±3.5% ±0.1 ±0.4 UNITS
3ADC, Typical 2ADC, Typical 50mADC, Typical
0.45
0.24
0.68 0.75
HIP5020
TABLE COMPONENT SUGGESTIONS EXAMPLE APPLICATION CIRCUITS COMPONENT CIRCUIT MBR0540 MBR0540 16µH, 220µF, OS-CON ESRMAX (100kHz) 100µF, OS-CON ESRMAX (100kHz) 0.1µF ±20% Ceramic ±20% Ceramic ±20% Ceramic 470pF Ceramic 680pF Ceramic 0.1µF ±20% Ceramic 220pF Ceramic 0.1µF ±20% Ceramic 0.1µF ±20% Ceramic 562K 348K 33.2K 200K 49.9K CIRCUIT MBR0540 Used 5µH, 220µF, Tantalum ESRMAX (100kHz) 100m 100µF, Tantalum ESRMAX (100kHz) 100m 0.1µF ±10% Ceramic 0.22µF ±10% Ceramic 0.22µF ±10% Ceramic 150pF Ceramic 390pF Ceramic 0.033µF ±10% Ceramic Used 0.1µF ±20% Ceramic 0.1µF ±20% Ceramic (Note) 12.4K (Note) 37.4K Used CIRCUIT 1N4148 Used 26µH, 390µF, 25V, Aluminum ESRMAX (100kHz) 390µF, Aluminum ESRMAX (100kHz) 0.1µF ±20% Ceramic ±20% Ceramic ±20% Ceramic 820pF ±10% Ceramic 1200pF Ceramic 0.01µF ±10% Ceramic Used 0.1µF ±20% Ceramic 0.1µF ±20% Ceramic 100K 61.9K 49.9K Used
NOTE: Both resistors available SOT-23 from California Micro Devices part PAC27A01
TABLE SUGGESTED SUPPLIERS COMPONENT Capacitors Aluminum Capacitors Aluminum Ceramic Capacitors Tantalum Capacitors Ceramic Tantalum Capacitors Aluminum SUPPLIER Sanyo PHONE NUMBER 501-633-5030 COMPONENT Inductors OCTA-PAC Inductors SUPPLIER Coiltronics PHONE NUMBER 407-241-7876
Panasonic
0774-32-1111
Pulse Engineering International Micrometals
619-674-8100
Sprague
207-324-4140
Inductors
607-785-1109
207-282-5111
Magnetic Cores Powdered Iron Magnetic Cores Kool Magnetic Cores Microlite
714-630-7420
United Chemi-Con
708-696-2000
Magnetics
412-282-8282
AlliedSignal Inc.
201-581-7653
HIP5020 Typical Performance Curves
3.3VDC OUTPUT VOLTAGE 12.6V INDUCTOR CURRENT 0.01 LOAD CURRENT EFFICIENCY 3.46 3.34 3.32 3.30 3.28
8.1V
0.001
TIME (ms)
FIGURE
FIGURE
FIGURE HIGH-EFFICIENCY CIRCUIT MEASURED PERFORMANCE EFFICIENCY LOAD CURRENT HYSTERETIC MODE OPERATION (VIN 11.1VDC, 0.1ADC
3.3VDC EFFICIENCY 5.4V OUTPUT VOLTAGE INDUCTOR CURRENT 0.01 LOAD CURRENT 3.32 3.31 3.30 3.29 3.28 3.27 0.000 0.040 0.080 0.120 TIME (ms) 0.160 0.200
0.001
FIGURE
FIGURE
FIGURE SMALL-SIZE CIRCUIT MEASURED PERFORMANCE EFFICIENCY LOAD CURRENT FULL LOAD TRANSIENT (1A/µs)
OUTPUT VOLTAGE INDUCTOR CURRENT 14.4V 3.34 3.32 3.30 3.28 3.26
EFFICIENCY
8.1V
0.001
0.01
LOAD CURRENT
TIME (ms)
FIGURE
FIGURE
FIGURE LOW-COST CIRCUIT PERFORMANCE PREDICTIONS EFFICIENCY LOAD CURRENT FULL LOAD TRANSIENT (100A/ms)
HIP5020
Design Information
HIP5020 optimized battery power systems with 4.5V input. integrated MOSFETs along with output filter form synchronous rectified, step-down (buck) converter. output regulated high output current peak-current-mode control. light loads, control automatically transitions hysteretic mode regulate output. HIP5020 regulates output voltage with peak-current control mode. peak-current-mode feedback, MOSFETs output inductor, parts peak-current control loop. outer voltage regulation loop then programs peak current level required. When averaged over many switching cycles, entire peakcurrent control loop simplified described voltage controlled current source. Figure shows simplified diagram this operation. current source supplies output capacitor load. outer voltage regulation loop consists error amplifier compensation components. error amplifier programs inductor current described above) value required regulate output voltage. Both error amplifier hysteretic comparator monitor feedback (FB) pin. During mode, feedback node voltage (VFB) held reference voltage (REF) voltage feedback loop. related
Detailed Operating following description refers symbols components functioal Block Diagram Figure Figure shows HIP5020 DC/DC converter. Operating Modes HIP5020 modes operation; Shutdown, Start-up, Hysteretic modes. controller draws only from input supply Shutdown mode. This mode activated when high. controller enters Start-up mode releasing pin, charge pump turns-on increase above under-voltage lockout threshold. Start-up mode, voltage SOFT increases rate capacitor SOFT pin. SOFT voltage limits rate-of-rise output voltage. output voltage regulated with peak current control mode high output current. output currents, controller automatically transitions Hysteretic mode output regulation. this mode, hysteretic comparator cycles control (RUN High) (RUN Low) function output voltage level. When (RUN Low), bias power removed from most control's functions (only reference hysteretic comparator operate with Low). converter replenishes output capacitor charge with short duration power cycles (RUN High) converter dissipates very little average power. resistor (R4) programs load current boundary (HMI) between Hysteretic modes. Mode HIP5020 operates mode high output currents. Each clock cycle oscillator sets Latch turns-on high side MOSFET (See Functional Block Diagram). current sensor supplies voltage proportional current high side MOSFET. Comparator resets latch once current signal exceeds summation error amplifier slope signals. upper MOSFET turns latch enables lower gate drive logic. current output inductor continues flow, reducing PHASE voltage displacing charge capacitances PHASE pin). lower MOSFET turns-on after voltage PHASE falls ground monitored phase comparator. lower MOSFET remains `on' continuous output inductor current until next cycle. discontinuous inductor current operation, phase comparator signals lower gate drive turn-off lower MOSFET when inductor current reaches zero monitoring phase voltage (rDS(ON)
CURRENT LIMIT HYSTERETIC COMPARATOR REF+ ERROR
PEAK-CURRENT CONTROL LOOP LOAD OUTPUT CAPACITOR
REF-
HIP5020
LOWER LIMIT
FIGURE SIMPLIFIED DIAGRAM OUTPUT VOLTAGE REGULATION MODE SWITCHING
Limiting error amplifier output voltage range provides both current-limit protection mechanism setting load current boundary between Hysteretic modes. Figure shows modes operation function error amplifier output load current. error amplifier output voltage tracks inductor current. upper error amplifier clamp limits peak inductor current which reduces pulse-width duty factor). This reduces output voltage with constant current characteristic. lower error amplifier limit sets minimum inductor current. load current demand below minimum inductor current, excess current adds charge output capacitor output voltage increases. voltage feedback (FB) also increases converter operates Hysteretic mode. lower error amplifier limit voltage (Hysteretic Mode Current) pin. level (VHMI) sets Run-to-Hysteretic mode load current boundary.
HIP5020
ERROR OUTPUT
output voltage ripple during Hysteretic Mode function (Hysteretic Mode Current) setting, output capacitor ESR, hysteretic voltage trip points. approximate ripple voltage
HYSTERETIC MODE VHMI OUTPUT LOAD MODE CURRENT LIMIT
Where hysteresis width (~20mV) (A/V) factor error amplifier output voltage peak current control gain (modulator gain). Protective Modes HIP5020 provides cycle-by-cycle current limiting protects against over-current. cycle-by-cycle current limit reduces pulse width (duty factor) peak inductor current levels exceeding current limit minimum). This results constant current output characteristic. OVLD toggles high indicate overload condition. Should current limit cause small pulse width saturating output inductor, over-current protection activates softstart cycle. simultaneous occurrence minimum pulse width current limit signals over-current condition. converter enters start-up mode fully discharging soft-start capacitor inhibiting operation. With continuous overload, over-current protection triggers soft-start function which inhibits operation until after soft-start capacitor first fully charges then fully discharges. This results very average input current. Soft-Start soft-start function programmed capacitor SOFT (C10). This capacitor initially discharged. Releasing pin, increasing above undervoltage lockout threshold initiates soft-start interval. internal 10µA source charges C10, converter output follows capacitor voltage, VSOFT. control establishes closed loop regulation when output voltage approaches level reference. Initiating shutdown mode rapidly discharges capacitor C10. Releasing initiates another start-up mode which charges capacitor VCC.
TIME
FIGURE OPERATING MODES WITH ERROR AMPLIFIER CLAMPS
Hysteretic Mode HIP5020 operates hysteretic mode with output current. this mode, hysteretic comparator cycles control (RUN High) (RUN Low) function output voltage voltage level. Figure illustrates averaged Hysteretic Mode operation with reference Figure light load, error amplifier output voltage held voltage (VHMI). This level commands inductor current that exceeds load current. excess current flows into output capacitor which increases output voltage (VO). voltage feedback loop longer holds reference voltage. When increases Upper Hysteretic Trip Level, signal transitions power-down most control's functions, load supplied output capacitor. After (and equivalent output voltage) drops below Lower Hysteretic Trip Level, transitions High, turning controller. converter replenishes charge output capacitor (C1). This cycle repeats regulate output voltage.
FIGURE TYPICAL HYSTERETIC MODE OPERATION
HIP5020 maintains peak-current control during Hysteretic mode. When signal transitions High, control functions reenergize oscillator sets Latch which turns-on high side MOSFET. inductor current increases resets latch turn MOSFET. This cycle-by-cycle operation identical mode operation. However, hysteretic mode, inductor current regulated level proportional VHMI. With very light loads, converter replenishes output capacitor charge switching cycles (RUN High) converter dissipates very little average power. Operation automatically transitions mode load increases above Run-to-Hysteretic mode load current boundary; signal simply stays High.
Should exceed upper hysteretic trip level, internal 10µA source stops charging C10. soft-start interval will resume when drops below lower hysteretic trip level.
Detailed Component Selection
application circuits shown Figure described Tables illustrate component trade-off achieve size, cost efficiency goals. design simulation software program available that simplifies small signal component selection (http://www.semi.harris.com). This section provides additional guidance selecting alternate components.
HIP5020
Output Capacitor output capacitor, smooths output voltage ripple DC-DC converter. size value depend upon output ripple requirement, dielectric characteristics, value output inductance switching frequency. Choose capacitor with impedance switching frequency meet output voltage ripple requirement. only specialized low-ESR capacitors intended switching-regulator applications. Capacitor impedance above switching frequency should also minimized. During Hysteretic mode operation, transition from high causes inductor current ramp from zero level very short time. This rate current change across output capacitor's equivalent series inductance (ESL) causes voltage spike that appears (attenuated) pin. rate current change must limited prevent hysteretic comparator from toggling between high low. Unfortunately, specified parameter. Work with your capacitor supplier measure capacitor's impedance switching frequency (and first harmonics switching frequency) select suitable component. most cases, multiple electrolytic capacitors small case size perform better than single large case capacitor. Output Inductor output inductor, sets ripple current influences converter efficiency. ripple current, related inductance switching frequency (FS), continuous inductor current. Increasing inductance switching frequency lowers ripple current output ripple voltage. inductance determined
Control Loop Design HIP5020 realizes excellent transient response with proper control loop design. device utilizes peak-current control with entire current loop integrated within HIP5020. Additionally, HIP5020 includes 12pF integration capacitor across error amplifier. (See Detailed Operating Description above.) Some applications need only resister capacitor complete design. capacitor, adds compensation slope peak current control loop (see Slope Compensation below). shows closed loop transfer function peaking around half switching frequency. stable design, make sure closed loop gain half switching frequency below -10dB. error amplifier compensation components regulate output voltage controlling current loop shown Figure compensation components shown Figure realize lead-lag circuit. resistor adjusts loop gain converter resistor capacitor pole zero. resistor does appear lead-lag transfer function. sets output voltage level. First stabilize control loop selecting then determine desired output voltage level.
REFERENCE 1.26V
ERROR COMPARATOR
HIP5020 12pF
Inductance function core permeability, core size, square number turns. power dissipation inductor also dependent upon number turns core. general, most power dissipation inductor's winding. Therefore, high permeability core material minimize number turns. sure flux full load current does saturate core. Recommended core materials include: Microlitefrom Allied Signal, ferrite, Kool-MuTM, molypermalloy (MMP), powdered iron. Switching Frequency oscillator produces sawtooth wave with amplitude 1.26V. switching frequency Select closest standard capacitance value according following formula:
FIGURE LEAD-LAG COMPENSATION CIRCUIT
Using built-in 12pF integration capacitor across error amplifier, transfer function, G(s) lead-lag network
where
Higher switching frequency decreases size output filter enables higher bandwidth converter faster response load transient. However, higher frequencies dissipate more power less efficient converter.
HIP5020 design simulation software (available Harris site) computes these values greatly simplifies following compensation design process. design DC-DC converter stable operation: Determine output capacitor's zero frequency, fESR which given Place compensation pole (p/2) zero frequency, fESR
Microliteis trademark Allied Signal Kool-Muis trademark Spang Company
1-10
HIP5020
Determine desired converter bandwidth frequency where loop gain unity). Bandwidth must below switching frequency. reasonable bandwidth approximately 1/10 switching frequency. Select compensation zero well below desired bandwidth frequency adjust necessary achieve desired phase margin (40o Minimum). Adjust gain (via iterate compensation zero gain needed achieve desired bandwidth phase margin. Measure closed-loop transfer function both minimum maximum input voltage both full load Run-to-Hysteretic mode load current boundary. sure note phase margin gain margin. single component compensate control loop detailed characteristics output capacitor, bandwidth, switching frequency meet strict requirements. bandwidth unity gain frequency) must much greater than zero frequency (fESR) much less than twice switching frequency. Additionally break frequency output capacitor's must much greater than switching frequency. these conditions exist, zero provides necessary phase boost. However, note that well controlled parameter variable with temperature aging. Select proper compensation gain confirm selection with closed-loop measurements. Additionally determine worst case variation estimate this effect converter stability. Output Voltage Setting resistor divider sets output voltage function reference voltage. Select achieve desired bandwidth then determine from:
1.26 1.26
switching frequency input voltage below 9.8V. Select capacitors according following:
0.088 0.12
gate upper N-channel MOSFET driven above input voltage internal gate drive with power supplied bootstrap circuit fast recovery, leakage diode recommended should high quality ceramic capacitor. Hysteretic Mode Current Setting voltage sets load current boundary between mode Hysteretic mode. This setting enables designer trade-off efficiency output voltage ripple output current. output voltage ripple higher Hysteretic mode compared with mode. Many systems tolerate higher power supply ripple light loads because reduced load induced ripple. designer should select load current boundary based upon converter efficiency characteristics known load characteristics. example, HIP5020 converter powering microprocessor load might select boundary between sleep active states operation. ripple voltage highest load current just below mode boundary. ripple voltage function hysteresis width, resistors hysteretic current setting (HMI) output capacitor described Hysteretic Mode section. Figure shows efficiency versus load different VHMI settings. efficiency light load current higher with higher settings. efficiency light load current higher VHMI setting. However, more efficient design higher ripple voltage load current between 0.2A 0.6A. load sensitive power supply ripple during this load range, lower efficiency setting should used.
VHMI 0.15V CIRCUIT 6VDC 25oC VHMI 0.5V
Slope Compensation Slope compensation necessary avoid current loop instability duty ratios above 50%. Select amount slope compensation according following:
EFFICIENCY
output voltage regulation improves with integrated resistor network. integrating resistors, variations track variations ratio remains constant this minimizes output voltage variation improve regulation. Integrated resistor networks available small SOT-23 packages such used Circuit
0.001
0.01
This value capacitance provides compensation ramp that reflected output inductor decreasing current slope. Charge Pump Bootstrap Design charge pump bootstrap circuit supply internal bias power HIP5020. majority bias power goes gate drives. charge pump operates
LOAD CURRENT
FIGURE EFFICIENCY LOAD CURRENT
voltage used clamp lower limit error amplifier output voltage minimum peak inductor current. This voltage 20µA current source resistor,
1-11
HIP5020
Soft-Start Soft-Start capacitor, that output voltage ramps final value with current between hysteretic mode current rated current. minimum value determined from:
SOFT
Detailed Characteristics
Charge Pump Regulator charge pump regulator supplies control power (VCC) internal functions HIP5020. charge pump operates input voltage levels below 9.8V disabled input voltages above 9.8V. Figure shows charge pump output voltage (VCC) function input voltage (VIN). input voltages below 9.8V nominally, charge pump operates regions voltage doubler voltage regulator. charge pump operates normal voltage doubler when below approximately 14.8V. charge pump limits approximately 14.8V regulation region. input voltages above 9.8V, charge pump disabled follows input voltage less diode drop.
where SOFT
Larger values will extend soft-start interval, TSOFT loading during Start-up mode lengthens TSOFT Bypass Filter Capacitors Capacitor supplies leading edge current each switching cycle. high quality (X7R dielectric ceramic) 0.1µF surface-mount capacitor recommended. Locate directly across PGND pins. Bypass internal supply with high quality (X7R dielectric ceramic) surface-mount capacitor (C4). Locate directly across pins. value capacitor should selected described Charge Pump Regulator above. single high quality (X7R dielectric ceramic) capacitor usually adequate. Some applications need high capacitance, electrolytic charge-pump operation. these applications, high quality capacitor parallel with electrolytic recommended. Locate directly across pins. form low-pass filter bias supply (VINF) reference hysteretic comparator functions. resistor 0.1µF Capacitor recommended. Locate directly across VINF pins. Thermal Design power ground (PGND) pins SOIC package provide thermal conduction path removing heat from HIP5020. Inside package, HIP5020 mounted copper structure with connections PGND (pins 23). Solder SOIC circuit board with copper ground plane remove heat from package. With good component layout square inches copper ground plane, junction-to-ambient thermal resistance 36oC/W. Most converter's power dissipation will HIP5020 output inductor, power dissipated HIP5020 estimated from converter's full load efficiency subtracting inductor's power dissipation junction temperature rise above ambient this power multiplied thermal resistance. HIP5020 design simulation software more accurate thermal simulations. sure keep junction temperature below 125oC reliable operation. Careful component layout good thermal design maximized efficiency reliability converter.
REGULATION REGION VOLTAGE DOUBLER REGION CHARGE PUMP DISABLED
INPUT VOLTAGE
FIGURE CHARGE PUMP REGULATOR INPUT VOLTAGE CHARACTERISTICS
charge pump used supply current external loads pin. Figure shows regulation characteristics charge pump various operating regions. These characteristics DC-DC converter (Circuit operating 100kHz with capacitors
CIRCUIT 8.65VDC
12VDC
5VDC
EXTERNAL LOAD (MADC)
FIGURE BIAS VOLTAGE (VCC) EXTERNAL LOAD CURRENT
1-12
HIP5020
charge pump suitable some applications external loads. sure that load tolerate voltage variation with input voltage. During Hysteretic Mode, external load should removed when converter turns off. Note that charge pump oscillator disabled with (see Operating Modes). external load could cause under-voltage lockout trip subsequent soft-start cycle. Light Load Power Dissipation converter efficiency power dissipation light load mainly function bias supplied HIP5020. Figure shows input current function input voltage states signal. summation both current into VINF pins. curve with signal High does include gate drive power.
High
MOSFET On-Resistance Conduction losses significant portion power dissipation DC-DC converter. HIP5020 conduction losses product square average output current MOSFET on-resistance rDS(ON). rDS(ON) MOSFETs function junction temperature. changes with input voltage shown Figure above. Figure shows maximum rDS(ON) both MOSFETs function input voltage junction temperature 25oC. junction temperature HIP5020 also effects rDS(ON). Figure shows rDS(ON) function temperature three gate voltage levels. rDS(ON) estimated given input voltage junction temperature follows: Assume that gate voltage equal VCC. Find gate voltage 25oC from Figure Multiply this number rDS(ON) shown Figure Interpolate necessary.
(µA)
0.10 25oC 0.09
rDS(ON)
0.08
0.07
FIGURE BIAS POWER CHARACTERISTICS
gate drive power function MOSFETs gate charge, voltage switching frequency. Figure shows combined gate energy required internal MOSFETs with charge pump characteristics. determine total bias power: Multiply value Figure switching frequency. product voltage current from High curve Figure Multiply ratio time Hysteretic period. product voltage current from curve Figure
0.06
0.05
INPUT VOLTAGE
FIGURE rDS(ON) INPUT VOLTAGE
VG-S VG-S
GATE ENERGY (µJ)
rDS(ON)
VG-S
TEMPERATURE (oC)
FIGURE rDS(ON) JUNCTION TEMPERATURE
FIGURE MOSFET GATE ENERGY CHARACTERISTICS INPUT VOLTAGE
1-13
HIP5020 Application Hints
Short Duration Interval Some converter designs observe series short interval pulses (RUN High) hysteretic mode that reduce light-load efficiency. interval interrupted voltage crossing over Upper Hysteretic Trip Level before output capacitor gains sufficient charge. This operation caused number factors: Poor physical layout. wide traces connect power components. Poor component choice. only power supply specific electrolytic capacitors. Additionally ceramic capacitors parallel with bulk electrolytic capacitors. Sudden voltage excursions across output capacitor error amplifier output. sure clear layout problems first. Poor layout only causes efficiency problems, source noise surrounding circuits. short interval still observed, capacitor added across each During transition from high, voltage starts Lower Hysteretic Trip Level. error amplifier activates output slews VHMI. This causes increase current compensation capacitor. Adding capacitor across slows rate voltage increase during transition from high decreases error amplifier slew rate. Voltage excursions across output capacitor circuit board traces after transition from high results increase inductor current ramps level, output voltage increases output capacitor's ESL. This voltage spike attenuated resistor divider, still appears pin. small capacitor across further attenuates output voltage spikes. small capacitor eliminates short duration interval, will reduce output voltage spikes. better solution better, higher quality output capacitor with ESL. Bootstrap Phase Diodes bootstrap function requires diode supply gate drive power upper N-channel MOSFET. Schottky recommended most applications fast switching speed forward voltage. fast-recovery diode used switching frequency, cost sensitive applications. Many applications will need Schottky diode from phase ground. internal body diode integrated MOSFET sufficiently fast. small Schottky diode added improve light load efficiency. This diode only conducts during short intervals 50ns) before after lower MOSFET conducts. most cases, Schottky ratted 0.5A sufficient.
1-14
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