WITH RISK COST REDUCTION MADE EASY today's market, cost
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FPGA/CPLD CONVERSION SERVICE
WITH
RISK
COST REDUCTION MADE EASY
today's market, cost reduction must maintain competitiveness. products need designed fast, before competition catches FPGA/CPLD usage provides early feedback designers. This allows them tune application prior production. FPGAs provide flexible combination between quick design cycle pre-production phases. specific design, customer paying FPGA resources that used. Programming associated PROM costs remain. soon customer's design frozen -cost well quality, power consumption manufacturability- become important criteria. This where Atmel conversion service helps purchasing engineering. Ultimate Logic Conversion (ULC) offers pin-to-pin, drop-in replacement customer's FPGA, generating immediate cost savings. Atmel does work. FPGAs converted with minimum involvement customer's engineering
Equivalent complexity, much smaller FPGA,
Atmel ULC, cial obligation does work customer's application
(sign-off required
0.25 0.18 technologies).
Atmel guaran-
tees working ULC. Atmel realizes that sometimes improvements features must added application remain competitive. This require change customer's code. Atmel will provide with additional charges customer have taken delivery least units 0.35 technology. With more than years experience 1,500 successful conversions, Atmel proven ability convert FPGAs help maximize cost reduction.
resources. Atmel's innovative design flow, based Verify-before-silicon techniques, allows Atmel deliver insystem guaranteed parts. There finan-
Cost Reduction Easy
FPGA replacement, immediate cost savings with risk
Minimum customer engineering involvement
In-system Guarantee Risk-Free Flexibility
Verify-before-silicon technique*
Charged only parts work
Free code updating after units delivered
0.35 technologies
FPGA device, programming resources total silicon area! With Atmel ULCs, these programming resources
removed saving space, thereby cost. customer also decide smaller package save board space.
FPGA Basic Cell Layout (110
These programming resources total silicon area!
years, Atmel's ULCs have been successfully replacing expensive FPGAs, saving space bringing easy, costeffective solutions wide range applications. High-end Modem Banking Machine
Sound Card Automotive
Road extended range design manufacturing capability available within Atmel offers cost-effective
WORLD CLASS TECHNOLOGY
solutions future. Complexity Kgates I/O's
2900 Kgate array gates I/O's 1.8V 0.18 Metal Layers I/O: 1.8V/3.3V 1730 Kbits DPRAM 1500 Kgate array gates I/O's 2.5V 0.25 Metal Layers I/O: 2.5V/3.3V-5V 1380 Kbits DPRAM Kgate array gates I/O's 2.5V/3.3V 0.35 Metal Layers I/O: 3.3V/5V Kbits DPRAM
Kgates I/O's I/O: 3.3V/5V
1400 Kgate array gates I/O's 2.5V/3.3V 0.35 Metal Layers buffer pitch I/O: 3.3V/5V
1998
1999
2000
2001
2002
Memory Blocks Supported Altera® Xilinx® DPRAM blocks others (Actel®, Quicklogic®, etc.) 0.35 Kbits DPRAM Kgate array gates.* 0.25 1380 Kbits DPRAM 1500 Kgate array gates.* 0.18 1730 Kbits DPRAM 2900 Kgate array gates.*
gate array gate FPGA gates)
Special IO's Supported CMOS, TTL, LVCMOS, LVTTL, PECL, (33/66 MHz) levels, GTL/GTL+, HSTL, SSTL2, SSTL3, CCT, AGP, LVDS. Telecommunication: core, 32/64, CAN, controller, etc. Communication: Reed-Solomon® decoder, Viterbi® decoder, HDLC, APCM. Others: 8051, FFT, PWM, etc. Power Supply 1.8V, 2.5V, 3.3V 3.3V core with tolerant/compliant I/O's. 2.5V core with 3.3V tolerant/compliant I/O's. Extensive Packaging Capabilities Latest fine pitch (1.0 compatible with
PLL/DLL 100% compatible with Altera Xilinx. Power Consumption static consumption about less than Virtex®, Apex® series. dynamic consumption about less than Virtex, Apex series. Frequency Matrix 0.35 0.25 0.18 Core (MHz) Periphery (MHz)
Xilinx Altera. Count: from 1156. Body Size: from CQFP, PQFP, TQFP, VQFP, JLCC, PLCC, PBGA, SOIC, TSOP, PDIP, Chip Scale, etc.
Feasibility Study Flow Atmel performs feasibility study every design before final conversion verification work started. This allows Atmel confirm size, package conversion lead-time, also discuss technical issues with customer. feasibility study, Atmel requires:
WORK
Design netlist (edif, Verilog®, VHDL, etc.) Test vectors available)
Circuit pinout checklist completed
FPGA Netlist
Customer Pinout
Checklist
Retarget/Optimization
Atmel Bonding Diagram
Synthesis Atmel Tool (Leonardo®, Synopsys®, etc.)
Atmel Netlist
Design Rule Check
Atmel Tool
Pre-Layout Functional Simulations
ModelSim (Mentor
Fault Simulations/ATPG
Advisor (Mentor)
Conversion Flow After receiving initial purchase order, design team proceeds with conversion verification programmable logic device ULC.
Clock Tree Synthesis Circuit Layout
Atmel Tool GateEnsemble® (Cadence®)
Atmel Netlist Delays
Static Timing Analysis
Prime Time® (Synopsys)
Functional Simulations
ModelSim (Mentor)
Adjust Timing
Programmed Parts
Functional Timing Comparison
Atmel Tool Tester (Schlumberger S15®, Nextest Maverick®)
First Article Delivery ULCs manufactured first pre-production parts delivered validation application. After customer approval, full production started.
CUSTOMER
Conversion Centers Near Customers USA: Europe: Jose Nantes France Eching Germany Camberley Milan Italy Nantes France
Asia Pacific:
Optional Improvements:
FPGAs merge single ASIC obsolescence replacement
Boundary scan insertion JTAG insertion
Customer Service Dedicated Product Line
Close customer interface support First Pass Success conversions done since 1998
Delivery Plan Agreement Consignment stock available Accounts
Field Application Support Dedicated engineers available interface with customers technical issues.
Quality Test
100% Atmel parts tested Optimized fault coverage Quality reliability monitoring
Obsolete ASICs
Atmel also converts ASICs into ULCs with similar conditions customers want develop second source avoid process obsolescence with their current ASIC vendor.
FPGA/CPLD
FPGA
CPLD
Altera
FLEX10K FLEX6000 ACEX
FLEX8000 APEX20K
MAX7000/A/B/S MAX9000
MAX5000 MAX3000/A
WWW.ATMEL.COM
Xilinx
XC4000E/EX/XL/XV/XLA XC3000 Spartan Spartan XC5200 Virtex VirtexE SpartanII SpartanIIE VirtexII
XC9500 XC7000
XC9500XV/XL
CoolRunner® XPLA2/XPLA3 CoolRunnerII
Actel
SX-A 40MX 42MX ProASIC
3200DX ACT3 1200XL ACT1 ACT2
Lattice
ispLSI5000V ispLSI6000 ispLSI8000 ipsLSI1000E/EA ispLSI2000/V/VE/E/VL/A ispLSI3000 MACH1 MACH2 MACH3 4/4A/4LV MACH5/5A/5LV
Agere®
ATT3000 ORCA2C-A ORCA2T-A ORCA2T-B ORCA3/3+
QuickLogic Cypress
pASIC1/2/3 Flash370 MAX340 Ultra37000 Delta39K
FPGA/CPLDs continually being introduced programmable logic vendors. device version device interested converting listed, contact your local Atmel sales representative sales office.
Xilinx Others Cypress Philips Actel Altera
Quicklogic Agere Lattice
Percentage 1,500 successful conversions FPGA/CPLD vendors.
Corporate Headquarters 2325 Orchard Parkway Jose, 95131, TEL.: (1)408) 441-0311 FAX.: (1)(408) 487-2600 Europe Atmel Sarl Route Arsenaux Case Postale CH-1705 Fribourg Switzerland TEL.: (41) 26-426-5555 FAX.: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza Mody Road Tsimhatsui East Kowloon Hong Kong TEL.: (852) 2721-9778 FAX.: (852) 2722-1369 Japan Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL.: (81) 3-3523-3551 FAX.: (81) 3-3523-7581 Product Contact Chantrerie 70602 44306 Nantes Cedex France TEL.: (33) FAX.: (33) e-mail literature@atmel.com Site http://www.atmel.com
©Atmel Corporation, 2002 Atmel Corporation makes warranty products, other than those expressly contained Company's standard warranty which detailed Atmel's Terms Conditions located Company's site. Company assumes responsibility errors which appear this document, reserves right change devices specifications detailed herein time without notice, does make commitment update information contained herein. licenses patents other intellectual property Atmel granted Company connection with sale Atmel products, expressly implication. Atmel's products authorized critical components life support devices systems. Atmel® registered trademark Atmel Corporation. Actel® registered trademark Actel Corporation, Agere® registered trademark Agere Systems, Inc., Altera® registered trademark Altera Corporation, Cypress® registered trademark Cypress Semiconductor Corporation, Advisor®, ModelSim® registered trademarks Mentor Graphics, Apex®, Gate Ensemble®, Reed-Solomon®, Viterbi® registered trademarks Cadence Design Systems, Inc., Innoveda DxDesigner® registered trademark Innoveda, Inc., Lattice® registered trademark Lattice Semiconductor Corporation, Leonardo Spectrum® registered trademark Synopsys, Nextest Maverick® registered trademark Nextest Systems Corporation, Prime Time® registered trademark Synopsys, Inc., QuickLogic registered trademark QuickLogic Corporation®, Sclumberger S15® registered trademark Schlumberger Technology, CoolRunner®, Spartan®, Virtex®, Xilinx® registered trademarks Xilinx, Inc. Other terms products trademarks Atmel others. Ref.: 4011A-ULC-05/02/15M
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