8-BIT, ECL-INTERFACED PROGRAMMABLE DELAY LINE (SERIES PDU10256H)

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8-BIT, ECL-INTERFACED PROGRAMMABLE DELAY LINE (SERIES PDU10256H)

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PDU10256H
8-BIT, ECL-INTERFACED PROGRAMMABLE DELAY LINE (SERIES PDU10256H)
Digitally programmable delay steps Monotonic delay-versus-address variation Precise stable delays Input outputs fully 10KH-ECL interfaced buffered Fits 48-pin socket
data delay devices, inc.
PACKAGES
DESCRIPTIONS
A0-A7 Signal Input Signal Output Address Bits Output Enable Volts Ground
PDU10256H-xxC5 PDU10256H-xxMC5
PDU10256H-xx PDU10256H-xxM
FUNCTIONAL DESCRIPTION
PDU10256H-series device 8-bit digitally programmable delay line. delay, TDA, from input (IN) output (OUT) depends address code (A7-A0) according following formula: TINC where address code, TINC incremental delay device, inherent delay device. incremental delay specified dash number device range from 0.5ns through 10ns, inclusively. enable (ENB) held during normal operation. When this signal brought HIGH, forced into state. address latched must remain asserted during normal operation.
SERIES SPECIFICATIONS
Total programmed delay tolerance: 2ns, whichever greater Inherent delay (TD0): 12ns typical Setup time propagation delay: Address input setup (TAIS): 3.6ns Disable output delay (TDISO): 1.7ns typical Operating temperature: Temperature coefficient: 100PPM/°C (excludes TD0) Supply voltage VEE: -5VDC Power Dissipation: 925mw typical load) Minimum pulse width: total delay
DASH NUMBER SPECIFICATIONS
Part Number PDU10256H-.5 PDU10256H-1 PDU10256H-2 PDU10256H-3 PDU10256H-4 PDU10256H-5 PDU10256H-6 PDU10256H-8 PDU10256H-10 Incremental Delay Step (ns) 10.0 Total Delay (ns) 127.5 12.8 25.5 38.2 1020 51.0 1275 63.8 1530 76.5 2040 2550
©1997 Data Delay Devices
NOTE: dash number between shown also available.
#97047
12/17/97
DATA DELAY DEVICES, INC.
Prospect Ave. Clifton, 07013
PDU10256H
APPLICATION NOTES
ADDRESS UPDATE
PDU10256H memory device. such, special precautions must taken when changing delay address order prevent spurious output signals. timing restrictions shown Figure After last signal edge delayed appeared pin, minimum time, TOAX, required before address lines change. This time given following relation: TOAX i-1) TINC where address codes, respectively. Violation this constraint may, depending history input signal, cause spurious signals appear pin. possibility spurious signals persists until required TOAX elapsed. similar situation occurs when using signal disable output while active. this case, unit must held disabled state until device able "clear" itself. This achieved holding signal high signal time given TDISH TINC Violation this constraint may, depending history input signal, cause spurious signals appear pin. possibility spurious signals persists until required TDISH elapsed.
INPUT RESTRICTIONS
There three types restrictions input pulse width period listed Characteristics table. recommended conditions those which delay tolerance specifications monotonicity guaranteed. suggested conditions those which signals will propagate through unit without significant distortion. absolute conditions those which unit will produce some type output given input. When operating unit between recommended absolute conditions, delays deviate from their values frequency. However, these deviations will remain constant from pulse pulse input pulse width period remain fixed. other words, delay unit exhibits frequency pulse width dependence when operated beyond recommended conditions. Please consult technical staff Data Delay Devices your application specific high-frequency requirements. Please note that increment tolerances listed represent design goal. Although most delay increments will fall within tolerance, they guaranteed throughout address range unit. Monotonicity however, guaranteed over addresses.
A7-A0 TAENS TENIS
TOAX TAIS
PWIN
TDISH
PWOUT
TDISO
Figure Timing Diagram
#97047
12/17/97
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
PDU10256H
DEVICE SPECIFICATIONS
TABLE CHARACTERISTICS
PARAMETER Total Programmable Delay Inherent Delay Disable Output Delay Address Enable Setup Time Address Input Setup Time Enable Input Setup Time Output Address Change Disable Hold Time Absolute Input Period Suggested Recommended Absolute Input Pulse Width Suggested Recommended SYMBOL TDISO TAENS TAIS TENIS TOAX TDISH PERIN PERIN PERIN PWIN PWIN PWIN 12.0 UNITS TINC
Text Text
TABLE ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply Voltage Input Voltage Storage Temperature Lead Temperature SYMBOL TSTRG TLEAD -7.0 UNITS NOTES
TABLE ELECTRICAL CHARACTERISTICS
75C) PARAMETER High Level Output Voltage Level Output Voltage High Level Input Voltage Level Input Voltage High Level Input Current Level Input Current SYMBOL -1.020 -1.950 -1.480 -0.735 -1.600 -1.070 UNITS NOTES MAX,50 MIN,
#97047
12/17/97
DATA DELAY DEVICES, INC.
Prospect Ave. Clifton, 07013
PDU10256H
PACKAGE DIMENSIONS
.400 TYP.
2.450 TYP.
.020 .320 TYP. MAX. .150 ±.030 .100 .600 .700 .800 1.400 1.500 1.600 1.800 2.200 2.300 .018 TYP.
.012 TYP. .300 TYP.
.075
PDU10256H-xx (Commercial DIP) PDU10256H-xxM (Military DIP)
.020 TYP.
.040 TYP.
.010±.002
.710 .590 ±.005 MAX.
.882 ±.005 .007 ±.005
.090 1.100 2.080±.020
.100
.280 MAX.
.050 ±.010
PDU10256H-xxC5 (Commercial SMD) PDU10256H-xxMC5 (Military SMD)
#97047
12/17/97
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
PDU10256H
DELAY LINE AUTOMATED TESTING
TEST CONDITIONS
INPUT: Ambient Temperature: 25oC Supply Voltage (Vcc): -5.0V 0.1V Input Pulse: Standard 10KH levels Source Impedance: Max. Rise/Fall Time: Max. (measured between 80%) Pulse Width: PWIN Total Delay Period: PERIN Total Delay OUTPUT: Load: Cload: Threshold: (VOH VOL) (Rising Falling)
NOTE: above conditions test only restrict operation device.
PULSE GENERATOR TRIG DEVICE UNDER TEST (DUT) TRIG OSCILLOSCOPE
ADDRESS SELECT
Test Setup
PERIN PWIN TRISE INPUT SIGNAL
TFALL
TFALL
TRISE OUTPUT SIGNAL
Timing Diagram Testing
#97047
12/17/97
DATA DELAY DEVICES, INC.
Prospect Ave. Clifton, 07013

8-BIT, ECL-INTERFACED PROGRAMMABLE DELAY LINE (SERIES PDU10256H)

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