4.5.1 Overview CY7C964 general-purpose interface device that prov
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CY7C964 Operation
4.5.1 Overview
CY7C964 general-purpose interface device that provides seamless support entire family VMEbus interface controllers. part also suitable many other general-purpose interface applications. Figure block diagram device, showing array latches, multiplexers, counters. LA[7:0]
LD[7:0]
Comp
D[7:0] Figure 4-3. CY7C964 Block Diagram
A[7:0]
VCOMP
This section document dissects high-level block diagram into lower-level functional blocks. General operational timing information presented block-by-block basis. This information provided designers wish implement generically-controlled interfaces. tables show control signal logic sequence needed operate communicate with each functions. Timing parameters included, which reference switching characteristics listed later this document.
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CY7C964 Operation
CY7C964 operation controlled combination external control signals internal state logic. Three internal asynchronous state control operating mode device. These bits referred BLT_STATE, BLT_INIT, DUAL_PATH. BLT_STATE during block transfer operations. block transfer initiation cycle generates rising edge BLT_INIT signal. DUAL_PATH signal output transparent latch within device that latches state LADO. These internal state bits must proper state communicate with internal logic device. functional tables include references these signals when their state required operation. designer must perform appropriate cycle device clear these latches needed prior desired functional cycle. internal latch signals other control signals that called within tables specific operation considered don't cares. Table 4-5. Examples References Control Signals Within Functional Tables Note BLT_STATE=(/BLT* /MWB*)+(BLT_STATE (/BLT*+/MWB*+LAEN)) Note BLT_INIT=(/BLT_STATE /BLT* /MWB*)+(BLT_INIT /BLT* /MWB*) Note DUAL_PATH=(LADO BLT_INIT)+(DUAL_PATH /BLT_INIT) LA[7:0]
LD[7:0]
Comp
D[7:0]
A[7:0]
VCOMP
Figure 4-4. CY7C964 Block Diagram: Address Counters Address Multiplexers
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CY7C964 Operation
4.5.2
Master Block Transfer Local Address Counter (C1)
Master Block Transfer Local Address Counter supplies local address LA[7:0] during master block transfer operations. This 8-bit synchronous counter cascadable using LCIN*/LCOUT* daisy-chain. counter powers uninitialized state must initialized predictable operation. counter loads from LD[7:0] when both MWB* BLT* control signals active (Low). enable counter onto LA[7:0], internal asynchronous latch (BLT_STATE) must Local Address Multiplexer must select counter falling edge MWB* BLT* increments controls High, shown Table 4-7, selected. internal latch multiplexer must also proper state increment counter. further information Local Address Multiplexer, section 4.5.3.
Table 4-6. Master Block Transfer Local Address Counter Operation Logic Functional Description Load counter Operational Description LD[7:0] valid falling edge MWB* LD[7:0] valid falling edge BLT* Increment counter MWB* falling edge LA[7:0] valid Required Condition BLT*=0, LAEN=0 MWB*=0, LAEN=0 LAEN=1, FC1=1, BLT_STATE=1[1] Parameter Set-up Hold Set-up Hold Prop Prop Set-up Hold Set-up Hold Prop Prop Prop
BLT* falling edge LA[7:0] valid LAEN=1, FC1=1, BLT_STATE=1[1] LCIN* valid MWB* falling edge LAEN=1, FC1=1, BLT_STATE=1[1]
LCIN* valid BLT* falling edge LAEN=1, FC1=1, BLT_STATE=1[1] Counter carry ter- falling edge LCOUT* minal count valid BLT* falling edge LCOUT* valid LCIN* valid LCOUT* valid Minimum pulse widths BLT* MWB* LAEN=1, FC1=1, BLT_STATE=1[1] LAEN=1, FC1=1, BLT_STATE=1[1] LAEN=1, FC1=1, BLT_STATE=1[1] LAEN=1, FC1=1, BLT_STATE=1[1]
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CY7C964 Operation
4.5.3
Local Address Multiplexer (S5)
Local Address Multiplexer routes outputs counters signals LA[7:0]. local address counter carry chain LCIN*/LCOUT* also controlled this multiplexer. High, counter drives LA[7:0] LCIN*/LCOUT* visible/driven respectively. When Low, drives LA[7:0] attached LCIN*/LCOUT* daisy-chain.
Table 4-7. Local Address Multiplexer Operation Logic Functional Description Select counter Select counter Select carry chain Select carry chain Operational Description rising edge LA[7:0] valid falling edge LA[7:0] valid rising edge LCOUT* valid falling edge LCOUT* valid Required Condition Parameter Prop Prop Prop Prop
4.5.4
Slave Block Transfer Local Address Counter/Latch (C2)
Slave Block Transfer Local address counter provides functions: counter slave block transfer operations transparent address latch VMEbus slave operations. When latch control signal LADI held counter transparent mode: Logic levels present will flow through device inputs local address multiplexer controls multiplexer must select counter source LA[7:0]. Driving either LADI High exclusively latches data present A[7:0]. counter increments LCIN* Low, High, rising edge occurs LADI. contents counter/latch enabled onto local data when LADI High. Counter initialized power-up; predictable operation counter should loaded prior use.
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CY7C964 Operation
Table 4-8. Slave Block Transfer Local Address Counter/Latch Operation Logic Functional Description Load counter Operational Description A[7:0] valid rising edge Required Condition LADI=0 Parameter Set-up Hold A[7:0] valid LADI rising edge D64=0 Increment counter LADI rising edge LA[7:0] D64=1, FC1=0 Set-up Hold Prop Set-up Hold Counter carry terminal count Minimum pulse width LADI rising edge LCOUT* LADI D64=1, FC1=0 Prop LCIN* active LADI rising edge D64=1
4.5.5
Master Block Transfer VMEbus Address Counter (C3)
VMEbus Master Block Transfer Address stores increments VMEbus address during master block transfer operations. counter loads from LA[7:0] rising edge MWB* provided that internal asynchronous latch BLT_STATE set. contents counter enabled onto A[7:0] pins internal asynchronous latch bits BLT_STATE multiplexer appropriate state. Depending state DUAL_PATH, either rising falling edge LADO increments Counter uses VCIN*/VCOUT* counter daisy-chain. This counter uninitialized power-up should initialized prior predictable operation.
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CY7C964 Operation
Table 4-9. Master Block Transfer VMEbus Address Counter Operation Logic Functional Description Load counter Increment counter Operational Description LA[7:0] valid rising edge MWB* LADO falling edge A[7:0] Required Condition BLT_STATE=1 BLT_INIT=1
Parameter Set-up Hold Prop
BLT_STATE=1[1] DUAL_PATH=1 BLT_INIT=0 BLT_STATE=1[1] DUAL_PATH=0 BLT_INIT=0
LADO rising edge A[7:0]
Prop
VCIN* valid LADO rising/falling edge Counter carry LADO falling edge VCOUT* valid LADO rising edge VCOUT* valid Minimum pulse width LADO (High) LADO (Low) BLT_STATE=1[1] DUAL_PATH=1 BLT_INIT=0 BLT_STATE=1[1] DUAL_PATH=0 BLT_INIT=0
Set-up t134 Hold t135 Prop
Prop
4.5.6
VMEbus Address Latch (L8) Multiplexer (S3)
VMEbus Address Latch Multiplexer selects source VMEbus address signals A[7:0]. information supplied A[7:0] originates three sources: block transfer data pipeline latch VMEbus master block transfer counter VMEbus address latch Table 4-10 shows latch information into VMEbus address latch control selection source signals A[7:0]. Latch uninitialized power-up predictable operation should loaded prior use.
Table 4-10. VMEbus Address Latch Multiplexer Operation Logic Functional Description Select Select Select Load Load Operational Description falling edge A[7:0] valid ABEN* falling edge A[7:0] valid falling edge A[7:0] valid LA[7:0] valid LADO rising edge LA[7:0] valid LADO rising edge Required Condition BLT_STATE=1[1] BLT_STATE=1 BLT_STATE=0
Parameter Prop Prop Prop Set-up Hold
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CY7C964 Operation
4.5.7
VMEbus Address Comparator
VMEbus Address Comparator made three logic elements: address mask register, address compare register, high-performance, 8-bit, equality comparator. compare mask registers control compare logic. mask register contains 8-bit value that enables disables bits comparator. compare register contains 8-bit pattern. enabled bits compare register matched against value A[7:0]. match detected (all active bits equal), VCOMP* output driven Low. Neither compare register mask register preset power-up must initialized predictable operation. writing compare register clears mask register. This prevents inadvertent address compares during configuration process. Chapter further information VMEbus address comparator.
LA[7:0]
LD[7:0]
Comp
D[7:0]
A[7:0]
VCOMP
Figure 4-5. CY7C964 Block Diagram: VMEbus Address Comparator
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CY7C964 Operation
Table 4-11. VMEbus Address Comparator Operation Logic Functional Description Select compare register Operational Description LDS, MWB* valid STROBE falling edge LD[7:0] valid STROBE rising edge LDS, MWB* valid STROBE falling edge LD[7:0] valid STROBE rising edge A[7:0] valid VCOMP* valid A[7:0] valid VCOMP* invalid Minimum pulse width STROBE minimum pulse width LDS=0, MWB*=1 Required Condition LDS=1, MWB*=1 Parameter Set-up Hold Set-up Hold Set-up Hold Set-up Hold Prop Prop
Load compare register
Select mask register
Load mask register
Compare
4.5.8
VMEbus Block Transfer Data Pipeline Multiplexer
Latches form two-stage high-performance data pipeline block transfer operations. These latches load from local signals LD[7:0], drive VMEbus address signals A[7:0]. Latches load from local data signals LD[7:0] combination with multiplexer drive D[7:0]. first cycle block transfer, data LD[7:0] written latch During second local data fetch block transfer operation (D64=1), data from LD[7:0] written latch data within latch moves fetches must performed form 64-bit block transfer data word. During non-D64 modes operation (D64=0), data from LD[7:0] written latch This normal data path from LD[7:0] D[7:0] non-D64 operation. Because latches implemented transparent latches, loaded from LD[7:0] when transparent (LEDO=0). None latches initialized power-up. Therefore, predictable operation, these latches should written prior their use.
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CY7C964 Operation
LA[7:0]
LD[7:0]
Comp
D[7:0]
A[7:0]
VCOMP
Figure 4-6. CY7C964 Block Diagram: Block Transfer Data Pipeline Multiplexer Table 4-12. VMEbus Block Transfer Data Pipeline Multiplexer Operation Logic Functional Description Load register Load register Drive A[7:0] Load register Load register Multiplexer selects drive D[7:0] Multiplexer selects drive D[7:0] Minimum pulse width Operational Description LD[7:0] valid LEDO rising edge LD[7:0] valid DENO* falling edge rising edge A[7:0] valid LD[7:0] valid DENO* rising edge LD[7:0] valid LEDO rising edge rising edge D[7:0] valid falling edge D[7:0] valid DENO* LEDO LEDO=0 BLT_STATE=1 Required Condition Parameter Set-up Hold Set-up Hold Prop Set-up Hold Set-up t131 Hold t132 Prop Prop
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CY7C964 Operation
4.5.9
VMEbus Block Transfer Data Demultiplexer
VMEbus block transfer data demultiplexer moves data from D[7:0]/A[7:0] LD[7:0]. demultiplexer consists three latches-L5, L7-and output multiplexer, During block transfer operations (D64=1), data written latches simultaneously rising edge LEDI. Multiplexer then selects either latch depending state source LD[7:0]. most applications, should connected LA2, showing that contains even 32-bit words (addresses 1016.) contains 32-bit words (address 1416.). Latch also used non-D64 operating modes. None these latches initialized power-up predictable operation should initialized prior use.
LA[7:0]
LD[7:0]
Comp
D[7:0]
A[7:0]
VCOMP
Figure 4-7. CY7C964 Block Diagram: Block Transfer Data Demultiplexer
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CY7C964 Operation
Table 4-13. VMEbus Block Transfer Data Pipeline Demultiplexer Operation Logic Functional Description Load register Operational Description D[7:0] valid DENIN* falling edge D[7:0] valid DENIN1* falling edge D[7:0] valid LEDI rising edge Required Condition DENIN1*=0, LEDI=0 Parameter Set-up Hold DENIN*=0, LEDI=0 Set-up Hold LEDO=0 Set-up Hold Load register A[7:0] valid LEDI rising edge LEDO=0 Set-up Hold Select rising edge LD[7:0] valid rising edge LD[7:0] valid Select Select Minimum pulse width falling edge LD[7:0] valid falling edge LD[7:0] valid DENIN* DENIN1* LEDI D64=1 LDS=1 D64=1 Prop Prop Prop Prop
Load register
Load register
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