Monolithic Digital LB1872 Polygon Mirror Scanner Driver

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Monolithic Digital LB1872 Polygon Mirror Scanner Driver

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Ordering number EN5625A
Monolithic Digital
LB1872
Polygon Mirror Scanner Driver
Overview
LB1872 3-phase brushless motor driver developed driving polygon mirror motor used laser printers similar products.
braking (free running when stopped) Built-in error amplifiers Full complement protection circuits, including thermal protection, voltage protection, current limiter circuits, provided chip.
Functions Features
Integrates circuits (speed control driver circuits) required laser printer polygon mirror motor drive single chip. Uses current linear drive technique minimal motor noise. Only small capacitors required output oscillation prevention. speed control adopted high-precision rotation with excellent jitter characteristics. Phase lock detection output with chattering prevention function Four rotation rates using single crystal oscillator support 240, 300, 400, operation. Arbitrary rotation rates acquired when external clock used. Deceleration function implemented short-circuit
Package Dimensions
unit: 3147B-DIP28H
[LB1872]
SANYO: DIP28H
Allowable power dissipation,
With arbitrarily large heat sink
Independent
Ambient temperature,
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, Chome, Ueno, Taito-ku, TOKYO, 110-0005 JAPAN
13098HA(OT) 5625-1/11
LB1872
Specifications
Absolute Maximum Ratings 25°C
Parameter Maximum supply voltage Maximum output current Allowable power dissipation Operating temperature Storage temperature Symbol max1 max2 Topr Tstg 0.5s Independent Arbitrarily large heat sink Conditions Ratings +150 Unit
Allowable Operating Ranges 25°C
Parameter Supply voltage 5.0-V fixed-voltage output current voltage voltage output current output current Symbol IREG VFGS IFGS Conditions Ratings Unit
Electrical Characteristics 25°C,
Parameter Current drain [Output Saturation Voltage] VAGC Source V(sat)1-1 V(sat)1-2 V(sat)2-1 V(sat)2-2 (leak) VREG VREG1 VREG2 VREG3 IB(HA) VHIN VICM VIOH VIO(FG) IB(FG) VB(FG) VOH(FG) VOL(FG) VSHL VSLH VFGL VFGSIL -500 Design target value (junction temperature) Design target value (junction temperature) Design target value 4.65 Symbol stop mode Conditions Ratings Unit
Sink Output leakage current [5-V Fixed-Voltage Output] Output voltage Voltage regulation Load regulation Temperature coefficient [Hall Input Block] Input bias current Differential-mode input range Common-mode input range Input offset voltage [Low Voltage Protection Circuit] Operating voltage Hysteresis [Thermal Protection Circuit] Shutdown temperature Hysteresis Amplifier] Input offset voltage Input bias current bias level Output high-level voltage Output low-level voltage Schmitt Input Block] Input hysteresis (high low) Input hysteresis (low high) Hysteresis Input operating level
5.35
mV/°C
VAGC With sine wave input Differential input: Design target value
Design target value
1/2VREG
VREG VREG
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5625-2/11
LB1872
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Parameter Output saturation voltage Output leakage current [Error Amplifier] Input offset voltage Input bias current bias level Output high-level voltage Output low-level voltage [Phase Comparator Output] Output high-level voltage Output low-level voltage Output source current Output sink current [Lock Detection Output] Output saturation voltage Output leakage current [Drive Block] Output idling voltage Forward gain Current limiter Brake command voltage [Reference Signal Block] Crystal oscillator frequency Low-level voltage High-level voltage Pin] External input frequency High-level input voltage Low-level input voltage Input open voltage Hysteresis High-level input current Low-level input current Pin] High-level input voltage Middle-level input voltage Low-level input voltage Input open voltage High-level input current Low-level input current [S/S Pin] High-level input voltage Low-level input voltage Input open voltage Hysteresis High-level input current Low-level input current [CLD Pin] Charge current Discharge current ICLD1 ICLD2 VCLD (Phase locked) VREG/2 (Phase unlocked) VIH(SS) VIL(SS) VIO(SS) VIS(SS) IIH(SS) IIL(SS) VS/S VREG VS/S VREG -350 -275 VREG VREG VIH(N2) VIM(N2) VIL(N2) VIO(N2) IIH(N2) IIL(N2) VREG -270 -200 VREG fI(N1) VIH(N1) VIL(N1) VIO(NI) VIS(N1) IIH(N1) IIL(N1) VREG external clock mode VREG -350 -275 10000 VREG VREG fOSC VOSCL IOSCH crystal oscillator mode IOSC -0.5 VOSC VOSCL GDF1 GDF2 VBRK When phase locked When unlocked 0.45 0.55 VLD(sat) ILDLEAK VPDH VPDL IPD+ IPD- -100 VREG/2 VREG/2 VREG VREG -0.6 VIO(ER) IB(ER) VB(ER) VOH(ER) VOL(ER) -500 IERI Design target value 1/2VREG Symbol VFGS(sat) IL(FGS) IFGS Conditions Ratings Unit
VREG VREG
5625-3/11
LB1872 Assignment Clock Divisor Switching
open Divisor 2048 512) 4096 512) 5120 512) 3072 512) EXT.
Three-Phase Logic Truth Table
OUT1 OUT2 OUT3
5625-4/11
LB1872 Equivalent Circuit Block Diagram
5625-5/11
LB1872 Functions
Symbol function Equivalent circuit
IN3-
Hall amplifier inputs input high state, reverse input state. Connect capacitor between inputs there noise Hall sensor signals. amplitude over under desirable Hall sensor signals. Kickback occur output input signal amplitude greater than p-p.
IN1- IN1+ IN2-
OUT3 OUT2 OUT1
Motor drive outputs Connect capacitors between motor outputs between motor outputs ground) oscillation occurs outputs. (Use capacitors range 0.47 µF.)
Output current detection Connect resistor (Rf) between this ground. output current limited IOUT VREG/Rf.
Power supply
Stabilized power supply output (5-V output) VREG Connect capacitor (about between this ground stabilization.
Crystal oscillator connections These pins used drive reference clock oscillator element. external clock (with frequency MHz) used, connect resistor (about series input clock signal through that resistor. Leave open this case.
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5625-6/11
LB1872
Continued from preceding page.
Symbol function Equivalent circuit
Control amplifier frequency correction Current limiter system closed loop oscillation prevented inserting capacitor (about 0.022 0.47 between this ground. capacitance this capacitor large, output current response characteristics degraded.
Error amplifier output When high, output current increased. Control amplifier
Error amplifier input
Phase comparator output (PLL output) phase error output changes duty pulse waveform. output current increased duty becomes smaller.
output mask time setting Chattering masked inserting capacitor (about 0.47 between this ground. startup time increased only masking used servo constants re-optimized.
Continued next page.
5625-7/11
LB1872
Continued from preceding page.
Symbol function Equivalent circuit
Phase lock detector output This goes state when phase locked. This open collector output.
Divisor switch Low: Middle: High: VREG This goes middle level when open.
Divisor switch external clock input Low: High: VREG This functions external clock input when middle level. This goes high level when open.
Start/stop control Low: Start High: Stop This goes high level when open.
pulse-converted output This outputs post-hysteresis comparator signal. This open collector output.
amplifier output FGOUT noise signal problem, e.g. discharge noise detected, insert capacitor (about 0.01 between this ground.
schmitt comparator
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5625-8/11
LB1872
Continued from preceding page.
Symbol function Equivalent circuit
FGIN-
amplifier input
amplifier frequency characteristics correction Insert capacitor (about between this ground.
Ground
LB1872 Functional Description Speed control circuit Since this adopts speed control circuit, provide high-precision, jitter-free, stable motor operation. This circuit compares phases (external clock) rising edge Schmitt output rising edge uses error output from that comparison control. internal clock system used, servo frequency determined following formula. Therefore, motor speed setting number pulses crystal oscillator frequency. fFG(servo) fOSC/N fOSC: Crystal oscillator frequency Clock divisor (See separately provided table.) external clock (input pin) used, controls motor speed holding servo frequency identical external clock frequency. Output drive circuit suppress motor noise much possible, this adopts three-phase full wave current linear drive technique. Also, adopts midpoint control technique prevent destruction output transistors. This uses short-circuit braking (lower side output) motor deceleration during speed switching lock pull stop mode, output turned off. motor with coil resistance (interphase) lower used, diodes (rectifying) inserted between outputs ground (for outputs) current limitation also applied during braking prevent excessive braking currents. Although this disadvantageous from standpoint, since states with large back states with high switching frequency amount time during which loads applied transistors will shorter, problems will particular severe. Current limiter circuit current limiter circuit peak current limiter whose limit current determined VRF/Rf (where (typical) current detection resistor).
5625-9/11
LB1872 Reference clock following three techniques used input reference clock used speed control. Crystal oscillator generated clock following circuit, consisting crystal element, capacitors, resistors, crystal oscillator circuit. Used oscillator stabilization. Used oscillator element coupling. Used overtone prevention. Improves oscillator margin.
Sample External Component Values
Oscillator frequency (MHz) (µF) (pF) (pF)
This circuit these component values only provided reference purposes. Consult with manufacturer crystal element concerning influence such factors characteristics crystal element itself stray capacitances printed circuit board wiring pattern assure that problems occur. (Notes printed circuit board wiring) Since crystal oscillator circuits high-frequency circuits, they easily influenced stray capacitances printed circuit board wiring. Therefore, lines external components must kept short possible lines must made narrow possible. this external circuit, connection between oscillator element (and particularly subject influence stray capacitance, requires special care. External clock (crystal oscillator equivalent: MHz) signal equivalent crystal oscillator signal input from external signal generator, input that signal through series resistor about pin. Leave open. External clock frequency equivalent: kHz) signal equivalent frequency input from external signal generator, middle level open) input that signal pin. this case, motor will remain stopped state (shortcircuit braking operation) even start input applied when clock input. However, since heating large output drive currents that flow short braking state (since lower side transistors phases driven) care required braking state must held extended periods. Hall input signals Even amplitude Hall sensor input signals changed motor, influence output will suppressed circuit. However, there discrepancies between amplitudes three phases, output phase switching timing shifted. output current will protection circuit start signal input when there signals applied Hall inputs. maximum operating frequency Hall inputs affected saturation state outputs. While there problems frequencies under (the frequency single Hall phase), higher operating frequency required, advantageous outputs remain unsaturated. outputs remain unsaturated state, this used frequencies about kHz. Since motors with higher speeds have higher operating frequencies, recommend using motors with four motor magnet poles. output output goes when phase locked. Phase lock determined speed error phase error only. Therefore, speed error when output during, example, lock pull-in, will change with acceleration signal. (The speed error will smaller lower accelerations.) necessary
5625-10/11
LB1872 stipulate speed error when output this must determined based result speed measurement motor state. This includes built-in circuit that masks output chattering (rapid switching between off) during phase lock pull-in. mask time determined shown below capacitance capacitor inserted between ground. 0.35 Mask time External capacitance (µF) chattering masked, output delayed mask time. Therefore care required, since speed error when changed mask time. Leave open there need masking. Power supply stabilization Since this provides large output currents, easily cause fluctuations power supply line voltage. Therefore, capacitors with adequate capacitances stabilization must inserted between ground pins. diodes inserted power supply lines prevent device destruction reverse power supply connection, power supply line voltage becomes especially liable fluctuations. this case, even larger capacitors required. External protection circuits application will include external motor constraint protection other external protection circuits, open collector transistor output shut drive current.
products described contained herein intended surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment like, failure which directly indirectly cause injury, death property loss. Anyone purchasing products described contained herein above-mentioned shall: Accept full responsibility indemnify defend SANYO ELECTRIC CO., LTD., affiliates, subsidiaries distributors their officers employees, jointly severally, against claims litigation damages, cost expenses associated with such use: impose responsibility fault negligence which cited such claim litigation SANYO ELECTRIC CO., LTD., affiliates, subsidiaries distributors their officers employees jointly severally. Information (including circuit diagrams circuit parameters) herein example only; guaranteed volume production. SANYO believes information herein accurate reliable, guarantees made implied regarding infringements intellectual property rights other rights third parties. This catalog provides information January, 1998. Specifications information herein subject change without notice. 5625-11/11

Monolithic Digital LB1872 Polygon Mirror Scanner Driver

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