SKEW CMOS CLOCK DRIVER WITH INTEGRATED LOOP FILTER operation nois
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QS5931 SKEW CMOS CLOCK DRIVER WITH INTEGRATED LOOP FILTER
SKEW CMOS CLOCK DRIVER WITH INTEGRATED LOOP FILTER
operation noise CMOS level outputs outputs, output <500ps output skew, Q0-Q4 Outputs 3-state reset while OE/RST disable feature frequency testing Internal loop filter network Internal VCO/2 option Balanced drive outputs ±36mA >2000V 80MHz maximum frequency Available QSOP package
QS5931
DESCRIPTION:
QS5931 Clock Driver uses internal phase locked loop (PLL) lock skew outputs reference clock input. outputs available: Q0-Q4, Q/2. Careful layout design ensure 500ps skew between Q0-Q4, outputs. QS5931 includes internal filter which provides excellent jitter characteristics eliminates need external components. Various combinations feedback divide-by-2 path allow applications customized linear operation over wide range input SYNC frequencies. also disabled PLL_EN signal allow frequency testing. QS5931 designed cost sensitive high-performance computing systems, workstations, multi-board computers, networking hardware, mainframe systems. Several used parallel scattered throughout system guaranteed skew, system-wide clock distribution networks. QSOP package, QS5931 clock driver represents best value small form factor, high-performance clock management products. more information clock driver products, Application Note AN-227.
FUNCTIONAL BLOCK DIAGRAM
FEEDBACK
PLL_EN
FREQ _SEL
SYNC E/RST
DETECTO FILTER
logo registered trademark Integrated Device Technology, Inc.
2002 Integrated Device Technology, Inc.
JANUARY 2002
DSC-5817/2
QS5931 SKEW CMOS CLOCK DRIVER WITH INTEGRATED LOOP FILTER
CONFIGURATION
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Description Input Voltage Maximum Power Dissipation 85°C) TSTG Storage Temperature Range -0.5 -0.5 +5.5 +150 Unit AVDD/VDD Supply Voltage Ground
OE/RST FEEDBACK AGND SYNC FREQ_SEL
SO20-8
PLL_EN
NOTE: Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. These stress ratings only, functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolutemaximum-rated conditions extended periods affect device reliability.
CAPACITANCE +25°C, 1MHz,
Pins COUT Typ. Max. Unit
QSOP VIEW
DESCRIPTION
Name SYNC FREQ_SEL FEEDBACK OE/RST PLL_EN AVDD AGND Description Reference clock input frequency select. choosing optimal operating frequency depending input frequency. HIGH higher frequencies, lower frequencies. feedback input which connected either output. External feedback provides flexibility different output frequency relationships. Frequency Selection Table more information. Clock outputs Clock output. Matched phase, frequency half frequency. Output enable/asynchronous reset. Resets output registers. When outputs held tri-stated condition. When outputs enabled. enable. Enables disables PLL. Allows SYNC input single-stepped system debug. Power supply output buffers Power supply phase lock loop other internal circuitries Ground supply output buffers Ground supply phase lock loop other internal circuitries
OUTPUT FREQUENCY SPECIFICATIONS
Industrial: -40°C +85°C, AVDD/VDD 5.0V
Symbol FMAX_Q FMAX_Q/2 FMIN_Q FMIN_Q/2 Description Frequency, Frequency, Frequency, Frequency, Units
QS5931 SKEW CMOS CLOCK DRIVER WITH INTEGRATED LOOP FILTER
FREQUENCY SELECTION TABLE
SYNC (MHz) Output Used FREQ_SEL HIGH HIGH Feedback Min. FMIN_Q/2 FMIN_Q FMIN_Q/2 FMIN_Q (allowable range) FMAX _Q/2 FMAX FMAX _Q/2 FMAX Output Frequency Relationships SYNC SYNC SYNC SYNC SYNC SYNC SYNC SYNC
NOTE: Operation specified SYNC frequency range guarantees that will operate optimal range 20MHz FMAX_Q Operation with Sync inputs outside specified frequency ranges result out-of-lock outputs. FREQ_SEL only affects frequency does affect output frequencies.
ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Industrial: -40°C +85°C, AVDD/VDD 5.0V
Symbol Parameter Input HIGH Voltage Input Voltage Output HIGH Voltage Output Voltage Input Hysteresis Output Leakage Current Input Leakage Current Conditions Guaranteed Logic HIGH Level Guaranteed Logic Level -24mA -100µA Min., 100µA VOUT GND, Max., Outputs Disabled AVDD Max., AVDD Min. Typ. Max. 0.45 Unit
Min., 24mA
POWER SUPPLY CHARACTERISTICS
Symbol IDDQ IDDD Parameter Quiescent Power Supply Current Power Supply Current Input HIGH Dynamic Power Supply Current Output Test Conditions Max., OE/RST LOW, SYNC LOW, outputs unloaded Max., Max., µA/MHz Typ. Max. Unit
INPUT TIMING REQUIREMENTS
Symbol tPWC Input Clock Frequency, SYNC Duty Cycle, SYNC
Description Maximum input rise fall times, 0.8V Input clock pulse, HIGH
Min.
Max. FMAX
Unit
NOTES: Output Frequency Frequency Selection tables more detail allowable SYNC input frequencies different speed grades with different FEEDBACK FREQ_SEL combinations. Where pulse witdh implied less than tWPC limit, tWPC limit applies
QS5931 SKEW CMOS CLOCK DRIVER WITH INTEGRATED LOOP FILTER
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Symbol tSKR tSKF tLOCK tPZH tPZL tPHZ tPLZ Output Rise/Fall Times, 0.2VDD 0.8VDD Output Disable Time, OE/RST HIGH Parameter Output Skew Between Rising Edges, Q0-Q4 Output Skew Between Falling Edges, Q0-Q4 Pulse Width, Q0-Q4, outputs, 80MHz Cycle-to-Cycle Jitter
Min. TCY/2 0.15
Max. TCY/2 0.15
Unit
SYNC Input Feedback Delay SYNC Phase Lock Output Enable Time, OE/RST HIGH
NOTES: Test Loads Waveforms test load termination. Skew specifications apply under identical environments (loading, temperature, VDD, device speed grade). Measured open loop mode PLL_EN Jitter characterized with output 20MHz. Frequency Selection Table information proper FREQ_SEL level specified input frequencies. measured device inputs 1.5V, output 80MHz.
QS5931 SKEW CMOS CLOCK DRIVER WITH INTEGRATED LOOP FILTER
TEST LOADS WAVEFORMS
7.0V TPUT
30pF
Test Circuit
1.0ns 1.0ns 0.8V 0.5V 0.2V
Test Circuit
3.0V 2.0V 1.5V 0.8V
CMOS Input Test Waveform
ABLE DISABLE
CMOS Output Waveform
1.5V NTROL INPU ALLY SWITC 0.5V 0.3V SWITC ALLY 0.5V 0.3V 3.5V
Enable Disable Times
TEST CIRCUIT used output enable/disable parameters. TEST CIRCUIT used other timing parameters.
QS5931 SKEW CMOS CLOCK DRIVER WITH INTEGRATED LOOP FILTER
TIMING DIAGRAM
SYNC
FEEDBACK
NOTES: Timing Diagram applies output connected FEEDBACK GND. VDD, negative edge FEEDBACK aligns with negative edge SYNC input, negative edges multiplied divided outputs align with negative edge SYNC. parameters measured 0.5VDD.
QS5931 SKEW CMOS CLOCK DRIVER WITH INTEGRATED LOOP FILTER
OPERATION
Phase Locked Loop (PLL) circuit included QS5931 provides replication incoming SYNC clock signals. manipulation that signal, such frequency multiplying, performed digital logic following (see block diagram). advantage circuit provide effective zero propagation delay between output input signals. fact, adding delay circuits feedback path, `propagation delay' even negative! simplified schematic QS5931 circuit shown below:
SIMPLIFIED DIAGRAM QS5931 FEEDBACK
INPU PHASE DETECTO
phase difference between output input frequencies feeds which drives outputs. Whichever output back, will stabilize same frequency input. Hence, this true negative feedback closed loop system. most applications, output will optimally have zero phase shift with respect input. fact, internal loop filter QS5931 typically provides within 150ps phase shift between input output.
user wishes vary phase difference (typically compensate backplane delays), this most easily accomplished adding delay circuits feedback path. respective output used feedback will advanced amount delay feedback path. other outputs will retain their proper relationships that output.
QS5931 SKEW CMOS CLOCK DRIVER WITH INTEGRATED LOOP FILTER
ORDERING INFORMATION
XXXX Device Type Speed Package
Quarter Size Outline Package
MHz. max. frequency MHz. max. frequency MHz. max. frequency
5931
Skew Clock Driver with Integrated Loop Filter
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