Differential Clock Generator Eight copies Differential Clock Outp
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PI6C210
Differential Clock Generator
Eight copies Differential Clock Output copy CLK33 copy 14.31818 Reference Clock copy Differential Clock External Resistor Current Reference Selection Logic Differential Swing Control, Test Mode, HI-Z, Power-Down, Spread Spectrum Available Packaging: 48-pin TSSOP package) 48-pin SSOP package)
Description
Pericoms PI6C210 produced using Companys advanced submicron technology. clocks provided HCLK HCLK_bar [0:7] outputs. These eight differential clock pairs MHz. swing amplitude configured MultSel0 MultSel1 pins.
Configuration
CLK33 MHz/SELA MHz_bar/SELB HCLK0 HCLK0_bar HCLK1 HCLK1_bar HCLK2 HCLK2_bar HCLK3 HCLK3_bar REFCLK SPREAD# XTALI XTALO SEL100/133 VDDA GNDA PWRDN# HCLK4 HCLK4_bar HCLK5 HCLK5_bar HCLK6 HCLK6_bar HCLK7 HCLK7_bar MULTSEL0 MULTSEL1 GNDA IREF VDDA
Block Diagram
XTAL_IN XTAL_OUT
REFCLK
48-pin
Spread# MultSel0 MultSel1 PWRDWN# Sel100/133 SelA SelB PLL2 Control Register PLL1
HCLK [0:7] HCLK_bar [0:7] CLK33 MHz_bar
PS8599
01/29/02
PI6C210 Differential Clock Generator
Description
Name HCLK HCLK _bar MHz, MHz_bar REFCLK XTALI XTALO SPREAD# PWRDN# SELA, SELB MultSel0, MultSel1 IREF Type cription Host Clock utputs. these eight Differential clock pairs MHz. swing amplitude configured Multsel0, Multsel1 pins. Reference Clock. Host clock divided Differential Clocks. 14.318 Reference Clock utput. 3.3V copies 14.318 reference clock. Crystal connection External Reference Frequency Input. Connect either 14.318 crystal external reference signal. Crystal Connection. output connection external 14.318 crystal. using external reference, this must left unconnected. Spread Spectrum Enable. 3.3V LVTTL compatible input that enables spread spectrum mode when held Power Down Input. 3.3V LVTTL compatible asynchronous input that requests device enter power- down mode when held low. Logic Select Pins. Select mode operation Select Pins swing amplitude HCLK HCLK _bar Power Supply Current Reference. This establishes reference current host clock pairs.
Group Skew Jitter Specification
Output Group Host Clock CLK33 REFCLK Pin-to-pin Pair-to-pair 100ps Cycle -cycle Jitte 150ps 500ps 1000ps 350ps Duty Cycle 45/55 45/55 45/55 45/55 Type Differential Single ended 3.3V Single ended 3.3V Single ended 3.3V Crossing 1.5V 1.5V 1.5V
Group Offset Specification
Group Host Host Offs requirement requirement Comme
PS8599
01/29/02
PI6C210 Differential Clock Generator
Select Signal Configurations
SEL100/133 SELA SELB HCLK TCLK CLK33 Disable TCLK Hz_bar Disable Disable Disable TCLK 14.318 14.318 14.318 14.318 14.318 14.318 TCLK Note Normal peration Test Mode (recommended) Test Mode (optional) utputs ptional ptional ptional RESERVED
Absolute Maximum Power Supply
Symbol VDD3 VDDQ3 Parame 3.3V Core Supply Voltage 3.3V Supply Voltage Storage Temperature Units Note
Note: Maximum exceed VDD3 +0.7V
Absolute Maximum
Symbol VIH3 VIL3 prot. Parame 3.3V Input High Voltage 3.3V Input Voltage Input Protection 2000 Units Note
Notes: Maximum exceed maximum 0.7V above Human body model
PS8599
01/29/02
PI6C210 Differential Clock Generator
Operating Requirements
Symbol VDD3 VIH3 VIL3 VOH3 VOL3 VPOH VPOL CXTAL Parame 3.3V Supply Voltage 3.3V Input High Voltage 3.3V Input Voltage Input Leakage Current 3.3V Output High Voltage 3.3V Output Voltage Output High Voltage Output Voltage Input Capacitance Xtal Capacitance Ambient Temperature Airflow 13.5 VDDQ3 0.55 22.5 Condition 3.3V VDD3 3.135 3.465 +0.3 Units Note
Notes: Signal edge required monotonic when transitioning through this region. This recommendation, absolute requirement. Input Leakage Current does include inputs with Pull-up Pull-down resistors. Inputs with resistors should state current requirements. power sequencing implied allowed required system. Conforms signaling specification. seen crystal. Device intended used with 17-20pF crystal. inputs referenced 3.3V power supply.
Maximum Current Draw During PWRDWN#
Parame Current from 3.3V supply Units Note Configured w/475 current reference resistor
Maximum Current Draw
Parame Current from 3.3V supply Units Note Max. power supply (3.465V), active, current reference resistor, Host
PS8599
01/29/02
PI6C210 Differential Clock Generator
Buffer Types
Buffe Name MHz, Host/Host_bar Range 3.135- 3.465 3.135- 3.465 Impe dance (Ohms Buffe Type Type Type Type
MHz, Operating Requirements
Symbol IOHMIN IOHMAX IOLMIN IOLMAX Parame Pull- Current Pull- Current Pull- down Current Pull- down Current 3.3V Type utput Rise Edge Rate 3.3V Type utput Rise Fall Rate Condition VOUT 1.0V VOUT 3.135V VOUT 1.95V VOUT 0.4V 3.3V 0.4V 2.4V 3.3V 2.4V 0.4V Units V/nS V/nS
CLK33 Operating Requirements
Symbol IOHMIN IOHMAX IOLMIN IOLMAX Parame Pull- Current Pull- Current Pull- down Current Pull- down Current 3.3V Type Output Rise Edge Rate 3.3V Type Output Rise Fall Rate Condition VOUT 1.0V VOUT 3.135V VOUT 1.95V VOUT 0.4V 3.3V 0.4V 2.4V 3.3V 2.4V 0.4V Units V/ns V/ns
PS8599
01/29/02
PI6C210 Differential Clock Generator
Current-Mode Output Buffer Characteristics HCLK, HCLK_bar [0:7]
VDD3 (3.3V -5%) Slope 1/RO
IOUT
IOUT VOUT 1.2V max.
1.2V
VOUT
Host Clock (HCSL) Buffer Characteristics
inimum VOUT 3000 (recommended) unspecified aximum unspecified 1.2V
Note: IOUT selectable depending implementation. parameters above, however, apply configurations. VOUT voltage device.
Current Accuracy
Conditions IOUT IOUT nominal (3.30V) 3.30 Load Nominal test load given configuration Nominal test load given configuration INOMINAL INOMINAL INOMINAL +12% INOMINAL
Note: INOMINAL refers expected current based configuration device.
PS8599
01/29/02
PI6C210 Differential Clock Generator
Timing Requirements
Symbol TPeriod AbsMinPeriod (VOH) Vcrossover TRISE TFALL Rise/Fall Matching vershoot Undershoot Duty Cycle TPeriod THIGH TRISE TFALL tPZL, tPZH tPLZ, tPZH tstable period high time time rise time fall time utput enable delay (all outputs) utput disable delay (all outputs) clock stabilization from power- 0.2V 30.0 12.0 12.0 10.0 10.0 Host/CPU Rise Time Host/CPU Fall Time Rise Time Fall Time Matching Parame Host period average Absolute minimum Host Period utput Current (Voltage given load) 7.35 12.9 (0.65) 7.65 14.9 (0.74) 0.05 +0.2V 0.2V 30.0 12.0 12.0 10.0 10.0 10.0 9.85 12.9 (0.65) 10.2 14.9 (0.74) 0.05 +0.2V Units Note 11,14 11,14 13,17 11,14 11,15 11,15 11,16 11,16 11,14 2,3,9 5,10 6,10
Notes: Output drivers must have monotonic rise/fall times through specified VOL/VOH levels. Period, Jitter, Offset, Skew measured rising edge @1.25V 2.5V clocks 1.5V 3.3V clocks. clock Host clock divided four Host MHz. clock Host clock divided three Host MHz. clock Host clock divided Host MHz. THIGH measured 2.0V 2.5V outputs, 2.4V 3.3V outputs. TLOW measured 0.4V outputs. time specified measured from when VDDQ achieves nominal operating level (typical condition VDDQ=3.3V) till frequency output stable operating within specification. TRISE TFALL measured transition through threshold region VOL=0.4V, VOH=2.4V (1mA) JEDEC Specification average period over period time must greater than minimum specified period. Calculated minimum edge-rate (1V/nS) guarantee 45/55% duty-cycle. Pulsewidth required wider faster edge-rate ensure dutycycle specification met. Test load RS=33.2 Ohms, RP=49.9. Must guaranteed realistic system environment. Configured IOH=6* IREF. Measured crossing points. Measured 80%. Determined fraction (TrpTrn) (Trp+Trn) where rising edge intersecting falling edge. These Min. Max. voltages currents assume power supply 3.30V. system considerations, voltages will need degraded account variation 3.3V supply.
PS8599 01/29/02
PI6C210 Differential Clock Generator
Lumped Capacitive Test Loads Single ended Outputs
Clock 3V66 Clock Load Load Units Note device load, possible loads device load device load
Notes: Maximum rise/fall times guaranteed maximum specified load each type output buffer. Minimum rise/fall times guaranteed minimum specified load each type output buffer. Rise/fall times specified with pure capacitive load shown. testing done with additional resistor parallel properly correlated with capacitie load.
Test nodes
Lumped Test Load Configurations Differential Host Clock Outputs
Minimum Maximum Lumped Resistive Test Loads
Clock Host Clocks Load Load Units Note
PS8599
01/29/02
PI6C210 Differential Clock Generator
Resistive Lumped Test Loads Differential Host Clock
Clock Host Clocks configurations Host Clocks configurations Host Clocks Double terminated Configuration 33.2 33.2 61.9 49.9 24.9 Units Ohms Ohms Ohms Note
Notes: Expected test load configuration unless otherwise noted. This environment test load. This assumes device configured environment. Test load environment. This assumes device configured environment. Suppliers must correlate parameters measured environment environment with appropriate configurations device each load. Test load dual terminated both source load) environment. configurations device intended create output current greater than 14mA these test loads appropriate. such configurations, value should used.
Volt Measure Points VDD3
Host Host_bar
2.4V 2.0V 1.5V 0.8V
Tperiod
0.4V
Host Waveforms
Component System Measure Points Single Ended Clocks
PWRDWN# Mode
PWRDWN# Asserted t/Hos t_bar Host Iref Host_bar undriven CLK33 14.318, applicable)
Notes: When PWRDWN# asserted, voltage must held across differential outputs. There specific timing requirements entering exiting PWRDWN# mode.
PS8599
01/29/02
PI6C210 Differential Clock Generator
Host Swing Select Functions
ultSe ultSe Board targe Trace ohms ohms ohms ohms ohms ohms ohms ohms equiv) equiv) equiv) equiv) equiv) equiv) equiv) equiv) VDD/3(3*Rr) 2.32mA Iref 2.32mA Iref 2.32mA 2.32mA Iref 2.32mA Iref 2.32mA Iref 2.32mA Iref 2.32mA Iref Iref Iref Iref Iref Iref Iref Iref Output Curre 5*Ire Iref Iref 6*Ire Iref Iref Iref Iref Iref Iref Iref Iref Iref Iref Iref Iref 2.32mA 0.71V 0.59V 0.85V 0.71V 0.56V 0.47V 0.99V 0.82V 0.75V 0.62V 0.90V 0.75V 0.60V 0.5V 1.05V 0.84V
Notes: entries boldface primary system configurations interest. outputs should optimized these configurations.
PS8599
01/29/02
PI6C210 Differential Clock Generator
48-pin TSSOP Packaging Mechanical
.236 .244
.488 12.4 .496 12.6 .047 1.20 SEATING PLANE
.004 0.09 .008 0.20 0.45 .018 0.75 .030 .319
X.XX X.XX
DENOTES DIMENSIONS MILLIMETERS
.0197 0.50
.007 .010 0.17 0.27
.002 .006 0.05 0.15
48-pin SSOP Packaging Mechanical
.291 .299 7.39 7.59
.395 .420 10.03 10.67
Gauge Plane .010 0.25 .620 .630 15.75 16.00 0.51 1.01
.008 0.20 Nom.
.015 0.381 .025 0.635
.110 2.79 .025 0.635 X.XX DENOTES DIMENSIONS X.XX MILLIMETERS .008 0.20 .0135 0.34
0-8°
.008 0.20 .016 0.40
Ordering Information
PI6C210A PI6C210V cription TSSO
Pericom Semiconductor Corporation 2380 Bering Drive Jose, 95131 1-800-435-2336 (408) 435-1100 http://www.pericom.com
PS8599 01/29/02
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