MC74ACT323 8-bit universal shift/storage register with3-state outputs.
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MC74ACT323 8-Input Universal Shift/Storage Register with Synchronous Reset Common Pins1
MC74ACT323 8-bit universal shift/storage register with3-state outputs. function similar MC74ACT299 with exception Synchronous Reset. Parallel load inputs flip-flop outputs multiplexed minimize count. Separate serial inputs outputs provided allow easy cascading. Four operation modes possible: hold (store), shift left, shift right parallel load.
MC74ACT323N AWLYYWW
Common Parallel Reduced Count Additional Serial Inputs Outputs Expansion Four Operating Modes: Shift Left, Shift Right, Load Store 3-State Outputs Bus-Oriented Applications Outputs Source/Sink Compatible Inputs
PDIP-20 SUFFIX CASE
SO-20 SUFFIX CASE 751D
ACT323 AWLYYWW
TSSOP-20 SUFFIX CASE 948E
ALYW
Assembly Location Wafer Year Work Week
ORDERING INFORMATION
Device MC74ACT323N MC74ACT323DW MC74ACT323DWR2 MC74ACT323DT Package PDIP-20 SOIC-20 SOIC-20 TSSOP-20 Shipping Units/Rail Units/Rail 1000 Tape Reel Units/Rail
MC74ACT323DTR2 TSSOP-20 2500 Tape Reel
Semiconductor Components Industries, LLC, 2001
June, 2001 Rev.
Publication Order Number: MC74ACT323/D
MC74ACT323
I/O7 I/O5 I/O3 I/O1
I/O7
I/O6
I/O4
I/O2
I/O0
I/O6
Figure Pinout: 20-Lead Packages Conductors (Top View)
ASSIGNMENT
OE1, I/O0-I/O7 FUNCTION Clock Pulse Input Serial Data Input Right Shift Serial Data Input Left Shift Mode Select Inputs Synchronous Master Reset 3-State Output Enable Inputs Multipled Parallel Data Inputs 3-State Parallel Data Outputs Serial Outputs
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7
Figure Logic Symbol TRUTH TABLE
Inputs Response Synchronous Reset; Parallel Load; I/On Shift Right; etc. Shift Left; etc. Hold Immaterial LOW-to-HIGH Clock Transition
I/O0
Please note that this diagram provided only understanding logic operations should used estimate propagation delays.
Figure LOGIC DIAGRAM
HIGH Voltage Level Voltage Level
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MC74ACT323
FUNCTIONAL DESCRIPTION MC74ACT323 contains eight edge- triggered D-type flip-flops interstage logic necessary perform synchronous reset, shift left, shift right, parallel load hold operations. type operation determined shown Mode Select Table. flip-flop outputs brought through state buffers separate pins that also serve data inputs parallel load mode. also brought other pins expansion serial shifting longer words. signal overrides Select inputs allows flip-flops reset next rising edge other state changes also initiated LOW-to-HIGH transition. Inputs change when clock either state provided only that recommended setup hold times, relative rising edge observed. HIGH signal either disables 3-state buffers puts pins high impedance state. this condition shift, hold, load reset operations still occur. 3-state buffers also disabled HIGH signals both preparation parallel load operation.
MAXIMUM RATINGS (Note
Symbol IGND TSTG Supply Voltage Input Voltage Output Voltage Input Diode Current Output Diode Current Output Sink/Source Current Supply Current Output Ground Current Output Storage Temperature Range Lead temperature, from Case Seconds Junction temperature under Bias Thermal resistance PDIP SOIC TSSOP PDIP SOIC TSSOP (Note Parameter Value *0.5 )7.0 *0.5 )0.5 *0.5 )0.5 )150 )150 Level Oxygen Index: Human Body Model (Note Machine Model (Note Charged Device Model (Note Above Below 85_C (Note 0.125 2000 >1000 $100 Unit _C/W
Power Dissipation Still 85_C
VESD
Moisture Sensitivity Flammability Rating Withstand Voltage
ILatch-Up
Latch-Up Performance
Absolute maximum continuous ratings those values beyond which damage device occur. Extended exposure these conditions conditions beyond those indicated adversely affect device reliability. Functional operation under absolute maximum-rated conditions implied. absolute maximum rating must observed. Tested EIA/JESD22-A114-A. Tested EIA/JESD22-A115-A. Tested JESD22-C101-A. Tested EIA/JESD78.
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MC74ACT323
RECOMMENDED OPERATING CONDITIONS
Symbol Vin, Vout Parameter Input Voltage (Referenced GND) Input Voltage, Output Voltage (Referenced GND) Operating Temperature, Package Types Input Rise Fall Time (Note Junction Temperature (PDIP) Output Current High Unit ns/V
Output Current Unused Inputs left open. inputs must tied high voltage level logic voltage level. from refer individual Data Sheets devices that differ from typical input rise fall times.
CHARACTERISTICS
+255C Symbol Parameter Minimum High Level Input Voltage Maximum Level Output Voltage DICCT Maximum Input Leakage Current Additional Maximum ICC/Input Maximum 3-State Current ±0.5 0.001 0.001 4.49 5.49 -405C +855C Unit Conditions VOUT VOUT IOUT *VIN IOUT *VIN VCC, (OE) VIL, VCC, VCC, VOLD 1.65 VOHD 3.85
Guaranteed Limits 3.86 4.86 0.36 0.36 ±0.1 3.76 4.76 0.44 0.44 ±1.0 ±5.0
Maximum Level Input Voltage
Minimum High Level Output Voltage
IOLD IOHD
Minimum Dynamic Output Current Maximum Quiescent Supply Current
*All outputs loaded; thresholds input associated with output under test. Maximum test duration output loaded time.
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MC74ACT323
CHARACTERISTICS (For Figures Waveforms, Figures
+25°C Symbol fmax tPLH tPHL tPLH tPZH tPZL tPHZ tPLZ Parameter Maximum Input Frequency Propagation Delay Propagation Delay Propagation Delay Output Enable Time Output Enable Time Output Disable Time Output Disable Time I/On VCC* 12.5 13.5 12.5 11.5 12.5 11.5 -40°C +85°C 14.5 12.5 13.5 12.5 Unit
*Voltage Range ±0.5
OPERATING REQUIREMENTS
Symbol Parameter Setup Time, HIGH Hold Time, HIGH Setup Time, HIGH Hold Time, HIGH Setup Time, HIGH Hold Time, HIGH I/On, DS0, I/On, DS0, HIGH VCC* +25°C -40°C +85°C Unit
Guaranteed Minimum
Pulse Width *Voltage Range ±0.5
CAPACITANCE
Symbol Input Capacitance Power Dissipation Capacitance Parameter Value Unit Test Conditions
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MC74ACT323
SWITCHING WAVEFORMS
1/fmax tPLH I/O0 I/O7 tTLH tTHL tPHL tPHL I/O0 I/O7
Figure
Figure
tPZL tPLZ tPZH tPHZ HIGH IMPEDANCE HIGH IMPEDANCE
tPZL tPLZ tPHZ HIGH IMPEDANCE HIGH IMPEDANCE
Q0-Q7
Q0-Q7
tPZH
Figure
Figure
VALID MODE SELECT DATA
Figure
INPUT OUTPUT DEVICE UNDER TEST SCOPE TEST POINT
*Includes probe capacitance
Figure Test Circuit
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MC74ACT323
PACKAGE DIMENSIONS
PDIP-20 SUFFIX PLASTIC PACKAGE CASE 738-03 ISSUE
NOTES: DIMENSIONING TOLERANCING ANSI Y14.5M, 1982. CONTROLLING DIMENSION: INCH. DIMENSION CENTER LEAD WHEN FORMED PARALLEL. DIMENSION DOES INCLUDE MOLD FLASH. INCHES 1.010 1.070 0.240 0.260 0.150 0.180 0.015 0.022 0.050 0.050 0.070 0.100 0.008 0.015 0.110 0.140 0.300 0.020 0.040 MILLIMETERS 25.66 27.17 6.10 6.60 3.81 4.57 0.39 0.55 1.27 1.27 1.77 2.54 0.21 0.38 2.80 3.55 7.62 0.51 1.01
SEATING PLANE
0.25 (0.010)
0.25 (0.010)
SO-20 SUFFIX PLASTIC SOIC PACKAGE CASE 751D-05 ISSUE
NOTES: DIMENSIONS MILLIMETERS. INTERPRET DIMENSIONS TOLERANCES ASME Y14.5M, 1994. DIMENSIONS INCLUDE MOLD PROTRUSION. MAXIMUM MOLD PROTRUSION 0.15 SIDE. DIMENSION DOES INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL 0.13 TOTAL EXCESS DIMENSION MAXIMUM MATERIAL CONDITION. MILLIMETERS 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 10.05 10.55 0.25 0.75 0.50 0.90
0.25
0.25
SEATING PLANE
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MC74ACT323
PACKAGE DIMENSIONS
TSSOP-20 SUFFIX PLASTIC TSSOP PACKAGE CASE 948E-02 ISSUE
0.15 (0.006)
0.10 (0.004)
IDENT
0.15 (0.006)
0.100 (0.004) SEATING
PLANE
DETAIL
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PUBLICATION ORDERING INFORMATION
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SECTION 0.25 (0.010) DETAIL
NOTES: DIMENSIONING TOLERANCING ANSI Y14.5M, 1982. CONTROLLING DIMENSION: MILLIMETER. DIMENSION DOES INCLUDE MOLD FLASH, PROTRUSIONS GATE BURRS. MOLD FLASH GATE BURRS SHALL EXCEED 0.15 (0.006) SIDE. DIMENSION DOES INCLUDE INTERLEAD FLASH PROTRUSION. INTERLEAD FLASH PROTRUSION SHALL EXCEED 0.25 (0.010) SIDE. DIMENSION DOES INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL 0.08 (0.003) TOTAL EXCESS DIMENSION MAXIMUM MATERIAL CONDITION. TERMINAL NUMBERS SHOWN REFERENCE ONLY. DIMENSION DETERMINED DATUM PLANE -W-. MILLIMETERS 6.40 6.60 4.30 4.50 -1.20 0.05 0.15 0.50 0.75 0.65 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 INCHES 0.252 0.260 0.169 0.177 -0.047 0.002 0.006 0.020 0.030 0.026 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252
MC74ACT323/D
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