64-voice RISC Cores High-speed CISC Control Processor Versatile Progra

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64-voice RISC Cores High-speed CISC Control Processor Versatile Progra

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128-voice Top-quality Wavetable Synthesis Chip
64-voice RISC Cores High-speed CISC Control Processor Versatile Programmable Digital Audio Routing Between DSPs Voices Allocated Synthesis and/or Effects and/or Audio Processing Maximum Single-shot Wavesize Samples Seconds 44.1 kHz) Samples Stored 16-bit Floating Point Format (20-bit Dynamic), 16-bit Linear, 8-bit Linear Standard Audio Processing Firmware Includes Equalizer, Surround, MPEG Audio Decoder (Level Sophisticated Built-in Cache Memories Allows Standard 16-bit ROMs/RAMs Guarantees Crisp Response Even Under Heavy Traffic Conditions Sound Set(1) under License from Roland® Corporation, Other Sound Sets Available 16-channel Audio-in, 16-channel Audio-out Bits Audio/Channel 28-bit Internal Audio Path Serial MIDI-In, Serial MIDI-Out Firmware/Wavetable Data Reside ROM, DRAM, SDRAM 256M Bytes External Memory with Support SIMM (DRAM) DIMM (SDRAM) High-speed 16-bit Burst Transfer Firmware Download Streaming Audio Compatible with SAM9707, Uses Proven Design Development Tools Sound Editor, Sound Bank Editor Algorithm Compiler, Assembler, Source Debugger Direct Development from Environment, Special Emulator Required Technology Single Low-frequency Crystal Built-in 3.3V Supply, 5V-tolerant I/Os Space-saving 144-lead TQFP Package Power-down Mode Typical Applications: Karaokes, High-range Multimedia, Classical Organs, Digital Pianos, Professional Keyboards, Musical Samplers Sound subject special licensing conditions. used musical instruments.
128-voice Integrated Sound Synthesizer SAM9708
Note:
Description
SAM9708 128-voice integrated synthesizer, integrating PDSP blocks memory management unit (MMU). PDSP block combination specialized 64-slot RISC-based digital signal processor (DSP), general-purpose 16-bit CISC-based control processor (P16), cache memory "intelligent" peripheral interface. Both PDSPs fully independent share same external memory through MMU.
Rev. 1772B-01/02
Block Diagrams
Figure SAM9708 Block Diagram
16-bit
PDSP
MIDI Audio
Memory
PDSP
Figure PDSP Block Diagram
Functions 16-bit MIDI
Control/Status MIDI UART Timers Host
Processor
16-bit CISC Processor Core Includes Data Boot
Synthesis/DSP
RISC Core Includes
Audio
Cache Memory
SAM9708
1772B-01/02
SAM9708
Description Function
Table Power Group
Name VCC1 VCC2 Count Type Function Power Ground. pins should returned digital ground. Core Power, +3.3V nominal 4.5V). pins should returned +3.3V. (except Memory Pad) Power, +3.0V +5.5V. pins should returned 3.3V case single 3.3V supply). Memory Power, +3.0V +5.5V. pins should returned (for DRAM) 3.3V (for SDRAM 3.3V ROM).
Table Group(1)
Name PC_D[15:0](2, Count Type Function 16-bit data host processor. Information these pins parallel MIDI (MPU-401 type applications) high-speed burst data transfers to/from external memory Selects internal registers: MPU-401 register processor Burst data (16-bit) processor MPU-401 register processor Burst data (16-bit) processor Chip select from host, active low. Write from host, active low. Read from host, active low. Open drain output buffer. Driven during 16-bit burst mode transfers synchronize host SAM9708 memory. Open drain output buffer; driven during 16-bit burst mode transfers. Indicates host that 16-bit progress. Tri-state output pin, active high. connected directly host line.
PC_A[2:0]
PC_CS PC_WR PC_RD PC_READY PC_IO16 PC_IRQ Notes:
TSout TSout TSout
group pins powered VCC1 power rail. PC_D pads have drive capabilities; other output pads have drive capabilities. interface with bus, VCC1 should connected power PC_D should buffered. Direction given PC_RD signal.
1772B-01/02
Table MIDI Audio Group(1)
Name MIDI1_IN MIDI2_IN MIDI1_OUT MIDI2_OUT OVCK_OUT BCK_OUT WS_OUT SD_OUT[7:0] SD_IN[7:0] Count Type Function Main MIDI input. Routed PDSP#1, also routed PDSP#2. Auxiliary MIDI input. Routed PDSP#2(2) Main MIDI output. Outputs from PDSP#1. Auxiliary MIDI output. Outputs from PDSP#2(2) Buffered output. Typically used drive external sigma/delta DAC/ADC 256. Audio data clock. Provides timing SD_OUT. Audio data word select. WS_OUT timing selected I2S- Japanese-compatible. stereo serial audio data output audio channels). Each output holds bits serial data frame. Audio data 22-bit precision(2). stereo serial audio data input audio channels). Each input holds bits serial data frame. Audio data received with 20-bit precision(2).
Notes:
MIDI Audio group pins powered VCC1 power rail. These pins have alternate functions GPIO pins (general-purpose input/output pins). "General-purpose Input/Output Routing" page more details.
Table Memory Group(1)
Name CK_OUT WA[26:0] Count Type Function Master clock SDRAM operation. Frequency times frequency (typ 45.1584 MHz). External memory address (ROM/SRAM/DRAM/SDRAM), 128M words (256M bytes). DRAM/SDRAM addresses time-multiplexed these pins follows: WA8: DRA0 DRA8 WA18: DRA9 WA20: DRA10 WA22: DRA11 SRAM byte select. Should connected lower address when 8-bit wide SRAM used. type (16-bit/8-bit) selected program. ROM/SRAM/DRAM/SDRAM data chip select, active SRAM chip select, active SRAM/DRAM/SDRAM write enable, active low. Timing compatible with SIMM DRAM early write feature. ROM/SRAM output enable, active
WD[15:0] WCS0 WCS1
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SAM9708
Table Memory Group(1) (Continued)
Name Count Type Function DRAM/SDRAM address strobe. reset tested determine memory type configuration (pulled high select SDRAM type). should pulled through external resistor. DRAM/SDRAM column address strobe. reset tested determine memory type configuration (pulled high select DRAM type). should pulled through external resistor. Indicates that DRAM/SDRAM memory refresh cycle progress. used with multiple SIMM/DIMM modules force refresh simultaneously modules. reset REFRESH tested select bootstrap state (pulled high start built-in bootstrap case ROMless applications).
REFRESH
Note:
Memory group pins powered VCC2 power rail.
Table Miscellaneous Group
Name TEST LDTEST PDWN RESET Count Type Function pass filter. Should connected external network. Test pin. Should returned GND. Test pin. Should returned GND. Power down, active Master reset input, active low. Schmidt trigger input. Crystal connection. Crystal frequency should (typ 11.2896 MHz). Crystal frequency internally multiplied provide master clock. also used external clock input (3.3V input). CANNOT USED DRIVE EXTERNAL CIRCUITRY
1772B-01/02
Pinout Number
Table Pinout Number
Number Name PC_D[10] PC_D[9] PC_D[8] PC_IO16 VCC1 PC_READY PC_RD PC_WR PC_A[0] PC_A[1] PC_IRQ PC_A[2] PC_CS PC_D[0] VCC1 PC_D[1] PC_D[2] PC_D[3] PC_D[4] PC_D[5] PC_D[6] PC_D[7] MIDI1_IN MIDI2_IN MIDI1_OUT MIDI2_OUT SD_IN[0] SD_IN[1] VCC1 Number Name SD_IN[2] SD_IN[3] SD_OUT[0] SD_OUT[1] SD_OUT[2] SD_OUT[3] WS_OUT BCK_OUT OVCK_OUT SD_IN[4] SD_IN[5] SD_IN[6] VCC1 SD_IN[7] SD_OUT[4] SD_OUT[5] SD_OUT[6] SD_OUT[7] WD[15] WD[14] WD[13] WD[12] VCC2 WD[11] WD[10] Number Name WD[9] WD[8] WD[7] WD[6] WD[5] WD[4] WD[3] VCC2 WD[2] WD[1] WD[0] WCS0 WCS1 CK_OUT WA[0] WA[1] WA[2] WA[3] VCC2 WA[4] WA[5] REFRESH WA[6] WA[7] WA[8] Number Name VCC2 WA[9] WA[10] WA[11] WA[12] WA[13] WA[14] WA[15] WA[16] WA[17] WA[18] WA[19] VCC2 WA[20] WA[21] WA[22] WA[23] WA[24] WA[25] WA[26] RESET TEST LDTEST PDWN PC_D[15] PC_D[14] PC_D[13] PC_D[12] VCC1 PC_D[11]
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SAM9708
Absolute Maximum Ratings
Table Absolute Maximum Ratings (All voltages with respect
Symbol Parameter Ambient temperature (Power applied) Storage temperature Voltage (except Voltage Supply voltage Supply voltage Maximum (except IRQ, ready) Maximum IOL, IRQ, ready -0.5 -0.5 -0.5 -0.5 +150 16.16 Unit
Recommended Operating Conditions
Table Recommended Operating Conditions
Symbol Note: Parameter Supply voltage(1) Supply voltage Operating ambient temperature 3.3/5.0 Unit
When using 3.3V supply, care must taken that voltage applied does exceed 0.5V.
Characteristics
Table Characteristics 25°C, 3.3V 10%)
Symbol Parameter Low-level input voltage High-level input voltage Low-level output voltage D[15:0], IRQ, ready: Others except LFT: -3.2 High-level output voltage D[15:0], IRQ, ready: Others except LFT: Power supply current (crystal frequency MHz) Power down supply current -0.5 -0.5 0.45 0.45 Unit
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RISC Signal Processor
Each engines operates frame-timing basis with frame subdivided into process slots. Each process itself divided into micro-instructions known "algorithms". different algorithms stored on-chip each private memory, allowing device programmed number audio signal generation/processing applications. Each engine capable generating simultaneous voices using algorithms such wavetable synthesis with interpolation, alternate loop resonant filtering each voice, total polyphony voices. Slots linked together RAM) allow implementation more complex synthesis algorithms. Each also includes pipelined two's complement multiplier, 28-bit pipelined adder eight 24-bit final accumulators. typical application uses around capacity engines synthesis, thus providing minimum 96-voice wavetable polyphony. remaining processing power used typical function like reverberation, chorus, direct sound, surround effect, equalizer, etc. Frequently-accessed parameter data stored banks on-chip memory each DSP. Sample data delay lines, which accessed relatively infrequently, stored external ROM, SRAM, DRAM SDRAM memory. combination localized micro-program memory localized parameter data allows micro-instructions execute MIPS) each DSP. Separate buses from each on-chip parameter memory banks allow highly parallel data movement increase effectiveness each micro-instruction. With this architecture, single micro-instruction accomplish simultaneous operations (add, multiply, load, store, etc.), providing total potential throughput million operations second (MOPS).
Control Processor Functions
Each control processors general-purpose 16-bit CISC processor core, that runs from external memory. boot/macro included on-chip accelerate commonly executed routines allow only devices external memory. Each also includes words local data memory. Each control processor writes parameter blocks within associated order control synthesis process. typical application, control processor parses interprets incoming commands from MIDI UART from parallel 16-bit interface then controls writing into parameter banks associated core. Slowly-changing synthesis functions, such LFOs, implemented control processor periodically updating parameter variables. Each control processor interfaces with other private peripheral devices, such system control status registers, on-chip MIDI UART, on-chip timers 16-bit interface through specialized "intelligent" peripheral logic. This logic automates many system transfers minimize amount overhead processing required from P16. parallel interface implemented using three address lines (A2, A0), chip select signal, read write strobes from host 16-bit data (PC_D0 PC_D15). This data cannot drive directly. External buffers external decoder (PAL) plug play required 16-bit addresses from into three address lines chip select from SAM9708. PDSP#1 responds addresses (A2A1A0 0XX), while PDSP#2 responds addresses (A2A1A0 1XX). Each PDSP parallel interface supports byte-wide interface 16-bit port dedicated burst transfers.
SAM9708
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SAM9708
byte-wide interface normally used implement MPU-401 UART-mode compatible interface. specified address A1A0 address being data register, address being status/control registers. Besides standard status bits MPU-401, additional bits provided expand MPU-401 protocol. Address A1A0 specifies 16-bit port. mainly used burst audio transfers to/from using very efficient instructions like OUTSW INSW which operate maximum bandwidth. This port also used fast program sound bank uploads.
Cache
memory management unit (MMU) allows external and/or memory resources shared between DSPs control processors. This allows single device (i.e., DRAM) serve sample memory storage/delay lines DSPs program storage/data memory control processors. cache allows dramatic reduction traffic with external ROM/RAM, allowing standard parts with sampling frequencies kHz. Average access request rate external memory only every frames each slot, which gives accesses synthesis frame. provide memory accesses frame, which leaves over accesses free frame used processors. This means that under full 128-voice polyphony traffic conditions, each instruction average execution time around sampling frequency. 128-voice polyphony assured only when samples played nominal frequency down-transposed. Simultaneously playing large number up-transposed samples adversely affect polyphony. more details possible polyphony given application, please refer application note "SAM9708 Memory Management Unit".
1772B-01/02
Timing Diagrams
timing conditions: 3.3V, 25°C; signals READY, CS16, with ohms pull-up, capacitance; signal with ohms pull-down, capacitance; other outputs except load capacitance timings refer tCK, which internal master clock period. internal master clock frequency times frequency Therefore tXTAL/4. sampling rate given 1/(tCK 1024). maximum crystal frequency/clock frequency 12.288 sampling rate). Figure Host Interface Read Cycle
tAVCS
Host Interface
tCSLRDL tPRD tRDHCSB
tRDLIORL tPIOR
READY
tCSLIOCS tCSHIOCS tIORHDV tRDLDV tRDH
CS16
Note:
valid only A2A1 SBHE
Figure Host Interface Write Cycle
tAVCS
tCSLWRL tPWR tWRHCSB
tWRLIORL tPIOR
READY
tCSLIOCS tIORHWRH tCSHIOCS
CS16
tDWS
tDWB
Note:
valid only A2A1
SAM9708
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SAM9708
Table Host Interface Timing Parameters
Symbol tAVCS tCSLDRL tRDHCSH tPRD tRDLDV tDRH tRDLIORL tPIRO tIORHDV tCSLIOCS tCSHIOCS tCSLRWRL tWRHCSH tPWR tWRLIORL tIORHWRH tDWS tDWH Notes: Parameter Address valid chip select Chip select high high pulse width Data valid from Data hold from ready from ready pulse width
Unit
ready rising data valid CS16 from CS16 high from high Chip select high high pulse width ready from ready high high Write data setup time Write data hold time
When data already loaded into internal SAM9708 output register. this case READY says high during read cycle. READY goes into only data ready loaded into/read from internal SAM9708 register. corresponds single worst-case situation. 12.288 MHz, READY likely never when using standard timing. CS16 asserted SAM9708 A2A1 indicate fast 16-bit transfer
1772B-01/02
External Memory Timing
External Memory Overview
following memories connected SAM9708: Flash memories, bits wide Static RAMs, bits bits wide DRAMs, bits wide SDRAMs, bits wide
DRAMs SDRAMs cannot connected same time. type dynamic connection determined power-up sensing level pins (see Table page "Memory Type Configuration Boot Configuration" page 25). Eight-bit wide static connected using additional Byte Select (RBS) address signal. allows access bytes SRAM within regular memory cycle, thereby providing bits data. Eight-bit wide SRAM connected only under control WCS1. selection bits/16 bits done firmware. static RAMs linear addressing (address lines WA26). DRAM SDRAMs time-multiplexed addressing with ROW/COL scheme (address lines DRA0 DRA11). Additionally, SDRAMs DRA0/DRA11 lines configuration DRA10 line auto precharge. ROM/SRAMs DRAM/SDRAM address line share same pins SAM9708. timing determined input signal DRAM. DRAM high beginning memory cycle, this indicates DRAM/SDRAM access. only type memory connected (i.e., SDRAM), then DRAM signal hardwired. Otherwise, should derived from external decoding high-order address lines.
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SAM9708
External Memory Timing Overview
memory cycle consists internal master clock cycles tCK). internal master clock period one-fourth clock period internal master clock provided CK_OUT when external SDRAM connected (RAS sensed high during RESET). Basic notes SDRAM timing: RESET should held least (SDRAM timing requirement idle cycles) SDRAM mode fixed sequential, burst length latency standard operation, programmed write burst length. SDRAM cycles read: ACTIVE READ AUTO PRECHARGE NOP. SDRAM cycles write: ACTIVE WRITE AUTO PRECHARGE SDRAM cycles refresh: AUTO REFRESH
Figure SRAM Basic Timing, DRAM
WAxx
WDxx
ROM/SRAM16 READ
SRAM16 WRITE
SRAM8 WRITE
1772B-01/02
Figure DRAM Basic Timing, DRAM High
DRAxx
REFRESH
WDxx
DRAM READ
DRAM WRITE
DRAM REFRESH
Figure SDRAM Basic Timing, DRAM High
DRCLK
DRAxx
REFRESH
WDxx
SDRAM READ
SDRAM WRITE
SDRAM AUTO REFRESH
SAM9708
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SAM9708
Figure SDRAM Init Sequence, DRAM High
DRCLK
DRAxx
REFRESH
PRECHARGE
AUTO REFRESH (TWO CYCLES)
LOAD MODE 020H
Table RAS/CAS Correspondence Physical Address(1)
Signal WA0/DRA0 WA1/DRA1 WA2/DRA2 WA3/DRA3 WA4/DRA4 WA5/DRA5 WA6/DRA6 WA7/DRA7 WA8/DRA8 WA18/DRA9 WA20/DRA10 WA22/DRA11 Note: Valid DRAM SDRAM unless otherwise stated. Value Time WA18 WA20 WA22 Value Time WA10 WA11 WA12 WA13 WA14 WA15 WA16 WA17 WA19 (DRAM) Don't care (SDRAM) WA21 (DRAM) High (SDRAM) WA23 (DRAM) Don't care (SDRAM)
1772B-01/02
Detailed External DRAM Timing
Figure Read Cycle
tRAS tRCD tASR DRA0 DRA11 tRAH tASC tCAH tCAS tCRP
tCAC tRAC WD15 tOFF
Figure Write Cycle (Early Write)
tRAS tRCD tASR DRA0 DRA11 tWCS tWCH tRAH tASC tCAH tCAS tCRP
WD15
SAM9708
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SAM9708
Figure Refresh Cycle (RAS Only)
tRAS tASR DRA0 DRA11
counter
tRAH
Table External DRAM Timing Parameters
Symbol tRAC tCAC tOFF tRAS tCAS tRCD tCRP tASR tRAH tASC tCAH tWCS tWCH Parameter Read/Write/Refresh cycle Access time from RAS/ Access time from CAS/ high output Hi-Z precharge time pulse width pulse width delay time precharge time address setup time address hold time Column address setup time Column address hold time Write command set-up time Write command hold time Write data set-up time Write data hold time Refresh counter average period (12-bit counter) Unit
following points should noted: multiplexed CAS, addressing support memory DRAM chips Mbits long number address lines column address lines identical. example, device type 416C1200 supported because organization with 10-bit 10-bit column. Device type 416C1000 supported because organization with 12-bit 8-bit column. signal normally used DRAM connection. represented only reference purposes. only counter refresh method employed, several banks DRAMs connected using simple external decoding. Linear address lines (WAx) used select between DRAM banks. example, SIMM module connected banks, with CAS0 CAS1 selections issued from WA20. During whole DRAM cycle (from rising), WCS0 asserted low.
1772B-01/02
equivalence between multiplexed DRAM address lines (DRA0 DRA11) corresponding linear addressing (WA0 WA23) follows:
DRA11 time time WA22 WA23 DRA10 WA20 WA21 DRA9 WA18 WA19 DRA8 WA17 DRA7 WA16 DRA6 WA15 DRA5 WA14 DRA4 WA13 DRA3 WA12 DRA2 WA11 DRA1 WA10 DRA0
save DRAM power consumption, cycled only when necessary. Therefore, depending firmware loaded, total board power consumption increase with synthesis processing traffic.
Detailed External Timing
Figure Read Cycle
WCS0 tSOE WA26 tPOE tACE WD15
Table External Timing Parameters
Symbol tCSOE tPOE tACE Parameter Read cycle time Chip select low/address valid Output enable pulse width Chip select/address access time Output enable access time Chip select high input data High Unit
SAM9708
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SAM9708
External Timing
Figure 16-bit SRAM Read Cycle
WCS1 tCSOE WA26 tPOE
tACE WD15
Figure 16-bit SRAM Write Cycle
WCS1 tCSWE WA26
WD15
Table External 16-bit SRAM Timing Parameters
Symbol tCSOE tPOE tACE Parameter Read cycle time Chip select low/address valid Output enable pulse width Chip select/address access time Output enable access time Chip select high input data Hi-Z Write cycle time Unit
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Table External 16-bit SRAM Timing Parameters (Continued)
Symbol tCSWE Parameter Write enable from Address Write pulse-width Data setup time Data hold time Unit
Figure 8-bit SRAM Read Cycle
WCS1 tCSOE WA26 tPOE
tACE
tORB
tACH
HIGH
Figure 8-bit SRAM Write Cycle
WCS1 tCSWE WA26
tDW1 tDH1
tDW2
HIGH
tDH2
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SAM9708
Table External 8-bit SRAM Timing Parameters
Symbol tCSOE tPOE tACE tORB tACH tCSWE tDW1 tDH1 tDW2 tDH2 Parameter Word bytes) read cycle time Chip select low/address valid Output enable pulse width Chip select/address byte access time Output enable byte access time Output enable byte select high Byte select high byte access time Chip select high input data High Word bytes) write cycle time from Address Write (low high byte) pulse width Data byte setup time Data byte hold time high second write pulse Data high byte setup time Data high byte hold time Unit
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Digital Audio Timing
Figure Digital Audio Timing Diagram
WSBD tCLBD
CLBD tSOD DABD0 DAAD0 tSOD
Table Digital Audio Timing Parameters
Symbol tSOD tCLBD Parameter CLBD rising WSBD change DABDx/DAADx valid prior/after CLBD rising CLBD cycle time Unit
Figure Digital Audio Frame Format
WSBD (I2S) CLBD
DABD0-7 DAAD0-7 bits) bits)
Note: DAAD always bits.
bits)
SAM9708
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SAM9708
Audio Routing
Each PDSP process eight digital audio inputs generate eight digital audio outputs total digital audio-in digital audio-out. eight outputs from DSP#2 individually routed DSP#1 inputs.
Figure Audio Routing
SD_IN[7:4] PDSP#1 SD_OUT[3:0]
SD_IN[3:0]
PDSP#2
SD_OUT[7:4]
MIDI Routing
nfigu ration assign MIDI_IN 1/MID SP#1 MIDI_IN2/MIDI_OUT2 PDSP#2. Alternatively, MIDI_IN1 routed same MIDI input both PDSPs. this case, MIDI_IN2 available general-purpose input. Also, MIDI_OUT2 necessary, defined general-purpose output.
Generalpurpose Input/Output Routing
MIDI_IN2, MIDI_OUT2, AUDIO_IN[7, AUDIO_OUT[7:1] pins individually routed general-purpose inputs outputs identified Table
Table General-purpose Input/Output Routing
GPIO GPIO_OUT[0] DSP#1 GPIO_OUT[1] DSP#1 GPIO_OUT[2] DSP#1 GPIO_OUT[3] DSP#1 GPIO_OUT[4] DSP#1 GPIO_OUT[5] DSP#1 GPIO_OUT[6] DSP#1 GPIO_OUT[7] DSP#1 GPIO_OUT[0] DSP#2 GPIO_OUT[1] DSP#2 GPIO_OUT[2] DSP#2 GPIO_OUT[3] DSP#2 GPIO_OUT[4] DSP#2 GPIO_OUT[5] DSP#2 GPIO_OUT[6] DSP#2 GPIO_OUT[7] DSP#2 MIDI2_OUT SD_OUT[1] SD_OUT[2] SD_OUT[3] SD_IN[0] SD_IN[1] SD_IN[2] SD_IN[3] SD_OUT[4] SD_OUT[5] SD_OUT[6] SD_OUT[7] MIDI2_IN SD_IN[5] SD_IN[6] SD_IN[7]
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Table General-purpose Input/Output Routing (Continued)
GPIO GPIO_IN[0] DSP#1 GPIO_IN[1] DSP#1 GPIO_IN[2] DSP#1 GPIO_IN[3] DSP#1 GPIO_IN[0] DSP#2 GPIO_IN[1] DSP#2 GPIO_IN[2] DSP#2 GPIO_IN[3] DSP#2 SD_IN[0] SD_IN[1] SD_IN[2] SD_IN[3] MIDI2_IN SD_IN[5] SD_IN[6] SD_IN[7]
Bi-processor Operation
Each PDSP access same memory space. Sample data, buffers programs therefore shared between PDSPs, thus minimizing memory requirements. Each possibility test read-only that identifies PDSP number belongs (PDSPID). This allows firmware make decisions according processor currently executing code. example, consider implementation 128-voice synthesizer. easy share traffic between PDSPs would have PDSP#1 process even MIDI-numbered notes, while PDSP#2 would process MIDI-numbered notes. this case, there would only single firmware processed both P16s, with some coding follows:
(PDSPID noteeven) then ProcessNote(); (PDSPID noteodd) then ProcessNote();
PDSPs also execute completely different firmware. this case, both types firmware start from address 100H, test PDSPID should done beginning program jump correct firmware.
Reset Power-down
During power-up, RESET input should held until crystal oscillator stabilized. This take about RESET signal normally derived from master reset. However, typical RC/diode power-up network also used some applications. After low-to-high transition RESET, following occurs: REFRESH sampled high high transition RESET then external SDRAM init cycles executed (see "Memory Type Configuration Boot Configuration" page 25). Both Synthesis/DSP enter idle state. REFRESH low, then both program execution starts from address 0100H space (WCS0 low). REFRESH high, then both program execution starts from address 0000H internal bootstrap space. Each internal bootstrap expects receive words from respective 16-bit burst transfer port, which will stored from 0100H 01FFH into external DRAM space. bootstrap then resumes control address 0100H. PDWN asserted low, then I/Os outputs will floated crystal oscillator will stopped. chip enters deep power-down sleep mode. exit power down, PDWN asserted high, then RESET applied.
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SAM9708
Memory Type Configuration Boot Configuration
power-up, when RESET input goes from high, RAS, REFRESH pins sampled SAM9708 determine memory type configuration boot type. RAS, REFRESH must pulled through external resistor select these different power-up configurations. memory type used pages (addresses [0-8000000h[, AD[27]=0) different type high pages (addresses [8000000h-10000000h[). Memory types allowed Flash/ROM, SRAM, DRAM SDRAM. When using (SRAM, DRAM SDRAM) page, must start bootstrap state. When bootstrap state, program execution starts address bootstrap, program execution starts address 100h. Bootstrap selected REFRESH pin.
Table Memory Type Boot Configuration
Level Detected Reset REFRESH Stand-alone Mode High High Bootstrap Mode High High High Note: High High SRAM DRAM SDRAM WCS0 RAS, RAS, Flash/ROM Flash/ROM Flash/ROM WCS1 WCS1 WCS1 High High Memory Type Flash/ROM Flash/ROM Flash/ROM Flash/ROM Selected WCS0 WCS0 WCS0 WCS0 Memory Type SRAM DRAM SDRAM Selected WCS1 RAS, RAS, Page High Page
Selected firmware
When accessing DRAM SDRAM, DRAM/SDRAM selected signals (WCS0 WCS1 inactive) addresses time-multiplexed WA[.] pins follows: WA8: DRA0 DRA8 WA18: DRA9 WA20: DRA10 WA22: DRA11 When accessing SRAM, Flash ROM, SRAM/Flash/ROM selected signals WCS0, WCS1 (RAS inactive) WA[26.0] address pins: pages: WCS0 WCS1 high pages: WCS0 WCS1
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Recommended Board Layout
GND, VCC, Distribution, Decouplings
Like HCMOS high-integration ICs, some rules board layout should followed reliable device operation: GND, VCC, pins should connected. planes strongly recommended below SAM9708. board distribution should grid form. 3.3V available, then connected 1N4148 diodes series. Recommended decoupling each corner with additional decoupling close crystal. requires single 0.1µF decoupling close
Crystal,
paths between crystal, crystal compensation capacitors, filter R-C-R SAM9708 should short shielded. ground return from compensation capacitors filter should plane from SAM9708. Parallel layout from DRA0 DRA11/WD0 WD15 should avoided. asynchronous high-transient current-type bus. Even short distances, induce pulses DRA0 DRA11/WD0 WD15 which corrupt address and/or data these buses. ground plane should implemented below bus, which connects both PC-ISA connector SAM9708 GND. ground plane should implemented below DRA0 DRA11/WD0 WD15 bus, which connects both DRAM SIMM grounds SAM9708.
Buses
Analog Section
specific AGND ground plane should provided, which connects ground single trace. digital signals should cross AGND plane. Refer Codec vendor recommended layout correct implementation analog section.
SAM9708
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SAM9708
Recommended Crystal Compensation Filter
Figure Recommended Crystal Compensation Filter
RESET PDWN
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Mechanical Dimensions
Figure 144-lead TQFP Package Drawing
Table 144-lead TQFP Package Dimensions millimeters)
0.17 1.40 0.05 1.35 21.90 19.90 21.90 19.90 0.45 1.50 0.10 1.40 22.00 20.00 22.00 20.00 0.60 0.50 0.22 0.27 1.60 0.15 1.45 22.10 20.10 22.10 20.10 0.75
SAM9708
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Corporate Headquarters
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Atmel Corporation 2002. Atmel Corporation makes warranty products, other than those expressly contained Company's standard warranty which detailed Atmel's Terms Conditions located Company's site. Company assumes responsibility errors which appear this document, reserves right change devices specifications detailed herein time without notice, does make commitment update information contained herein. licenses patents other intellectual property Atmel granted Company connection with sale Atmel products, expressly implication. Atmel's products authorized critical Atmel® registered trademark Atmel Corporation. Roland® Sound logo registered trademarks Roland Corporation. General MIDI logo under licence Midi Manufacturers Association. Other terms product names trademarks others. Printed recycled paper.
1772B-01/02/0M

64-voice RISC Cores High-speed CISC Control Processor Versatile Progra

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