VirtexTM-E Field Programmable Gate Arrays DS022-1 (v2.2) November

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VirtexTM-E Field Programmable Gate Arrays DS022-1 (v2.2) November

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VirtexTM-E Field Programmable Gate Arrays
DS022-1 (v2.2) November 2001
Preliminary Product Specification
Features
Fast, High-Density FPGA Family Densities from system gates internal performance (four levels) Designed low-power operation compliant 32/64-bit, 66-MHz Highly Flexible SelectI/O+Technology Supports high-performance interface standards singled-ended I/Os differential pairs aggregate bandwidth Gb/s Differential Signalling Support LVDS (622 Mb/s), BLVDS (Bus LVDS), LVPECL Differential signals input, output, Compatible with standard differential devices LVPECL LVDS clock inputs 300+ clocks Proprietary High-Performance SelectLinkTechnology Double Data Rate (DDR) Virtex-E link Web-based generation methodology Sophisticated SelectRAM+Memory Hierarchy internal configurable distributed synchronous internal block True Dual-PortBlockRAM capability Memory bandwidth 1.66 Tb/s (equivalent bandwidth over RAMBUS channels) Designed high-performance Interfaces External Memories ZBT* SRAMs Mb/s SDRAMs Supported free Synthesizable reference design
trademark Integrated Device Technology, Inc.
High-Performance Built-In Clock Management Circuitry Eight fully digital Delay-Locked Loops (DLLs) Digitally-Synthesized duty cycle Double Data Rate (DDR) Applications Clock Multiply Divide Zero-delay conversion high-speed LVPECL/LVDS clocks standard Flexible Architecture Balances Speed Density Dedicated carry logic high-speed arithmetic Dedicated multiplier support Cascade chain wide-input function Abundant registers/latches with clock enable, dual synchronous/asynchronous reset Internal 3-state bussing IEEE 1149.1 boundary-scan logic Die-temperature sensor diode Supported Xilinx Foundationand Alliance SeriesDevelopment Systems Further compile time reduction Internet Team Design (ITD) tool ideal million-plus gate density designs Wide selection workstation platforms SRAM-Based In-System Configuration Unlimited re-programmability Advanced Packaging Options Chip-scale 1.27 HQ/PQ 0.18 6-Layer Metal Process 100% Factory Tested
2001 Xilinx, Inc. rights reserved. Xilinx trademarks, registered trademarks, patents, disclaimers listed other trademarks registered trademarks property their respective owners. specifications subject change without notice.
DS022-1 (v2.2) November 2001 Preliminary Product Specification
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Module
VirtexTM-E Field Programmable Gate Arrays
Table Virtex-E Field-Programmable Gate Array Family Members Device XCV50E XCV100E XCV200E XCV300E XCV400E XCV600E XCV1000E XCV1600E XCV2000E XCV2600E XCV3200E System Gates 71,693 128,236 306,393 411,955 569,952 985,882 1,569,178 2,188,742 2,541,952 3,263,755 4,074,387 Logic Gates 20,736 32,400 63,504 82,944 129,600 186,624 331,776 419,904 518,400 685,584 876,096 Array Logic Cells 1,728 2,700 5,292 6,912 10,800 15,552 27,648 34,992 43,200 57,132 73,008 Differential Pairs User BlockRAM Bits 65,536 81,920 114,688 131,072 163,840 294,912 393,216 589,824 655,360 753,664 851,968 Distributed Bits 24,576 38,400 75,264 98,304 153,600 221,184 393,216 497,664 614,400 812,544 1,038,336
Virtex-E Compared Virtex Devices
Virtex-E family offers 43,200 logic cells devices faster than Virtex family. performance increased Mb/s using Source Synchronous data transmission architectures synchronous system performance using singled-ended SelectI/O technology. Additional standards supported, notably LVPECL, LVDS, BLVDS, which pins signal. Almost signal pins used these standards. Virtex-E devices have faster (250 MHz) block SelectRAM, individual RAMs same size structure Virtex family. They also have eight DLLs instead four Virtex devices. Each individual slightly improved with easier clock mirroring frequency multiplication. VCCINT, supply voltage internal logic memory, instead Virtex devices. Advanced processing 0.18 design rules have resulted smaller dice, faster speed, lower power consumption. pins tolerant, tolerant with external resistor. supported. With addition appropriate external resistors, tolerate voltage desired. Banking rules different. With Virtex devices, input buffers powered VCCINT. With Virtex-E devices, LVTTL, LVCMOS2, input buffers powered supply voltage VCCO.
Virtex-E family bitstream-compatible with Virtex family, Virtex designs compiled into equivalent Virtex-E devices. same device same package Virtex-E Virtex families pin-compatible with some minor exceptions. data sheet pinout section details.
General Description
Virtex-E FPGA family delivers high-performance, high-capacity programmable logic solutions. Dramatic increases silicon efficiency result from optimizing architecture place-and-route efficiency exploiting aggressive 6-layer metal 0.18 CMOS process. These advances make Virtex-E FPGAs powerful flexible alternatives mask-programmed gate arrays. Virtex-E family includes nine members Table Building experience gained from Virtex FPGAs, Virtex-E family evolutionary step forward programmable logic design. Combining wide variety programmable system features, rich hierarchy fast, flexible interconnect resources, advanced process technology, Virtex-E family delivers high-speed high-capacity programmable logic solution that enhances design flexibility while reducing time-to-market.
Virtex-E Architecture
Virtex-E devices feature flexible, regular architecture that comprises array configurable logic blocks (CLBs) surrounded programmable input/output blocks (IOBs), interconnected rich hierarchy fast, versatile routing
Module
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DS022-1 (v2.2) November 2001 Preliminary Product Specification
VirtexTM-E Field Programmable Gate Arrays
resources. abundance routing resources permits Virtex-E family accommodate even largest most complex designs. Virtex-E FPGAs SRAM-based, customized loading configuration data into internal memory cells. Configuration data read from external SPROM (master serial mode), written into FPGA (SelectMAPTM, slave serial, JTAG modes). standard Xilinx Foundation Seriesand Alliance SeriesDevelopment systems deliver complete design support Virtex-E, covering every aspect from behavioral schematic entry, through simulation, automatic design translation implementation, creation downloading configuration stream.
Table Performance Common Circuit Functions Function Register-to-Register Adder Pipelined Multiplier Address Decoder 16:1 Multiplexer Parity Tree Bits Virtex-E (-7)
Higher Performance
Virtex-E devices provide better performance than previous generations FPGAs. Designs achieve synchronous system clock rates including Mb/s using Source Synchronous data transmission architechtures. Virtex-E I/Os comply fully with specifications, interfaces implemented that operate MHz. While performance design-dependent, many designs operate internally speeds excess achieve over MHz. Table shows performance data representative circuits, using worst-case timing parameters.
Chip-to-Chip HSTL Class LVTTL,16mA, fast slew LVDS LVPECL
Virtex-E Device/Package Combinations Maximum
Table Virtex-E Family Maximum User Device/Package (Excluding Dedicated Clock Pins) CS144 PQ240 HQ240 BG352 BG432 BG560 FG256 FG456 FG676 FG680 FG860 FG900 FG1156 100E 200E 300E 400E 600E 1000E 1600E 2000E 2600E 3200E
DS022-1 (v2.2) November 2001 Preliminary Product Specification
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Module
VirtexTM-E Field Programmable Gate Arrays
Virtex-E Ordering Information
Example: XCV300E-6PQ240C
Device Type Temperature Range Commercial Industrial +100 Number Pins Package Type Ball Grid Array Fine Pitch Ball Grid Array High Heat Dissipation
DS022_043_07200
Speed Grade (-6,
Figure Ordering Information
Revision History
following table shows revision history this document. Date 12/7/99 1/10/00 1/28/00 Version Initial Xilinx release. Re-released with spd.txt 1.18, FG860/900/1156 package information, additional DLL, Select SelectI/O information. Added Delay Measurement Methodology table, updated SelectI/O section, Figures text explaining Table TBYP values, buffered Line info, Timing Measurement notes, notes Tables corrected F1156 pinout table footnote references. Updated pinout tables, page corrected Figure Correction table Numerous minor edits. Data sheet upgraded Preliminary. Preview numbers added Virtex-E Electrical Characteristics tables. Reformatted entire document follow style guidelines. Changed speed grade values tables pages 35-37. values added Virtex-E Electrical Characteristics tables. XCV2600E XCV3200E numbers added Virtex-E Electrical Characteristics tables (Module Corrected user count XCV100E device Table (Module Changed several pins Connect XCV100E" removed duplicate VCCINT pins Table (Module Changed connect XCV600E" Table (Module Changed "VREF option only XCV600E" Table (Module Corrected pair Table (Module XCV1000E, XCV1600E". Revision
2/29/00 5/23/00 7/10/0
8/1/00 9/20/0
Module
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DS022-1 (v2.2) November 2001 Preliminary Product Specification
VirtexTM-E Field Programmable Gate Arrays
Date 11/20/0
Version
Revision Upgraded speed grade numbers Virtex-E Electrical Characteristics tables Preliminary. Updated minimums Table added notes Table Added note Absolute Maximum Ratings. Changed speed grade numbers TSHCKO32, TREG, TBCCS, TICKOF. Changed minimum hold times -0.4 under Global Clock Setup Hold LVTTL Standard, with DLL. Revised maximum TDLLPW speed grade Timing Parameters. Changed GCLK0 BA22 FG860 package Table Revised footnote Table Added numbers Virtex-E Electrical Characteristics tables XCV1000E XCV2000E devices. Updated Table Table include values XCV400E XCV600E devices. Revised Table include pinout information XCV400E XCV600E devices BG560 package. Updated footnotes Table include XCV2600E XCV3200E devices. Updated numerous values Virtex-E Switching Characteristics tables. Converted data sheet modularized format. Virtex-E Data Sheet section. Updated Virtex-E Device/Package Combinations Maximum table show XCV3200E FG1156 package. Minor edits.
2/12/01
4/2/01 10/25/01 11/09/01
Virtex-E Data Sheet
Virtex-E Data Sheet contains following modules: DS022-1, Virtex-E 1.8V FPGAs:
Introduction Ordering Information (Module
DS022-3, Virtex-E 1.8V FPGAs:
Switching Characteristics (Module
DS022-2, Virtex-E 1.8V FPGAs:
Functional Description (Module
DS022-4, Virtex-E 1.8V FPGAs:
Pinout Tables (Module
DS022-1 (v2.2) November 2001 Preliminary Product Specification
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Module

VirtexTM-E Field Programmable Gate Arrays DS022-1 (v2.2) November

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