DR8051CPU high performance, area optimized soft core single-chip 8-bit

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DR8051CPU high performance, area optimized soft core single-chip 8-bit

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High Performance Configurable 8-bit Microcontroller 3.01
DR8051CPU high performance, area optimized soft core single-chip 8-bit embedded controller dedicated operation with fast (typically on-chip) slow (off-chip) memories. core been designed with special concern about power consumption. Additionally advanced power management unit makes DR8051CPU core perfect portable equipment where power consumption mandatory. DR8051CPU soft core 100% binarycompatible with industry standard 8051 8bit microcontroller. There configurations DR8051CPU: Harward where external data program buses separated, Neumann with common program external data bus. DR8051CPU RISC architecture times faster compared standard architecture executes 65-200 million instructions second. This performance also exploited great advantage power applications where core clocked seven times more slowly than original implementation performance penalty. DR8051CPU delivered with fully automated testbench complete tests allowing easy package validation each stage design flow.
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FEATURES
100% software compatible with industry standard 8051 RISC architecture enables execute instructions times faster compared standard 8051 times faster multiplication times faster division bytes internal (on-chip) Data Memory bytes Program Memory bytes external (off-chip) Data Memory User programmable Program Memory Wait States solution wide range memories speed User programmable External Data Memory Wait States solution wide range memories speed De-multiplexed Address/Data allow easy connection memory Interface additional Special Function Registers Fully synthesizable, static synchronous design with positive edge clocking internal tri-states
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Copyright 1999-2003 Digital Core Design. Rights Reserved.
Scan test ready virtual clock frequency 0.35u technological process
CONFIGURATION
following parameters DR8051CPU core easy adjusted requirements dedicated application technology. Configuration core prepared effortless changing appropriate constants package file. There need change parts code.
Memory style Program Memory type Program Memory waitstates Harward Neumann synchronous asynchronous used (0-7) unused used unused synchronous asynchronous used (0-7) unused subroutines location
PERIPHERALS
DoCDdebug unit
Processor execution control Halt Step into instruction Skip instruction Read-write processor contents Program Counter (PC) Program Memory Internal (direct) Data Memory Special Function Registers (SFRs) External Data Memory Hardware execution breakpoints Program Memory Internal (direct) Data Memory Special Function Registers (SFRs) External Data Memory Hardware breakpoints activated certain Program address (PC) Address write into memory Address read from memory Address write into memory required data Address read from memory required data Three wire communication interface
Program Memory writes Internal Data Memory type External Data Memory size External Data Memory wait-states
Interrupts Power Management Mode Stop mode debug unit
used unused used unused used unused
DELIVERABLES
Source code: VHDL Source Code or/and VERILOG Source Code or/and Encrypted, plain text EDIF netlist VHDL VERILOG test bench environment Active-HDL automatic simulation macros ModelSim automatic simulation macros Tests with reference responses Technical documentation Installation notes core specification Datasheet Synthesis scripts Example application Technical support Core implementation support months maintenance
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Power Management Unit
Power management mode Switchback feature Stop mode
Interrupt Controller
priority levels external interrupt sources
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Copyright 1999-2003 Digital Core Design. Rights Reserved.
Delivery Core updates, minor major versions changes Delivery documentation updates Phone email support
SYMBOL
reset ramdatai(7:0) ramdatao(7:0) ramaddr(7:0) ramoe ramwe sfrdatao(7:0) sfraddr(7:0) sfroe sfrwe prgdatao(7:0) prgdataz prgaddr(15:0) prgrd prgwr xramdatao(7:0) xramdataz xramaddr(23:0) xramrd xramwr docddatao docdclk stop
LICENSING
Comprehensible clearly defined licensing methods without royalty fees make using Core easy simply. Single Design license allows Core single FPGA bitstream ASIC implementation. Unlimited Designs, Year licenses allow Core unlimited number FPGA bitstreams ASIC implementations. cases number Core instantiations within design, number manufactured chips unlimited. There time restriction except Year license where time limited months. Single Design license
VHDL, Verilog source code called Source Encrypted, plain text EDIF called Netlist
sfrdatai(7:0)
prgdatai(7:0)
xramdatai(7:0)
int0 int1 docddatai
Year license
Encrypted Netlist only
Unlimited Designs license
Source Netlist
BLOCK DIAGRAM
reset prgdatai(7:0) prgdatao(7:0) prgdataz prgaddr(15:0) prgrd prgwr xramdatai(7:0) xramdatao(7:0) xramdataz xramaddr(23:0) xramrd xramwr ramdatai(7:0) ramdatao(7:0) ramaddr(7:0) ramoe ramwe sfrdatai(7:0) sfrdatao(7:0) sfraddr(7:0) sfroe sfrwe
Opcode Decoder
Upgrade from
Source Netlist Single Design Unlimited Designs
Program Memory Interface
Control Unit
External Memory Interface
Interrupt Controller
int0 int1
Internal Data Memory Interface
Power Management Unit
stop
User Interface
DoCDDebug Unit
docddatai docddatao docdclk
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Copyright 1999-2003 Digital Core Design. Rights Reserved.
PINS DESCRIPTION
reset ramdatai[7:0] sfrdatai[7:0] prgdatai[7:0] xramdatai[7:0] int0 int1 docddatai ramdatao[7:0] ramaddr[7:0] ramoe ramwe sfrdatao[7:0] sfraddr[7:0] sfroe sfrwe prgaddr[15:0] prgdatao[7:0] prgdataz prgrd prgwr xramdatao[7:0] xramdataz xramaddr[23:0] xramrd xramwr docddatao docdclk stop
TYPE
input input input input input input input input input output output output output output output output output output output output output output output output output output output output output output output
DESCRIPTION
Global clock Global synchronous reset Data from Internal Data Memory Data from user SFRs Input data from Program Memory Data from External Data Memory External interrupt line External interrupt line DoCDdata input Data Internal Data Memory Internal Data Memory address Internal Data Memory output enable Internal Data Memory write enable Data user SFRs User SFRs address User SFRs output enable User SFRs write enable Program Memory address Output data Program Memory PRGDATA tri-state buffers control line Program Memory read Program Memory write Data External Data Memory XDATA tri-state buffers control line External Data Memory address External Data Memory read External Data Memory write DoCDdata output DoCDclock line Power management mode indicator Stop mode indicator
Program Memory Interface Contains Program Counter (PC) related logic. performs instructions code fetching. Program Memory also written. This feature allows usage small boot loader loading program into RAM, EPROM FLASH EEPROM storage UART, SPI, DoCDmodule. Program fetch cycle length programmed user. This feature called Program Memory Wait States, allows core work with different speed program memories. External Memory Interface Contains memory access related registers such Data Pointer High (DPH0), Data Pointer (DPL0), Data Page Pointer (DPP0), MOVX address register (MXAX) STRETCH registers. performs memory addressing data transfers. Allows applications software access external data memory. DPP0 register used segments swapping. STRETCH register allows flexible timing management while accessing different speed system devices programming XRAMWR XRAMRD pulse width between clock periods. Internal Data Memory Interface Internal Data Memory interface controls access into internal bytes memory. contains 8-bit Stack Pointer (SP) register related logic. User SFRs Interface Special Function Registers interface controls access special registers. contains standard used defined registers related logic. User defined external devices quickly accessed (read, written, modified) using direct addressing mode instructions. Interrupt Controller Interrupt control module responsible interrupt manage system external internal interrupt sources. contains interrupt related registers such Interrupt Enable (IE), Interrupt Priority (IP) (TCON) registers. Power Management Unit Block contains advanced power saving mechanisms with switchback feature, allowing external clock control logic stop clocking (Stop mode) core lower clock frequency (Power Management Mode) significantly reduce power consumption. Switchback feature allows UARTs, interrupts processed full speed mode enabled. very desired when
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UNITS SUMMARY
Arithmetic Logic Unit performs arithmetic logic operations during execution instruction. contains accumulator (ACC), Program Status Word (PSW), registers related logic such arithmetic unit, logic unit, multiplier divider. Opcode Decoder Performs instruction opcode decoding control functions other blocks. Control Unit Performs core synchronization data flow control. This module directly connected Opcode Decoder manages execution microcontroller tasks.
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Copyright 1999-2003 Digital Core Design. Rights Reserved.
microcontroller planned portable power critical applications. DoCDDebug Unit it's real-time hardware debugger provides debugging capability whole system. contrast other onchip debuggers DoCDprovides non-intrusive debugging running application. halt, run, step into skip instruction, read/write contents microcontroller including registers, internal, external, program memories, SFRs including user defined peripherals. Hardware breakpoints controlled program memory, internal external data memories, well SFRs. Hardware breakpoint executed write/read occurred particular address with certain data pattern without pattern. DoCDsystem includes three-wire interface complete tools communicate work with core real time debugging. built scalable unit some features turned save silicon reduce power consumption. special care power consumption been taken, when debugger used automatically switched power save mode. Finally whole debugger turned when debug option longer used.
Function 8-bit addition (immediate data) 8-bit addition (direct addressing) 8-bit addition (indirect addressing) 8-bit addition (register addressing) 8-bit subtraction (immediate data) 8-bit subtraction (direct addressing) 8-bit subtraction (indirect addressing) 8-bit subtraction (register addressing) 8-bit multiplication 8-bit division 16-bit addition 16-bit subtraction 16-bit multiplication 32-bit addition 32-bit subtraction 32-bit multiplication Average speed improvement:
Improvement 7,20 6,00 6,00 7,20 7,20 6,00 6,00 7,20 10,67 9,60 7,20 7,64 9,75 7,20 7,43 9,04 7,58
Dhrystone Benchmark Version used measure Core performance. following table gives survey about DR8051CPU performance terms Dhrystone/sec MIPS rating.
Device 80C51 80C310 DR8051CPU Target ORCA Clock frequency Dhry/sec (VAX MIPS) (0.153) 1550 (0.882) 6452 (3.672)
Core performance terms Dhrystones
PERFORMANCE
following tables give survey about Core area performance Programmable Logic Devices after Place Route (all features peripherals have been included):
Device ORCA Speed grade Fmax
8000 6452 6000
4000 1550 2000
80C51 (12MHz) DR8051CPU (40MHz) 80C310 (33MHz)
Core performance LATTICE® devices
user most important application speed improvement. most commonly used arithmetic functions their improvements shown table below. improvement computed {80C51 clock periods} divided {DR8051CPU clock periods} required execute identical function. More details available core documentation.
Area utilized each unit DR8051CPU core vendor specific technologies summarized table below.
Component CPU* Interrupt Controller Power Management Unit Total area Area
[LC/PFU] [FFs]
1510 1630
*CPU consisted ALU, Opcode Decoder, Control Unit, Program Internal External Memory Interfaces, User SFRs Interface
Core components area utilization
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main features each DR8051 family member have been summarized table below. gives briefly member characterization helping user select most suitable Core application. User specify peripheral (including listed below others) requests core modifications.
Program Memory space Internal Data Memory space External Data Memory space External Data Memory Wait States Power Management Unit Interface additional SFRs Program Memory Wait States
Architecture speed grade
Compare/Capture
Interrupt sources
Stack space size
Timer/Counters
Interrupt levels
Master Controller Slave Controller
Design
DR8051CPU DR8051 DR8051XP
DR8051 family High Performance Microcontroller Cores
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Fixed Point Coprocessor Floating Point Coprocessor
Data Pointers
Watchdog
Ports
UART
CONTACTS
modification special request please contact Digital Core Design local distributors. Headquarters: Wroclawska 41-902 Bytom, POLAND e-mail: iinffo@dcd.pll o@dcd tel.
Field Office: Texas Research Park 14815 Omicron suite Antonio, 78245,USA e-mail: iinffoUS@dcd.pll oUS@dcd tel. 8268 7511
Distributors: Micro Tech Components GmbH Reitweg 89407 Dillingen, GERMANY
e-mail MTCiinffo@mttc.de
tel. 9071 7945-0 9071 7945-20 Territory: Germany, Austria, Switzerland
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Copyright 1999-2003 Digital Core Design. Rights Reserved.

DR8051CPU high performance, area optimized soft core single-chip 8-bit

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