Quad 2-Input Exclusive-OR Gate CD74AC86 'ACT86 quad 2-input Exclu

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Quad 2-Input Exclusive-OR Gate CD74AC86 'ACT86 quad 2-input Exclu

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CD74AC86, CD54/74ACT86
Quad 2-Input Exclusive-OR Gate
CD74AC86 'ACT86 quad 2-input Exclusive-OR gates that utilize Advanced CMOS Logic technology
September 1998 Revised 2000
/Title (CD74 AC86, CD74 ACT86 /Subject (Quad 2-Input ExclusiveOR Gate) /Autho /Keywords (Harris Semiconductor, Advan CMOS Harris Semiconductor, Advan TTL) /Creator /DOCI pdf-
Features
Buffered Inputs Typical Propagation Delay 3.2ns 25oC, 50pF Exceeds Protection MIL-STD-883, Method 3015 SCR-Latchup-Resistant CMOS Process Circuit Design Speed Bipolar FASTTM/AS/S with Significantly Reduced Power Consumption Balanced Propagation Delays Types Feature 1.5V 5.5V Operation Balanced Noise Immunity Supply ±24mA Output Drive Current Fanout FASTICs Drives Transmission Lines
Ordering Information
PART NUMBER CD74AC86E CD74AC86M CD54ACT86F3A CD74ACT86E CD74ACT86M NOTES: When ordering, entire part number. suffix obtain variant tape reel. Wafer this part number available which meets electrical specifications. Please contact your local sales office customer service ordering information. TEMP. RANGE (oC) 70oC, 70oC, 70oC, 70oC, SOIC SOIC CERDIP PDIP PACKAGE PDIP
Pinout
CD54ACT86 (CERDIP) CD74AC86, CD74ACT86 (PDIP, SOIC) VIEW
Functional Diagram
TRUTH TABLE INPUTS
CAUTION: These devices sensitive electrostatic discharge. Users should follow proper Handling Procedures. FASTis Trademark Fairchild Semiconductor. Copyright 2000, Texas Instruments Incorporated
OUTPUT
CD74AC86, CD54/74ACT86
Absolute Maximum Ratings
Supply Voltage, -0.5V Input Diode Current, -0.5V 0.5V .±20mA Output Diode Current, -0.5V 0.5V .±50mA Output Source Sink Current Output Pin, -0.5V 0.5V .±50mA Ground Current, IGND (Note .±100mA
Thermal Information
Thermal Resistance (Typical, Note (oC/W) PDIP Package SOIC Package Maximum Junction Temperature (Plastic Package) 150oC Maximum Storage Temperature Range .-65oC 150oC Maximum Lead Temperature (Soldering 10s) 300oC
Operating Conditions
Temperature Range, -55oC 125oC Supply Voltage Range, (Note .4.5V 5.5V Input Output Voltage, Input Rise Fall Slew Rate, dt/dv 4.5V 5.5V 10ns (Max)
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
NOTES: outputs device, ±25mA each additional output. Unless otherwise specified, voltages referenced ground. measured with component mounted evaluation board free air.
Electrical Specifications
TEST CONDITIONS PARAMETER TYPES High Level Input Voltage Level Input Voltage High Level Output Voltage -0.05 -0.05 -0.05 (Note (Note Level Output Voltage 0.05 0.05 0.05 (Note (Note 3.85 2.58 3.94 1.65 0.36 0.36 3.85 2.48 3.85 1.65 0.44 0.44 1.65 3.85 3.85 1.65 1.65 SYMBOL (mA) 25oC -40oC 85oC -55oC 125oC UNITS
CD74AC86, CD54/74ACT86
Electrical Specifications
(Continued) TEST CONDITIONS PARAMETER Input Leakage Current Quiescent Supply Current, TYPES High Level Input Voltage Level Input Voltage High Level Output Voltage -0.05 (Note (Note Level Output Voltage 0.05 (Note (Note Input Leakage Current Quiescent Supply Current, Additional Supply Current Input Inputs High Unit Load NOTES: Test output time 1-second maximum duration. Measurement made forcing current measuring voltage minimize power dissipation. Test verifies minimum transmission-line-drive capability 85oC, 125oC. -2.1 3.94 0.36 ±0.1 3.85 0.44 1.65 3.85 1.65 SYMBOL (mA) 25oC ±0.1 -40oC 85oC -55oC 125oC UNITS
Input Load Table
INPUT UNIT LOAD 0.48
NOTE: Unit load limit specified Electrical Specifications Table, e.g., 2.4mA 25oC.
Switching Specifications Input 3ns, 50pF (Worst Case)
-40oC 85oC PARAMETER TYPES Propagation Delay, Input Output tPHL, tPLH (Note (Note 13.7 15.1 10.8 SYMBOL -55oC 125oC UNITS
CD74AC86, CD54/74ACT86
Switching Specifications Input 3ns, 50pF (Worst Case)
PARAMETER Input Capacitance Power Dissipation Capacitance TYPES Propagation Delay, Input Output Input Capacitance Power Dissipation Capacitance NOTES: Limits tested 100%. 3.3V 3.6V, 5.5V, 4.5V. used determine dynamic power consumption gate. VCC2 (CPD ACT: VCC2 (CPD where input frequency, output load capacitance, supply voltage. tPHL, tPLH (Note (Note 13.3 14.6 SYMBOL (Note (Continued) -55oC 125oC UNITS
-40oC 85oC
OUTPUT (NOTE) tPLH tPHL OUTPUT OUTPUT LOAD 50pF
NOTE: Series Only: When 1.5V, Input Level Input Switching Voltage, Output Switching Voltage, 1.5V
FIGURE FIGURE PROPAGATION DELAY TIMES
IMPORTANT NOTICE Texas Instruments subsidiaries (TI) reserve right make changes their products discontinue product service without notice, advise customers obtain latest version relevant information verify, before placing orders, that information being relied current complete. products sold subject terms conditions sale supplied time order acknowledgment, including those pertaining warranty, patent infringement, limitation liability. warrants performance semiconductor products specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques utilized extent deems necessary support this warranty. Specific testing parameters each device necessarily performed, except those mandated government requirements. Customers responsible their applications using components. order minimize risks associated with customer's applications, adequate design operating safeguards must provided customer minimize inherent procedural hazards. assumes liability applications assistance customer product design. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right covering relating combination, machine, process which such semiconductor products services might used. TI's publication information regarding third party's products services does constitute TI's approval, warranty endorsement thereof.
Copyright 2000, Texas Instruments Incorporated

Quad 2-Input Exclusive-OR Gate CD74AC86 'ACT86 quad 2-input Exclu

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