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MC74HC161A HC163A identical pinout LS161 LS163. device inputs compatib


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MC74HC161A, MC74HC163A Presettable Counters
MC74HC161A HC163A identical pinout LS161 LS163. device inputs compatible with standard CMOS outputs; with pull-up resistors, they compatible with LSTTL outputs. HC161A HC163A programmable 4-bit binary counters with asynchronous synchronous reset, respectively.
Output Drive Capability: LSTTL Loads Outputs Directly Interface CMOS, NMOS, Operating Voltage Range: Input Current: High Noise Immunity Characteristic CMOS Devices Compliance with Requirements Defined JEDEC Standard Chip Complexity: FETs Equivalent Gates
MC74HC16xAN AWLYYWW
PDIP-16 SUFFIX CASE
HC16xA AWLYWW
RESET CLOCK ENABLE
RIPPLE CARRY ENABLE LOAD
SO-16 SUFFIX CASE 751B
TSSOP-16 SUFFIX CASE 948F
16xA ALYW
Figure Assignment
Assembly Location Wafer Year Work Week
FUNCTION TABLE
Inputs Clock Reset* Load Enable Enable Output Reset Load Preset Data Count Count Count
ORDERING INFORMATION
Device MC74HC161AN MC74HC161AD MC74HC161ADR2 MC74HC161ADT MC74HC161ADTR2 MC74HC163AN MC74HC163AD MC74HC163ADR2 MC74HC163ADT MC74HC163ADTR2 Package PDIP-16 SOIC-16 SOIC-16 TSSOP-16 TSSOP-16 PDIP-16 SOIC-16 SOIC-16 TSSOP-16 TSSOP-16 Shipping 2000/Box 48/Rail 2500/Reel 96/Rail 2500/Reel 2000/Box 48/Rail 2500/Reel 96/Rail 2500/Reel
*HC163A only. HC161A Asynchronous Reset Device high level, level, don't care
Semiconductor Components Industries, LLC, 2001
June, 2001 Rev.
Publication Order Number: MC74HC161A/D
MC74HC161A, MC74HC163A
PRESET DATA INPUTS
RIPPLE CARRY BINARY OUTPUT
CLOCK
RESET LOAD COUNT ENABLES ENABLE ENABLE
Figure Logic Diagram
DEVICE/MODE TABLE
Count Mode Binary Binary Device Reset Mode HC161A HC163A Asynchronous Synchronous
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MC74HC161A, MC74HC163A
MAXIMUM RATINGS (Note
Symbol IGND TSTG Supply Voltage Input Voltage Output Voltage Input Diode Current Output Diode Current Output Sink Current Supply Current Supply Ground Current Ground Storage Temperature Range Lead Temperature, from Case Seconds Junction Temperature Under Bias Thermal Resistance PDIP SOIC TSSOP PDIP SOIC TSSOP (Note Parameter Value *0.5 )7.0 *0.5 )0.5 *0.5 )0.5 )150 )150 Level Oxygen Index: Human Body Model (Note Machine Model (Note Charged Device Model (Note Above Below 85_C (Note UL-94-VO (0.125 u2000 u200 u1000 $300 Unit _C/W
Power Dissipation Still 85_C
VESD
Moisture Sensitivity Flammability Rating Withstand Voltage
ILATCH-UP
Latch-Up Performance
Absolute maximum continuous ratings those values beyond which damage device occur. Extended exposure these conditions conditions beyond those indicated adversely affect device reliability. Functional operation under absolute maximum-rated conditions implied. absolute maximum rating must observed. Tested EIA/JESD22-A114-A. Tested EIA/JESD22-A115-A. Tested JESD22-C101-A. Tested EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol Supply Voltage Parameter (Referenced GND) Unit
Vin, Vout Input Voltage, Output Voltage (Referenced GND) Operating Temperature, Package Types Input Rise Fall Time (Figure )125 1000 Unused inputs left open. inputs must tied high- low-logic input voltage level.
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Information typical parametric values found Semiconductor High-Speed CMOS Data Book (DL129/D).
ELECTRICAL CHARACTERISTICS (Voltages Referenced GND)
Symbol
Maximum Quiescent Supply Current
Maximum Input Leakage Current
Maximum Low-Level Output Voltage
Minimum High-Level Output Voltage
Maximum Low-Level Input Voltage
Minimum High-Level Input Voltage
Parameter
|Iout|
|Iout|
Iout
|Iout| |Iout| |Iout|
|Iout| |Iout| |Iout|
Vout |Iout|
Vout |Iout|
MC74HC161A, MC74HC163A
Test Conditions
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25_C 1.35 3.15 0.26 0.26 0.26 2.48 3.98 5.48 Guaranteed Limit 85_C 1.35 3.15 0.33 0.33 0.33 2.34 3.84 5.34 125_C 1.35 3.15 Unit
ELECTRICAL CHARACTERISTICS Input
Symbol tTLH, tTHL tPHL tPHL tPLH tPHL tPLH tPHL tPHL tPLH fmax Maximum Input Capacitance Maximum Output Transition Time, Output Maximum Propagation Delay, Reset Ripple Carry (HC161A Only) Maximum Propagation Delay, Clock Ripple Carry Maximum Propagation Delay, Enable Ripple Carry Maximum Propagation Delay, Reset (HC161A Only) Maximum Propagation Delay, Clock Maximum Clock Frequency (50% Duty Cycle) (Note Parameter
propagation delays with loads other than information typical parametric values, Semiconductor High-Speed CMOS Data Book (DL129/D).
Power Dissipation Capacitance (Per Gate) (Note 11.) Used determine no-load dynamic power consumption: load considerations, Semiconductor High-Speed CMOS Data Book (DL129/D).
Applies noncascaded/nonsynchronous clocked configurations only with synchronously cascaded counters. Clock Ripple Carry propagation delays. Enable Enable Clock setup times Clock Enable Enable hold times determine fmax. However, Ripple Carry each stage tied Clock next stage (nonsynchronously clocked) fmax table above applicable. Applications information this data sheet.
MC74HC161A, MC74HC163A
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Figure 25_C Typical 25°C, Guaranteed Limit 85_C 125_C Unit
TIMING REQUIREMENTS Input
Symbol trec trec Maximum Input Rise Fall Times Minimum Pulse Width, Reset (HC161A Only) Minimum Pulse Width, Clock Minimum Recovery Time, Load Inactive Clock Minimum Recovery Time, Reset Inactive Clock (HC161A Only) Minimum Hold Time, Clock Enable Enable Minimum Hold Time, Clock Reset (HC163A Only) Minimum Hold Time, Clock Load Preset Data Inputs Minimum Setup Time, Enable Enable Clock Minimum Setup Time, Reset Clock (HC163A Only) Minimum Setup Time, Load Clock Minimum Setup Time, Preset Data Inputs Clock Parameter
MC74HC161A, MC74HC163A
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Figure 25_C 1000 Guaranteed Limit 85_C 1000 125_C 1000 Unit
MC74HC161A, MC74HC163A
FUNCTION DESCRIPTION HC161A/163A programmable 4-bit synchronous counters that feature parallel Load, synchronous asynchronous Reset, Carry Output cascading, count-enable controls. HC161A HC163A binary counters with asynchronous Reset synchronous Reset, respectively.
INPUTS Clock (Pin CONTROL FUNCTIONS Resetting
level Reset (Pin resets internal flip-flops sets outputs through level. HC161A resets asynchronously, HC163A resets with rising edge Clock input (synchronous reset).
Loading
internal flip-flops toggle output count advances with rising edge Clock input. addition, control functions, such resetting loading, occur with rising edge Clock input.
Preset Data Inputs (Pins
With rising edge Clock, level Load (Pin loads data from Preset Data input pins (P0, into internal flip-flops onto output pins, through count function disabled long Load low.
Count Enable/Disable
These data inputs programmable counting. Data these pins synchronously loaded into internal flip-flops appear counter outputs. (Pin least-significant (Pin most-significant bit.
OUTPUTS (Pins
These devices have count-enable control pins: Enable (Pin Enable (Pin 10). devices count when these pins Load high. logic equation
Count Enable Enable Enable Load
These counter outputs. (Pin least-significant (Pin most-significant bit.
Ripple Carry (Pin
count either enabled disabled control inputs according Table general, Enable count-enable control: Enable both count-enable Ripple-Carry Output control.
Table Count Enable/Disable
Control Inputs Load Enable Enable Result Outputs Count Count Count Count High when Q0-Q3 maximum* High when Q0-Q3 maximum* Ripple Carry
When counter maximum state, 1111, this output goes high, providing external look-ahead carry pulse that used enable successive cascaded counters. Ripple Carry remains high only during maximum count state. logic equation this output
Ripple Carry Enable
OUTPUT STATE DIAGRAMS
through maximum when 1111.
Figure Binary Counters
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MC74HC161A, MC74HC163A
SWITCHING WAVEFORMS
1/fmax tPLH tPHL OUTPUT tTLH tTHL OUTPUT CLOCK RESET tPHL trec
CLOCK
Figure
Figure
ENABLE
tPHL CLOCK tTHL RESET
tPLH RIPPLE CARRY tTLH
Figure
Figure HC163A Only
VALID INPUTS LOAD CLOCK trec CLOCK ENABLE ENABLE VALID
Figure
Figure
TEST CIRCUIT
TEST POINT OUTPUT DEVICE UNDER TEST
*Includes probe capacitance
Figure http://onsemi.com
LOAD LOAD
Figure 4-Bit Binary Counter with Asynchronous Reset (MC74HC161A)
LOAD LOAD LOAD LOAD
MC74HC161A, MC74HC163A
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LOAD LOAD
ENABLE
VCC= LOAD LOAD
RIPPLE CARRY
ENABLE RESET
LOAD CLOCK
flip-flops shown circuit diagrams Toggle-Enable flip-flops. Toggle- Enable flip-flop combination flip-flop flip-flop. When loading data from Preset inputs Load signal used disable Toggle input (Tn) flip-flop. logic level input then clocked output flip-flop next rising edge clock. logic zero Reset device input forces internal clock high resets output flip-flop low.
MC74HC161A, MC74HC163A
Sequence illustrated waveforms: Reset outputs zero. Preset binary twelve. Count thirteen, fourteen, fifteen, zero, two. Inhibit. RESET (HC161A) RESET (HC163A) LOAD
(ASYNCHRONOUS) (SYNCHRONOUS)
PRESET DATA INPUTS CLOCK (HC161A) CLOCK (HC163A)
COUNT ENABLES
ENABLE ENABLE
OUTPUTS RIPPLE CARRY RESET
LOAD
INHIBIT
COUNT
Figure Timing Diagram
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LOAD LOAD
Figure 4-Bit Binary Counter with Synchronous Reset (MC74HC163A)
LOAD LOAD LOAD LOAD
MC74HC161A, MC74HC163A
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LOAD LOAD
ENABLE
VCC= LOAD LOAD
RIPPLE CARRY
ENABLE RESET
LOAD CLOCK
flip-flops shown circuit diagrams Toggle-Enable flip-flops. Toggle- Enable flip-flop combination flip-flop flip-flop. When loading data from Preset inputs Load signal used disable Toggle input (Tn) flip-flop. logic level input then clocked output flip-flop next rising edge clock. logic zero Reset device input forces internal clock high resets output flip-flop low.
MC74HC161A, MC74HC163A
TYPICAL APPLICATIONS CASCADING
LOAD INPUTS INPUTS INPUTS
LOAD COUNT DISABLE COUNT DISABLE ENABLE RIPPLE ENABLE CARRY CLOCK RESET OUTPUTS CLOCK
LOAD ENABLE RIPPLE ENABLE CARRY CLOCK
LOAD ENABLE RIPPLE ENABLE CARRY CLOCK MORE SIGNIFICANT STAGES
OUTPUTS
OUTPUTS
NOTE: When used these cascaded configurations clock fmax guaranteed limits apply. Actual performance will depend number stages. This limitation times between Enable (Port) Clock.
Figure N-Bit Synchronous Counters
INPUTS
INPUTS
INPUTS
LOAD ENABLE ENABLE LOAD ENABLE RIPPLE ENABLE CARRY CLOCK CLOCK RESET LOAD ENABLE RIPPLE ENABLE CARRY CLOCK LOAD ENABLE RIPPLE ENABLE CARRY CLOCK MORE SIGNIFICANT STAGES
OUTPUTS
OUTPUTS
OUTPUTS
Figure Nibble Ripple Counter http://onsemi.com
MC74HC161A, MC74HC163A
TYPICAL APPLICATIONS VARYING MODULUS
HC163A OTHER INPUTS OPTIONAL BUFFER NOISE REJECTION
HC163A OTHER INPUTS RESET OPTIONAL BUFFER NOISE REJECTION OUTPUT
OUTPUT
RESET
Figure Modulo-5 Counter
Figure Modulo-11 Counter
HC163A facilitates designing counters modulus with minimal external logic. output glitch-free synchronous Reset.
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MC74HC161A, MC74HC163A
PACKAGE DIMENSIONS
PDIP-16 SUFFIX CASE 648-08 ISSUE
NOTES: DIMENSIONING TOLERANCING ANSI Y14.5M, 1982. CONTROLLING DIMENSION: INCH. DIMENSION CENTER LEADS WHEN FORMED PARALLEL. DIMENSION DOES INCLUDE MOLD FLASH. ROUNDED CORNERS OPTIONAL. INCHES 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 0.050 0.008 0.015 0.110 0.130 0.295 0.305 0.020 0.040 MILLIMETERS 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 1.27 0.21 0.38 2.80 3.30 7.50 7.74 0.51 1.01
SEATING PLANE
0.25 (0.010)
SUFFIX SOIC CASE 751B-05 ISSUE
NOTES: DIMENSIONING TOLERANCING ANSI Y14.5M, 1982. CONTROLLING DIMENSION: MILLIMETER. DIMENSIONS INCLUDE MOLD PROTRUSION. MAXIMUM MOLD PROTRUSION 0.15 (0.006) SIDE. DIMENSION DOES INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL 0.127 (0.005) TOTAL EXCESS DIMENSION MAXIMUM MATERIAL CONDITION. MILLIMETERS 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 0.19 0.25 0.10 0.25 5.80 6.20 0.25 0.50 INCHES 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 0.008 0.009 0.004 0.009 0.229 0.244 0.010 0.019
0.25 (0.010)
SEATING PLANE
0.25 (0.010)
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MC74HC161A, MC74HC163A
PACKAGE DIMENSIONS
TSSOP-16 SUFFIX CASE 948F-01 ISSUE
0.10 (0.004) 0.15 (0.006)
IDENT.
SECTION
0.15 (0.006)
0.25 (0.010)
DETAIL
NOTES: DIMENSIONING TOLERANCING ANSI Y14.5M, 1982. CONTROLLING DIMENSION: MILLIMETER. DIMENSION DOES INCLUDE MOLD FLASH. PROTRUSIONS GATE BURRS. MOLD FLASH GATE BURRS SHALL EXCEED 0.15 (0.006) SIDE. DIMENSION DOES INCLUDE INTERLEAD FLASH PROTRUSION. INTERLEAD FLASH PROTRUSION SHALL EXCEED 0.25 (0.010) SIDE. DIMENSION DOES INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL 0.08 (0.003) TOTAL EXCESS DIMENSION MAXIMUM MATERIAL CONDITION. TERMINAL NUMBERS SHOWN REFERENCE ONLY. DIMENSION DETERMINED DATUM PLANE -W-. MILLIMETERS 4.90 5.10 4.30 4.50 -1.20 0.05 0.15 0.50 0.75 0.65 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 INCHES 0.193 0.200 0.169 0.177 -0.047 0.002 0.006 0.020 0.030 0.026 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252
0.10 (0.004) SEATING
PLANE
DETAIL
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MC74HC161A, MC74HC163A
Semiconductor trademarks Semiconductor Components Industries, (SCILLC). SCILLC reserves right make changes without further notice products herein. SCILLC makes warranty, representation guarantee regarding suitability products particular purpose, does SCILLC assume liability arising application product circuit, specifically disclaims liability, including without limitation special, consequential incidental damages. "Typical" parameters which provided SCILLC data sheets and/or specifications vary different applications actual performance vary over time. operating parameters, including "Typicals" must validated each customer application customer's technical experts. SCILLC does convey license under patent rights rights others. SCILLC products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure SCILLC product could create situation where personal injury death occur. Should Buyer purchase SCILLC products such unintended unauthorized application, Buyer shall indemnify hold SCILLC officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that SCILLC negligent regarding design manufacture part. SCILLC Equal Opportunity/Affirmative Action Employer.
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MC74HC161A/D

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