2.7V 3.3V Read/Write Access Time Sector Erase Architecture Sixty-

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2.7V 3.3V Read/Write Access Time Sector Erase Architecture Sixty-

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32-Mbit Flash 4-Mbit/8-Mbit SRAM Single 66-ball CBGA Package 2.7V 3.3V Operating Voltage
2.7V 3.3V Read/Write Access Time Sector Erase Architecture
Sixty-three Word (64K Byte) Sectors with Individual Write Lockout Eight Word Byte) Sectors with Individual Write Lockout Fast Word Program Time Fast Sector Erase Time Suspend/Resume Feature Erase Program Supports Reading Programming from Sector Suspending Erase Different Sector Supports Reading Word Suspending Programming Other Word Low-power Operation Active Standby Data Polling, Toggle Bit, Ready/Busy Program Detection Write Protection Accelerated Program/Erase Operations RESET Input Device Initialization Sector Lockdown Support Bottom Boot Block Configuration Available 128-bit Protection Register
32-megabit Flash 4-megabit/ 8-megabit SRAM Stack Memory AT52BR3224 AT52BR3224T AT52BR3228 AT52BR3228T Preliminary
SRAM
4-megabit (256K 16)/8-megabit (512K 2.7V 3.3V Access Time Fully Static Operation Tri-state Output 1.2V (Min) Data Retention Industrial Temperature Range
Device Number AT52BR3224 AT52BR3224T AT52BR3228 AT52BR3228T
Flash Boot Location Bottom Bottom
Flash Plane Architecture
SRAM Configuration 256K 256K 512K 512K
Rev. 1682A-10/01
Configurations
Name
RESET RDY/BUSY I/O0 I/O15 SVCC SGND SCS1 SCS2
AT52BR3224(T)/3228(T) (Top View)
Function
Flash/SRAM Common Address Input Flash Address Input Flash Chip Enable Flash Output Enable Flash Write Enablee Flash Reset Flash READY/BUSY Output Flash Power Supply Accelerated Program/Erase Operations Flash Power Flash Ground Data Inputs/Outputs Connect SRAM Lower Byte SRAM Upper Byte SRAM Power SRAM Ground SRAM Chip Select SRAM Chip Select SRAM Write Enable SRAM Output Enable
I/O7 I/O5
I/O15 I/O14 I/O13 I/O6 I/O4
RDY/BUSY
SGND I/O12 SCS2 SVCC I/O11 I/O9 I/O10 I/O8 I/O2 I/O0 I/O3 I/O1 SCS1
AT52BR3224(T)/3228(T)
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AT52BR3224(T)/3228(T)
Block Diagram
ADDRESS
RDY/BUSY
32-Mbit FLASH
4/8-Mbit SRAM
SCS1 SCS2
DATA
Description
AT52BR3224(T) combines 32-megabit Flash 4-megabit SRAM (organized 256K stacked 66-ball CBGA package. AT52BR3228(T) combines 32-megabit Flash 8-megabit SRAM (organized 512K stacked 66-ball CBGA package. stacked modules operate 2.7V 3.3V industrial temperature range.
Absolute Maximum Ratings
Temperature under Bias -40°C +85°C Storage Temperature -55°C +150°C Input Voltages except RESET (including Pins) with Respect Ground .-0.2V +3.3V Voltage with Respect Ground .-0.2V 6.25V Voltage RESET with Respect Ground .-0.2V +13.5V Output Voltages with Respect Ground .-0.2V +0.2V *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions beyond those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
Operating Range
AT52BR3224(T)/3228(T)-85 Operating Temperature (Case) Power Supply Industrial -40°C 85°C 2.7V 3.3V
1682A-10/01
32-megabit Flash Description
32-megabit Flash memory organized 2,097,152 words bits each. data appears I/O0 I/O15. memory divided into sectors erase operations. device features control signals avoid contention. This device read reprogrammed using single power supply, making ideally suited in-system programming. device powers read mode. Command sequences used place device other operation modes such program erase. device capability protect data sector (see "Sector Lockdown" section). increase flexibility device, contains Erase Suspend Program Suspend feature. This feature will erase program hold amount time user read data from program data remaining sectors within memory. program erase cycle detected READY/BUSY pin, Data Polling toggle bit. provides data protection faster programming. When input below 0.8V, program erase functions inhibited. When 1.65V above, normal program erase operations performed. With 5.0V 12.0V, program erase operations accelerated. six-byte command (Enter Single Pulse Program Mode) sequence remove requirement entering three-byte program sequence offered further improve programming time. After entering six-byte code, only single pulses write control lines required writing into device. This mode (Single Pulse Byte/Word Program) exited powering down device, pulsing RESET minimum then bringing back VCC. Erase, Erase Suspend/Resume Program Suspend/Resume commands will work while this mode; entered they will result data being programmed into device. recommended that six-byte code reside software final product only exist external programming code.
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32-megabit Flash Memory Block Diagram
I/O0 I/O15
OUTPUT BUFFER
INPUT BUFFER
OUTPUT MULTIPLEXER
INPUT BUFFER
STATUS REGISTER
DATA REGISTER
IDENTIFIER REGISTER
COMMAND REGISTER RESET
ADDRESS LATCH DATA COMPARATOR
RDY/BUSY WRITE STATE MACHINE
Y-DECODER
Y-GATING
PROGRAM/ERASE VOLTAGE SWITCH
X-DECODER
MAIN MEMORY
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Device Operation
READ: 32-megabit Flash accessed like EPROM. When high, data stored memory location determined address pins asserted outputs. outputs high impedance state whenever high. This dual-line control gives designers flexibility preventing contention. COMMAND SEQUENCES: When device first powered will reset read standby mode, depending upon state control line inputs. order perform other device functions, series command sequences entered into device. command sequences shown "Command Definition Hex" table page (I/O8 I/O15 don't care inputs command codes). command sequences written applying pulse input with (respectively) high. address latched falling edge whichever occurs last. data latched first rising edge Standard microprocessor write timings used. address locations used command sequences affected entering command sequences. RESET: RESET input provided ease some system applications. When RESET logic high level, device standard operating mode. level RESET input halts present device operation puts outputs device high impedance state. When high level reasserted RESET pin, device returns read standby mode, depending upon state control inputs. ERASURE: Before word reprogrammed, must erased. erased state memory bits logical "1". entire device erased using Chip Erase command individual sectors erased using Sector Erase command. CHIP ERASE: entire device erased time using six-byte chip erase software code. After chip erase been initiated, device will internally time erase operation that external clocks required. maximum time erase chip tEC. sector lockdown been enabled, chip erase will erase data sector that been locked out; will erase only unprotected sectors. After chip erase, device will return read standby mode. SECTOR ERASE: alternative full chip erase, device organized into sectors (SA0 SA70) that individually erased. Sector Erase command six-bus cycle operation. sector address latched falling edge sixth cycle while data input command latched rising edge sector erase starts after rising edge sixth cycle. erase operation internally controlled; will automatically time completion. maximum time erase sector tSEC. When sector programming lockdown feature enabled, sector will erase (from same Sector Erase command). attempt erase sector that been protected will result operation terminating WORD PROGRAMMING: Once memory block erased, programmed logical "0") word-by-word basis. Programming accomplished internal device command register four-bus cycle operation. device will automatically generate required internal program pulses. commands written chip during embedded programming cycle will ignored. hardware reset happens during programming, data location being programmed will corrupted. Please note that data cannot programmed back "1"; only erase operations convert "0"s "1"s. Programming completed after specified cycle time. Data Polling feature Toggle feature
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used indicate program cycle. erase/program status "1", device able verify that erase program operation performed successfully. PIN: circuitry 32-megabit Flash designed that device programmed erased from power supply from input pin. When greater than 1.65V less than equal pin, device selects supply programming erase operations. When greater than supply, device will select input power supply programming erase operations. device will allow some variations between input power supply selection program erase operations. within 0.3V 2.65V 3.6V, then program erase operations will disregard input signal. When signal used program erase operations, must 0.5V 0.5V range ensure proper operation. cannot left floating. PROGRAM/ERASE STATUS: device provides several bits determine status program erase operation: I/O2, I/O3, I/O5, I/O6 I/O7. "Status Table" page following four sections describe function these bits. provide greater flexibility system designers, 32-megabit Flash contains programmable configuration register. configuration register allows user specify status operation. configuration register different values, "00" "01". configuration register "00", part will automatically return read mode after successful program erase operation. configuration register "01", Product Exit command must given after successful program erase operation before part will return read mode. important note that whether configuration register "00" "01", unsuccessful program erase operation requires using Product Exit command return device read mode. default value (after power-up) configuration register "00". Using four-bus cycle Configuration Register command shown "Command Definition Hex" table page value configuration register changed. Voltages applied RESET will alter value configuration register. value configuration register will affect operation I/O7 status described below. DATA POLLING: 32-megabit Flash features Data Polling indicate program cycle. status configuration register "00", during program cycle attempted read last word loaded will result complement loaded data I/O7. Once program cycle been completed, true data valid outputs next cycle begin. During chip sector erase operation, attempt read device will give I/O7. Once program erase cycle completed, true data will read from device. Data Polling begin time during program cycle. Please "Status Table" page more details. status configuration register "01", I/O7 status will while device actively programming erasing data. I/O7 will high when device completed program erase operation. Once I/O7 gone high, status information other pins checked. Data Polling status must used conjunction with erase/program status shown algorithm Figures page TOGGLE BIT: addition Data Polling 32-megabit Flash provides another method determining program erase cycle. During program erase operation, successive attempts read data from memory will result I/O6 toggling between zero. Once program cycle completed, I/O6 will stop toggling
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valid data will read. Examining toggle begin time during program cycle. Please "Status Table" page more details. toggle status should used conjunction with erase/program status shown algorithm Figures page ERASE/PROGRAM STATUS BIT: device offers status I/O5, which indicates whether program erase operation exceeded specified internal pulse count limit. status "1", device unable verify that erase word program operation been successfully performed. device also output I/O5 system tries program location that previously programmed "0". Only erase operation change back "1". program (Sector Erase) command issued protected sector, protected sector will programmed (erased). device will status read mode I/O5 status will high, indicating program (erase) operation complete requested. Once erase/program status been "1", system must write Product Exit command return read mode. erase/program status while erase program operation still progress. Please "Status Table" page more details. STATUS BIT: 32-megabit Flash provides status I/O3, which provides information regarding voltage level pin. During program erase operation, voltage high enough perform desired operation successfully, I/O3 status will "1". Once status been "1", system must write Product Exit command return read mode. other hand, voltage level high enough perform program erase operation successfully, status will output "0". Please "Status Table" page more details. SECTOR LOCKDOWN: Each sector programming lockdown feature. This feature prevents programming data designated sectors once feature been enabled. These sectors contain secure code that used bring system. Enabling lockdown feature will allow boot code stay device while data rest device updated. This feature does have activated; sector's usage write-protected region optional user. power-up reset, sectors unlocked. activate lockdown specific sector, six-bus cycle Sector Lockdown command must issued. Once sector been locked down, contents sector read-only cannot erased programmed. SECTOR LOCKDOWN DETECTION: software method available determine programming sector locked down. When device software product identification mode (see "Software Product Identification Entry/Exit" sections page 27), read from address location 00002H within sector will show programming sector locked down. data I/O0 low, sector programmed; data I/O0 high, program lockdown feature been enabled sector cannot programmed. software product identification exit code should used return standard operation. SECTOR LOCKDOWN OVERRIDE: only unlock sector that locked down through reset power-up cycles. After power-up reset, content sector that locked down erased reprogrammed. ERASE SUSPEND/ERASE RESUME: Erase Suspend command allows system interrupt sector chip erase operation then program read data from different sector within memory. After Erase Suspend command given, device requires maximum time suspend erase operation. After
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erase operation been suspended, system then read data program data other sector within device. address required during Erase Suspend command. During sector erase suspend, another sector cannot erased. resume sector erase operation, system must write Erase Resume command. Erase Resume command one-bus cycle command. device also supports erase suspend during complete chip erase. While chip erase suspended, user read from sector within memory that protected. command sequence chip erase suspend sector erase suspend same. PROGRAM SUSPEND/PROGRAM RESUME: Program Suspend command allows system interrupt programming operation then read data from different word within memory. After Program Suspend command given, device requires maximum suspend programming operation. After programming operation been suspended, system then read data from other word within device. address required during program suspend operation. resume programming operation, system must write Program Resume command. program suspend resume one-bus cycle commands. command sequence erase suspend program suspend same, command sequence erase resume program resume same. PRODUCT IDENTIFICATION: product identification mode identifies device manufacturer Atmel. accessed hardware software operation. hardware operation mode used external programmer identify correct programming algorithm Atmel product. details, "Operating Modes" page (for hardware operation) "Software Product Identification Entry/Exit" sections page manufacturer device codes same both modes. 128-BIT PROTECTION REGISTER: 32-megabit Flash contains 128-bit register that used security purposes system design. protection register divided into 64-bit blocks. blocks designated block block data block non-changeable programmed factory with unique number. data block programmed user locked such that data block cannot reprogrammed. program block protection register, four-bus cycle Program Protection Register command must used shown "Command Definition Hex" table page lock block four-bus cycle Lock Protection Register command must used shown "Command Definition Hex" table. Data must zero during fourth cycle. other data bits during fourth cycle don't cares. determine whether block locked out, Product Entry command given followed read operation from address 80H. data zero, block locked. data one, block reprogrammed. Please "Protection Register Addressing Table" page address locations protection register. read protection register, Product Entry command given followed normal read operation from address within protection register. After determining whether block protected not, reading protection register, Product Exit command must given prior performing other operation. RDY/BUSY: 32-megabit Flash, open-drain READY/BUSY output provides another method detecting program erase operation. RDY/BUSY actively pulled during internal program erase cycles released completion cycle. open-drain connection allows OR-tying several devices same RDY/BUSY line. Please "Status Table" page more details.
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HARDWARE DATA PROTECTION: Hardware Data Protection feature protects against inadvertent programs Flash following ways: sense: below 1.8V (typical), program function inhibited. power-on delay: once reached sense level, device will automatically time (typical) before programming. Program inhibit: holding low, high high inhibits program cycles. Noise filter: pulses less than (typical) inputs will initiate program cycle. Program inhibit: less than VILPP. power-on delay: once reached 1.65V, program erase operations inhibited INPUT LEVELS: While operating with 2.65V 3.6V power supply, address inputs control inputs (OE, driven from 5.5V without adversely affecting operation device. lines only driven from 0.6V. OUTPUT LEVELS: 32-megabit Flash, output high levels (VOH) equal VCCQ 0.2V (not VCC). 2.65V 3.6V output levels, VCCQ must tied VCC. 1.8V 2.2V output levels, VCCQ must regulated 2.0V 10%, while must regulated 2.65V 3.0V (for minimum power).
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Figure Data Polling Algorithm (Configuration Register Figure Data Polling Algorithm (Configuration Register
START
START
Read I/O7 I/O0 Addr
Read I/O7 I/O0 Addr
I/O7
I/O7 Data?
I/O3, I/O5
I/O3, I/O5
Read I/O7 I/O0 Addr
Program/Erase Operation Successful, Write Product Exit Command
Program/Erase Operation Successful, Write Product Exit Command
I/O7 Data?
Note:
Program/Erase Operation Successful, Write Product Exit Command Program/Erase Operation Successful, Device Read Mode
Valid address programming. During sector erase operation, valid address sector address within sector being erased. During chip erase, valid address non-protected sector address.
Notes:
Valid address programming. During sector erase operation, valid address sector address within sector being erased. During chip erase, valid address non-protected sector address. I/O7 should rechecked even I/O5 because I/O7 change simultaneously with I/O5.
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Figure Toggle Algorithm (Configuration Register
Figure Toggle Algorithm (Configuration Register
START
START
Read I/O7 I/O0
Read I/O7 I/O0
Read I/O7 I/O0
Read I/O7 I/O0
Toggle Toggle?
Toggle Toggle? I/O3, I/O5
I/O3, I/O5
Read I/O7 I/O0 Twice
Read I/O7 I/O0 Twice
Toggle Toggle? Program/Erase Operation Successful, Write Product Exit Command
Toggle Toggle?
Program/Erase Operation Successful
Program/Erase Operation Successful, Write Product Exit Command
Program/Erase Operation Successful, Write Product Exit Command
Note:
system should recheck toggle even I/O5 because toggle stop toggling I/O5 changes "1".
Note:
system should recheck toggle even I/O5 because toggle stop toggling I/O5 changes "1".
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AT52BR3224(T)/3228(T)
Status Table
Status I/O7 Configuration Register Programming Erasing Erase Suspended Read Erasing Sector Erase Suspended Read Non-erasing Sector Erase Suspended Program Non-erasing Sector Notes: I/O7 DATA I/O7 I/O7 DATA I/O6 00/01 TOGGLE TOGGLE DATA TOGGLE I/O5(1) 00/01 DATA I/O3(2) 00/01 DATA I/O2 00/01 TOGGLE TOGGLE DATA TOGGLE RDY/BUSY 00/01
I/O5 switches when program erase operation exceeded maximum time limits when program sector erase operation performed protected sector. I/O3 switches when level high enough successfully perform program erase operations.
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Command Definition Hex(1)
Command Sequence Read Chip Erase Sector Erase Word Program Enter Single Pulse Program Mode Single Pulse Word Program Sector Lockdown Erase/Program Suspend Erase/Program Resume Product Entry Product Exit
Cycles
Cycle Addr Addr Addr Data DOUT
Cycle Addr Data
Cycle Addr Data Addr
Cycle Data
Cycle Addr Data
Cycle Addr Data
AAA(2)
Addr
(3)(4)
AAA(2)
SA(3)(4)
Product Exit(5) Program Protection Register Lock Protection Register Block Status Block Protection Configuration Register
Addr
DOUT(6) 00/01(7)
Notes:
DATA FORMAT shown each cycle follows; I/O7 I/O0 (Hex). word operation I/O15 I/O8 don't care. ADDRESS FORMAT shown each cycle follows: (Hex). Address through don't care. Since Don't Care, replaced with 2AA. sector address. word address within sector used designate sector address (see pages details). Once sector lockdown mode, data protected sector cannot changed unless chip reset power cycled. Either Product Exit commands used. data "0", block locked. data "1", block reprogrammed. default state (after power-up) configuration register "00".
Absolute Maximum Ratings*
Temperature under Bias -55°C +125°C Storage Temperature -65°C +150°C Input Voltages (including Pins) with Respect Ground .-0.6V +6.25V Output Voltages with Respect Ground .-0.6V 0.6V Voltage with Respect Ground .-0.6V +13.0V *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions beyond those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
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AT52BR3224(T)/3228(T)
Protection Register Addressing Table
Word Note: Factory Factory Factory Factory User User User User Block
address lines specified above table must when accessing protection register, i.e.,
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Bottom Boot 32-megabit Flash Sector Address Table
Sector SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 Size (Words) Address Range (A20 00000 00FFF 01000 01FFF 02000 02FFF 03000 03FFF 04000 04FFF 05000 05FFF 06000 06FFF 07000 07FFF 08000 0FFFF 10000 17FFF 18000 1FFFF 20000 27FFF 28000 2FFFF 30000 37FFF 38000 3FFFF 40000 47FFF 48000 4FFFF 50000 57FFF 58000 5FFFF 60000 67FFF 68000 6FFFF 70000 77FFF 78000 7FFFF 80000 87FFF 88000 8FFFF 90000 97FFF 98000 9FFFF A0000 A7FFF A8000 AFFFF B0000 B7FFF B8000 BFFFF C0000 C7FFF C8000 CFFFF D0000 D7FFF D8000 DFFFF E0000 E7FFF
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Bottom Boot 32-megabit Flash Sector Address Table (Continued)
Sector SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 Size (Words) Address Range (A20 E8000 EFFFF F0000 F7FFF F8000 FFFFF 100000 107FFF 108000 10FFFF 110000 117FFF 118000 11FFFF 120000 127FFF 128000 12FFFF 130000 137FFF 138000 13FFFF 140000 147FFF 148000 14FFFF 150000 157FFF 158000 15FFFF 160000 167FFF 168000 16FFFF 170000 177FFF 178000 17FFFF 180000 187FFF 188000 18FFFF 190000 197FFF 198000 19FFFF 1A0000 1A7FFF 1A8000 1AFFFF 1B0000 1B7FFF 1B8000 1BFFFF 1C0000 1C7FFF 1C8000 1CFFFF 1D0000 1D7FFF 1D8000 1DFFFF 1E0000 1E7FFF 1E8000 1EFFFF 1F0000 -1F7FFF 1F8000 1FFFF
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Boot 32-megabit Flash Sector Address Table
Sector SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 Size (Words) Address Range (A20 00000 07FFF 08000 0FFFF 10000 17FFF 18000 1FFFF 20000 27FFF 28000 2FFFF 30000 37FFF 38000 3FFFF 40000 47FFF 48000 4FFFF 50000 57FFF 58000 5FFFF 60000 67FFF 68000 6FFFF 70000 77FFF 78000 7FFFF 80000 87FFF 88000 8FFFF 90000 97FFF 98000 9FFFF A0000 A7FFF A8000 AFFFF B0000 B7FFF B8000 BFFFF C0000 C7FFF C8000 CFFFF D0000 D7FFF D8000 DFFFF E0000 E7FFF E8000 EFFFF F0000 F7FFF F8000 FFFFF 100000 107FFF 108000 10FFFF 110000 117FFF 118000 11FFFF
SA35
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Boot 32-megabit Flash Sector Address Table (Continued)
Sector Size (Words) Address Range (A20 120000 127FFF 128000 12FFFF 130000 137FFF 138000 13FFFF 140000 147FFF 148000 14FFFF 150000 157FFF 158000 15FFFF 160000 167FFF 168000 16FFFF 170000 177FFF 178000 17FFFF 180000 187FFF 188000 18FFFF 190000 197FFF 198000 19FFFF 1A0000 1A7FFF 1A8000 1AFFFF 1B0000 1B7FFF 1B8000 1BFFFF 1C0000 1C7FFF 1C8000 1CFFFF 1D0000 1D7FFF 1D8000 1DFFFF 1E0000 1E7FFF 1E8000 1EFFFF 1F0000 1F7FFF 1F8000 1F8FFF 1F9000 1F9FFF 1FA000 1FAFFF 1FB000 1FBFFF 1FC000 1FCFFF 1FD000 1FDFFF 1FE000 1FEFFF 1FF000 1FFFFF
SA36
SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70
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Operating Range
AT52BR3224(T)-85 Operating Temperature (Case) Power Supply Industrial -40°C 85°C 2.7V 3.3V AT52BR3228(T)-85 -40°C 85°C 2.7V 3.3V
Operating Modes
Mode Read Program/Erase
RESET
VIHPP VILPP(7)
DOUT High-Z
Standby/Program Inhibit
Program Inhibit
Output Disable Reset Product Identification Hardware
High-Z High-Z
VIL, VH(3), VIL, VH(3), VIL, VIH,
Manufacturer Code(4) Device Code(4) Manufacturer Code(4) Device Code(4)
Software(5)
Notes:
VIH. Refer programming waveforms page 12.0V 0.5V. Manufacturer Code: 001FH, Device Code: 00C8H (x16)-AT52BR3224/3228; 00C9H (x16)-AT52BR3224T/3228T. details under "Software Product Identification Entry/Exit" page VIHPP (min) 1.65V; VIHPP (max) 3.6V. faster erase/program operations, 5.0V 0.5V 0.5V. VILPP (max) 0.8V.
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Characteristics
Symbol ISB1 ISB2 ISB3 (1)(2) ICC1 IPP1 ICC2 IPP2 ICC3 IPP3 VOL1 VOL2 VOH1 Parameter Input Load Current Output Leakage Current Standby Current CMOS Standby Current Standby Current Active Read Current Programming Current (VPP VCC) Input Load Current Programming Current (VPP 5.0V 0.5V) Programming Current (VPP 5.0V 0.5V) Programming Current (VPP 12.0V 0.5V) Programming Current (VPP 12.0V 0.5V) Input Voltage Input High Voltage Output Voltage Output Voltage -400 -400 -100 -100 VCCQ 2.6V VCCQ 2.6V VCCQ 2.6V VCCQ 2.6V VCCQ 0.45 0.20 3.0V 3.0V Condition VI/O 0.3V 2.0V 2.0V VCC, 2.85V MHz; IOUT -100 Units
Output High Voltage
VOH2
Output High Voltage
VCCQ
Notes:
3.3V 3.6V, (max) erase mode,
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Read Characteristics
AT52BR3224(T)-85 Symbol tACC tCE(1) tOE(2) tDF(3)(4) Parameter Read Cycle Time Address Output Delay Output Delay Output Delay Output Float Output Hold from Address, whichever occurred first RESET Output Delay AT52BR3228(T)-85 Units
Read Waveforms(1)(2)(3)(4)
ADDRESS ADDRESS VALID
tACC
RESET HIGH
OUTPUT VALID
OUTPUT
Notes:
delayed tACC after address transition without impact tACC. delayed after falling edge without impact tACC after address change without impact tACC. specified from whichever occurs first pF). This parameter characterized 100% tested.
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Input Test Waveforms Measurement Level
Output Test Load
Capacitance
MHz, 25°C(1)
Symbol COUT Units Conditions VOUT
Note:
This parameter characterized 100% tested.
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Word Load Characteristics
Symbol tAS, tOES tDH, tOEH tWPH Parameter Address, Setup Time Address Hold Time Chip Select Setup Time Chip Select Hold Time Write Pulse Width Data Setup Time Data, Hold Time Write Pulse Width High Units
Word Load Waveforms
Controlled
Controlled
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Program Cycle Characteristics
Symbol tBPVPP tWPH tECVPP tSEC tSECVPP Parameter Word Programming Time (VIHPP 4.5V) Word Programming Time (VPP 4.5V) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Write Pulse Width Write Pulse Width High Write Cycle Time Reset Pulse Width Chip Erase Cycle Time (VPP 4.5V) Chip Erase Cycle Time (VPP 4.5V) Sector Erase Cycle Time (VPP 4.5V) Sector Erase Cycle Time (VPP 4.5V) Erase Suspend Time Program Suspend Time Units seconds seconds
Program Cycle Waveforms
PROGRAM CYCLE
tWPH
ADDRESS
INPUT DATA
DATA
Sector Chip Erase Cycle Waveforms
tWPH
Note
A0-A20
WORD WORD WORD WORD Note WORD
DATA
WORD
Notes:
must high only when both low. chip erase, address should 555. sector erase, address depends what sector erased. (See note under "Command Definitions Hex" page 14.) chip erase, data should 10H, sector erase, data should 30H.
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Data Polling Characteristics(1)
Symbol tOEH Notes: Parameter Data Hold Time Hold Time Output Delay
Units
Write Recovery Time These parameters characterized 100% tested. spec Read Characteristics" page
Data Polling Waveforms
I/O7 A0-A20 tOEH HIGH
Toggle Characteristics(1)
Symbol tOEH tOEHP Notes: Parameter Data Hold Time Hold Time Output Delay High Pulse Write Recovery Time These parameters characterized 100% tested. spec Read Characteristics" page
Units
Toggle Waveforms(1)(2)(3)
Notes:
Toggling either both will operate toggle bit. tOEHP specification must toggling input(s). Beginning ending state I/O6 will vary. address location used address should vary.
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Software Product Identification Entry(1)
LOAD DATA ADDRESS
Sector Lockdown Enable Algorithm(1)
LOAD DATA ADDRESS
LOAD DATA ADDRESS
LOAD DATA ADDRESS
LOAD DATA ADDRESS
LOAD DATA ADDRESS
ENTER PRODUCT IDENTIFICATION MODE(2)(3)(5)
LOAD DATA ADDRESS
Software Product Identification Exit(1)(6)
LOAD DATA ADDRESS LOAD DATA ADDRESS
LOAD DATA ADDRESS
LOAD DATA ADDRESS
EXIT PRODUCT IDENTIFICATION MODE(4)
LOAD DATA SECTOR ADDRESS
PAUSE µs(2)
LOAD DATA ADDRESS
Notes:
Data Format: I/O15 I/O8 (Don't Care); I/O7 I/O0 (Hex)
Address Format: (Hex), A-1, (Don't Care). Sector Lockdown feature enabled.
EXIT PRODUCT IDENTIFICATION MODE(4)
Notes:
Data Format: I/O15 I/O8 (Don't Care); I/O7 I/O0 (Hex)
Address Format: (Hex), A-1, (Don't Care). VIL. Manufacturer Code read VIL; Device Code read VIH. device does remain identification mode powered down. device returns standard operation mode. Manufacturer Code: 001FH(x16) Device Code: 00C8 AT52BR3224/3228. 00C9H AT52BR3224T/3228T. Either Product Exit commands used.
1682A-10/01
4-megabit SRAM Description
4-megabit SRAM high-speed, super low-power CMOS SRAM organized 256K words bits. SRAM uses high-performance full CMOS process technology designed high-speed low-power circuit technology. particularly well-suited high-density low-power system application. This device data retention mode that guarantees data remain valid minimum power supply voltage 1.2V.
Fully Static Operation Tri-state Output Compatible Inputs Outputs Battery Backup
1.2V (Min) Data Retention
Voltage
Speed (ns)
Operation Current/ICC (mA) (Max)
Standby Current (µA) (Max)
Temperature (°C)
Block Diagram
DECODER SENSE I/O0
DATA BUFFER
BLOCK DECODER
DECODER
INPUT BUFFER
I/O7 I/O8
MEMORY ARRAY 256K WRITE DRIVER
COLUMN DECODER
I/O15
SCS1 SCS2
AT52BR3224(T)/3228(T)
1682A-10/01
AT52BR3224(T)/3228(T)
Absolute Maximum Ratings(1)
Symbol VIN, VOUT TSTG Note: Parameter Input/Output Voltage Power Supply Operating Temperature Storage Temperature Power Dissipation Rating -0.3 -0.3 Unit
Stresses greater than those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device under these other conditions above those indicated operation this specification implied. Exposure absolute maximum rating conditions extended period affect reliability.
Truth Table
SCS1 H(1)
SCS2
SLB(2)
SUB(2)
Mode
I/O0 I/O7
I/O8 I/O15
Power
Deselected
High-Z
High-Z
Standby
Output Disabled
High-Z
High-Z
Active
High-Z Write
High-Z High-Z High-Z DOUT DOUT High-Z Active Active
DOUT High-Z Read DOUT DOUT
Notes:
VIH, VIL, Don't Care (VIL VIH) SUB, (Upper, Lower Byte Enable). These active inputs allow individual bytes written read. When LOW, data written read lower byte, I/O0 I/O7. When LOW, data written read upper byte, I/O8 I/O15.
Recommended Operating Condition
Symbol
Parameter Supply Voltage Ground Input High Voltage Input Voltage
-0.31
Unit
Note:
Undershoot: -1.5V pulse width less than Undershoot sampled, 100% tested.
1682A-10/01
Electrical Characteristics
-40°C 85°C
Symbol Parameter Input Leakage Current Output Leakage Current Test Condition VOUT VCC, SCS1 SCS2=VIL VIH, SCS1 VIL, SCS2=VIH, VIL, II/O SCS1 VIL, SCS2 VIH, VIL, Cycle Time 100% Duty, II/O SCS1 0.2V, SCS2 0.2V 0.2V 0.2V, Cycle Time 100% Duty, II/O Standby Current (TTL Input) SCS1 SCS2 SUB, SCS1 0.2V SCS2 0.2V SUB, 0.2V 0.2V 0.2V -0.1 Unit
ICC1
Operating Power Supply Current Average Operating Current
ISB1
Standby Current (CMOS Input)
Output Output High
Capacitance(1)
(Temp 25°C, MHz)
Symbol COUT Note: Parameter Input Capacitance (Add, SCS1, SCS2, SLB, SUB, SWE, SOE) Output Capacitance (I/O) Condition VI/O Unit
These parameters sampled 100% tested.
AT52BR3224(T)/3228(T)
1682A-10/01
AT52BR3224(T)/3228(T)
Characteristics
-40°C 85°C, Unless Otherwise Specified
Symbol tACS tCLZ tOLZ tBLZ tCHZ tOHZ tBHZ tWHZ Parameter Read Cycle Time Address Access Time Chip Select Access Time Output Enable Output Valid SLB, Access Time Chip Select Output Output Enable Output SLB, Enable Output Chip Deselection Output High Disable Output High SLB, Disable Output High Output Hold from Address Change Write Cycle Time Chip Selection Write Address Valid Write SLB, Valid Write Address Setup Time Write Pulse Width Write Recovery Time Write Output High Data Write Time Overlap Data Hold from Write Time Output Active from Write Unit
Test Conditions
-40°C 85°C, Unless Otherwise Specified
Parameter Input Pulse Level Input Rise Fall Time Input Output Timing Reference Level Output Load Load Load Value 0.4V 2.2V 1.5V Load Load
1682A-10/01
Test Loads
1.8V
4091 DOUT
3273
Note:
Including scope capacitance.
AT52BR3224(T)/3228(T)
1682A-10/01
AT52BR3224(T)/3228(T)
Timing Diagrams
Read Cycle 1(1),(4)
ADDRESS tACS SCS1
SCS2 SUB, tOLZ(3) tBLZ(3) DATA HIGH-Z tCLZ(3) DATA VALID tOHZ tBHZ(3) tCHZ(3)
Read Cycle 2(1),(2),(4)
ADDRESS DATA
PREVIOUS DATA DATA VALID
Read Cycle 3(1),(2),(4)
SCS1 SUB,
SCS2
tACS tCLZ
DATA VALID
tCHZ
DATA
Notes:
Read Cycle occurs whenever high low, while and/or SCS1 SCS2 active status. VIL. Transition measured from steady state voltage. This parameter sampled 100% tested. SCS1 high standby, active. SCS2 standby, high active. high standby, active.
1682A-10/01
Write Cycle (SWE Controlled)(1),(4),(8)
ADDRESS
tWR(2)
SCS1
SCS2
SUB,
DATA VALID tWHZ(3)(7)
DATA
HIGH-Z
DATA
Write Cycle (SCS1, SCS2 Controlled)(1),(4),(8)
ADDRESS
tWR(2)
SCS1
SCS2
SUB,
HIGH-Z
DATA
DATA VALID HIGH-Z
DATA
Notes:
write occurs during overlap SWE, SCS1, high SCS2 and/or SLB. measured from earlier SCS1, SLB, SUB, going high SCS2 going write cycle. During this period, pins output state that input signals opposite phase output must applied. SCS1, transition SCS2 high transition occur simultaneously with transition after transition, outputs remain high impedance state. (data out) same phase with write data this write cycle. (data out) read data next address. Transition measured from steady state. This parameter sampled 100% tested. SCS1 high standby, active SCS2 standby, high active. high standby, active.
AT52BR3224(T)/3228(T)
1682A-10/01
AT52BR3224(T)/3228(T)
Data Retention Electric Characteristic
-40°C 85°C
Symbol Parameter Data Retention Test Condition SCS1 0.2V SCS2 0.2V SUB, 0.2V 0.2V 0.2V Vcc=1.5V, SCS1 0.2V SCS2 0.2V SUB, 0.2V 0.2V 0.2V Data Retention Timing Diagram Unit
ICCDR
Data Retention Current
tCDR Notes:
Chip Deselect Data Retention Time Operating Recovery Time
Typical values under condition 25°C. Typical values sampled 100% tested. read cycle time.
Data Retention Timing Diagram
2.7V tCDR
DATA RETENTION MODE
SCS1 0.2V
SCS1
Data Retention Timing Diagram
2.7V SCS2 tCDR
DATA RETENTION MODE
0.4V
SCS2 0.2V
1682A-10/01
8-megabit SRAM Description
8-megabit SRAM high-speed, super low-power CMOS SRAM organized 512K words bits. SRAM uses high-performance full CMOS process technology designed high-speed low-power circuit technology. particularly well-suited high-density low-power system application. This device data retention mode that guarantees data remain valid minimum power supply voltage 1.2V.
Fully Static Operation Tri-state Output Compatible Inputs Outputs Battery Backup
1.2V (Min) Data Retention
Voltage
Speed (ns)
Operation Current/ICC (mA) (Max)
Standby Current (µA) (Max)
Temperature (°C)
Block Diagram
DECODER SENSE I/O0
DATA BUFFER
BLOCK DECODER
DECODER
INPUT BUFFER
I/O7 I/O8
MEMORY ARRAY 512K WRITE DRIVER
COLUMN DECODER
I/O15
SCS1 SCS2
AT52BR3224(T)/3228(T)
1682A-10/01
AT52BR3224(T)/3228(T)
Absolute Maximum Ratings(1)
Symbol VIN, VOUT TSTG Note: Parameter Input/Output Voltage Power Supply Operating Temperature Storage Temperature Power Dissipation Rating -0.3 -0.3 Unit
Stresses greater than those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device under these other conditions above those indicated operation this specification implied. Exposure absolute maximum rating conditions extended period affect reliability.
Truth Table
SCS1
SCS2
SLB(2)
SUB(2)
Mode
I/O0 I/O7
I/O8 I/O15
Power
Deselected
High-Z
High-Z
Standby
Output Disabled
High-Z
High-Z
Active
High-Z Write
High-Z High-Z High-Z DOUT DOUT High-Z Active Active
DOUT High-Z Read DOUT DOUT
Notes:
VIH, VIL, Don't Care (VIL VIH) SUB, (Upper, Lower Byte Enable). These active inputs allow individual bytes written read. When LOW, data written read lower byte, I/O0 I/O7. When LOW, data written read upper byte, I/O8 I/O15.
Recommended Operating Condition
Symbol VIL(1) Note: Parameter Supply Voltage Ground Input High Voltage Input Voltage -0.31(1) Unit
Undershoot: -1.5V pulse width less than Undershoot sampled, 100% tested.
1682A-10/01
Electrical Characteristics
-40°C 85°C
Symbol Parameter Input Leakage Current Output Leakage Current Test Condition VOUT VCC, SCS1 SCS2=VIL VIH, SCS1 VIL, SCS2=VIH, VIL, II/O SCS1 VIL, SCS2 VIH, VIL, Cycle Time 100% Duty, II/O SCS1 0.2V, SCS2 0.2V 0.2V 0.2V, Cycle Time 100% Duty, II/O Standby Current (TTL Input) SCS1 SCS2 SUB, SCS1 0.2V SCS2 0.2V SUB, 0.2V 0.2V 0.2V -0.1 Unit
ICC1
Operating Power Supply Current Average Operating Current
ISB1
Standby Current (CMOS Input)
Output Output High
Capacitance(1)
(Temp 25°C, MHz)
Symbol COUT Note: Parameter Input Capacitance (Add, SCS1, SCS2, SLB, SUB, SWE, SOE) Output Capacitance (I/O) Condition VI/O Unit
These parameters sampled 100% tested.
AT52BR3224(T)/3228(T)
1682A-10/01
AT52BR3224(T)/3228(T)
Characteristics
-40°C 85°C, Unless Otherwise Specified
Symbol tACS tCLZ tOLZ tBLZ tCHZ tOHZ tBHZ tWHZ Parameter Read Cycle Time Address Access Time Chip Select Access Time Output Enable Output Valid SLB, Access Time Chip Select Output Output Enable Output SLB, Enable Output Chip Deselection Output High Disable Output High SLB, Disable Output High Output Hold from Address Change Write Cycle Time Chip Selection Write Address Valid Write SLB, Valid Write Address Setup Time Write Pulse Width Write Recovery Time Write Output High Data Write Time Overlap Data Hold from Write Time Output Active from Write Unit
Test Conditions
-40°C 85°C, Unless Otherwise Specified
Parameter Input Pulse Level Input Rise Fall Time Input Output Timing Reference Level Output Load Load Load Value 0.4V 2.2V 1.5V Load Load
1682A-10/01
Test Loads
2.8V
1045 DOUT
2048
Note:
Including scope capacitance.
AT52BR3224(T)/3228(T)
1682A-10/01
AT52BR3224(T)/3228(T)
Timing Diagrams
Read Cycle 1(1),(4)
ADDRESS tACS SCS1
SCS2 SUB, tOLZ(3) tBLZ(3) DATA HIGH-Z tCLZ(3) DATA VALID tOHZ tBHZ(3) tCHZ(3)
Read Cycle 2(1),(2),(4)
ADDRESS DATA
PREVIOUS DATA DATA VALID
Read Cycle 3(1),(2),(4)
SCS1 SUB,
SCS2
tACS tCLZ
DATA VALID
tCHZ
DATA
Notes:
Read Cycle occurs whenever high low, while and/or SCS1 SCS2 active status. VIL. Transition measured from steady state voltage. This parameter sampled 100% tested. SCS1 high standby, active. SCS2 standby, high active. high standby, active.
1682A-10/01
Write Cycle (SWE Controlled)(1),(4),(8)
ADDRESS
tWR(2)
SCS1
SCS2
SUB,
DATA VALID tWHZ(3)(7)
DATA
HIGH-Z
DATA
Write Cycle (SCS1, SCS2 Controlled)(1),(4),(8)
ADDRESS
tWR(2)
SCS1
SCS2
SUB,
HIGH-Z
DATA
DATA VALID HIGH-Z
DATA
Notes:
write occurs during overlap SWE, SCS1, high SCS2 and/or SLB. measured from earlier SCS1, SLB, SUB, going high SCS2 going write cycle. During this period, pins output state that input signals opposite phase output must applied. SCS1, transition SCS2 high transition occur simultaneously with transition after transition, outputs remain high impedance state. (data out) same phase with write data this write cycle. (data out) read data next address. Transition measured from steady state. This parameter sampled 100% tested. SCS1 high standby, active SCS2 standby, high active. high standby, active.
AT52BR3224(T)/3228(T)
1682A-10/01
AT52BR3224(T)/3228(T)
Data Retention Electric Characteristic
-40°C 85°C
Symbol Parameter Data Retention Test Condition SCS1 0.2V SCS2 0.2V SUB, 0.2V 0.2V 0.2V Vcc=1.5V, SCS1 0.2V SCS2 0.2V SUB, 0.2V 0.2V 0.2V Data Retention Timing Diagram Unit
ICCDR
Data Retention Current
tCDR Notes:
Chip Deselect Data Retention Time Operating Recovery Time
Typical values under condition 25°C. Typical values sampled 100% tested. read cycle time.
Data Retention Timing Diagram
2.7V tCDR
DATA RETENTION MODE
SCS1 0.2V
SCS1
Data Retention Timing Diagram
2.7V SCS2 tCDR
DATA RETENTION MODE
0.4V
SCS2 0.2V
1682A-10/01
AT52BR3224T Ordering Information
tACC (ns) Ordering Code AT52BR3224-85CI AT52BR3224T-85CI AT52BR3228-85CI AT52BR3228T-85CI Flash Boot Block Bottom Bottom Flash Plane Architecture SRAM 256K 256K 512K 512K Package 66C4 66C4 66C4 66C4 Operation Range Industrial (-40° 85°C) Industrial (-40° 85°C) Industrial (-40° 85°C) Industrial (-40° 85°C)
Package Type 66C4 66-ball, Plastic Chip-size Ball Grid Array Package (CBGA)
AT52BR3224(T)/3228(T)
1682A-10/01
AT52BR3224(T)/3228(T)
Packaging Information
66C4 CBGA
Marked Identifier
0.12
Seating Plane
SIDE VIEW
VIEW
1.10
BALL CORNER
1.20
BOTTOM VIEW
SYMBOL
COMMON DIMENSIONS (*Unit Measure
0.25 10.90
11.00 8.80
1.20 11.10
NOTE
7.90
8.00 5.60 0.80 0.40
8.10
8/29/01
2325 Orchard Parkway TITLE: 66C4, ball (12X8 Array), 11x8x1.2mm body, 0.8mm ball pitch Jose, 95131 Chip-scale Ball Grid Array package (CBGA)
DRAWING
66C4
1682A-10/01
Atmel Headquarters
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1682A-10/01/0M

2.7V 3.3V Read/Write Access Time Sector Erase Architecture Sixty-

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